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Commit | Line | Data |
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1db09b84 | 1 | /* |
b3305981 | 2 | * QEMU PowerPC e500-based platforms |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
0d75590d | 17 | #include "qemu/osdep.h" |
a8d25326 | 18 | #include "qemu-common.h" |
2c65db5e | 19 | #include "qemu/datadir.h" |
ab3dd749 | 20 | #include "qemu/units.h" |
da34e65c | 21 | #include "qapi/error.h" |
e6eaabeb | 22 | #include "e500.h" |
3eddc1be | 23 | #include "e500-ccsr.h" |
1422e32d | 24 | #include "net/net.h" |
1de7afc9 | 25 | #include "qemu/config-file.h" |
0d09e41a | 26 | #include "hw/char/serial.h" |
a2cb15b0 | 27 | #include "hw/pci/pci.h" |
4a18e7c9 | 28 | #include "hw/boards.h" |
9c17d615 PB |
29 | #include "sysemu/sysemu.h" |
30 | #include "sysemu/kvm.h" | |
71e8a915 | 31 | #include "sysemu/reset.h" |
54d31236 | 32 | #include "sysemu/runstate.h" |
1db09b84 | 33 | #include "kvm_ppc.h" |
9c17d615 | 34 | #include "sysemu/device_tree.h" |
0d09e41a | 35 | #include "hw/ppc/openpic.h" |
8d085cf0 | 36 | #include "hw/ppc/openpic_kvm.h" |
0d09e41a | 37 | #include "hw/ppc/ppc.h" |
a27bd6c7 | 38 | #include "hw/qdev-properties.h" |
4a18e7c9 | 39 | #include "hw/loader.h" |
ca20cf32 | 40 | #include "elf.h" |
4a18e7c9 | 41 | #include "hw/sysbus.h" |
022c62cb | 42 | #include "exec/address-spaces.h" |
1de7afc9 | 43 | #include "qemu/host-utils.h" |
922a01a0 | 44 | #include "qemu/option.h" |
0d09e41a | 45 | #include "hw/pci-host/ppce500.h" |
f7087343 AG |
46 | #include "qemu/error-report.h" |
47 | #include "hw/platform-bus.h" | |
fdfb7f2c | 48 | #include "hw/net/fsl_etsec/etsec.h" |
7abb479c | 49 | #include "hw/i2c/i2c.h" |
64552b6b | 50 | #include "hw/irq.h" |
1db09b84 | 51 | |
cefd3cdb | 52 | #define EPAPR_MAGIC (0x45504150) |
1db09b84 | 53 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
9dd5eba1 | 54 | #define DTC_LOAD_PAD 0x1800000 |
75bb6589 | 55 | #define DTC_PAD_MASK 0xFFFFF |
ab3dd749 | 56 | #define DTB_MAX_SIZE (8 * MiB) |
75bb6589 LY |
57 | #define INITRD_LOAD_PAD 0x2000000 |
58 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 | 59 | |
ab3dd749 | 60 | #define RAM_SIZES_ALIGN (64 * MiB) |
1db09b84 | 61 | |
b3305981 | 62 | /* TODO: parameterize */ |
ed2bc496 | 63 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL |
dffb1dc2 | 64 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
a911b7a9 | 65 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
dffb1dc2 BB |
66 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
67 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL | |
68 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL | |
ed2bc496 | 69 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
dffb1dc2 | 70 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
b88e77f4 | 71 | #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL |
7abb479c | 72 | #define MPC8544_I2C_REGS_OFFSET 0x3000ULL |
82e345f5 | 73 | #define MPC8XXX_GPIO_IRQ 47 |
7abb479c AR |
74 | #define MPC8544_I2C_IRQ 43 |
75 | #define RTC_REGS_OFFSET 0x68 | |
1db09b84 | 76 | |
0c36ab71 BM |
77 | #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) |
78 | ||
3b989d49 AG |
79 | struct boot_info |
80 | { | |
81 | uint32_t dt_base; | |
cba2026a | 82 | uint32_t dt_size; |
3b989d49 AG |
83 | uint32_t entry; |
84 | }; | |
85 | ||
347dd79d AG |
86 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
87 | int nr_slots, int *len) | |
0dbc0798 | 88 | { |
347dd79d AG |
89 | int i = 0; |
90 | int slot; | |
91 | int pci_irq; | |
9e2c1298 | 92 | int host_irq; |
347dd79d AG |
93 | int last_slot = first_slot + nr_slots; |
94 | uint32_t *pci_map; | |
95 | ||
96 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); | |
97 | pci_map = g_malloc(*len); | |
98 | ||
99 | for (slot = first_slot; slot < last_slot; slot++) { | |
100 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { | |
101 | pci_map[i++] = cpu_to_be32(slot << 11); | |
102 | pci_map[i++] = cpu_to_be32(0x0); | |
103 | pci_map[i++] = cpu_to_be32(0x0); | |
104 | pci_map[i++] = cpu_to_be32(pci_irq + 1); | |
105 | pci_map[i++] = cpu_to_be32(mpic); | |
9e2c1298 AG |
106 | host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
107 | pci_map[i++] = cpu_to_be32(host_irq + 1); | |
347dd79d AG |
108 | pci_map[i++] = cpu_to_be32(0x1); |
109 | } | |
0dbc0798 | 110 | } |
347dd79d AG |
111 | |
112 | assert((i * sizeof(uint32_t)) == *len); | |
113 | ||
114 | return pci_map; | |
0dbc0798 AG |
115 | } |
116 | ||
a053a7ce AG |
117 | static void dt_serial_create(void *fdt, unsigned long long offset, |
118 | const char *soc, const char *mpic, | |
119 | const char *alias, int idx, bool defcon) | |
120 | { | |
2fb513d3 | 121 | char *ser; |
a053a7ce | 122 | |
2fb513d3 | 123 | ser = g_strdup_printf("%s/serial@%llx", soc, offset); |
5a4348d1 PC |
124 | qemu_fdt_add_subnode(fdt, ser); |
125 | qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); | |
126 | qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); | |
127 | qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); | |
128 | qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); | |
129 | qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); | |
130 | qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); | |
131 | qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); | |
132 | qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); | |
a053a7ce AG |
133 | |
134 | if (defcon) { | |
90ee4e01 ND |
135 | /* |
136 | * "linux,stdout-path" and "stdout" properties are deprecated by linux | |
137 | * kernel. New platforms should only use the "stdout-path" property. Set | |
138 | * the new property and continue using older property to remain | |
139 | * compatible with the existing firmware. | |
140 | */ | |
5a4348d1 | 141 | qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); |
90ee4e01 | 142 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); |
a053a7ce | 143 | } |
2fb513d3 | 144 | g_free(ser); |
a053a7ce AG |
145 | } |
146 | ||
b88e77f4 AG |
147 | static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) |
148 | { | |
149 | hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; | |
150 | int irq0 = MPC8XXX_GPIO_IRQ; | |
151 | gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); | |
016f7758 AG |
152 | gchar *poweroff = g_strdup_printf("%s/power-off", soc); |
153 | int gpio_ph; | |
b88e77f4 AG |
154 | |
155 | qemu_fdt_add_subnode(fdt, node); | |
156 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); | |
157 | qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); | |
158 | qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); | |
159 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); | |
160 | qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); | |
161 | qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); | |
016f7758 AG |
162 | gpio_ph = qemu_fdt_alloc_phandle(fdt); |
163 | qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); | |
164 | qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); | |
165 | ||
166 | /* Power Off Pin */ | |
167 | qemu_fdt_add_subnode(fdt, poweroff); | |
168 | qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); | |
169 | qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); | |
b88e77f4 AG |
170 | |
171 | g_free(node); | |
016f7758 | 172 | g_free(poweroff); |
b88e77f4 AG |
173 | } |
174 | ||
7abb479c AR |
175 | static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) |
176 | { | |
177 | int offset = RTC_REGS_OFFSET; | |
178 | ||
179 | gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); | |
180 | qemu_fdt_add_subnode(fdt, rtc); | |
181 | qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); | |
182 | qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); | |
183 | qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); | |
184 | ||
185 | g_free(rtc); | |
186 | } | |
187 | ||
188 | static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, | |
189 | const char *alias) | |
190 | { | |
191 | hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; | |
192 | int irq0 = MPC8544_I2C_IRQ; | |
193 | ||
194 | gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); | |
195 | qemu_fdt_add_subnode(fdt, i2c); | |
196 | qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); | |
197 | qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); | |
198 | qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); | |
199 | qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); | |
200 | qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); | |
201 | qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); | |
202 | qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); | |
203 | ||
204 | g_free(i2c); | |
205 | } | |
206 | ||
207 | ||
f7087343 AG |
208 | typedef struct PlatformDevtreeData { |
209 | void *fdt; | |
210 | const char *mpic; | |
211 | int irq_start; | |
212 | const char *node; | |
213 | PlatformBusDevice *pbus; | |
214 | } PlatformDevtreeData; | |
215 | ||
fdfb7f2c AG |
216 | static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) |
217 | { | |
218 | eTSEC *etsec = ETSEC_COMMON(sbdev); | |
219 | PlatformBusDevice *pbus = data->pbus; | |
220 | hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
221 | int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); | |
222 | int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); | |
223 | int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); | |
224 | gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); | |
225 | gchar *group = g_strdup_printf("%s/queue-group", node); | |
226 | void *fdt = data->fdt; | |
227 | ||
228 | assert((int64_t)mmio0 >= 0); | |
229 | assert(irq0 >= 0); | |
230 | assert(irq1 >= 0); | |
231 | assert(irq2 >= 0); | |
232 | ||
233 | qemu_fdt_add_subnode(fdt, node); | |
234 | qemu_fdt_setprop_string(fdt, node, "device_type", "network"); | |
235 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); | |
236 | qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); | |
237 | qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); | |
238 | qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); | |
239 | ||
240 | qemu_fdt_add_subnode(fdt, group); | |
241 | qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); | |
242 | qemu_fdt_setprop_cells(fdt, group, "interrupts", | |
243 | data->irq_start + irq0, 0x2, | |
244 | data->irq_start + irq1, 0x2, | |
245 | data->irq_start + irq2, 0x2); | |
246 | ||
247 | g_free(node); | |
248 | g_free(group); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
4f01a637 | 253 | static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) |
f7087343 AG |
254 | { |
255 | PlatformDevtreeData *data = opaque; | |
256 | bool matched = false; | |
257 | ||
fdfb7f2c AG |
258 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { |
259 | create_devtree_etsec(sbdev, data); | |
260 | matched = true; | |
261 | } | |
262 | ||
f7087343 AG |
263 | if (!matched) { |
264 | error_report("Device %s is not supported by this machine yet.", | |
265 | qdev_fw_name(DEVICE(sbdev))); | |
266 | exit(1); | |
267 | } | |
f7087343 AG |
268 | } |
269 | ||
a3fc8396 | 270 | static void platform_bus_create_devtree(PPCE500MachineState *pms, |
03f04809 | 271 | void *fdt, const char *mpic) |
f7087343 | 272 | { |
a3fc8396 | 273 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
03f04809 | 274 | gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); |
f7087343 | 275 | const char platcomp[] = "qemu,platform\0simple-bus"; |
03f04809 IM |
276 | uint64_t addr = pmc->platform_bus_base; |
277 | uint64_t size = pmc->platform_bus_size; | |
278 | int irq_start = pmc->platform_bus_first_irq; | |
f7087343 AG |
279 | |
280 | /* Create a /platform node that we can put all devices into */ | |
281 | ||
282 | qemu_fdt_add_subnode(fdt, node); | |
283 | qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); | |
284 | ||
285 | /* Our platform bus region is less than 32bit big, so 1 cell is enough for | |
286 | address and size */ | |
287 | qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); | |
288 | qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); | |
289 | qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); | |
290 | ||
291 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); | |
292 | ||
a3fc8396 IM |
293 | /* Create dt nodes for dynamic devices */ |
294 | PlatformDevtreeData data = { | |
295 | .fdt = fdt, | |
296 | .mpic = mpic, | |
297 | .irq_start = irq_start, | |
298 | .node = node, | |
299 | .pbus = pms->pbus_dev, | |
300 | }; | |
f7087343 | 301 | |
a3fc8396 IM |
302 | /* Loop through all dynamic sysbus devices and create nodes for them */ |
303 | foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); | |
f7087343 AG |
304 | |
305 | g_free(node); | |
306 | } | |
307 | ||
03f04809 | 308 | static int ppce500_load_device_tree(PPCE500MachineState *pms, |
a8170e5e AK |
309 | hwaddr addr, |
310 | hwaddr initrd_base, | |
28290f37 | 311 | hwaddr initrd_size, |
903585de AG |
312 | hwaddr kernel_base, |
313 | hwaddr kernel_size, | |
28290f37 | 314 | bool dry_run) |
1db09b84 | 315 | { |
03f04809 | 316 | MachineState *machine = MACHINE(pms); |
fe6b6346 | 317 | unsigned int smp_cpus = machine->smp.cpus; |
03f04809 | 318 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
28290f37 | 319 | CPUPPCState *env = first_cpu->env_ptr; |
dbf916d8 | 320 | int ret = -1; |
3ef96221 | 321 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; |
7ec632b4 | 322 | int fdt_size; |
dbf916d8 | 323 | void *fdt; |
5de6b46d | 324 | uint8_t hypercall[16]; |
0c36ab71 BM |
325 | uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; |
326 | uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; | |
621d05e3 | 327 | int i; |
ebb9518a | 328 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
2fb513d3 GK |
329 | char *soc; |
330 | char *mpic; | |
19ac9dea | 331 | uint32_t mpic_ph; |
a911b7a9 | 332 | uint32_t msi_ph; |
2fb513d3 GK |
333 | char *gutil; |
334 | char *pci; | |
335 | char *msi; | |
347dd79d AG |
336 | uint32_t *pci_map = NULL; |
337 | int len; | |
3627757e AG |
338 | uint32_t pci_ranges[14] = |
339 | { | |
03f04809 IM |
340 | 0x2000000, 0x0, pmc->pci_mmio_bus_base, |
341 | pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, | |
3627757e AG |
342 | 0x0, 0x20000000, |
343 | ||
344 | 0x1000000, 0x0, 0x0, | |
03f04809 | 345 | pmc->pci_pio_base >> 32, pmc->pci_pio_base, |
3627757e AG |
346 | 0x0, 0x10000, |
347 | }; | |
f2ce39b4 PB |
348 | const char *dtb_file = machine->dtb; |
349 | const char *toplevel_compat = machine->dt_compatible; | |
d1b93565 AG |
350 | |
351 | if (dtb_file) { | |
352 | char *filename; | |
353 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); | |
354 | if (!filename) { | |
355 | goto out; | |
356 | } | |
357 | ||
358 | fdt = load_device_tree(filename, &fdt_size); | |
2343dd11 | 359 | g_free(filename); |
d1b93565 AG |
360 | if (!fdt) { |
361 | goto out; | |
362 | } | |
363 | goto done; | |
364 | } | |
1db09b84 | 365 | |
2636fcb6 | 366 | fdt = create_device_tree(&fdt_size); |
5cea8590 PB |
367 | if (fdt == NULL) { |
368 | goto out; | |
369 | } | |
1db09b84 AJ |
370 | |
371 | /* Manipulate device tree in memory. */ | |
5a4348d1 PC |
372 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); |
373 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); | |
51b852b7 | 374 | |
5a4348d1 PC |
375 | qemu_fdt_add_subnode(fdt, "/memory"); |
376 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
377 | qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, | |
378 | sizeof(mem_reg_property)); | |
1db09b84 | 379 | |
5a4348d1 | 380 | qemu_fdt_add_subnode(fdt, "/chosen"); |
3b989d49 | 381 | if (initrd_size) { |
5a4348d1 PC |
382 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
383 | initrd_base); | |
3b989d49 AG |
384 | if (ret < 0) { |
385 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
386 | } | |
1db09b84 | 387 | |
5a4348d1 PC |
388 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
389 | (initrd_base + initrd_size)); | |
3b989d49 AG |
390 | if (ret < 0) { |
391 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
392 | } | |
903585de AG |
393 | |
394 | } | |
395 | ||
396 | if (kernel_base != -1ULL) { | |
397 | qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", | |
398 | kernel_base >> 32, kernel_base, | |
399 | kernel_size >> 32, kernel_size); | |
3b989d49 | 400 | } |
1db09b84 | 401 | |
5a4348d1 | 402 | ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
3ef96221 | 403 | machine->kernel_cmdline); |
1db09b84 AJ |
404 | if (ret < 0) |
405 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
406 | ||
407 | if (kvm_enabled()) { | |
911d6e7a AG |
408 | /* Read out host's frequencies */ |
409 | clock_freq = kvmppc_get_clockfreq(); | |
410 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
411 | |
412 | /* indicate KVM hypercall interface */ | |
5a4348d1 PC |
413 | qemu_fdt_add_subnode(fdt, "/hypervisor"); |
414 | qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", | |
415 | "linux,kvm"); | |
5de6b46d | 416 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); |
5a4348d1 PC |
417 | qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", |
418 | hypercall, sizeof(hypercall)); | |
1a61a9ae SY |
419 | /* if KVM supports the idle hcall, set property indicating this */ |
420 | if (kvmppc_get_hasidle(env)) { | |
5a4348d1 | 421 | qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); |
1a61a9ae | 422 | } |
1db09b84 | 423 | } |
3b989d49 | 424 | |
625e665b | 425 | /* Create CPU nodes */ |
5a4348d1 PC |
426 | qemu_fdt_add_subnode(fdt, "/cpus"); |
427 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
428 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
625e665b | 429 | |
1e3debf0 AG |
430 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
431 | the first node as boot node and be happy */ | |
432 | for (i = smp_cpus - 1; i >= 0; i--) { | |
440c8152 | 433 | CPUState *cpu; |
2fb513d3 | 434 | char *cpu_name; |
03f04809 | 435 | uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); |
10f25a46 | 436 | |
440c8152 | 437 | cpu = qemu_get_cpu(i); |
55e5c285 | 438 | if (cpu == NULL) { |
1e3debf0 AG |
439 | continue; |
440 | } | |
440c8152 | 441 | env = cpu->env_ptr; |
1e3debf0 | 442 | |
2fb513d3 | 443 | cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); |
5a4348d1 PC |
444 | qemu_fdt_add_subnode(fdt, cpu_name); |
445 | qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); | |
446 | qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
447 | qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | |
6d536570 | 448 | qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); |
5a4348d1 PC |
449 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", |
450 | env->dcache_line_size); | |
451 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
452 | env->icache_line_size); | |
453 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
454 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
455 | qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
55e5c285 | 456 | if (cpu->cpu_index) { |
5a4348d1 PC |
457 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); |
458 | qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", | |
459 | "spin-table"); | |
460 | qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", | |
461 | cpu_release_addr); | |
1e3debf0 | 462 | } else { |
5a4348d1 | 463 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); |
1e3debf0 | 464 | } |
2fb513d3 | 465 | g_free(cpu_name); |
1db09b84 AJ |
466 | } |
467 | ||
5a4348d1 | 468 | qemu_fdt_add_subnode(fdt, "/aliases"); |
5da96624 | 469 | /* XXX These should go into their respective devices' code */ |
2fb513d3 | 470 | soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); |
5a4348d1 PC |
471 | qemu_fdt_add_subnode(fdt, soc); |
472 | qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); | |
473 | qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, | |
474 | sizeof(compatible_sb)); | |
475 | qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); | |
476 | qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); | |
477 | qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, | |
03f04809 | 478 | pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, |
5a4348d1 | 479 | MPC8544_CCSRBAR_SIZE); |
5da96624 | 480 | /* XXX should contain a reasonable value */ |
5a4348d1 | 481 | qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); |
5da96624 | 482 | |
2fb513d3 | 483 | mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
5a4348d1 PC |
484 | qemu_fdt_add_subnode(fdt, mpic); |
485 | qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); | |
486 | qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); | |
487 | qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, | |
488 | 0x40000); | |
489 | qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); | |
490 | qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); | |
491 | mpic_ph = qemu_fdt_alloc_phandle(fdt); | |
492 | qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); | |
493 | qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); | |
494 | qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); | |
19ac9dea | 495 | |
0cfc6e8d AG |
496 | /* |
497 | * We have to generate ser1 first, because Linux takes the first | |
498 | * device it finds in the dt as serial output device. And we generate | |
499 | * devices in reverse order to the dt. | |
500 | */ | |
9bca0edb | 501 | if (serial_hd(1)) { |
79c0ff2c AG |
502 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
503 | soc, mpic, "serial1", 1, false); | |
504 | } | |
505 | ||
9bca0edb | 506 | if (serial_hd(0)) { |
79c0ff2c AG |
507 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
508 | soc, mpic, "serial0", 0, true); | |
509 | } | |
0cfc6e8d | 510 | |
7abb479c AR |
511 | /* i2c */ |
512 | dt_i2c_create(fdt, soc, mpic, "i2c"); | |
513 | ||
514 | dt_rtc_create(fdt, "i2c", "rtc"); | |
515 | ||
516 | ||
2fb513d3 GK |
517 | gutil = g_strdup_printf("%s/global-utilities@%llx", soc, |
518 | MPC8544_UTIL_OFFSET); | |
5a4348d1 PC |
519 | qemu_fdt_add_subnode(fdt, gutil); |
520 | qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); | |
521 | qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); | |
522 | qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); | |
2fb513d3 | 523 | g_free(gutil); |
f5038483 | 524 | |
2fb513d3 | 525 | msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
5a4348d1 PC |
526 | qemu_fdt_add_subnode(fdt, msi); |
527 | qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); | |
528 | qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); | |
529 | msi_ph = qemu_fdt_alloc_phandle(fdt); | |
530 | qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); | |
531 | qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); | |
532 | qemu_fdt_setprop_cells(fdt, msi, "interrupts", | |
a911b7a9 AG |
533 | 0xe0, 0x0, |
534 | 0xe1, 0x0, | |
535 | 0xe2, 0x0, | |
536 | 0xe3, 0x0, | |
537 | 0xe4, 0x0, | |
538 | 0xe5, 0x0, | |
539 | 0xe6, 0x0, | |
540 | 0xe7, 0x0); | |
5a4348d1 PC |
541 | qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); |
542 | qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); | |
2fb513d3 | 543 | g_free(msi); |
a911b7a9 | 544 | |
2fb513d3 GK |
545 | pci = g_strdup_printf("/pci@%llx", |
546 | pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); | |
5a4348d1 PC |
547 | qemu_fdt_add_subnode(fdt, pci); |
548 | qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); | |
549 | qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); | |
550 | qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); | |
551 | qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, | |
552 | 0x0, 0x7); | |
553 | pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), | |
03f04809 | 554 | pmc->pci_first_slot, pmc->pci_nr_slots, |
492ec48d | 555 | &len); |
5a4348d1 PC |
556 | qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); |
557 | qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); | |
558 | qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); | |
559 | qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); | |
3627757e | 560 | for (i = 0; i < 14; i++) { |
0dbc0798 AG |
561 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
562 | } | |
5a4348d1 PC |
563 | qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
564 | qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); | |
2eaaac1f | 565 | qemu_fdt_setprop_cells(fdt, pci, "reg", |
03f04809 IM |
566 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, |
567 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), | |
2eaaac1f | 568 | 0, 0x1000); |
5a4348d1 PC |
569 | qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
570 | qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); | |
571 | qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); | |
572 | qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); | |
573 | qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); | |
2fb513d3 | 574 | g_free(pci); |
0dbc0798 | 575 | |
03f04809 | 576 | if (pmc->has_mpc8xxx_gpio) { |
b88e77f4 AG |
577 | create_dt_mpc8xxx_gpio(fdt, soc, mpic); |
578 | } | |
2fb513d3 | 579 | g_free(soc); |
b88e77f4 | 580 | |
a3fc8396 IM |
581 | if (pms->pbus_dev) { |
582 | platform_bus_create_devtree(pms, fdt, mpic); | |
f7087343 | 583 | } |
2fb513d3 | 584 | g_free(mpic); |
f7087343 | 585 | |
03f04809 | 586 | pmc->fixup_devtree(fdt); |
e6eaabeb SW |
587 | |
588 | if (toplevel_compat) { | |
5a4348d1 PC |
589 | qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, |
590 | strlen(toplevel_compat) + 1); | |
e6eaabeb SW |
591 | } |
592 | ||
d1b93565 | 593 | done: |
28290f37 | 594 | if (!dry_run) { |
5a4348d1 | 595 | qemu_fdt_dumpdtb(fdt, fdt_size); |
28290f37 | 596 | cpu_physical_memory_write(addr, fdt, fdt_size); |
cba2026a | 597 | } |
cba2026a | 598 | ret = fdt_size; |
b2fb7a43 | 599 | g_free(fdt); |
7ec632b4 | 600 | |
1db09b84 | 601 | out: |
347dd79d | 602 | g_free(pci_map); |
1db09b84 | 603 | |
04088adb | 604 | return ret; |
1db09b84 AJ |
605 | } |
606 | ||
28290f37 | 607 | typedef struct DeviceTreeParams { |
03f04809 | 608 | PPCE500MachineState *machine; |
28290f37 AG |
609 | hwaddr addr; |
610 | hwaddr initrd_base; | |
611 | hwaddr initrd_size; | |
903585de AG |
612 | hwaddr kernel_base; |
613 | hwaddr kernel_size; | |
f7087343 | 614 | Notifier notifier; |
28290f37 AG |
615 | } DeviceTreeParams; |
616 | ||
617 | static void ppce500_reset_device_tree(void *opaque) | |
618 | { | |
619 | DeviceTreeParams *p = opaque; | |
03f04809 | 620 | ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, |
903585de AG |
621 | p->initrd_size, p->kernel_base, p->kernel_size, |
622 | false); | |
28290f37 AG |
623 | } |
624 | ||
f7087343 AG |
625 | static void ppce500_init_notify(Notifier *notifier, void *data) |
626 | { | |
627 | DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); | |
628 | ppce500_reset_device_tree(p); | |
629 | } | |
630 | ||
03f04809 | 631 | static int ppce500_prep_device_tree(PPCE500MachineState *machine, |
28290f37 AG |
632 | hwaddr addr, |
633 | hwaddr initrd_base, | |
903585de AG |
634 | hwaddr initrd_size, |
635 | hwaddr kernel_base, | |
636 | hwaddr kernel_size) | |
28290f37 AG |
637 | { |
638 | DeviceTreeParams *p = g_new(DeviceTreeParams, 1); | |
3ef96221 | 639 | p->machine = machine; |
28290f37 AG |
640 | p->addr = addr; |
641 | p->initrd_base = initrd_base; | |
642 | p->initrd_size = initrd_size; | |
903585de AG |
643 | p->kernel_base = kernel_base; |
644 | p->kernel_size = kernel_size; | |
28290f37 AG |
645 | |
646 | qemu_register_reset(ppce500_reset_device_tree, p); | |
f7087343 AG |
647 | p->notifier.notify = ppce500_init_notify; |
648 | qemu_add_machine_init_done_notifier(&p->notifier); | |
28290f37 AG |
649 | |
650 | /* Issue the device tree loader once, so that we get the size of the blob */ | |
03f04809 IM |
651 | return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, |
652 | kernel_base, kernel_size, true); | |
28290f37 AG |
653 | } |
654 | ||
cba2026a | 655 | /* Create -kernel TLB entries for BookE. */ |
a36848ff | 656 | hwaddr booke206_page_size_to_tlb(uint64_t size) |
d1e256fe | 657 | { |
ab3dd749 | 658 | return 63 - clz64(size / KiB); |
d1e256fe AG |
659 | } |
660 | ||
cefd3cdb | 661 | static int booke206_initial_map_tsize(CPUPPCState *env) |
3b989d49 | 662 | { |
cba2026a | 663 | struct boot_info *bi = env->load_info; |
cefd3cdb | 664 | hwaddr dt_end; |
cba2026a AG |
665 | int ps; |
666 | ||
667 | /* Our initial TLB entry needs to cover everything from 0 to | |
668 | the device tree top */ | |
669 | dt_end = bi->dt_base + bi->dt_size; | |
670 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
fb37c302 AG |
671 | if (ps & 1) { |
672 | /* e500v2 can only do even TLB size bits */ | |
673 | ps++; | |
674 | } | |
cefd3cdb BB |
675 | return ps; |
676 | } | |
677 | ||
678 | static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) | |
679 | { | |
680 | int tsize; | |
681 | ||
682 | tsize = booke206_initial_map_tsize(env); | |
683 | return (1ULL << 10 << tsize); | |
684 | } | |
685 | ||
686 | static void mmubooke_create_initial_mapping(CPUPPCState *env) | |
687 | { | |
688 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); | |
689 | hwaddr size; | |
690 | int ps; | |
691 | ||
692 | ps = booke206_initial_map_tsize(env); | |
cba2026a | 693 | size = (ps << MAS1_TSIZE_SHIFT); |
d1e256fe | 694 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
695 | tlb->mas2 = 0; |
696 | tlb->mas7_3 = 0; | |
d1e256fe | 697 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
698 | |
699 | env->tlb_dirty = true; | |
3b989d49 AG |
700 | } |
701 | ||
b3305981 | 702 | static void ppce500_cpu_reset_sec(void *opaque) |
5c145dac | 703 | { |
38f92da6 | 704 | PowerPCCPU *cpu = opaque; |
259186a7 | 705 | CPUState *cs = CPU(cpu); |
5c145dac | 706 | |
259186a7 | 707 | cpu_reset(cs); |
5c145dac | 708 | |
27103424 | 709 | cs->exception_index = EXCP_HLT; |
3b989d49 AG |
710 | } |
711 | ||
b3305981 | 712 | static void ppce500_cpu_reset(void *opaque) |
3b989d49 | 713 | { |
38f92da6 | 714 | PowerPCCPU *cpu = opaque; |
259186a7 | 715 | CPUState *cs = CPU(cpu); |
38f92da6 | 716 | CPUPPCState *env = &cpu->env; |
3b989d49 AG |
717 | struct boot_info *bi = env->load_info; |
718 | ||
259186a7 | 719 | cpu_reset(cs); |
3b989d49 AG |
720 | |
721 | /* Set initial guest state. */ | |
259186a7 | 722 | cs->halted = 0; |
ab3dd749 | 723 | env->gpr[1] = (16 * MiB) - 8; |
3b989d49 | 724 | env->gpr[3] = bi->dt_base; |
cefd3cdb BB |
725 | env->gpr[4] = 0; |
726 | env->gpr[5] = 0; | |
727 | env->gpr[6] = EPAPR_MAGIC; | |
728 | env->gpr[7] = mmubooke_initial_mapsize(env); | |
729 | env->gpr[8] = 0; | |
730 | env->gpr[9] = 0; | |
3b989d49 | 731 | env->nip = bi->entry; |
cba2026a | 732 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
733 | } |
734 | ||
03f04809 | 735 | static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, |
2104d4f5 | 736 | IrqLines *irqs) |
82fc73b6 | 737 | { |
82fc73b6 SW |
738 | DeviceState *dev; |
739 | SysBusDevice *s; | |
740 | int i, j, k; | |
03f04809 | 741 | MachineState *machine = MACHINE(pms); |
fe6b6346 | 742 | unsigned int smp_cpus = machine->smp.cpus; |
03f04809 | 743 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
82fc73b6 | 744 | |
3e80f690 | 745 | dev = qdev_new(TYPE_OPENPIC); |
d2623129 | 746 | object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); |
03f04809 | 747 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
d85937e6 SW |
748 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); |
749 | ||
82fc73b6 | 750 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 751 | sysbus_realize_and_unref(s, &error_fatal); |
82fc73b6 SW |
752 | |
753 | k = 0; | |
754 | for (i = 0; i < smp_cpus; i++) { | |
755 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
2104d4f5 | 756 | sysbus_connect_irq(s, k++, irqs[i].irq[j]); |
82fc73b6 SW |
757 | } |
758 | } | |
759 | ||
d85937e6 SW |
760 | return dev; |
761 | } | |
762 | ||
03f04809 | 763 | static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, |
2104d4f5 | 764 | IrqLines *irqs, Error **errp) |
d85937e6 SW |
765 | { |
766 | DeviceState *dev; | |
d85937e6 | 767 | CPUState *cs; |
d85937e6 | 768 | |
3e80f690 | 769 | dev = qdev_new(TYPE_KVM_OPENPIC); |
03f04809 | 770 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
d85937e6 | 771 | |
668f62ec | 772 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { |
fe656ebd | 773 | object_unparent(OBJECT(dev)); |
d85937e6 SW |
774 | return NULL; |
775 | } | |
776 | ||
bdc44640 | 777 | CPU_FOREACH(cs) { |
d85937e6 SW |
778 | if (kvm_openpic_connect_vcpu(dev, cs)) { |
779 | fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", | |
780 | __func__); | |
781 | abort(); | |
782 | } | |
783 | } | |
784 | ||
785 | return dev; | |
786 | } | |
787 | ||
03f04809 | 788 | static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, |
c91c187f | 789 | MemoryRegion *ccsr, |
2104d4f5 | 790 | IrqLines *irqs) |
d85937e6 | 791 | { |
03f04809 | 792 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
d85937e6 SW |
793 | DeviceState *dev = NULL; |
794 | SysBusDevice *s; | |
d85937e6 SW |
795 | |
796 | if (kvm_enabled()) { | |
fe656ebd | 797 | Error *err = NULL; |
d85937e6 | 798 | |
4376c40d | 799 | if (kvm_kernel_irqchip_allowed()) { |
03f04809 | 800 | dev = ppce500_init_mpic_kvm(pmc, irqs, &err); |
d85937e6 | 801 | } |
4376c40d | 802 | if (kvm_kernel_irqchip_required() && !dev) { |
c29b77f9 MA |
803 | error_reportf_err(err, |
804 | "kernel_irqchip requested but unavailable: "); | |
fe656ebd | 805 | exit(1); |
d85937e6 SW |
806 | } |
807 | } | |
808 | ||
809 | if (!dev) { | |
03f04809 | 810 | dev = ppce500_init_mpic_qemu(pms, irqs); |
d85937e6 SW |
811 | } |
812 | ||
d85937e6 | 813 | s = SYS_BUS_DEVICE(dev); |
82fc73b6 SW |
814 | memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, |
815 | s->mmio[0].memory); | |
816 | ||
c91c187f | 817 | return dev; |
82fc73b6 SW |
818 | } |
819 | ||
016f7758 AG |
820 | static void ppce500_power_off(void *opaque, int line, int on) |
821 | { | |
822 | if (on) { | |
cf83f140 | 823 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
016f7758 AG |
824 | } |
825 | } | |
826 | ||
03f04809 | 827 | void ppce500_init(MachineState *machine) |
1db09b84 | 828 | { |
39186d8a | 829 | MemoryRegion *address_space_mem = get_system_memory(); |
03f04809 IM |
830 | PPCE500MachineState *pms = PPCE500_MACHINE(machine); |
831 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); | |
1db09b84 | 832 | PCIBus *pci_bus; |
e2684c0b | 833 | CPUPPCState *env = NULL; |
3812c71f AG |
834 | uint64_t loadaddr; |
835 | hwaddr kernel_base = -1LL; | |
836 | int kernel_size = 0; | |
837 | hwaddr dt_base = 0; | |
838 | hwaddr initrd_base = 0; | |
839 | int initrd_size = 0; | |
840 | hwaddr cur_base = 0; | |
841 | char *filename; | |
8d622594 DE |
842 | const char *payload_name; |
843 | bool kernel_as_payload; | |
3812c71f | 844 | hwaddr bios_entry = 0; |
8d622594 | 845 | target_long payload_size; |
3812c71f AG |
846 | struct boot_info *boot_info; |
847 | int dt_size; | |
82fc73b6 | 848 | int i; |
fe6b6346 | 849 | unsigned int smp_cpus = machine->smp.cpus; |
d575a6ce BB |
850 | /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and |
851 | * 4 respectively */ | |
852 | unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; | |
2104d4f5 | 853 | IrqLines *irqs; |
c91c187f | 854 | DeviceState *dev, *mpicdev; |
e2684c0b | 855 | CPUPPCState *firstenv = NULL; |
3eddc1be | 856 | MemoryRegion *ccsr_addr_space; |
dffb1dc2 | 857 | SysBusDevice *s; |
3eddc1be | 858 | PPCE500CCSRState *ccsr; |
7abb479c | 859 | I2CBus *i2c; |
1db09b84 | 860 | |
2104d4f5 | 861 | irqs = g_new0(IrqLines, smp_cpus); |
e61c36d5 | 862 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 863 | PowerPCCPU *cpu; |
55e5c285 | 864 | CPUState *cs; |
e61c36d5 | 865 | qemu_irq *input; |
397b457d | 866 | |
a2c93f06 | 867 | cpu = POWERPC_CPU(object_new(machine->cpu_type)); |
397b457d | 868 | env = &cpu->env; |
55e5c285 | 869 | cs = CPU(cpu); |
1db09b84 | 870 | |
00469dc3 | 871 | if (env->mmu_model != POWERPC_MMU_BOOKE206) { |
6f76b817 AF |
872 | error_report("MMU model %i not supported by this machine", |
873 | env->mmu_model); | |
00469dc3 VP |
874 | exit(1); |
875 | } | |
876 | ||
a2c93f06 TJB |
877 | /* |
878 | * Secondary CPU starts in halted state for now. Needs to change | |
879 | * when implementing non-kernel boot. | |
880 | */ | |
881 | object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, | |
882 | &error_fatal); | |
883 | qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); | |
884 | ||
e61c36d5 AG |
885 | if (!firstenv) { |
886 | firstenv = env; | |
887 | } | |
1db09b84 | 888 | |
a915249f | 889 | input = (qemu_irq *)env->irq_inputs; |
2104d4f5 GK |
890 | irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; |
891 | irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
6a450df9 | 892 | env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; |
03f04809 | 893 | env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; |
3b989d49 | 894 | |
0c36ab71 | 895 | ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); |
e61c36d5 AG |
896 | |
897 | /* Register reset handler */ | |
5c145dac AG |
898 | if (!i) { |
899 | /* Primary CPU */ | |
900 | struct boot_info *boot_info; | |
901 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
b3305981 | 902 | qemu_register_reset(ppce500_cpu_reset, cpu); |
5c145dac AG |
903 | env->load_info = boot_info; |
904 | } else { | |
905 | /* Secondary CPUs */ | |
b3305981 | 906 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
5c145dac | 907 | } |
e61c36d5 | 908 | } |
3b989d49 | 909 | |
e61c36d5 | 910 | env = firstenv; |
3b989d49 | 911 | |
3538e846 IM |
912 | if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { |
913 | error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); | |
914 | exit(EXIT_FAILURE); | |
915 | } | |
1db09b84 AJ |
916 | |
917 | /* Register Memory */ | |
97316645 | 918 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
1db09b84 | 919 | |
3e80f690 | 920 | dev = qdev_new("e500-ccsr"); |
3eddc1be | 921 | object_property_add_child(qdev_get_machine(), "e500-ccsr", |
d2623129 | 922 | OBJECT(dev)); |
3c6ef471 | 923 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
3eddc1be BB |
924 | ccsr = CCSR(dev); |
925 | ccsr_addr_space = &ccsr->ccsr_space; | |
03f04809 | 926 | memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, |
3eddc1be | 927 | ccsr_addr_space); |
dffb1dc2 | 928 | |
03f04809 | 929 | mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); |
ef0efa1a | 930 | g_free(irqs); |
d0b72631 | 931 | |
1db09b84 | 932 | /* Serial */ |
9bca0edb | 933 | if (serial_hd(0)) { |
3eddc1be | 934 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
c91c187f | 935 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
9bca0edb | 936 | serial_hd(0), DEVICE_BIG_ENDIAN); |
2d48377a | 937 | } |
1db09b84 | 938 | |
9bca0edb | 939 | if (serial_hd(1)) { |
3eddc1be | 940 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
c91c187f | 941 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
9bca0edb | 942 | serial_hd(1), DEVICE_BIG_ENDIAN); |
2d48377a | 943 | } |
7abb479c | 944 | /* I2C */ |
3e80f690 | 945 | dev = qdev_new("mpc-i2c"); |
7abb479c | 946 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 947 | sysbus_realize_and_unref(s, &error_fatal); |
7abb479c AR |
948 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); |
949 | memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, | |
950 | sysbus_mmio_get_region(s, 0)); | |
951 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | |
1373b15b | 952 | i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); |
7abb479c | 953 | |
1db09b84 | 954 | |
b0fb8423 | 955 | /* General Utility device */ |
3e80f690 | 956 | dev = qdev_new("mpc8544-guts"); |
dffb1dc2 | 957 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 958 | sysbus_realize_and_unref(s, &error_fatal); |
3eddc1be | 959 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
dffb1dc2 | 960 | sysbus_mmio_get_region(s, 0)); |
b0fb8423 | 961 | |
1db09b84 | 962 | /* PCI */ |
3e80f690 | 963 | dev = qdev_new("e500-pcihost"); |
d2623129 | 964 | object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); |
03f04809 | 965 | qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); |
3016dca0 | 966 | qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); |
dffb1dc2 | 967 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 968 | sysbus_realize_and_unref(s, &error_fatal); |
d575a6ce | 969 | for (i = 0; i < PCI_NUM_PINS; i++) { |
c91c187f | 970 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); |
d575a6ce BB |
971 | } |
972 | ||
3eddc1be | 973 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
dffb1dc2 BB |
974 | sysbus_mmio_get_region(s, 0)); |
975 | ||
d461e3b9 | 976 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
977 | if (!pci_bus) |
978 | printf("couldn't create PCI controller!\n"); | |
979 | ||
1db09b84 | 980 | if (pci_bus) { |
1db09b84 AJ |
981 | /* Register network interfaces. */ |
982 | for (i = 0; i < nb_nics; i++) { | |
52310c3f | 983 | pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); |
1db09b84 AJ |
984 | } |
985 | } | |
986 | ||
5c145dac | 987 | /* Register spinning region */ |
03f04809 | 988 | sysbus_create_simple("e500-spin", pmc->spin_base, NULL); |
5c145dac | 989 | |
03f04809 | 990 | if (pmc->has_mpc8xxx_gpio) { |
016f7758 AG |
991 | qemu_irq poweroff_irq; |
992 | ||
3e80f690 | 993 | dev = qdev_new("mpc8xxx_gpio"); |
b88e77f4 | 994 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 995 | sysbus_realize_and_unref(s, &error_fatal); |
c91c187f | 996 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); |
b88e77f4 AG |
997 | memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, |
998 | sysbus_mmio_get_region(s, 0)); | |
016f7758 AG |
999 | |
1000 | /* Power Off GPIO at Pin 0 */ | |
1001 | poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); | |
1002 | qdev_connect_gpio_out(dev, 0, poweroff_irq); | |
b88e77f4 AG |
1003 | } |
1004 | ||
f7087343 | 1005 | /* Platform Bus Device */ |
03f04809 | 1006 | if (pmc->has_platform_bus) { |
3e80f690 | 1007 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
f7087343 | 1008 | dev->id = TYPE_PLATFORM_BUS_DEVICE; |
03f04809 IM |
1009 | qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); |
1010 | qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); | |
3c6ef471 | 1011 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
a3fc8396 | 1012 | pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); |
f7087343 | 1013 | |
a3fc8396 | 1014 | s = SYS_BUS_DEVICE(pms->pbus_dev); |
03f04809 IM |
1015 | for (i = 0; i < pmc->platform_bus_num_irqs; i++) { |
1016 | int irqn = pmc->platform_bus_first_irq + i; | |
c91c187f | 1017 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); |
f7087343 AG |
1018 | } |
1019 | ||
1020 | memory_region_add_subregion(address_space_mem, | |
03f04809 | 1021 | pmc->platform_bus_base, |
f7087343 AG |
1022 | sysbus_mmio_get_region(s, 0)); |
1023 | } | |
1024 | ||
8d622594 DE |
1025 | /* |
1026 | * Smart firmware defaults ahead! | |
1027 | * | |
1028 | * We follow the following table to select which payload we execute. | |
1029 | * | |
1030 | * -kernel | -bios | payload | |
1031 | * ---------+-------+--------- | |
1032 | * N | Y | u-boot | |
1033 | * N | N | u-boot | |
1034 | * Y | Y | u-boot | |
1035 | * Y | N | kernel | |
1036 | * | |
1037 | * This ensures backwards compatibility with how we used to expose | |
1038 | * -kernel to users but allows them to run through u-boot as well. | |
1039 | */ | |
1040 | kernel_as_payload = false; | |
cd7b9498 | 1041 | if (machine->firmware == NULL) { |
8d622594 DE |
1042 | if (machine->kernel_filename) { |
1043 | payload_name = machine->kernel_filename; | |
1044 | kernel_as_payload = true; | |
1045 | } else { | |
1046 | payload_name = "u-boot.e500"; | |
1047 | } | |
1048 | } else { | |
cd7b9498 | 1049 | payload_name = machine->firmware; |
8d622594 DE |
1050 | } |
1051 | ||
1052 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); | |
3b4f50bd PM |
1053 | if (!filename) { |
1054 | error_report("could not find firmware/kernel file '%s'", payload_name); | |
1055 | exit(1); | |
1056 | } | |
8d622594 | 1057 | |
4366e1db | 1058 | payload_size = load_elf(filename, NULL, NULL, NULL, |
6cdda0ff | 1059 | &bios_entry, &loadaddr, NULL, NULL, |
8d622594 DE |
1060 | 1, PPC_ELF_MACHINE, 0, 0); |
1061 | if (payload_size < 0) { | |
1062 | /* | |
1063 | * Hrm. No ELF image? Try a uImage, maybe someone is giving us an | |
1064 | * ePAPR compliant kernel | |
1065 | */ | |
f831f955 | 1066 | loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
8d622594 DE |
1067 | payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, |
1068 | NULL, NULL); | |
1069 | if (payload_size < 0) { | |
371b74e2 | 1070 | error_report("could not load firmware '%s'", filename); |
8d622594 DE |
1071 | exit(1); |
1072 | } | |
1073 | } | |
1074 | ||
1075 | g_free(filename); | |
1076 | ||
1077 | if (kernel_as_payload) { | |
1078 | kernel_base = loadaddr; | |
1079 | kernel_size = payload_size; | |
1080 | } | |
1081 | ||
1082 | cur_base = loadaddr + payload_size; | |
ab3dd749 | 1083 | if (cur_base < 32 * MiB) { |
b4a5f24a | 1084 | /* u-boot occupies memory up to 32MB, so load blobs above */ |
ab3dd749 | 1085 | cur_base = 32 * MiB; |
b4a5f24a | 1086 | } |
8d622594 DE |
1087 | |
1088 | /* Load bare kernel only if no bios/u-boot has been provided */ | |
1089 | if (machine->kernel_filename && !kernel_as_payload) { | |
3812c71f AG |
1090 | kernel_base = cur_base; |
1091 | kernel_size = load_image_targphys(machine->kernel_filename, | |
1092 | cur_base, | |
3538e846 | 1093 | machine->ram_size - cur_base); |
1db09b84 | 1094 | if (kernel_size < 0) { |
6f76b817 AF |
1095 | error_report("could not load kernel '%s'", |
1096 | machine->kernel_filename); | |
1db09b84 AJ |
1097 | exit(1); |
1098 | } | |
528e536e | 1099 | |
3812c71f | 1100 | cur_base += kernel_size; |
1db09b84 AJ |
1101 | } |
1102 | ||
1103 | /* Load initrd. */ | |
3ef96221 | 1104 | if (machine->initrd_filename) { |
528e536e | 1105 | initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
3ef96221 | 1106 | initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, |
3538e846 | 1107 | machine->ram_size - initrd_base); |
1db09b84 AJ |
1108 | |
1109 | if (initrd_size < 0) { | |
6f76b817 AF |
1110 | error_report("could not load initial ram disk '%s'", |
1111 | machine->initrd_filename); | |
1db09b84 AJ |
1112 | exit(1); |
1113 | } | |
528e536e AG |
1114 | |
1115 | cur_base = initrd_base + initrd_size; | |
1db09b84 AJ |
1116 | } |
1117 | ||
3812c71f | 1118 | /* |
8d622594 DE |
1119 | * Reserve space for dtb behind the kernel image because Linux has a bug |
1120 | * where it can only handle the dtb if it's within the first 64MB of where | |
1121 | * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD | |
1122 | * ensures enough space between kernel and initrd. | |
3812c71f | 1123 | */ |
8d622594 | 1124 | dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
3538e846 | 1125 | if (dt_base + DTB_MAX_SIZE > machine->ram_size) { |
371b74e2 | 1126 | error_report("not enough memory for device tree"); |
1db09b84 | 1127 | exit(1); |
3812c71f | 1128 | } |
1db09b84 | 1129 | |
03f04809 | 1130 | dt_size = ppce500_prep_device_tree(pms, dt_base, |
3812c71f AG |
1131 | initrd_base, initrd_size, |
1132 | kernel_base, kernel_size); | |
1133 | if (dt_size < 0) { | |
6f76b817 | 1134 | error_report("couldn't load device tree"); |
3812c71f | 1135 | exit(1); |
1db09b84 | 1136 | } |
3812c71f AG |
1137 | assert(dt_size < DTB_MAX_SIZE); |
1138 | ||
1139 | boot_info = env->load_info; | |
1140 | boot_info->entry = bios_entry; | |
1141 | boot_info->dt_base = dt_base; | |
1142 | boot_info->dt_size = dt_size; | |
1db09b84 | 1143 | } |
3eddc1be | 1144 | |
d0c2b0d0 | 1145 | static void e500_ccsr_initfn(Object *obj) |
3eddc1be | 1146 | { |
d0c2b0d0 XZ |
1147 | PPCE500CCSRState *ccsr = CCSR(obj); |
1148 | memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", | |
3eddc1be | 1149 | MPC8544_CCSRBAR_SIZE); |
3eddc1be BB |
1150 | } |
1151 | ||
1152 | static const TypeInfo e500_ccsr_info = { | |
1153 | .name = TYPE_CCSR, | |
1154 | .parent = TYPE_SYS_BUS_DEVICE, | |
1155 | .instance_size = sizeof(PPCE500CCSRState), | |
d0c2b0d0 | 1156 | .instance_init = e500_ccsr_initfn, |
3eddc1be BB |
1157 | }; |
1158 | ||
03f04809 IM |
1159 | static const TypeInfo ppce500_info = { |
1160 | .name = TYPE_PPCE500_MACHINE, | |
1161 | .parent = TYPE_MACHINE, | |
1162 | .abstract = true, | |
a3fc8396 | 1163 | .instance_size = sizeof(PPCE500MachineState), |
03f04809 IM |
1164 | .class_size = sizeof(PPCE500MachineClass), |
1165 | }; | |
1166 | ||
3eddc1be BB |
1167 | static void e500_register_types(void) |
1168 | { | |
1169 | type_register_static(&e500_ccsr_info); | |
03f04809 | 1170 | type_register_static(&ppce500_info); |
3eddc1be BB |
1171 | } |
1172 | ||
1173 | type_init(e500_register_types) |