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Commit | Line | Data |
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1db09b84 | 1 | /* |
b3305981 | 2 | * QEMU PowerPC e500-based platforms |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
1db09b84 AJ |
17 | #include "config.h" |
18 | #include "qemu-common.h" | |
e6eaabeb | 19 | #include "e500.h" |
3eddc1be | 20 | #include "e500-ccsr.h" |
1422e32d | 21 | #include "net/net.h" |
1de7afc9 | 22 | #include "qemu/config-file.h" |
4a18e7c9 | 23 | #include "hw/hw.h" |
0d09e41a | 24 | #include "hw/char/serial.h" |
a2cb15b0 | 25 | #include "hw/pci/pci.h" |
4a18e7c9 | 26 | #include "hw/boards.h" |
9c17d615 PB |
27 | #include "sysemu/sysemu.h" |
28 | #include "sysemu/kvm.h" | |
1db09b84 | 29 | #include "kvm_ppc.h" |
9c17d615 | 30 | #include "sysemu/device_tree.h" |
0d09e41a PB |
31 | #include "hw/ppc/openpic.h" |
32 | #include "hw/ppc/ppc.h" | |
4a18e7c9 | 33 | #include "hw/loader.h" |
ca20cf32 | 34 | #include "elf.h" |
4a18e7c9 | 35 | #include "hw/sysbus.h" |
022c62cb | 36 | #include "exec/address-spaces.h" |
1de7afc9 | 37 | #include "qemu/host-utils.h" |
0d09e41a | 38 | #include "hw/pci-host/ppce500.h" |
1db09b84 | 39 | |
cefd3cdb | 40 | #define EPAPR_MAGIC (0x45504150) |
1db09b84 AJ |
41 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
42 | #define UIMAGE_LOAD_BASE 0 | |
9dd5eba1 | 43 | #define DTC_LOAD_PAD 0x1800000 |
75bb6589 | 44 | #define DTC_PAD_MASK 0xFFFFF |
b8dec144 | 45 | #define DTB_MAX_SIZE (8 * 1024 * 1024) |
75bb6589 LY |
46 | #define INITRD_LOAD_PAD 0x2000000 |
47 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
48 | |
49 | #define RAM_SIZES_ALIGN (64UL << 20) | |
50 | ||
b3305981 | 51 | /* TODO: parameterize */ |
ed2bc496 AG |
52 | #define MPC8544_CCSRBAR_BASE 0xE0000000ULL |
53 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL | |
dffb1dc2 | 54 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
a911b7a9 | 55 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
dffb1dc2 BB |
56 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
57 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL | |
58 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL | |
59 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ | |
60 | MPC8544_PCI_REGS_OFFSET) | |
ed2bc496 AG |
61 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
62 | #define MPC8544_PCI_IO 0xE1000000ULL | |
dffb1dc2 | 63 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
ed2bc496 | 64 | #define MPC8544_SPIN_BASE 0xEF000000ULL |
1db09b84 | 65 | |
3b989d49 AG |
66 | struct boot_info |
67 | { | |
68 | uint32_t dt_base; | |
cba2026a | 69 | uint32_t dt_size; |
3b989d49 AG |
70 | uint32_t entry; |
71 | }; | |
72 | ||
347dd79d AG |
73 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
74 | int nr_slots, int *len) | |
0dbc0798 | 75 | { |
347dd79d AG |
76 | int i = 0; |
77 | int slot; | |
78 | int pci_irq; | |
9e2c1298 | 79 | int host_irq; |
347dd79d AG |
80 | int last_slot = first_slot + nr_slots; |
81 | uint32_t *pci_map; | |
82 | ||
83 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); | |
84 | pci_map = g_malloc(*len); | |
85 | ||
86 | for (slot = first_slot; slot < last_slot; slot++) { | |
87 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { | |
88 | pci_map[i++] = cpu_to_be32(slot << 11); | |
89 | pci_map[i++] = cpu_to_be32(0x0); | |
90 | pci_map[i++] = cpu_to_be32(0x0); | |
91 | pci_map[i++] = cpu_to_be32(pci_irq + 1); | |
92 | pci_map[i++] = cpu_to_be32(mpic); | |
9e2c1298 AG |
93 | host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
94 | pci_map[i++] = cpu_to_be32(host_irq + 1); | |
347dd79d AG |
95 | pci_map[i++] = cpu_to_be32(0x1); |
96 | } | |
0dbc0798 | 97 | } |
347dd79d AG |
98 | |
99 | assert((i * sizeof(uint32_t)) == *len); | |
100 | ||
101 | return pci_map; | |
0dbc0798 AG |
102 | } |
103 | ||
a053a7ce AG |
104 | static void dt_serial_create(void *fdt, unsigned long long offset, |
105 | const char *soc, const char *mpic, | |
106 | const char *alias, int idx, bool defcon) | |
107 | { | |
108 | char ser[128]; | |
109 | ||
110 | snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); | |
111 | qemu_devtree_add_subnode(fdt, ser); | |
112 | qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); | |
113 | qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); | |
114 | qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); | |
115 | qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); | |
116 | qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); | |
7e99826c | 117 | qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); |
a053a7ce AG |
118 | qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); |
119 | qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); | |
120 | ||
121 | if (defcon) { | |
122 | qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); | |
123 | } | |
124 | } | |
125 | ||
b3305981 | 126 | static int ppce500_load_device_tree(CPUPPCState *env, |
e6eaabeb | 127 | PPCE500Params *params, |
a8170e5e AK |
128 | hwaddr addr, |
129 | hwaddr initrd_base, | |
130 | hwaddr initrd_size) | |
1db09b84 | 131 | { |
dbf916d8 | 132 | int ret = -1; |
e6eaabeb | 133 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; |
7ec632b4 | 134 | int fdt_size; |
dbf916d8 | 135 | void *fdt; |
5de6b46d | 136 | uint8_t hypercall[16]; |
911d6e7a AG |
137 | uint32_t clock_freq = 400000000; |
138 | uint32_t tb_freq = 400000000; | |
621d05e3 | 139 | int i; |
ebb9518a | 140 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
5da96624 | 141 | char soc[128]; |
19ac9dea AG |
142 | char mpic[128]; |
143 | uint32_t mpic_ph; | |
a911b7a9 | 144 | uint32_t msi_ph; |
f5038483 | 145 | char gutil[128]; |
0dbc0798 | 146 | char pci[128]; |
a911b7a9 | 147 | char msi[128]; |
347dd79d AG |
148 | uint32_t *pci_map = NULL; |
149 | int len; | |
3627757e AG |
150 | uint32_t pci_ranges[14] = |
151 | { | |
152 | 0x2000000, 0x0, 0xc0000000, | |
153 | 0x0, 0xc0000000, | |
154 | 0x0, 0x20000000, | |
155 | ||
156 | 0x1000000, 0x0, 0x0, | |
157 | 0x0, 0xe1000000, | |
158 | 0x0, 0x10000, | |
159 | }; | |
2ff3de68 MA |
160 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
161 | const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); | |
162 | const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); | |
d1b93565 AG |
163 | |
164 | if (dtb_file) { | |
165 | char *filename; | |
166 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); | |
167 | if (!filename) { | |
168 | goto out; | |
169 | } | |
170 | ||
171 | fdt = load_device_tree(filename, &fdt_size); | |
172 | if (!fdt) { | |
173 | goto out; | |
174 | } | |
175 | goto done; | |
176 | } | |
1db09b84 | 177 | |
2636fcb6 | 178 | fdt = create_device_tree(&fdt_size); |
5cea8590 PB |
179 | if (fdt == NULL) { |
180 | goto out; | |
181 | } | |
1db09b84 AJ |
182 | |
183 | /* Manipulate device tree in memory. */ | |
3627757e AG |
184 | qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); |
185 | qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); | |
51b852b7 | 186 | |
dd0bcfca AG |
187 | qemu_devtree_add_subnode(fdt, "/memory"); |
188 | qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); | |
189 | qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
190 | sizeof(mem_reg_property)); | |
1db09b84 | 191 | |
f5231aaf | 192 | qemu_devtree_add_subnode(fdt, "/chosen"); |
3b989d49 AG |
193 | if (initrd_size) { |
194 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
195 | initrd_base); | |
196 | if (ret < 0) { | |
197 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
198 | } | |
1db09b84 | 199 | |
3b989d49 AG |
200 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
201 | (initrd_base + initrd_size)); | |
202 | if (ret < 0) { | |
203 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
204 | } | |
205 | } | |
1db09b84 AJ |
206 | |
207 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
e6eaabeb | 208 | params->kernel_cmdline); |
1db09b84 AJ |
209 | if (ret < 0) |
210 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
211 | ||
212 | if (kvm_enabled()) { | |
911d6e7a AG |
213 | /* Read out host's frequencies */ |
214 | clock_freq = kvmppc_get_clockfreq(); | |
215 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
216 | |
217 | /* indicate KVM hypercall interface */ | |
d50f71a5 | 218 | qemu_devtree_add_subnode(fdt, "/hypervisor"); |
5de6b46d AG |
219 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", |
220 | "linux,kvm"); | |
221 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
222 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
223 | hypercall, sizeof(hypercall)); | |
1a61a9ae SY |
224 | /* if KVM supports the idle hcall, set property indicating this */ |
225 | if (kvmppc_get_hasidle(env)) { | |
226 | qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); | |
227 | } | |
1db09b84 | 228 | } |
3b989d49 | 229 | |
625e665b AG |
230 | /* Create CPU nodes */ |
231 | qemu_devtree_add_subnode(fdt, "/cpus"); | |
232 | qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
233 | qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
234 | ||
1e3debf0 AG |
235 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
236 | the first node as boot node and be happy */ | |
237 | for (i = smp_cpus - 1; i >= 0; i--) { | |
440c8152 | 238 | CPUState *cpu; |
621d05e3 | 239 | char cpu_name[128]; |
1d2e5c52 | 240 | uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); |
10f25a46 | 241 | |
440c8152 | 242 | cpu = qemu_get_cpu(i); |
55e5c285 | 243 | if (cpu == NULL) { |
1e3debf0 AG |
244 | continue; |
245 | } | |
440c8152 | 246 | env = cpu->env_ptr; |
1e3debf0 | 247 | |
55e5c285 AF |
248 | snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", |
249 | cpu->cpu_index); | |
1e3debf0 | 250 | qemu_devtree_add_subnode(fdt, cpu_name); |
621d05e3 AG |
251 | qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); |
252 | qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
1e3debf0 | 253 | qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); |
55e5c285 | 254 | qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index); |
1e3debf0 AG |
255 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", |
256 | env->dcache_line_size); | |
257 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
258 | env->icache_line_size); | |
259 | qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
260 | qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
261 | qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
55e5c285 | 262 | if (cpu->cpu_index) { |
1e3debf0 AG |
263 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); |
264 | qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); | |
1d2e5c52 AG |
265 | qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", |
266 | cpu_release_addr); | |
1e3debf0 AG |
267 | } else { |
268 | qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); | |
269 | } | |
1db09b84 AJ |
270 | } |
271 | ||
0cfc6e8d | 272 | qemu_devtree_add_subnode(fdt, "/aliases"); |
5da96624 | 273 | /* XXX These should go into their respective devices' code */ |
ed2bc496 | 274 | snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); |
5da96624 AG |
275 | qemu_devtree_add_subnode(fdt, soc); |
276 | qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); | |
ebb9518a AG |
277 | qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, |
278 | sizeof(compatible_sb)); | |
5da96624 AG |
279 | qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); |
280 | qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); | |
3627757e AG |
281 | qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, |
282 | MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, | |
5da96624 | 283 | MPC8544_CCSRBAR_SIZE); |
5da96624 AG |
284 | /* XXX should contain a reasonable value */ |
285 | qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); | |
286 | ||
dffb1dc2 | 287 | snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
19ac9dea AG |
288 | qemu_devtree_add_subnode(fdt, mpic); |
289 | qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); | |
f5fba9d2 | 290 | qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); |
dffb1dc2 BB |
291 | qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, |
292 | 0x40000); | |
19ac9dea | 293 | qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); |
7e99826c | 294 | qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); |
19ac9dea AG |
295 | mpic_ph = qemu_devtree_alloc_phandle(fdt); |
296 | qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); | |
297 | qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); | |
298 | qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); | |
299 | ||
0cfc6e8d AG |
300 | /* |
301 | * We have to generate ser1 first, because Linux takes the first | |
302 | * device it finds in the dt as serial output device. And we generate | |
303 | * devices in reverse order to the dt. | |
304 | */ | |
dffb1dc2 | 305 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
a053a7ce | 306 | soc, mpic, "serial1", 1, false); |
dffb1dc2 | 307 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
a053a7ce | 308 | soc, mpic, "serial0", 0, true); |
0cfc6e8d | 309 | |
ed2bc496 | 310 | snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, |
dffb1dc2 | 311 | MPC8544_UTIL_OFFSET); |
f5038483 AG |
312 | qemu_devtree_add_subnode(fdt, gutil); |
313 | qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); | |
dffb1dc2 | 314 | qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); |
f5038483 AG |
315 | qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); |
316 | ||
a911b7a9 AG |
317 | snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
318 | qemu_devtree_add_subnode(fdt, msi); | |
319 | qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); | |
320 | qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); | |
321 | msi_ph = qemu_devtree_alloc_phandle(fdt); | |
322 | qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); | |
323 | qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); | |
324 | qemu_devtree_setprop_cells(fdt, msi, "interrupts", | |
325 | 0xe0, 0x0, | |
326 | 0xe1, 0x0, | |
327 | 0xe2, 0x0, | |
328 | 0xe3, 0x0, | |
329 | 0xe4, 0x0, | |
330 | 0xe5, 0x0, | |
331 | 0xe6, 0x0, | |
332 | 0xe7, 0x0); | |
333 | qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); | |
334 | qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); | |
335 | ||
ed2bc496 | 336 | snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); |
0dbc0798 AG |
337 | qemu_devtree_add_subnode(fdt, pci); |
338 | qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); | |
339 | qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); | |
340 | qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); | |
341 | qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, | |
342 | 0x0, 0x7); | |
347dd79d | 343 | pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), |
492ec48d AG |
344 | params->pci_first_slot, params->pci_nr_slots, |
345 | &len); | |
347dd79d | 346 | qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); |
0dbc0798 | 347 | qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); |
7e99826c | 348 | qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); |
0dbc0798 | 349 | qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); |
3627757e | 350 | for (i = 0; i < 14; i++) { |
0dbc0798 AG |
351 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
352 | } | |
a911b7a9 | 353 | qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
0dbc0798 | 354 | qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); |
3627757e AG |
355 | qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, |
356 | MPC8544_PCI_REGS_BASE, 0, 0x1000); | |
0dbc0798 AG |
357 | qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
358 | qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); | |
359 | qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); | |
360 | qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); | |
361 | qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); | |
362 | ||
e6eaabeb SW |
363 | params->fixup_devtree(params, fdt); |
364 | ||
365 | if (toplevel_compat) { | |
366 | qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, | |
367 | strlen(toplevel_compat) + 1); | |
368 | } | |
369 | ||
d1b93565 | 370 | done: |
71193433 | 371 | qemu_devtree_dumpdtb(fdt, fdt_size); |
04088adb | 372 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
cba2026a AG |
373 | if (ret < 0) { |
374 | goto out; | |
375 | } | |
7267c094 | 376 | g_free(fdt); |
cba2026a | 377 | ret = fdt_size; |
7ec632b4 | 378 | |
1db09b84 | 379 | out: |
347dd79d | 380 | g_free(pci_map); |
1db09b84 | 381 | |
04088adb | 382 | return ret; |
1db09b84 AJ |
383 | } |
384 | ||
cba2026a | 385 | /* Create -kernel TLB entries for BookE. */ |
a8170e5e | 386 | static inline hwaddr booke206_page_size_to_tlb(uint64_t size) |
d1e256fe | 387 | { |
cba2026a | 388 | return 63 - clz64(size >> 10); |
d1e256fe AG |
389 | } |
390 | ||
cefd3cdb | 391 | static int booke206_initial_map_tsize(CPUPPCState *env) |
3b989d49 | 392 | { |
cba2026a | 393 | struct boot_info *bi = env->load_info; |
cefd3cdb | 394 | hwaddr dt_end; |
cba2026a AG |
395 | int ps; |
396 | ||
397 | /* Our initial TLB entry needs to cover everything from 0 to | |
398 | the device tree top */ | |
399 | dt_end = bi->dt_base + bi->dt_size; | |
400 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
fb37c302 AG |
401 | if (ps & 1) { |
402 | /* e500v2 can only do even TLB size bits */ | |
403 | ps++; | |
404 | } | |
cefd3cdb BB |
405 | return ps; |
406 | } | |
407 | ||
408 | static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) | |
409 | { | |
410 | int tsize; | |
411 | ||
412 | tsize = booke206_initial_map_tsize(env); | |
413 | return (1ULL << 10 << tsize); | |
414 | } | |
415 | ||
416 | static void mmubooke_create_initial_mapping(CPUPPCState *env) | |
417 | { | |
418 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); | |
419 | hwaddr size; | |
420 | int ps; | |
421 | ||
422 | ps = booke206_initial_map_tsize(env); | |
cba2026a | 423 | size = (ps << MAS1_TSIZE_SHIFT); |
d1e256fe | 424 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
425 | tlb->mas2 = 0; |
426 | tlb->mas7_3 = 0; | |
d1e256fe | 427 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
428 | |
429 | env->tlb_dirty = true; | |
3b989d49 AG |
430 | } |
431 | ||
b3305981 | 432 | static void ppce500_cpu_reset_sec(void *opaque) |
5c145dac | 433 | { |
38f92da6 | 434 | PowerPCCPU *cpu = opaque; |
259186a7 | 435 | CPUState *cs = CPU(cpu); |
38f92da6 | 436 | CPUPPCState *env = &cpu->env; |
5c145dac | 437 | |
259186a7 | 438 | cpu_reset(cs); |
5c145dac AG |
439 | |
440 | /* Secondary CPU starts in halted state for now. Needs to change when | |
441 | implementing non-kernel boot. */ | |
259186a7 | 442 | cs->halted = 1; |
5c145dac | 443 | env->exception_index = EXCP_HLT; |
3b989d49 AG |
444 | } |
445 | ||
b3305981 | 446 | static void ppce500_cpu_reset(void *opaque) |
3b989d49 | 447 | { |
38f92da6 | 448 | PowerPCCPU *cpu = opaque; |
259186a7 | 449 | CPUState *cs = CPU(cpu); |
38f92da6 | 450 | CPUPPCState *env = &cpu->env; |
3b989d49 AG |
451 | struct boot_info *bi = env->load_info; |
452 | ||
259186a7 | 453 | cpu_reset(cs); |
3b989d49 AG |
454 | |
455 | /* Set initial guest state. */ | |
259186a7 | 456 | cs->halted = 0; |
3b989d49 AG |
457 | env->gpr[1] = (16<<20) - 8; |
458 | env->gpr[3] = bi->dt_base; | |
cefd3cdb BB |
459 | env->gpr[4] = 0; |
460 | env->gpr[5] = 0; | |
461 | env->gpr[6] = EPAPR_MAGIC; | |
462 | env->gpr[7] = mmubooke_initial_mapsize(env); | |
463 | env->gpr[8] = 0; | |
464 | env->gpr[9] = 0; | |
3b989d49 | 465 | env->nip = bi->entry; |
cba2026a | 466 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
467 | } |
468 | ||
d85937e6 SW |
469 | static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, |
470 | qemu_irq **irqs) | |
82fc73b6 | 471 | { |
82fc73b6 SW |
472 | DeviceState *dev; |
473 | SysBusDevice *s; | |
474 | int i, j, k; | |
475 | ||
e1766344 | 476 | dev = qdev_create(NULL, TYPE_OPENPIC); |
82fc73b6 | 477 | qdev_prop_set_uint32(dev, "model", params->mpic_version); |
d85937e6 SW |
478 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); |
479 | ||
82fc73b6 SW |
480 | qdev_init_nofail(dev); |
481 | s = SYS_BUS_DEVICE(dev); | |
482 | ||
483 | k = 0; | |
484 | for (i = 0; i < smp_cpus; i++) { | |
485 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
486 | sysbus_connect_irq(s, k++, irqs[i][j]); | |
487 | } | |
488 | } | |
489 | ||
d85937e6 SW |
490 | return dev; |
491 | } | |
492 | ||
493 | static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, | |
494 | qemu_irq **irqs) | |
495 | { | |
496 | DeviceState *dev; | |
497 | CPUPPCState *env; | |
498 | CPUState *cs; | |
499 | int r; | |
500 | ||
dd49c038 | 501 | dev = qdev_create(NULL, TYPE_KVM_OPENPIC); |
d85937e6 SW |
502 | qdev_prop_set_uint32(dev, "model", params->mpic_version); |
503 | ||
504 | r = qdev_init(dev); | |
505 | if (r) { | |
506 | return NULL; | |
507 | } | |
508 | ||
509 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
510 | cs = ENV_GET_CPU(env); | |
511 | ||
512 | if (kvm_openpic_connect_vcpu(dev, cs)) { | |
513 | fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", | |
514 | __func__); | |
515 | abort(); | |
516 | } | |
517 | } | |
518 | ||
519 | return dev; | |
520 | } | |
521 | ||
522 | static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr, | |
523 | qemu_irq **irqs) | |
524 | { | |
d85937e6 SW |
525 | qemu_irq *mpic; |
526 | DeviceState *dev = NULL; | |
527 | SysBusDevice *s; | |
528 | int i; | |
529 | ||
530 | mpic = g_new(qemu_irq, 256); | |
531 | ||
532 | if (kvm_enabled()) { | |
36ad0e94 MA |
533 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
534 | bool irqchip_allowed = qemu_opt_get_bool(machine_opts, | |
d85937e6 | 535 | "kernel_irqchip", true); |
36ad0e94 MA |
536 | bool irqchip_required = qemu_opt_get_bool(machine_opts, |
537 | "kernel_irqchip", false); | |
d85937e6 SW |
538 | |
539 | if (irqchip_allowed) { | |
540 | dev = ppce500_init_mpic_kvm(params, irqs); | |
541 | } | |
542 | ||
543 | if (irqchip_required && !dev) { | |
544 | fprintf(stderr, "%s: irqchip requested but unavailable\n", | |
545 | __func__); | |
546 | abort(); | |
547 | } | |
548 | } | |
549 | ||
550 | if (!dev) { | |
551 | dev = ppce500_init_mpic_qemu(params, irqs); | |
552 | } | |
553 | ||
82fc73b6 SW |
554 | for (i = 0; i < 256; i++) { |
555 | mpic[i] = qdev_get_gpio_in(dev, i); | |
556 | } | |
557 | ||
d85937e6 | 558 | s = SYS_BUS_DEVICE(dev); |
82fc73b6 SW |
559 | memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, |
560 | s->mmio[0].memory); | |
561 | ||
562 | return mpic; | |
563 | } | |
564 | ||
e6eaabeb | 565 | void ppce500_init(PPCE500Params *params) |
1db09b84 | 566 | { |
39186d8a | 567 | MemoryRegion *address_space_mem = get_system_memory(); |
2646c133 | 568 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
1db09b84 | 569 | PCIBus *pci_bus; |
e2684c0b | 570 | CPUPPCState *env = NULL; |
1db09b84 AJ |
571 | uint64_t elf_entry; |
572 | uint64_t elf_lowaddr; | |
a8170e5e AK |
573 | hwaddr entry=0; |
574 | hwaddr loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 575 | target_long kernel_size=0; |
75bb6589 LY |
576 | target_ulong dt_base = 0; |
577 | target_ulong initrd_base = 0; | |
528e536e AG |
578 | target_long initrd_size = 0; |
579 | target_ulong cur_base = 0; | |
82fc73b6 | 580 | int i; |
1db09b84 | 581 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
a915249f | 582 | qemu_irq **irqs, *mpic; |
be13cc7a | 583 | DeviceState *dev; |
e2684c0b | 584 | CPUPPCState *firstenv = NULL; |
3eddc1be | 585 | MemoryRegion *ccsr_addr_space; |
dffb1dc2 | 586 | SysBusDevice *s; |
3eddc1be | 587 | PPCE500CCSRState *ccsr; |
1db09b84 | 588 | |
e61c36d5 | 589 | /* Setup CPUs */ |
e6eaabeb SW |
590 | if (params->cpu_model == NULL) { |
591 | params->cpu_model = "e500v2_v30"; | |
ef250db6 AG |
592 | } |
593 | ||
a915249f AG |
594 | irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
595 | irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
e61c36d5 | 596 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 597 | PowerPCCPU *cpu; |
55e5c285 | 598 | CPUState *cs; |
e61c36d5 | 599 | qemu_irq *input; |
397b457d | 600 | |
e6eaabeb | 601 | cpu = cpu_ppc_init(params->cpu_model); |
397b457d | 602 | if (cpu == NULL) { |
e61c36d5 AG |
603 | fprintf(stderr, "Unable to initialize CPU!\n"); |
604 | exit(1); | |
605 | } | |
397b457d | 606 | env = &cpu->env; |
55e5c285 | 607 | cs = CPU(cpu); |
1db09b84 | 608 | |
e61c36d5 AG |
609 | if (!firstenv) { |
610 | firstenv = env; | |
611 | } | |
1db09b84 | 612 | |
a915249f AG |
613 | irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); |
614 | input = (qemu_irq *)env->irq_inputs; | |
615 | irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; | |
616 | irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
55e5c285 | 617 | env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; |
68c2dd70 | 618 | env->mpic_iack = MPC8544_CCSRBAR_BASE + |
bd25922e | 619 | MPC8544_MPIC_REGS_OFFSET + 0xa0; |
3b989d49 | 620 | |
a34a92b9 | 621 | ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
622 | |
623 | /* Register reset handler */ | |
5c145dac AG |
624 | if (!i) { |
625 | /* Primary CPU */ | |
626 | struct boot_info *boot_info; | |
627 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
b3305981 | 628 | qemu_register_reset(ppce500_cpu_reset, cpu); |
5c145dac AG |
629 | env->load_info = boot_info; |
630 | } else { | |
631 | /* Secondary CPUs */ | |
b3305981 | 632 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
5c145dac | 633 | } |
e61c36d5 | 634 | } |
3b989d49 | 635 | |
e61c36d5 | 636 | env = firstenv; |
3b989d49 | 637 | |
1db09b84 AJ |
638 | /* Fixup Memory size on a alignment boundary */ |
639 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
43d03f29 | 640 | params->ram_size = ram_size; |
1db09b84 AJ |
641 | |
642 | /* Register Memory */ | |
2c9b15ca | 643 | memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); |
c5705a77 | 644 | vmstate_register_ram_global(ram); |
2646c133 | 645 | memory_region_add_subregion(address_space_mem, 0, ram); |
1db09b84 | 646 | |
3eddc1be BB |
647 | dev = qdev_create(NULL, "e500-ccsr"); |
648 | object_property_add_child(qdev_get_machine(), "e500-ccsr", | |
649 | OBJECT(dev), NULL); | |
650 | qdev_init_nofail(dev); | |
651 | ccsr = CCSR(dev); | |
652 | ccsr_addr_space = &ccsr->ccsr_space; | |
653 | memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, | |
654 | ccsr_addr_space); | |
dffb1dc2 | 655 | |
82fc73b6 | 656 | mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); |
d0b72631 | 657 | |
1db09b84 | 658 | /* Serial */ |
2d48377a | 659 | if (serial_hds[0]) { |
3eddc1be | 660 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
cdbb912a | 661 | 0, mpic[42], 399193, |
2ff0c7c3 | 662 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 663 | } |
1db09b84 | 664 | |
2d48377a | 665 | if (serial_hds[1]) { |
3eddc1be | 666 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
cdbb912a | 667 | 0, mpic[42], 399193, |
59de4f98 | 668 | serial_hds[1], DEVICE_BIG_ENDIAN); |
2d48377a | 669 | } |
1db09b84 | 670 | |
b0fb8423 | 671 | /* General Utility device */ |
dffb1dc2 BB |
672 | dev = qdev_create(NULL, "mpc8544-guts"); |
673 | qdev_init_nofail(dev); | |
674 | s = SYS_BUS_DEVICE(dev); | |
3eddc1be | 675 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
dffb1dc2 | 676 | sysbus_mmio_get_region(s, 0)); |
b0fb8423 | 677 | |
1db09b84 | 678 | /* PCI */ |
dffb1dc2 | 679 | dev = qdev_create(NULL, "e500-pcihost"); |
492ec48d | 680 | qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); |
dffb1dc2 BB |
681 | qdev_init_nofail(dev); |
682 | s = SYS_BUS_DEVICE(dev); | |
683 | sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); | |
684 | sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); | |
685 | sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); | |
686 | sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); | |
3eddc1be | 687 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
dffb1dc2 BB |
688 | sysbus_mmio_get_region(s, 0)); |
689 | ||
d461e3b9 | 690 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
691 | if (!pci_bus) |
692 | printf("couldn't create PCI controller!\n"); | |
693 | ||
1356b98d | 694 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); |
1db09b84 AJ |
695 | |
696 | if (pci_bus) { | |
1db09b84 AJ |
697 | /* Register network interfaces. */ |
698 | for (i = 0; i < nb_nics; i++) { | |
29b358f9 | 699 | pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); |
1db09b84 AJ |
700 | } |
701 | } | |
702 | ||
5c145dac AG |
703 | /* Register spinning region */ |
704 | sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); | |
705 | ||
1db09b84 | 706 | /* Load kernel. */ |
e6eaabeb SW |
707 | if (params->kernel_filename) { |
708 | kernel_size = load_uimage(params->kernel_filename, &entry, | |
709 | &loadaddr, NULL); | |
1db09b84 | 710 | if (kernel_size < 0) { |
e6eaabeb SW |
711 | kernel_size = load_elf(params->kernel_filename, NULL, NULL, |
712 | &elf_entry, &elf_lowaddr, NULL, 1, | |
713 | ELF_MACHINE, 0); | |
1db09b84 AJ |
714 | entry = elf_entry; |
715 | loadaddr = elf_lowaddr; | |
716 | } | |
717 | /* XXX try again as binary */ | |
718 | if (kernel_size < 0) { | |
719 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
e6eaabeb | 720 | params->kernel_filename); |
1db09b84 AJ |
721 | exit(1); |
722 | } | |
528e536e AG |
723 | |
724 | cur_base = loadaddr + kernel_size; | |
b8dec144 AG |
725 | |
726 | /* Reserve space for dtb */ | |
727 | dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK; | |
728 | cur_base += DTB_MAX_SIZE; | |
1db09b84 AJ |
729 | } |
730 | ||
731 | /* Load initrd. */ | |
e6eaabeb | 732 | if (params->initrd_filename) { |
528e536e | 733 | initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
e6eaabeb | 734 | initrd_size = load_image_targphys(params->initrd_filename, initrd_base, |
d7585251 | 735 | ram_size - initrd_base); |
1db09b84 AJ |
736 | |
737 | if (initrd_size < 0) { | |
738 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
e6eaabeb | 739 | params->initrd_filename); |
1db09b84 AJ |
740 | exit(1); |
741 | } | |
528e536e AG |
742 | |
743 | cur_base = initrd_base + initrd_size; | |
1db09b84 AJ |
744 | } |
745 | ||
746 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
e6eaabeb | 747 | if (params->kernel_filename) { |
5c145dac | 748 | struct boot_info *boot_info; |
cba2026a | 749 | int dt_size; |
5c145dac | 750 | |
e6eaabeb SW |
751 | dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, |
752 | initrd_size); | |
cba2026a | 753 | if (dt_size < 0) { |
1db09b84 AJ |
754 | fprintf(stderr, "couldn't load device tree\n"); |
755 | exit(1); | |
756 | } | |
b8dec144 | 757 | assert(dt_size < DTB_MAX_SIZE); |
1db09b84 | 758 | |
e61c36d5 | 759 | boot_info = env->load_info; |
3b989d49 AG |
760 | boot_info->entry = entry; |
761 | boot_info->dt_base = dt_base; | |
cba2026a | 762 | boot_info->dt_size = dt_size; |
1db09b84 AJ |
763 | } |
764 | ||
3b989d49 | 765 | if (kvm_enabled()) { |
1db09b84 | 766 | kvmppc_init(); |
3b989d49 | 767 | } |
1db09b84 | 768 | } |
3eddc1be BB |
769 | |
770 | static int e500_ccsr_initfn(SysBusDevice *dev) | |
771 | { | |
772 | PPCE500CCSRState *ccsr; | |
773 | ||
774 | ccsr = CCSR(dev); | |
40c5dce9 | 775 | memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", |
3eddc1be BB |
776 | MPC8544_CCSRBAR_SIZE); |
777 | return 0; | |
778 | } | |
779 | ||
780 | static void e500_ccsr_class_init(ObjectClass *klass, void *data) | |
781 | { | |
782 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
783 | k->init = e500_ccsr_initfn; | |
784 | } | |
785 | ||
786 | static const TypeInfo e500_ccsr_info = { | |
787 | .name = TYPE_CCSR, | |
788 | .parent = TYPE_SYS_BUS_DEVICE, | |
789 | .instance_size = sizeof(PPCE500CCSRState), | |
790 | .class_init = e500_ccsr_class_init, | |
791 | }; | |
792 | ||
793 | static void e500_register_types(void) | |
794 | { | |
795 | type_register_static(&e500_ccsr_info); | |
796 | } | |
797 | ||
798 | type_init(e500_register_types) |