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Commit | Line | Data |
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1db09b84 | 1 | /* |
b3305981 | 2 | * QEMU PowerPC e500-based platforms |
1db09b84 AJ |
3 | * |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
0d75590d | 17 | #include "qemu/osdep.h" |
a8d25326 | 18 | #include "qemu-common.h" |
2c65db5e | 19 | #include "qemu/datadir.h" |
ab3dd749 | 20 | #include "qemu/units.h" |
da34e65c | 21 | #include "qapi/error.h" |
e6eaabeb | 22 | #include "e500.h" |
3eddc1be | 23 | #include "e500-ccsr.h" |
1422e32d | 24 | #include "net/net.h" |
1de7afc9 | 25 | #include "qemu/config-file.h" |
0d09e41a | 26 | #include "hw/char/serial.h" |
a2cb15b0 | 27 | #include "hw/pci/pci.h" |
4a18e7c9 | 28 | #include "hw/boards.h" |
9c17d615 PB |
29 | #include "sysemu/sysemu.h" |
30 | #include "sysemu/kvm.h" | |
71e8a915 | 31 | #include "sysemu/reset.h" |
54d31236 | 32 | #include "sysemu/runstate.h" |
1db09b84 | 33 | #include "kvm_ppc.h" |
9c17d615 | 34 | #include "sysemu/device_tree.h" |
0d09e41a | 35 | #include "hw/ppc/openpic.h" |
8d085cf0 | 36 | #include "hw/ppc/openpic_kvm.h" |
0d09e41a | 37 | #include "hw/ppc/ppc.h" |
a27bd6c7 | 38 | #include "hw/qdev-properties.h" |
4a18e7c9 | 39 | #include "hw/loader.h" |
ca20cf32 | 40 | #include "elf.h" |
4a18e7c9 | 41 | #include "hw/sysbus.h" |
022c62cb | 42 | #include "exec/address-spaces.h" |
1de7afc9 | 43 | #include "qemu/host-utils.h" |
922a01a0 | 44 | #include "qemu/option.h" |
0d09e41a | 45 | #include "hw/pci-host/ppce500.h" |
f7087343 AG |
46 | #include "qemu/error-report.h" |
47 | #include "hw/platform-bus.h" | |
fdfb7f2c | 48 | #include "hw/net/fsl_etsec/etsec.h" |
7abb479c | 49 | #include "hw/i2c/i2c.h" |
64552b6b | 50 | #include "hw/irq.h" |
1db09b84 | 51 | |
cefd3cdb | 52 | #define EPAPR_MAGIC (0x45504150) |
1db09b84 | 53 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
9dd5eba1 | 54 | #define DTC_LOAD_PAD 0x1800000 |
75bb6589 | 55 | #define DTC_PAD_MASK 0xFFFFF |
ab3dd749 | 56 | #define DTB_MAX_SIZE (8 * MiB) |
75bb6589 LY |
57 | #define INITRD_LOAD_PAD 0x2000000 |
58 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 | 59 | |
ab3dd749 | 60 | #define RAM_SIZES_ALIGN (64 * MiB) |
1db09b84 | 61 | |
b3305981 | 62 | /* TODO: parameterize */ |
ed2bc496 | 63 | #define MPC8544_CCSRBAR_SIZE 0x00100000ULL |
dffb1dc2 | 64 | #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL |
a911b7a9 | 65 | #define MPC8544_MSI_REGS_OFFSET 0x41600ULL |
dffb1dc2 BB |
66 | #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL |
67 | #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL | |
68 | #define MPC8544_PCI_REGS_OFFSET 0x8000ULL | |
ed2bc496 | 69 | #define MPC8544_PCI_REGS_SIZE 0x1000ULL |
dffb1dc2 | 70 | #define MPC8544_UTIL_OFFSET 0xe0000ULL |
b88e77f4 | 71 | #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL |
7abb479c | 72 | #define MPC8544_I2C_REGS_OFFSET 0x3000ULL |
82e345f5 | 73 | #define MPC8XXX_GPIO_IRQ 47 |
7abb479c AR |
74 | #define MPC8544_I2C_IRQ 43 |
75 | #define RTC_REGS_OFFSET 0x68 | |
1db09b84 | 76 | |
3b989d49 AG |
77 | struct boot_info |
78 | { | |
79 | uint32_t dt_base; | |
cba2026a | 80 | uint32_t dt_size; |
3b989d49 AG |
81 | uint32_t entry; |
82 | }; | |
83 | ||
347dd79d AG |
84 | static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, |
85 | int nr_slots, int *len) | |
0dbc0798 | 86 | { |
347dd79d AG |
87 | int i = 0; |
88 | int slot; | |
89 | int pci_irq; | |
9e2c1298 | 90 | int host_irq; |
347dd79d AG |
91 | int last_slot = first_slot + nr_slots; |
92 | uint32_t *pci_map; | |
93 | ||
94 | *len = nr_slots * 4 * 7 * sizeof(uint32_t); | |
95 | pci_map = g_malloc(*len); | |
96 | ||
97 | for (slot = first_slot; slot < last_slot; slot++) { | |
98 | for (pci_irq = 0; pci_irq < 4; pci_irq++) { | |
99 | pci_map[i++] = cpu_to_be32(slot << 11); | |
100 | pci_map[i++] = cpu_to_be32(0x0); | |
101 | pci_map[i++] = cpu_to_be32(0x0); | |
102 | pci_map[i++] = cpu_to_be32(pci_irq + 1); | |
103 | pci_map[i++] = cpu_to_be32(mpic); | |
9e2c1298 AG |
104 | host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); |
105 | pci_map[i++] = cpu_to_be32(host_irq + 1); | |
347dd79d AG |
106 | pci_map[i++] = cpu_to_be32(0x1); |
107 | } | |
0dbc0798 | 108 | } |
347dd79d AG |
109 | |
110 | assert((i * sizeof(uint32_t)) == *len); | |
111 | ||
112 | return pci_map; | |
0dbc0798 AG |
113 | } |
114 | ||
a053a7ce AG |
115 | static void dt_serial_create(void *fdt, unsigned long long offset, |
116 | const char *soc, const char *mpic, | |
117 | const char *alias, int idx, bool defcon) | |
118 | { | |
2fb513d3 | 119 | char *ser; |
a053a7ce | 120 | |
2fb513d3 | 121 | ser = g_strdup_printf("%s/serial@%llx", soc, offset); |
5a4348d1 PC |
122 | qemu_fdt_add_subnode(fdt, ser); |
123 | qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); | |
124 | qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); | |
125 | qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); | |
126 | qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); | |
127 | qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); | |
128 | qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); | |
129 | qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); | |
130 | qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); | |
a053a7ce AG |
131 | |
132 | if (defcon) { | |
90ee4e01 ND |
133 | /* |
134 | * "linux,stdout-path" and "stdout" properties are deprecated by linux | |
135 | * kernel. New platforms should only use the "stdout-path" property. Set | |
136 | * the new property and continue using older property to remain | |
137 | * compatible with the existing firmware. | |
138 | */ | |
5a4348d1 | 139 | qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); |
90ee4e01 | 140 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); |
a053a7ce | 141 | } |
2fb513d3 | 142 | g_free(ser); |
a053a7ce AG |
143 | } |
144 | ||
b88e77f4 AG |
145 | static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) |
146 | { | |
147 | hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; | |
148 | int irq0 = MPC8XXX_GPIO_IRQ; | |
149 | gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); | |
016f7758 AG |
150 | gchar *poweroff = g_strdup_printf("%s/power-off", soc); |
151 | int gpio_ph; | |
b88e77f4 AG |
152 | |
153 | qemu_fdt_add_subnode(fdt, node); | |
154 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); | |
155 | qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); | |
156 | qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); | |
157 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); | |
158 | qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); | |
159 | qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); | |
016f7758 AG |
160 | gpio_ph = qemu_fdt_alloc_phandle(fdt); |
161 | qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); | |
162 | qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); | |
163 | ||
164 | /* Power Off Pin */ | |
165 | qemu_fdt_add_subnode(fdt, poweroff); | |
166 | qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); | |
167 | qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); | |
b88e77f4 AG |
168 | |
169 | g_free(node); | |
016f7758 | 170 | g_free(poweroff); |
b88e77f4 AG |
171 | } |
172 | ||
7abb479c AR |
173 | static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) |
174 | { | |
175 | int offset = RTC_REGS_OFFSET; | |
176 | ||
177 | gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); | |
178 | qemu_fdt_add_subnode(fdt, rtc); | |
179 | qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); | |
180 | qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); | |
181 | qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); | |
182 | ||
183 | g_free(rtc); | |
184 | } | |
185 | ||
186 | static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, | |
187 | const char *alias) | |
188 | { | |
189 | hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; | |
190 | int irq0 = MPC8544_I2C_IRQ; | |
191 | ||
192 | gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); | |
193 | qemu_fdt_add_subnode(fdt, i2c); | |
194 | qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); | |
195 | qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); | |
196 | qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); | |
197 | qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); | |
198 | qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); | |
199 | qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); | |
200 | qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); | |
201 | ||
202 | g_free(i2c); | |
203 | } | |
204 | ||
205 | ||
f7087343 AG |
206 | typedef struct PlatformDevtreeData { |
207 | void *fdt; | |
208 | const char *mpic; | |
209 | int irq_start; | |
210 | const char *node; | |
211 | PlatformBusDevice *pbus; | |
212 | } PlatformDevtreeData; | |
213 | ||
fdfb7f2c AG |
214 | static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) |
215 | { | |
216 | eTSEC *etsec = ETSEC_COMMON(sbdev); | |
217 | PlatformBusDevice *pbus = data->pbus; | |
218 | hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
219 | int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); | |
220 | int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); | |
221 | int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); | |
222 | gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); | |
223 | gchar *group = g_strdup_printf("%s/queue-group", node); | |
224 | void *fdt = data->fdt; | |
225 | ||
226 | assert((int64_t)mmio0 >= 0); | |
227 | assert(irq0 >= 0); | |
228 | assert(irq1 >= 0); | |
229 | assert(irq2 >= 0); | |
230 | ||
231 | qemu_fdt_add_subnode(fdt, node); | |
232 | qemu_fdt_setprop_string(fdt, node, "device_type", "network"); | |
233 | qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); | |
234 | qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); | |
235 | qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); | |
236 | qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); | |
237 | ||
238 | qemu_fdt_add_subnode(fdt, group); | |
239 | qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); | |
240 | qemu_fdt_setprop_cells(fdt, group, "interrupts", | |
241 | data->irq_start + irq0, 0x2, | |
242 | data->irq_start + irq1, 0x2, | |
243 | data->irq_start + irq2, 0x2); | |
244 | ||
245 | g_free(node); | |
246 | g_free(group); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
4f01a637 | 251 | static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) |
f7087343 AG |
252 | { |
253 | PlatformDevtreeData *data = opaque; | |
254 | bool matched = false; | |
255 | ||
fdfb7f2c AG |
256 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { |
257 | create_devtree_etsec(sbdev, data); | |
258 | matched = true; | |
259 | } | |
260 | ||
f7087343 AG |
261 | if (!matched) { |
262 | error_report("Device %s is not supported by this machine yet.", | |
263 | qdev_fw_name(DEVICE(sbdev))); | |
264 | exit(1); | |
265 | } | |
f7087343 AG |
266 | } |
267 | ||
a3fc8396 | 268 | static void platform_bus_create_devtree(PPCE500MachineState *pms, |
03f04809 | 269 | void *fdt, const char *mpic) |
f7087343 | 270 | { |
a3fc8396 | 271 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
03f04809 | 272 | gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); |
f7087343 | 273 | const char platcomp[] = "qemu,platform\0simple-bus"; |
03f04809 IM |
274 | uint64_t addr = pmc->platform_bus_base; |
275 | uint64_t size = pmc->platform_bus_size; | |
276 | int irq_start = pmc->platform_bus_first_irq; | |
f7087343 AG |
277 | |
278 | /* Create a /platform node that we can put all devices into */ | |
279 | ||
280 | qemu_fdt_add_subnode(fdt, node); | |
281 | qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); | |
282 | ||
283 | /* Our platform bus region is less than 32bit big, so 1 cell is enough for | |
284 | address and size */ | |
285 | qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); | |
286 | qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); | |
287 | qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); | |
288 | ||
289 | qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); | |
290 | ||
a3fc8396 IM |
291 | /* Create dt nodes for dynamic devices */ |
292 | PlatformDevtreeData data = { | |
293 | .fdt = fdt, | |
294 | .mpic = mpic, | |
295 | .irq_start = irq_start, | |
296 | .node = node, | |
297 | .pbus = pms->pbus_dev, | |
298 | }; | |
f7087343 | 299 | |
a3fc8396 IM |
300 | /* Loop through all dynamic sysbus devices and create nodes for them */ |
301 | foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); | |
f7087343 AG |
302 | |
303 | g_free(node); | |
304 | } | |
305 | ||
03f04809 | 306 | static int ppce500_load_device_tree(PPCE500MachineState *pms, |
a8170e5e AK |
307 | hwaddr addr, |
308 | hwaddr initrd_base, | |
28290f37 | 309 | hwaddr initrd_size, |
903585de AG |
310 | hwaddr kernel_base, |
311 | hwaddr kernel_size, | |
28290f37 | 312 | bool dry_run) |
1db09b84 | 313 | { |
03f04809 | 314 | MachineState *machine = MACHINE(pms); |
fe6b6346 | 315 | unsigned int smp_cpus = machine->smp.cpus; |
03f04809 | 316 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
28290f37 | 317 | CPUPPCState *env = first_cpu->env_ptr; |
dbf916d8 | 318 | int ret = -1; |
3ef96221 | 319 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; |
7ec632b4 | 320 | int fdt_size; |
dbf916d8 | 321 | void *fdt; |
5de6b46d | 322 | uint8_t hypercall[16]; |
911d6e7a AG |
323 | uint32_t clock_freq = 400000000; |
324 | uint32_t tb_freq = 400000000; | |
621d05e3 | 325 | int i; |
ebb9518a | 326 | char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; |
2fb513d3 GK |
327 | char *soc; |
328 | char *mpic; | |
19ac9dea | 329 | uint32_t mpic_ph; |
a911b7a9 | 330 | uint32_t msi_ph; |
2fb513d3 GK |
331 | char *gutil; |
332 | char *pci; | |
333 | char *msi; | |
347dd79d AG |
334 | uint32_t *pci_map = NULL; |
335 | int len; | |
3627757e AG |
336 | uint32_t pci_ranges[14] = |
337 | { | |
03f04809 IM |
338 | 0x2000000, 0x0, pmc->pci_mmio_bus_base, |
339 | pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, | |
3627757e AG |
340 | 0x0, 0x20000000, |
341 | ||
342 | 0x1000000, 0x0, 0x0, | |
03f04809 | 343 | pmc->pci_pio_base >> 32, pmc->pci_pio_base, |
3627757e AG |
344 | 0x0, 0x10000, |
345 | }; | |
2ff3de68 MA |
346 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
347 | const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); | |
348 | const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); | |
d1b93565 AG |
349 | |
350 | if (dtb_file) { | |
351 | char *filename; | |
352 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); | |
353 | if (!filename) { | |
354 | goto out; | |
355 | } | |
356 | ||
357 | fdt = load_device_tree(filename, &fdt_size); | |
2343dd11 | 358 | g_free(filename); |
d1b93565 AG |
359 | if (!fdt) { |
360 | goto out; | |
361 | } | |
362 | goto done; | |
363 | } | |
1db09b84 | 364 | |
2636fcb6 | 365 | fdt = create_device_tree(&fdt_size); |
5cea8590 PB |
366 | if (fdt == NULL) { |
367 | goto out; | |
368 | } | |
1db09b84 AJ |
369 | |
370 | /* Manipulate device tree in memory. */ | |
5a4348d1 PC |
371 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); |
372 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); | |
51b852b7 | 373 | |
5a4348d1 PC |
374 | qemu_fdt_add_subnode(fdt, "/memory"); |
375 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
376 | qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, | |
377 | sizeof(mem_reg_property)); | |
1db09b84 | 378 | |
5a4348d1 | 379 | qemu_fdt_add_subnode(fdt, "/chosen"); |
3b989d49 | 380 | if (initrd_size) { |
5a4348d1 PC |
381 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
382 | initrd_base); | |
3b989d49 AG |
383 | if (ret < 0) { |
384 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
385 | } | |
1db09b84 | 386 | |
5a4348d1 PC |
387 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
388 | (initrd_base + initrd_size)); | |
3b989d49 AG |
389 | if (ret < 0) { |
390 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
391 | } | |
903585de AG |
392 | |
393 | } | |
394 | ||
395 | if (kernel_base != -1ULL) { | |
396 | qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", | |
397 | kernel_base >> 32, kernel_base, | |
398 | kernel_size >> 32, kernel_size); | |
3b989d49 | 399 | } |
1db09b84 | 400 | |
5a4348d1 | 401 | ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
3ef96221 | 402 | machine->kernel_cmdline); |
1db09b84 AJ |
403 | if (ret < 0) |
404 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
405 | ||
406 | if (kvm_enabled()) { | |
911d6e7a AG |
407 | /* Read out host's frequencies */ |
408 | clock_freq = kvmppc_get_clockfreq(); | |
409 | tb_freq = kvmppc_get_tbfreq(); | |
5de6b46d AG |
410 | |
411 | /* indicate KVM hypercall interface */ | |
5a4348d1 PC |
412 | qemu_fdt_add_subnode(fdt, "/hypervisor"); |
413 | qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", | |
414 | "linux,kvm"); | |
5de6b46d | 415 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); |
5a4348d1 PC |
416 | qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", |
417 | hypercall, sizeof(hypercall)); | |
1a61a9ae SY |
418 | /* if KVM supports the idle hcall, set property indicating this */ |
419 | if (kvmppc_get_hasidle(env)) { | |
5a4348d1 | 420 | qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); |
1a61a9ae | 421 | } |
1db09b84 | 422 | } |
3b989d49 | 423 | |
625e665b | 424 | /* Create CPU nodes */ |
5a4348d1 PC |
425 | qemu_fdt_add_subnode(fdt, "/cpus"); |
426 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
427 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
625e665b | 428 | |
1e3debf0 AG |
429 | /* We need to generate the cpu nodes in reverse order, so Linux can pick |
430 | the first node as boot node and be happy */ | |
431 | for (i = smp_cpus - 1; i >= 0; i--) { | |
440c8152 | 432 | CPUState *cpu; |
2fb513d3 | 433 | char *cpu_name; |
03f04809 | 434 | uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); |
10f25a46 | 435 | |
440c8152 | 436 | cpu = qemu_get_cpu(i); |
55e5c285 | 437 | if (cpu == NULL) { |
1e3debf0 AG |
438 | continue; |
439 | } | |
440c8152 | 440 | env = cpu->env_ptr; |
1e3debf0 | 441 | |
2fb513d3 | 442 | cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); |
5a4348d1 PC |
443 | qemu_fdt_add_subnode(fdt, cpu_name); |
444 | qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); | |
445 | qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); | |
446 | qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | |
6d536570 | 447 | qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); |
5a4348d1 PC |
448 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", |
449 | env->dcache_line_size); | |
450 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", | |
451 | env->icache_line_size); | |
452 | qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); | |
453 | qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); | |
454 | qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); | |
55e5c285 | 455 | if (cpu->cpu_index) { |
5a4348d1 PC |
456 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); |
457 | qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", | |
458 | "spin-table"); | |
459 | qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", | |
460 | cpu_release_addr); | |
1e3debf0 | 461 | } else { |
5a4348d1 | 462 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); |
1e3debf0 | 463 | } |
2fb513d3 | 464 | g_free(cpu_name); |
1db09b84 AJ |
465 | } |
466 | ||
5a4348d1 | 467 | qemu_fdt_add_subnode(fdt, "/aliases"); |
5da96624 | 468 | /* XXX These should go into their respective devices' code */ |
2fb513d3 | 469 | soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); |
5a4348d1 PC |
470 | qemu_fdt_add_subnode(fdt, soc); |
471 | qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); | |
472 | qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, | |
473 | sizeof(compatible_sb)); | |
474 | qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); | |
475 | qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); | |
476 | qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, | |
03f04809 | 477 | pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, |
5a4348d1 | 478 | MPC8544_CCSRBAR_SIZE); |
5da96624 | 479 | /* XXX should contain a reasonable value */ |
5a4348d1 | 480 | qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); |
5da96624 | 481 | |
2fb513d3 | 482 | mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); |
5a4348d1 PC |
483 | qemu_fdt_add_subnode(fdt, mpic); |
484 | qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); | |
485 | qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); | |
486 | qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, | |
487 | 0x40000); | |
488 | qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); | |
489 | qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); | |
490 | mpic_ph = qemu_fdt_alloc_phandle(fdt); | |
491 | qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); | |
492 | qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); | |
493 | qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); | |
19ac9dea | 494 | |
0cfc6e8d AG |
495 | /* |
496 | * We have to generate ser1 first, because Linux takes the first | |
497 | * device it finds in the dt as serial output device. And we generate | |
498 | * devices in reverse order to the dt. | |
499 | */ | |
9bca0edb | 500 | if (serial_hd(1)) { |
79c0ff2c AG |
501 | dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, |
502 | soc, mpic, "serial1", 1, false); | |
503 | } | |
504 | ||
9bca0edb | 505 | if (serial_hd(0)) { |
79c0ff2c AG |
506 | dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, |
507 | soc, mpic, "serial0", 0, true); | |
508 | } | |
0cfc6e8d | 509 | |
7abb479c AR |
510 | /* i2c */ |
511 | dt_i2c_create(fdt, soc, mpic, "i2c"); | |
512 | ||
513 | dt_rtc_create(fdt, "i2c", "rtc"); | |
514 | ||
515 | ||
2fb513d3 GK |
516 | gutil = g_strdup_printf("%s/global-utilities@%llx", soc, |
517 | MPC8544_UTIL_OFFSET); | |
5a4348d1 PC |
518 | qemu_fdt_add_subnode(fdt, gutil); |
519 | qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); | |
520 | qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); | |
521 | qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); | |
2fb513d3 | 522 | g_free(gutil); |
f5038483 | 523 | |
2fb513d3 | 524 | msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); |
5a4348d1 PC |
525 | qemu_fdt_add_subnode(fdt, msi); |
526 | qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); | |
527 | qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); | |
528 | msi_ph = qemu_fdt_alloc_phandle(fdt); | |
529 | qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); | |
530 | qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); | |
531 | qemu_fdt_setprop_cells(fdt, msi, "interrupts", | |
a911b7a9 AG |
532 | 0xe0, 0x0, |
533 | 0xe1, 0x0, | |
534 | 0xe2, 0x0, | |
535 | 0xe3, 0x0, | |
536 | 0xe4, 0x0, | |
537 | 0xe5, 0x0, | |
538 | 0xe6, 0x0, | |
539 | 0xe7, 0x0); | |
5a4348d1 PC |
540 | qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); |
541 | qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); | |
2fb513d3 | 542 | g_free(msi); |
a911b7a9 | 543 | |
2fb513d3 GK |
544 | pci = g_strdup_printf("/pci@%llx", |
545 | pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); | |
5a4348d1 PC |
546 | qemu_fdt_add_subnode(fdt, pci); |
547 | qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); | |
548 | qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); | |
549 | qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); | |
550 | qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, | |
551 | 0x0, 0x7); | |
552 | pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), | |
03f04809 | 553 | pmc->pci_first_slot, pmc->pci_nr_slots, |
492ec48d | 554 | &len); |
5a4348d1 PC |
555 | qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); |
556 | qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); | |
557 | qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); | |
558 | qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); | |
3627757e | 559 | for (i = 0; i < 14; i++) { |
0dbc0798 AG |
560 | pci_ranges[i] = cpu_to_be32(pci_ranges[i]); |
561 | } | |
5a4348d1 PC |
562 | qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); |
563 | qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); | |
2eaaac1f | 564 | qemu_fdt_setprop_cells(fdt, pci, "reg", |
03f04809 IM |
565 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, |
566 | (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), | |
2eaaac1f | 567 | 0, 0x1000); |
5a4348d1 PC |
568 | qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); |
569 | qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); | |
570 | qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); | |
571 | qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); | |
572 | qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); | |
2fb513d3 | 573 | g_free(pci); |
0dbc0798 | 574 | |
03f04809 | 575 | if (pmc->has_mpc8xxx_gpio) { |
b88e77f4 AG |
576 | create_dt_mpc8xxx_gpio(fdt, soc, mpic); |
577 | } | |
2fb513d3 | 578 | g_free(soc); |
b88e77f4 | 579 | |
a3fc8396 IM |
580 | if (pms->pbus_dev) { |
581 | platform_bus_create_devtree(pms, fdt, mpic); | |
f7087343 | 582 | } |
2fb513d3 | 583 | g_free(mpic); |
f7087343 | 584 | |
03f04809 | 585 | pmc->fixup_devtree(fdt); |
e6eaabeb SW |
586 | |
587 | if (toplevel_compat) { | |
5a4348d1 PC |
588 | qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, |
589 | strlen(toplevel_compat) + 1); | |
e6eaabeb SW |
590 | } |
591 | ||
d1b93565 | 592 | done: |
28290f37 | 593 | if (!dry_run) { |
5a4348d1 | 594 | qemu_fdt_dumpdtb(fdt, fdt_size); |
28290f37 | 595 | cpu_physical_memory_write(addr, fdt, fdt_size); |
cba2026a | 596 | } |
cba2026a | 597 | ret = fdt_size; |
b2fb7a43 | 598 | g_free(fdt); |
7ec632b4 | 599 | |
1db09b84 | 600 | out: |
347dd79d | 601 | g_free(pci_map); |
1db09b84 | 602 | |
04088adb | 603 | return ret; |
1db09b84 AJ |
604 | } |
605 | ||
28290f37 | 606 | typedef struct DeviceTreeParams { |
03f04809 | 607 | PPCE500MachineState *machine; |
28290f37 AG |
608 | hwaddr addr; |
609 | hwaddr initrd_base; | |
610 | hwaddr initrd_size; | |
903585de AG |
611 | hwaddr kernel_base; |
612 | hwaddr kernel_size; | |
f7087343 | 613 | Notifier notifier; |
28290f37 AG |
614 | } DeviceTreeParams; |
615 | ||
616 | static void ppce500_reset_device_tree(void *opaque) | |
617 | { | |
618 | DeviceTreeParams *p = opaque; | |
03f04809 | 619 | ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, |
903585de AG |
620 | p->initrd_size, p->kernel_base, p->kernel_size, |
621 | false); | |
28290f37 AG |
622 | } |
623 | ||
f7087343 AG |
624 | static void ppce500_init_notify(Notifier *notifier, void *data) |
625 | { | |
626 | DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); | |
627 | ppce500_reset_device_tree(p); | |
628 | } | |
629 | ||
03f04809 | 630 | static int ppce500_prep_device_tree(PPCE500MachineState *machine, |
28290f37 AG |
631 | hwaddr addr, |
632 | hwaddr initrd_base, | |
903585de AG |
633 | hwaddr initrd_size, |
634 | hwaddr kernel_base, | |
635 | hwaddr kernel_size) | |
28290f37 AG |
636 | { |
637 | DeviceTreeParams *p = g_new(DeviceTreeParams, 1); | |
3ef96221 | 638 | p->machine = machine; |
28290f37 AG |
639 | p->addr = addr; |
640 | p->initrd_base = initrd_base; | |
641 | p->initrd_size = initrd_size; | |
903585de AG |
642 | p->kernel_base = kernel_base; |
643 | p->kernel_size = kernel_size; | |
28290f37 AG |
644 | |
645 | qemu_register_reset(ppce500_reset_device_tree, p); | |
f7087343 AG |
646 | p->notifier.notify = ppce500_init_notify; |
647 | qemu_add_machine_init_done_notifier(&p->notifier); | |
28290f37 AG |
648 | |
649 | /* Issue the device tree loader once, so that we get the size of the blob */ | |
03f04809 IM |
650 | return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, |
651 | kernel_base, kernel_size, true); | |
28290f37 AG |
652 | } |
653 | ||
cba2026a | 654 | /* Create -kernel TLB entries for BookE. */ |
a36848ff | 655 | hwaddr booke206_page_size_to_tlb(uint64_t size) |
d1e256fe | 656 | { |
ab3dd749 | 657 | return 63 - clz64(size / KiB); |
d1e256fe AG |
658 | } |
659 | ||
cefd3cdb | 660 | static int booke206_initial_map_tsize(CPUPPCState *env) |
3b989d49 | 661 | { |
cba2026a | 662 | struct boot_info *bi = env->load_info; |
cefd3cdb | 663 | hwaddr dt_end; |
cba2026a AG |
664 | int ps; |
665 | ||
666 | /* Our initial TLB entry needs to cover everything from 0 to | |
667 | the device tree top */ | |
668 | dt_end = bi->dt_base + bi->dt_size; | |
669 | ps = booke206_page_size_to_tlb(dt_end) + 1; | |
fb37c302 AG |
670 | if (ps & 1) { |
671 | /* e500v2 can only do even TLB size bits */ | |
672 | ps++; | |
673 | } | |
cefd3cdb BB |
674 | return ps; |
675 | } | |
676 | ||
677 | static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) | |
678 | { | |
679 | int tsize; | |
680 | ||
681 | tsize = booke206_initial_map_tsize(env); | |
682 | return (1ULL << 10 << tsize); | |
683 | } | |
684 | ||
685 | static void mmubooke_create_initial_mapping(CPUPPCState *env) | |
686 | { | |
687 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); | |
688 | hwaddr size; | |
689 | int ps; | |
690 | ||
691 | ps = booke206_initial_map_tsize(env); | |
cba2026a | 692 | size = (ps << MAS1_TSIZE_SHIFT); |
d1e256fe | 693 | tlb->mas1 = MAS1_VALID | size; |
cba2026a AG |
694 | tlb->mas2 = 0; |
695 | tlb->mas7_3 = 0; | |
d1e256fe | 696 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; |
93dd5e85 SW |
697 | |
698 | env->tlb_dirty = true; | |
3b989d49 AG |
699 | } |
700 | ||
b3305981 | 701 | static void ppce500_cpu_reset_sec(void *opaque) |
5c145dac | 702 | { |
38f92da6 | 703 | PowerPCCPU *cpu = opaque; |
259186a7 | 704 | CPUState *cs = CPU(cpu); |
5c145dac | 705 | |
259186a7 | 706 | cpu_reset(cs); |
5c145dac | 707 | |
27103424 | 708 | cs->exception_index = EXCP_HLT; |
3b989d49 AG |
709 | } |
710 | ||
b3305981 | 711 | static void ppce500_cpu_reset(void *opaque) |
3b989d49 | 712 | { |
38f92da6 | 713 | PowerPCCPU *cpu = opaque; |
259186a7 | 714 | CPUState *cs = CPU(cpu); |
38f92da6 | 715 | CPUPPCState *env = &cpu->env; |
3b989d49 AG |
716 | struct boot_info *bi = env->load_info; |
717 | ||
259186a7 | 718 | cpu_reset(cs); |
3b989d49 AG |
719 | |
720 | /* Set initial guest state. */ | |
259186a7 | 721 | cs->halted = 0; |
ab3dd749 | 722 | env->gpr[1] = (16 * MiB) - 8; |
3b989d49 | 723 | env->gpr[3] = bi->dt_base; |
cefd3cdb BB |
724 | env->gpr[4] = 0; |
725 | env->gpr[5] = 0; | |
726 | env->gpr[6] = EPAPR_MAGIC; | |
727 | env->gpr[7] = mmubooke_initial_mapsize(env); | |
728 | env->gpr[8] = 0; | |
729 | env->gpr[9] = 0; | |
3b989d49 | 730 | env->nip = bi->entry; |
cba2026a | 731 | mmubooke_create_initial_mapping(env); |
3b989d49 AG |
732 | } |
733 | ||
03f04809 | 734 | static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, |
2104d4f5 | 735 | IrqLines *irqs) |
82fc73b6 | 736 | { |
82fc73b6 SW |
737 | DeviceState *dev; |
738 | SysBusDevice *s; | |
739 | int i, j, k; | |
03f04809 | 740 | MachineState *machine = MACHINE(pms); |
fe6b6346 | 741 | unsigned int smp_cpus = machine->smp.cpus; |
03f04809 | 742 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
82fc73b6 | 743 | |
3e80f690 | 744 | dev = qdev_new(TYPE_OPENPIC); |
d2623129 | 745 | object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); |
03f04809 | 746 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
d85937e6 SW |
747 | qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); |
748 | ||
82fc73b6 | 749 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 750 | sysbus_realize_and_unref(s, &error_fatal); |
82fc73b6 SW |
751 | |
752 | k = 0; | |
753 | for (i = 0; i < smp_cpus; i++) { | |
754 | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { | |
2104d4f5 | 755 | sysbus_connect_irq(s, k++, irqs[i].irq[j]); |
82fc73b6 SW |
756 | } |
757 | } | |
758 | ||
d85937e6 SW |
759 | return dev; |
760 | } | |
761 | ||
03f04809 | 762 | static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, |
2104d4f5 | 763 | IrqLines *irqs, Error **errp) |
d85937e6 SW |
764 | { |
765 | DeviceState *dev; | |
d85937e6 | 766 | CPUState *cs; |
d85937e6 | 767 | |
3e80f690 | 768 | dev = qdev_new(TYPE_KVM_OPENPIC); |
03f04809 | 769 | qdev_prop_set_uint32(dev, "model", pmc->mpic_version); |
d85937e6 | 770 | |
668f62ec | 771 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { |
fe656ebd | 772 | object_unparent(OBJECT(dev)); |
d85937e6 SW |
773 | return NULL; |
774 | } | |
775 | ||
bdc44640 | 776 | CPU_FOREACH(cs) { |
d85937e6 SW |
777 | if (kvm_openpic_connect_vcpu(dev, cs)) { |
778 | fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", | |
779 | __func__); | |
780 | abort(); | |
781 | } | |
782 | } | |
783 | ||
784 | return dev; | |
785 | } | |
786 | ||
03f04809 | 787 | static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, |
c91c187f | 788 | MemoryRegion *ccsr, |
2104d4f5 | 789 | IrqLines *irqs) |
d85937e6 | 790 | { |
03f04809 | 791 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); |
d85937e6 SW |
792 | DeviceState *dev = NULL; |
793 | SysBusDevice *s; | |
d85937e6 SW |
794 | |
795 | if (kvm_enabled()) { | |
fe656ebd | 796 | Error *err = NULL; |
d85937e6 | 797 | |
4376c40d | 798 | if (kvm_kernel_irqchip_allowed()) { |
03f04809 | 799 | dev = ppce500_init_mpic_kvm(pmc, irqs, &err); |
d85937e6 | 800 | } |
4376c40d | 801 | if (kvm_kernel_irqchip_required() && !dev) { |
c29b77f9 MA |
802 | error_reportf_err(err, |
803 | "kernel_irqchip requested but unavailable: "); | |
fe656ebd | 804 | exit(1); |
d85937e6 SW |
805 | } |
806 | } | |
807 | ||
808 | if (!dev) { | |
03f04809 | 809 | dev = ppce500_init_mpic_qemu(pms, irqs); |
d85937e6 SW |
810 | } |
811 | ||
d85937e6 | 812 | s = SYS_BUS_DEVICE(dev); |
82fc73b6 SW |
813 | memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, |
814 | s->mmio[0].memory); | |
815 | ||
c91c187f | 816 | return dev; |
82fc73b6 SW |
817 | } |
818 | ||
016f7758 AG |
819 | static void ppce500_power_off(void *opaque, int line, int on) |
820 | { | |
821 | if (on) { | |
cf83f140 | 822 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
016f7758 AG |
823 | } |
824 | } | |
825 | ||
03f04809 | 826 | void ppce500_init(MachineState *machine) |
1db09b84 | 827 | { |
39186d8a | 828 | MemoryRegion *address_space_mem = get_system_memory(); |
03f04809 IM |
829 | PPCE500MachineState *pms = PPCE500_MACHINE(machine); |
830 | const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); | |
1db09b84 | 831 | PCIBus *pci_bus; |
e2684c0b | 832 | CPUPPCState *env = NULL; |
3812c71f AG |
833 | uint64_t loadaddr; |
834 | hwaddr kernel_base = -1LL; | |
835 | int kernel_size = 0; | |
836 | hwaddr dt_base = 0; | |
837 | hwaddr initrd_base = 0; | |
838 | int initrd_size = 0; | |
839 | hwaddr cur_base = 0; | |
840 | char *filename; | |
8d622594 DE |
841 | const char *payload_name; |
842 | bool kernel_as_payload; | |
3812c71f | 843 | hwaddr bios_entry = 0; |
8d622594 | 844 | target_long payload_size; |
3812c71f AG |
845 | struct boot_info *boot_info; |
846 | int dt_size; | |
82fc73b6 | 847 | int i; |
fe6b6346 | 848 | unsigned int smp_cpus = machine->smp.cpus; |
d575a6ce BB |
849 | /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and |
850 | * 4 respectively */ | |
851 | unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; | |
2104d4f5 | 852 | IrqLines *irqs; |
c91c187f | 853 | DeviceState *dev, *mpicdev; |
e2684c0b | 854 | CPUPPCState *firstenv = NULL; |
3eddc1be | 855 | MemoryRegion *ccsr_addr_space; |
dffb1dc2 | 856 | SysBusDevice *s; |
3eddc1be | 857 | PPCE500CCSRState *ccsr; |
7abb479c | 858 | I2CBus *i2c; |
1db09b84 | 859 | |
2104d4f5 | 860 | irqs = g_new0(IrqLines, smp_cpus); |
e61c36d5 | 861 | for (i = 0; i < smp_cpus; i++) { |
397b457d | 862 | PowerPCCPU *cpu; |
55e5c285 | 863 | CPUState *cs; |
e61c36d5 | 864 | qemu_irq *input; |
397b457d | 865 | |
a2c93f06 | 866 | cpu = POWERPC_CPU(object_new(machine->cpu_type)); |
397b457d | 867 | env = &cpu->env; |
55e5c285 | 868 | cs = CPU(cpu); |
1db09b84 | 869 | |
00469dc3 | 870 | if (env->mmu_model != POWERPC_MMU_BOOKE206) { |
6f76b817 AF |
871 | error_report("MMU model %i not supported by this machine", |
872 | env->mmu_model); | |
00469dc3 VP |
873 | exit(1); |
874 | } | |
875 | ||
a2c93f06 TJB |
876 | /* |
877 | * Secondary CPU starts in halted state for now. Needs to change | |
878 | * when implementing non-kernel boot. | |
879 | */ | |
880 | object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, | |
881 | &error_fatal); | |
882 | qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); | |
883 | ||
e61c36d5 AG |
884 | if (!firstenv) { |
885 | firstenv = env; | |
886 | } | |
1db09b84 | 887 | |
a915249f | 888 | input = (qemu_irq *)env->irq_inputs; |
2104d4f5 GK |
889 | irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; |
890 | irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; | |
6a450df9 | 891 | env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; |
03f04809 | 892 | env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; |
3b989d49 | 893 | |
a34a92b9 | 894 | ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); |
e61c36d5 AG |
895 | |
896 | /* Register reset handler */ | |
5c145dac AG |
897 | if (!i) { |
898 | /* Primary CPU */ | |
899 | struct boot_info *boot_info; | |
900 | boot_info = g_malloc0(sizeof(struct boot_info)); | |
b3305981 | 901 | qemu_register_reset(ppce500_cpu_reset, cpu); |
5c145dac AG |
902 | env->load_info = boot_info; |
903 | } else { | |
904 | /* Secondary CPUs */ | |
b3305981 | 905 | qemu_register_reset(ppce500_cpu_reset_sec, cpu); |
5c145dac | 906 | } |
e61c36d5 | 907 | } |
3b989d49 | 908 | |
e61c36d5 | 909 | env = firstenv; |
3b989d49 | 910 | |
3538e846 IM |
911 | if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { |
912 | error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); | |
913 | exit(EXIT_FAILURE); | |
914 | } | |
1db09b84 AJ |
915 | |
916 | /* Register Memory */ | |
97316645 | 917 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
1db09b84 | 918 | |
3e80f690 | 919 | dev = qdev_new("e500-ccsr"); |
3eddc1be | 920 | object_property_add_child(qdev_get_machine(), "e500-ccsr", |
d2623129 | 921 | OBJECT(dev)); |
3c6ef471 | 922 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
3eddc1be BB |
923 | ccsr = CCSR(dev); |
924 | ccsr_addr_space = &ccsr->ccsr_space; | |
03f04809 | 925 | memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, |
3eddc1be | 926 | ccsr_addr_space); |
dffb1dc2 | 927 | |
03f04809 | 928 | mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); |
ef0efa1a | 929 | g_free(irqs); |
d0b72631 | 930 | |
1db09b84 | 931 | /* Serial */ |
9bca0edb | 932 | if (serial_hd(0)) { |
3eddc1be | 933 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, |
c91c187f | 934 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
9bca0edb | 935 | serial_hd(0), DEVICE_BIG_ENDIAN); |
2d48377a | 936 | } |
1db09b84 | 937 | |
9bca0edb | 938 | if (serial_hd(1)) { |
3eddc1be | 939 | serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, |
c91c187f | 940 | 0, qdev_get_gpio_in(mpicdev, 42), 399193, |
9bca0edb | 941 | serial_hd(1), DEVICE_BIG_ENDIAN); |
2d48377a | 942 | } |
7abb479c | 943 | /* I2C */ |
3e80f690 | 944 | dev = qdev_new("mpc-i2c"); |
7abb479c | 945 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 946 | sysbus_realize_and_unref(s, &error_fatal); |
7abb479c AR |
947 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); |
948 | memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, | |
949 | sysbus_mmio_get_region(s, 0)); | |
950 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | |
1373b15b | 951 | i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); |
7abb479c | 952 | |
1db09b84 | 953 | |
b0fb8423 | 954 | /* General Utility device */ |
3e80f690 | 955 | dev = qdev_new("mpc8544-guts"); |
dffb1dc2 | 956 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 957 | sysbus_realize_and_unref(s, &error_fatal); |
3eddc1be | 958 | memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, |
dffb1dc2 | 959 | sysbus_mmio_get_region(s, 0)); |
b0fb8423 | 960 | |
1db09b84 | 961 | /* PCI */ |
3e80f690 | 962 | dev = qdev_new("e500-pcihost"); |
d2623129 | 963 | object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); |
03f04809 | 964 | qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); |
3016dca0 | 965 | qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); |
dffb1dc2 | 966 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 967 | sysbus_realize_and_unref(s, &error_fatal); |
d575a6ce | 968 | for (i = 0; i < PCI_NUM_PINS; i++) { |
c91c187f | 969 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); |
d575a6ce BB |
970 | } |
971 | ||
3eddc1be | 972 | memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, |
dffb1dc2 BB |
973 | sysbus_mmio_get_region(s, 0)); |
974 | ||
d461e3b9 | 975 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
976 | if (!pci_bus) |
977 | printf("couldn't create PCI controller!\n"); | |
978 | ||
1db09b84 | 979 | if (pci_bus) { |
1db09b84 AJ |
980 | /* Register network interfaces. */ |
981 | for (i = 0; i < nb_nics; i++) { | |
52310c3f | 982 | pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); |
1db09b84 AJ |
983 | } |
984 | } | |
985 | ||
5c145dac | 986 | /* Register spinning region */ |
03f04809 | 987 | sysbus_create_simple("e500-spin", pmc->spin_base, NULL); |
5c145dac | 988 | |
03f04809 | 989 | if (pmc->has_mpc8xxx_gpio) { |
016f7758 AG |
990 | qemu_irq poweroff_irq; |
991 | ||
3e80f690 | 992 | dev = qdev_new("mpc8xxx_gpio"); |
b88e77f4 | 993 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 994 | sysbus_realize_and_unref(s, &error_fatal); |
c91c187f | 995 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); |
b88e77f4 AG |
996 | memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, |
997 | sysbus_mmio_get_region(s, 0)); | |
016f7758 AG |
998 | |
999 | /* Power Off GPIO at Pin 0 */ | |
1000 | poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); | |
1001 | qdev_connect_gpio_out(dev, 0, poweroff_irq); | |
b88e77f4 AG |
1002 | } |
1003 | ||
f7087343 | 1004 | /* Platform Bus Device */ |
03f04809 | 1005 | if (pmc->has_platform_bus) { |
3e80f690 | 1006 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
f7087343 | 1007 | dev->id = TYPE_PLATFORM_BUS_DEVICE; |
03f04809 IM |
1008 | qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); |
1009 | qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); | |
3c6ef471 | 1010 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
a3fc8396 | 1011 | pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); |
f7087343 | 1012 | |
a3fc8396 | 1013 | s = SYS_BUS_DEVICE(pms->pbus_dev); |
03f04809 IM |
1014 | for (i = 0; i < pmc->platform_bus_num_irqs; i++) { |
1015 | int irqn = pmc->platform_bus_first_irq + i; | |
c91c187f | 1016 | sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); |
f7087343 AG |
1017 | } |
1018 | ||
1019 | memory_region_add_subregion(address_space_mem, | |
03f04809 | 1020 | pmc->platform_bus_base, |
f7087343 AG |
1021 | sysbus_mmio_get_region(s, 0)); |
1022 | } | |
1023 | ||
8d622594 DE |
1024 | /* |
1025 | * Smart firmware defaults ahead! | |
1026 | * | |
1027 | * We follow the following table to select which payload we execute. | |
1028 | * | |
1029 | * -kernel | -bios | payload | |
1030 | * ---------+-------+--------- | |
1031 | * N | Y | u-boot | |
1032 | * N | N | u-boot | |
1033 | * Y | Y | u-boot | |
1034 | * Y | N | kernel | |
1035 | * | |
1036 | * This ensures backwards compatibility with how we used to expose | |
1037 | * -kernel to users but allows them to run through u-boot as well. | |
1038 | */ | |
1039 | kernel_as_payload = false; | |
cd7b9498 | 1040 | if (machine->firmware == NULL) { |
8d622594 DE |
1041 | if (machine->kernel_filename) { |
1042 | payload_name = machine->kernel_filename; | |
1043 | kernel_as_payload = true; | |
1044 | } else { | |
1045 | payload_name = "u-boot.e500"; | |
1046 | } | |
1047 | } else { | |
cd7b9498 | 1048 | payload_name = machine->firmware; |
8d622594 DE |
1049 | } |
1050 | ||
1051 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); | |
3b4f50bd PM |
1052 | if (!filename) { |
1053 | error_report("could not find firmware/kernel file '%s'", payload_name); | |
1054 | exit(1); | |
1055 | } | |
8d622594 | 1056 | |
4366e1db | 1057 | payload_size = load_elf(filename, NULL, NULL, NULL, |
6cdda0ff | 1058 | &bios_entry, &loadaddr, NULL, NULL, |
8d622594 DE |
1059 | 1, PPC_ELF_MACHINE, 0, 0); |
1060 | if (payload_size < 0) { | |
1061 | /* | |
1062 | * Hrm. No ELF image? Try a uImage, maybe someone is giving us an | |
1063 | * ePAPR compliant kernel | |
1064 | */ | |
f831f955 | 1065 | loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
8d622594 DE |
1066 | payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, |
1067 | NULL, NULL); | |
1068 | if (payload_size < 0) { | |
371b74e2 | 1069 | error_report("could not load firmware '%s'", filename); |
8d622594 DE |
1070 | exit(1); |
1071 | } | |
1072 | } | |
1073 | ||
1074 | g_free(filename); | |
1075 | ||
1076 | if (kernel_as_payload) { | |
1077 | kernel_base = loadaddr; | |
1078 | kernel_size = payload_size; | |
1079 | } | |
1080 | ||
1081 | cur_base = loadaddr + payload_size; | |
ab3dd749 | 1082 | if (cur_base < 32 * MiB) { |
b4a5f24a | 1083 | /* u-boot occupies memory up to 32MB, so load blobs above */ |
ab3dd749 | 1084 | cur_base = 32 * MiB; |
b4a5f24a | 1085 | } |
8d622594 DE |
1086 | |
1087 | /* Load bare kernel only if no bios/u-boot has been provided */ | |
1088 | if (machine->kernel_filename && !kernel_as_payload) { | |
3812c71f AG |
1089 | kernel_base = cur_base; |
1090 | kernel_size = load_image_targphys(machine->kernel_filename, | |
1091 | cur_base, | |
3538e846 | 1092 | machine->ram_size - cur_base); |
1db09b84 | 1093 | if (kernel_size < 0) { |
6f76b817 AF |
1094 | error_report("could not load kernel '%s'", |
1095 | machine->kernel_filename); | |
1db09b84 AJ |
1096 | exit(1); |
1097 | } | |
528e536e | 1098 | |
3812c71f | 1099 | cur_base += kernel_size; |
1db09b84 AJ |
1100 | } |
1101 | ||
1102 | /* Load initrd. */ | |
3ef96221 | 1103 | if (machine->initrd_filename) { |
528e536e | 1104 | initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
3ef96221 | 1105 | initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, |
3538e846 | 1106 | machine->ram_size - initrd_base); |
1db09b84 AJ |
1107 | |
1108 | if (initrd_size < 0) { | |
6f76b817 AF |
1109 | error_report("could not load initial ram disk '%s'", |
1110 | machine->initrd_filename); | |
1db09b84 AJ |
1111 | exit(1); |
1112 | } | |
528e536e AG |
1113 | |
1114 | cur_base = initrd_base + initrd_size; | |
1db09b84 AJ |
1115 | } |
1116 | ||
3812c71f | 1117 | /* |
8d622594 DE |
1118 | * Reserve space for dtb behind the kernel image because Linux has a bug |
1119 | * where it can only handle the dtb if it's within the first 64MB of where | |
1120 | * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD | |
1121 | * ensures enough space between kernel and initrd. | |
3812c71f | 1122 | */ |
8d622594 | 1123 | dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
3538e846 | 1124 | if (dt_base + DTB_MAX_SIZE > machine->ram_size) { |
371b74e2 | 1125 | error_report("not enough memory for device tree"); |
1db09b84 | 1126 | exit(1); |
3812c71f | 1127 | } |
1db09b84 | 1128 | |
03f04809 | 1129 | dt_size = ppce500_prep_device_tree(pms, dt_base, |
3812c71f AG |
1130 | initrd_base, initrd_size, |
1131 | kernel_base, kernel_size); | |
1132 | if (dt_size < 0) { | |
6f76b817 | 1133 | error_report("couldn't load device tree"); |
3812c71f | 1134 | exit(1); |
1db09b84 | 1135 | } |
3812c71f AG |
1136 | assert(dt_size < DTB_MAX_SIZE); |
1137 | ||
1138 | boot_info = env->load_info; | |
1139 | boot_info->entry = bios_entry; | |
1140 | boot_info->dt_base = dt_base; | |
1141 | boot_info->dt_size = dt_size; | |
1db09b84 | 1142 | } |
3eddc1be | 1143 | |
d0c2b0d0 | 1144 | static void e500_ccsr_initfn(Object *obj) |
3eddc1be | 1145 | { |
d0c2b0d0 XZ |
1146 | PPCE500CCSRState *ccsr = CCSR(obj); |
1147 | memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", | |
3eddc1be | 1148 | MPC8544_CCSRBAR_SIZE); |
3eddc1be BB |
1149 | } |
1150 | ||
1151 | static const TypeInfo e500_ccsr_info = { | |
1152 | .name = TYPE_CCSR, | |
1153 | .parent = TYPE_SYS_BUS_DEVICE, | |
1154 | .instance_size = sizeof(PPCE500CCSRState), | |
d0c2b0d0 | 1155 | .instance_init = e500_ccsr_initfn, |
3eddc1be BB |
1156 | }; |
1157 | ||
03f04809 IM |
1158 | static const TypeInfo ppce500_info = { |
1159 | .name = TYPE_PPCE500_MACHINE, | |
1160 | .parent = TYPE_MACHINE, | |
1161 | .abstract = true, | |
a3fc8396 | 1162 | .instance_size = sizeof(PPCE500MachineState), |
03f04809 IM |
1163 | .class_size = sizeof(PPCE500MachineClass), |
1164 | }; | |
1165 | ||
3eddc1be BB |
1166 | static void e500_register_types(void) |
1167 | { | |
1168 | type_register_static(&e500_ccsr_info); | |
03f04809 | 1169 | type_register_static(&ppce500_info); |
3eddc1be BB |
1170 | } |
1171 | ||
1172 | type_init(e500_register_types) |