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Commit | Line | Data |
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ae0bfb79 | 1 | |
3cbee15b | 2 | /* |
4d7ca41e | 3 | * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator |
3cbee15b JM |
4 | * |
5 | * Copyright (c) 2004-2007 Fabrice Bellard | |
6 | * Copyright (c) 2007 Jocelyn Mayer | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
baec1910 | 26 | #include "hw/hw.h" |
0d09e41a | 27 | #include "hw/ppc/ppc.h" |
baec1910 | 28 | #include "mac.h" |
0d09e41a PB |
29 | #include "hw/input/adb.h" |
30 | #include "hw/timer/m48t59.h" | |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
1422e32d | 32 | #include "net/net.h" |
0d09e41a | 33 | #include "hw/isa/isa.h" |
baec1910 AF |
34 | #include "hw/pci/pci.h" |
35 | #include "hw/boards.h" | |
0d09e41a PB |
36 | #include "hw/nvram/fw_cfg.h" |
37 | #include "hw/char/escc.h" | |
baec1910 AF |
38 | #include "hw/ide.h" |
39 | #include "hw/loader.h" | |
ca20cf32 | 40 | #include "elf.h" |
9c17d615 | 41 | #include "sysemu/kvm.h" |
dc333cd6 | 42 | #include "kvm_ppc.h" |
9c17d615 | 43 | #include "sysemu/blockdev.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
3cbee15b | 45 | |
e4bcb14c | 46 | #define MAX_IDE_BUS 2 |
271dd5e0 BS |
47 | #define CFG_ADDR 0xf0000510 |
48 | ||
513f789f BS |
49 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
50 | { | |
51 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
52 | return 0; | |
53 | } | |
54 | ||
409dbce5 AJ |
55 | |
56 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
57 | { | |
58 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
59 | } | |
60 | ||
a8170e5e | 61 | static hwaddr round_page(hwaddr addr) |
b9e17a34 AG |
62 | { |
63 | return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; | |
64 | } | |
65 | ||
1bba0dc9 AF |
66 | static void ppc_heathrow_reset(void *opaque) |
67 | { | |
cd79664f | 68 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 69 | |
cd79664f | 70 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
71 | } |
72 | ||
5f072e1f | 73 | static void ppc_heathrow_init(QEMUMachineInitArgs *args) |
3cbee15b | 74 | { |
5f072e1f EH |
75 | ram_addr_t ram_size = args->ram_size; |
76 | const char *cpu_model = args->cpu_model; | |
77 | const char *kernel_filename = args->kernel_filename; | |
78 | const char *kernel_cmdline = args->kernel_cmdline; | |
79 | const char *initrd_filename = args->initrd_filename; | |
80 | const char *boot_device = args->boot_device; | |
c92bb2c7 | 81 | MemoryRegion *sysmem = get_system_memory(); |
72c33dd7 | 82 | PowerPCCPU *cpu = NULL; |
e2684c0b | 83 | CPUPPCState *env = NULL; |
5cea8590 | 84 | char *filename; |
3cbee15b | 85 | qemu_irq *pic, **heathrow_irqs; |
3cbee15b | 86 | int linux_boot, i; |
c92bb2c7 AK |
87 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
88 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
b9e17a34 | 89 | uint32_t kernel_base, initrd_base, cmdline_base = 0; |
7373048c | 90 | int32_t kernel_size, initrd_size; |
3cbee15b | 91 | PCIBus *pci_bus; |
d037834a | 92 | PCIDevice *macio; |
07a7484e AF |
93 | MACIOIDEState *macio_ide; |
94 | DeviceState *dev; | |
293c867d | 95 | BusState *adb_bus; |
ae0bfb79 | 96 | int bios_size; |
45fa67fb | 97 | MemoryRegion *pic_mem; |
07a7484e | 98 | MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); |
513f789f | 99 | uint16_t ppc_boot_device; |
f455e98c | 100 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
271dd5e0 | 101 | void *fw_cfg; |
3cbee15b JM |
102 | |
103 | linux_boot = (kernel_filename != NULL); | |
104 | ||
105 | /* init CPUs */ | |
3cbee15b | 106 | if (cpu_model == NULL) |
f2fde45a | 107 | cpu_model = "G3"; |
3cbee15b | 108 | for (i = 0; i < smp_cpus; i++) { |
72c33dd7 AF |
109 | cpu = cpu_ppc_init(cpu_model); |
110 | if (cpu == NULL) { | |
aaed909a FB |
111 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
112 | exit(1); | |
113 | } | |
72c33dd7 AF |
114 | env = &cpu->env; |
115 | ||
b0fb43d8 AJ |
116 | /* Set time-base frequency to 16.6 Mhz */ |
117 | cpu_ppc_tb_init(env, 16600000UL); | |
cd79664f | 118 | qemu_register_reset(ppc_heathrow_reset, cpu); |
3cbee15b JM |
119 | } |
120 | ||
121 | /* allocate RAM */ | |
6b4079f8 AJ |
122 | if (ram_size > (2047 << 20)) { |
123 | fprintf(stderr, | |
124 | "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", | |
125 | ((unsigned int)ram_size / (1 << 20))); | |
126 | exit(1); | |
127 | } | |
128 | ||
2c9b15ca | 129 | memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size); |
c5705a77 | 130 | vmstate_register_ram_global(ram); |
c92bb2c7 | 131 | memory_region_add_subregion(sysmem, 0, ram); |
a748ab6d | 132 | |
3cbee15b | 133 | /* allocate and load BIOS */ |
2c9b15ca | 134 | memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE); |
c5705a77 | 135 | vmstate_register_ram_global(bios); |
3cbee15b | 136 | if (bios_name == NULL) |
992e5acd | 137 | bios_name = PROM_FILENAME; |
5cea8590 | 138 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
c92bb2c7 AK |
139 | memory_region_set_readonly(bios, true); |
140 | memory_region_add_subregion(sysmem, PROM_ADDR, bios); | |
992e5acd BS |
141 | |
142 | /* Load OpenBIOS (ELF) */ | |
5cea8590 | 143 | if (filename) { |
409dbce5 AJ |
144 | bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, |
145 | 1, ELF_MACHINE, 0); | |
7267c094 | 146 | g_free(filename); |
5cea8590 PB |
147 | } else { |
148 | bios_size = -1; | |
149 | } | |
3cbee15b | 150 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 | 151 | hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); |
3cbee15b JM |
152 | exit(1); |
153 | } | |
3cbee15b | 154 | |
3cbee15b | 155 | if (linux_boot) { |
36bee1e3 | 156 | uint64_t lowaddr = 0; |
ca20cf32 BS |
157 | int bswap_needed; |
158 | ||
159 | #ifdef BSWAP_NEEDED | |
160 | bswap_needed = 1; | |
161 | #else | |
162 | bswap_needed = 0; | |
163 | #endif | |
3cbee15b | 164 | kernel_base = KERNEL_LOAD_ADDR; |
409dbce5 AJ |
165 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
166 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
52f163b7 BS |
167 | if (kernel_size < 0) |
168 | kernel_size = load_aout(kernel_filename, kernel_base, | |
ca20cf32 BS |
169 | ram_size - kernel_base, bswap_needed, |
170 | TARGET_PAGE_SIZE); | |
52f163b7 BS |
171 | if (kernel_size < 0) |
172 | kernel_size = load_image_targphys(kernel_filename, | |
173 | kernel_base, | |
174 | ram_size - kernel_base); | |
3cbee15b | 175 | if (kernel_size < 0) { |
2ac71179 | 176 | hw_error("qemu: could not load kernel '%s'\n", |
3cbee15b JM |
177 | kernel_filename); |
178 | exit(1); | |
179 | } | |
180 | /* load initrd */ | |
181 | if (initrd_filename) { | |
b9e17a34 | 182 | initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); |
dcac9679 PB |
183 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
184 | ram_size - initrd_base); | |
3cbee15b | 185 | if (initrd_size < 0) { |
2ac71179 PB |
186 | hw_error("qemu: could not load initial ram disk '%s'\n", |
187 | initrd_filename); | |
3cbee15b JM |
188 | exit(1); |
189 | } | |
b9e17a34 | 190 | cmdline_base = round_page(initrd_base + initrd_size); |
3cbee15b JM |
191 | } else { |
192 | initrd_base = 0; | |
193 | initrd_size = 0; | |
b9e17a34 | 194 | cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); |
3cbee15b | 195 | } |
6ac0e82d | 196 | ppc_boot_device = 'm'; |
3cbee15b JM |
197 | } else { |
198 | kernel_base = 0; | |
199 | kernel_size = 0; | |
200 | initrd_base = 0; | |
201 | initrd_size = 0; | |
28c5af54 | 202 | ppc_boot_device = '\0'; |
0d913fdb | 203 | for (i = 0; boot_device[i] != '\0'; i++) { |
28c5af54 | 204 | /* TOFIX: for now, the second IDE channel is not properly |
0d913fdb | 205 | * used by OHW. The Mac floppy disk are not emulated. |
28c5af54 JM |
206 | * For now, OHW cannot boot from the network. |
207 | */ | |
208 | #if 0 | |
0d913fdb JM |
209 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
210 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 211 | break; |
0d913fdb | 212 | } |
28c5af54 | 213 | #else |
0d913fdb JM |
214 | if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { |
215 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 216 | break; |
0d913fdb | 217 | } |
28c5af54 JM |
218 | #endif |
219 | } | |
220 | if (ppc_boot_device == '\0') { | |
8a901def | 221 | fprintf(stderr, "No valid boot device for G3 Beige machine\n"); |
28c5af54 JM |
222 | exit(1); |
223 | } | |
3cbee15b JM |
224 | } |
225 | ||
3cbee15b | 226 | /* Register 2 MB of ISA IO space */ |
968d683c | 227 | isa_mmio_init(0xfe000000, 0x00200000); |
3cbee15b JM |
228 | |
229 | /* XXX: we register only 1 output pin for heathrow PIC */ | |
7267c094 | 230 | heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); |
3cbee15b | 231 | heathrow_irqs[0] = |
7267c094 | 232 | g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); |
3cbee15b JM |
233 | /* Connect the heathrow PIC outputs to the 6xx bus */ |
234 | for (i = 0; i < smp_cpus; i++) { | |
235 | switch (PPC_INPUT(env)) { | |
236 | case PPC_FLAGS_INPUT_6xx: | |
237 | heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); | |
238 | heathrow_irqs[i][0] = | |
239 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; | |
240 | break; | |
241 | default: | |
2ac71179 | 242 | hw_error("Bus model not supported on OldWorld Mac machine\n"); |
3cbee15b JM |
243 | } |
244 | } | |
245 | ||
246 | /* init basic PC hardware */ | |
247 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
2ac71179 | 248 | hw_error("Only 6xx bus is supported on heathrow machine\n"); |
3cbee15b | 249 | } |
23c5e4ca | 250 | pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); |
aee97b84 AK |
251 | pci_bus = pci_grackle_init(0xfec00000, pic, |
252 | get_system_memory(), | |
253 | get_system_io()); | |
3e20ad3a | 254 | pci_vga_init(pci_bus); |
aae9366a | 255 | |
b39491a8 | 256 | escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], |
7fa9ae1a | 257 | serial_hds[1], ESCC_CLOCK, 4); |
2c9b15ca | 258 | memory_region_init_alias(escc_bar, NULL, "escc-bar", |
5b15f275 | 259 | escc_mem, 0, memory_region_size(escc_mem)); |
aae9366a | 260 | |
cb457d76 | 261 | for(i = 0; i < nb_nics; i++) |
07caea31 | 262 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
0d913fdb | 263 | |
e4bcb14c | 264 | |
75717903 | 265 | ide_drive_get(hd, MAX_IDE_BUS); |
bd4524ed | 266 | |
d037834a | 267 | macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); |
07a7484e | 268 | dev = DEVICE(macio); |
45fa67fb AF |
269 | qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ |
270 | qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE */ | |
271 | qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ | |
272 | macio_init(macio, pic_mem, escc_bar); | |
07a7484e AF |
273 | |
274 | /* First IDE channel is a MAC IDE on the MacIO bus */ | |
275 | macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), | |
276 | "ide")); | |
277 | macio_ide_init_drives(macio_ide, hd); | |
278 | ||
279 | /* Second IDE channel is a CMD646 on the PCI bus */ | |
280 | hd[0] = hd[MAX_IDE_DEVS]; | |
281 | hd[1] = hd[MAX_IDE_DEVS + 1]; | |
282 | hd[3] = hd[2] = NULL; | |
283 | pci_cmd646_ide_init(pci_bus, hd, 0); | |
3cbee15b | 284 | |
293c867d AF |
285 | dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); |
286 | adb_bus = qdev_get_child_bus(dev, "adb.0"); | |
287 | dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); | |
2e4a7c9c | 288 | qdev_init_nofail(dev); |
293c867d | 289 | dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); |
2e4a7c9c | 290 | qdev_init_nofail(dev); |
45fa67fb | 291 | |
094b287f | 292 | if (usb_enabled(false)) { |
afb9a60e | 293 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
3cbee15b JM |
294 | } |
295 | ||
296 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) | |
297 | graphic_depth = 15; | |
298 | ||
3cbee15b JM |
299 | /* No PCI init: the BIOS will do it */ |
300 | ||
271dd5e0 | 301 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
70db9222 | 302 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
271dd5e0 BS |
303 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
304 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
305 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); | |
513f789f BS |
306 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); |
307 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
308 | if (kernel_cmdline) { | |
b9e17a34 AG |
309 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); |
310 | pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); | |
513f789f BS |
311 | } else { |
312 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
313 | } | |
314 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
315 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
316 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); | |
7f1aec5f LV |
317 | |
318 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); | |
319 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); | |
320 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); | |
321 | ||
45024f09 | 322 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); |
dc333cd6 AG |
323 | if (kvm_enabled()) { |
324 | #ifdef CONFIG_KVM | |
45024f09 AG |
325 | uint8_t *hypercall; |
326 | ||
dc333cd6 | 327 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); |
7267c094 | 328 | hypercall = g_malloc(16); |
45024f09 AG |
329 | kvmppc_get_hypercall(env, hypercall, 16); |
330 | fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); | |
331 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); | |
dc333cd6 AG |
332 | #endif |
333 | } else { | |
334 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec()); | |
335 | } | |
a1014f25 AG |
336 | /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ |
337 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000); | |
dc333cd6 | 338 | |
513f789f | 339 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3cbee15b JM |
340 | } |
341 | ||
f80f9ec9 | 342 | static QEMUMachine heathrow_machine = { |
4d7ca41e | 343 | .name = "g3beige", |
4b32e168 AL |
344 | .desc = "Heathrow based PowerMAC", |
345 | .init = ppc_heathrow_init, | |
3d878caa | 346 | .max_cpus = MAX_CPUS, |
46214a27 | 347 | #ifndef TARGET_PPC64 |
0c257437 | 348 | .is_default = 1, |
46214a27 | 349 | #endif |
e4ada29e | 350 | DEFAULT_MACHINE_OPTIONS, |
3cbee15b | 351 | }; |
f80f9ec9 AL |
352 | |
353 | static void heathrow_machine_init(void) | |
354 | { | |
355 | qemu_register_machine(&heathrow_machine); | |
356 | } | |
357 | ||
358 | machine_init(heathrow_machine_init); |