[mirror_qemu.git] / hw / ppc / mac_oldworld.c


/*
 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "mac.h"
#include "hw/input/adb.h"
#include "hw/timer/m48t59.h"
#include "sysemu/sysemu.h"
#include "net/net.h"
#include "hw/isa/isa.h"
#include "hw/pci/pci.h"
#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
#include "hw/ide.h"
#include "hw/loader.h"
#include "elf.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"

#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510
#define TBFREQ 16600000UL

static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
    return 0;
}


static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static hwaddr round_page(hwaddr addr)
{
    return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}

static void ppc_heathrow_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static void ppc_heathrow_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    const char *boot_device = machine->boot_order;
    MemoryRegion *sysmem = get_system_memory();
    PowerPCCPU *cpu = NULL;
    CPUPPCState *env = NULL;
    char *filename;
    qemu_irq *pic, **heathrow_irqs;
    int linux_boot, i;
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *isa = g_new(MemoryRegion, 1);
    uint32_t kernel_base, initrd_base, cmdline_base = 0;
    int32_t kernel_size, initrd_size;
    PCIBus *pci_bus;
    PCIDevice *macio;
    MACIOIDEState *macio_ide;
    DeviceState *dev;
    BusState *adb_bus;
    int bios_size;
    MemoryRegion *pic_mem;
    MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
    uint16_t ppc_boot_device;
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    void *fw_cfg;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "G3";
    for (i = 0; i < smp_cpus; i++) {
        cpu = cpu_ppc_init(cpu_model);
        if (cpu == NULL) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        env = &cpu->env;

        /* Set time-base frequency to 16.6 Mhz */
        cpu_ppc_tb_init(env,  TBFREQ);
        qemu_register_reset(ppc_heathrow_reset, cpu);
    }

    /* allocate RAM */
    if (ram_size > (2047 << 20)) {
        fprintf(stderr,
                "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
                ((unsigned int)ram_size / (1 << 20)));
        exit(1);
    }

    memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(sysmem, 0, ram);

    /* allocate and load BIOS */
    memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE);
    vmstate_register_ram_global(bios);
    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    memory_region_set_readonly(bios, true);
    memory_region_add_subregion(sysmem, PROM_ADDR, bios);

    /* Load OpenBIOS (ELF) */
    if (filename) {
        bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
                             1, ELF_MACHINE, 0);
        g_free(filename);
    } else {
        bios_size = -1;
    }
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
        exit(1);
    }

    if (linux_boot) {
        uint64_t lowaddr = 0;
        int bswap_needed;

#ifdef BSWAP_NEEDED
        bswap_needed = 1;
#else
        bswap_needed = 0;
#endif
        kernel_base = KERNEL_LOAD_ADDR;
        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, kernel_base,
                                    ram_size - kernel_base, bswap_needed,
                                    TARGET_PAGE_SIZE);
        if (kernel_size < 0)
            kernel_size = load_image_targphys(kernel_filename,
                                              kernel_base,
                                              ram_size - kernel_base);
        if (kernel_size < 0) {
            hw_error("qemu: could not load kernel '%s'\n",
                      kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                hw_error("qemu: could not load initial ram disk '%s'\n",
                         initrd_filename);
                exit(1);
            }
            cmdline_base = round_page(initrd_base + initrd_size);
        } else {
            initrd_base = 0;
            initrd_size = 0;
            cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
        }
        ppc_boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
        ppc_boot_device = '\0';
        for (i = 0; boot_device[i] != '\0'; i++) {
            /* TOFIX: for now, the second IDE channel is not properly
             *        used by OHW. The Mac floppy disk are not emulated.
             *        For now, OHW cannot boot from the network.
             */
#if 0
            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
                ppc_boot_device = boot_device[i];
                break;
            }
#else
            if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
                ppc_boot_device = boot_device[i];
                break;
            }
#endif
        }
        if (ppc_boot_device == '\0') {
            fprintf(stderr, "No valid boot device for G3 Beige machine\n");
            exit(1);
        }
    }

    /* Register 2 MB of ISA IO space */
    memory_region_init_alias(isa, NULL, "isa_mmio",
                             get_system_io(), 0, 0x00200000);
    memory_region_add_subregion(sysmem, 0xfe000000, isa);

    /* XXX: we register only 1 output pin for heathrow PIC */
    heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
    heathrow_irqs[0] =
        g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
    /* Connect the heathrow PIC outputs to the 6xx bus */
    for (i = 0; i < smp_cpus; i++) {
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
            heathrow_irqs[i][0] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            break;
        default:
            hw_error("Bus model not supported on OldWorld Mac machine\n");
        }
    }

    /* init basic PC hardware */
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
        hw_error("Only 6xx bus is supported on heathrow machine\n");
    }
    pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
    pci_bus = pci_grackle_init(0xfec00000, pic,
                               get_system_memory(),
                               get_system_io());
    pci_vga_init(pci_bus);

    escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
                               serial_hds[1], ESCC_CLOCK, 4);
    memory_region_init_alias(escc_bar, NULL, "escc-bar",
                             escc_mem, 0, memory_region_size(escc_mem));

    for(i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);


    ide_drive_get(hd, MAX_IDE_BUS);

    macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
    dev = DEVICE(macio);
    qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
    qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
    qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
    qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
    qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
    macio_init(macio, pic_mem, escc_bar);

    macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
                                                        "ide[0]"));
    macio_ide_init_drives(macio_ide, hd);

    macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
                                                        "ide[1]"));
    macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);

    dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
    adb_bus = qdev_get_child_bus(dev, "adb.0");
    dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
    qdev_init_nofail(dev);
    dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
    qdev_init_nofail(dev);

    if (usb_enabled(false)) {
        pci_create_simple(pci_bus, -1, "pci-ohci");
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    /* No PCI init: the BIOS will do it */

    fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
    if (kernel_cmdline) {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
    } else {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
    }
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);

    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);

    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        uint8_t *hypercall;

        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
        hypercall = g_malloc(16);
        kvmppc_get_hypercall(env, hypercall, 16);
        fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
    } else {
        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ);
    }
    /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000);

    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}

static QEMUMachine heathrow_machine = {
    .name = "g3beige",
    .desc = "Heathrow based PowerMAC",
    .init = ppc_heathrow_init,
    .max_cpus = MAX_CPUS,
#ifndef TARGET_PPC64
    .is_default = 1,
#endif
    .default_boot_order = "cd", /* TOFIX "cad" when Mac floppy is implemented */
};

static void heathrow_machine_init(void)
{
    qemu_register_machine(&heathrow_machine);
}

machine_init(heathrow_machine_init);
Commit	Line	Data
ae0bfb79	1
3cbee15b	2	/*
4d7ca41e	3	* QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
3cbee15b JM	4	*
	5	* Copyright (c) 2004-2007 Fabrice Bellard
	6	* Copyright (c) 2007 Jocelyn Mayer
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
baec1910	26	#include "hw/hw.h"
0d09e41a	27	#include "hw/ppc/ppc.h"
baec1910	28	#include "mac.h"
0d09e41a PB	29	#include "hw/input/adb.h"
0d09e41a PB	30	#include "hw/timer/m48t59.h"
9c17d615	31	#include "sysemu/sysemu.h"
1422e32d	32	#include "net/net.h"
0d09e41a	33	#include "hw/isa/isa.h"
baec1910 AF	34	#include "hw/pci/pci.h"
baec1910 AF	35	#include "hw/boards.h"
0d09e41a PB	36	#include "hw/nvram/fw_cfg.h"
0d09e41a PB	37	#include "hw/char/escc.h"
baec1910 AF	38	#include "hw/ide.h"
baec1910 AF	39	#include "hw/loader.h"
ca20cf32	40	#include "elf.h"
9c17d615	41	#include "sysemu/kvm.h"
dc333cd6	42	#include "kvm_ppc.h"
9c17d615	43	#include "sysemu/blockdev.h"
022c62cb	44	#include "exec/address-spaces.h"
3cbee15b	45
e4bcb14c	46	#define MAX_IDE_BUS 2
271dd5e0	47	#define CFG_ADDR 0xf0000510
536d8cda	48	#define TBFREQ 16600000UL
271dd5e0	49
513f789f BS	50	static int fw_cfg_boot_set(void opaque, const char boot_device)
	51	{
	52	fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
	53	return 0;
	54	}
	55
409dbce5 AJ	56
	57	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	58	{
	59	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	60	}
	61
a8170e5e	62	static hwaddr round_page(hwaddr addr)
b9e17a34 AG	63	{
	64	return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
	65	}
	66
1bba0dc9 AF	67	static void ppc_heathrow_reset(void *opaque)
1bba0dc9 AF	68	{
cd79664f	69	PowerPCCPU *cpu = opaque;
1bba0dc9	70
cd79664f	71	cpu_reset(CPU(cpu));
1bba0dc9 AF	72	}
1bba0dc9 AF	73
3ef96221	74	static void ppc_heathrow_init(MachineState *machine)
3cbee15b	75	{
3ef96221 MA	76	ram_addr_t ram_size = machine->ram_size;
	77	const char *cpu_model = machine->cpu_model;
	78	const char *kernel_filename = machine->kernel_filename;
	79	const char *kernel_cmdline = machine->kernel_cmdline;
	80	const char *initrd_filename = machine->initrd_filename;
	81	const char *boot_device = machine->boot_order;
c92bb2c7	82	MemoryRegion *sysmem = get_system_memory();
72c33dd7	83	PowerPCCPU *cpu = NULL;
e2684c0b	84	CPUPPCState *env = NULL;
5cea8590	85	char *filename;
3cbee15b	86	qemu_irq pic, *heathrow_irqs;
3cbee15b	87	int linux_boot, i;
c92bb2c7 AK	88	MemoryRegion *ram = g_new(MemoryRegion, 1);
c92bb2c7 AK	89	MemoryRegion *bios = g_new(MemoryRegion, 1);
7d52857e	90	MemoryRegion *isa = g_new(MemoryRegion, 1);
b9e17a34	91	uint32_t kernel_base, initrd_base, cmdline_base = 0;
7373048c	92	int32_t kernel_size, initrd_size;
3cbee15b	93	PCIBus *pci_bus;
d037834a	94	PCIDevice *macio;
07a7484e AF	95	MACIOIDEState *macio_ide;
07a7484e AF	96	DeviceState *dev;
293c867d	97	BusState *adb_bus;
ae0bfb79	98	int bios_size;
45fa67fb	99	MemoryRegion *pic_mem;
07a7484e	100	MemoryRegion escc_mem, escc_bar = g_new(MemoryRegion, 1);
513f789f	101	uint16_t ppc_boot_device;
f455e98c	102	DriveInfo hd[MAX_IDE_BUS MAX_IDE_DEVS];
271dd5e0	103	void *fw_cfg;
3cbee15b JM	104
	105	linux_boot = (kernel_filename != NULL);
	106
	107	/* init CPUs */
3cbee15b	108	if (cpu_model == NULL)
f2fde45a	109	cpu_model = "G3";
3cbee15b	110	for (i = 0; i < smp_cpus; i++) {
72c33dd7 AF	111	cpu = cpu_ppc_init(cpu_model);
72c33dd7 AF	112	if (cpu == NULL) {
aaed909a FB	113	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	114	exit(1);
	115	}
72c33dd7 AF	116	env = &cpu->env;
72c33dd7 AF	117
b0fb43d8	118	/* Set time-base frequency to 16.6 Mhz */
536d8cda	119	cpu_ppc_tb_init(env, TBFREQ);
cd79664f	120	qemu_register_reset(ppc_heathrow_reset, cpu);
3cbee15b JM	121	}
	122
	123	/* allocate RAM */
6b4079f8 AJ	124	if (ram_size > (2047 << 20)) {
	125	fprintf(stderr,
	126	"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
	127	((unsigned int)ram_size / (1 << 20)));
	128	exit(1);
	129	}
	130
2c9b15ca	131	memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size);
c5705a77	132	vmstate_register_ram_global(ram);
c92bb2c7	133	memory_region_add_subregion(sysmem, 0, ram);
a748ab6d	134
3cbee15b	135	/* allocate and load BIOS */
2c9b15ca	136	memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE);
c5705a77	137	vmstate_register_ram_global(bios);
3cbee15b	138	if (bios_name == NULL)
992e5acd	139	bios_name = PROM_FILENAME;
5cea8590	140	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
c92bb2c7 AK	141	memory_region_set_readonly(bios, true);
c92bb2c7 AK	142	memory_region_add_subregion(sysmem, PROM_ADDR, bios);
992e5acd BS	143
992e5acd BS	144	/* Load OpenBIOS (ELF) */
5cea8590	145	if (filename) {
409dbce5 AJ	146	bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
409dbce5 AJ	147	1, ELF_MACHINE, 0);
7267c094	148	g_free(filename);
5cea8590 PB	149	} else {
	150	bios_size = -1;
	151	}
3cbee15b	152	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
5cea8590	153	hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
3cbee15b JM	154	exit(1);
3cbee15b JM	155	}
3cbee15b	156
3cbee15b	157	if (linux_boot) {
36bee1e3	158	uint64_t lowaddr = 0;
ca20cf32 BS	159	int bswap_needed;
	160
	161	#ifdef BSWAP_NEEDED
	162	bswap_needed = 1;
	163	#else
	164	bswap_needed = 0;
	165	#endif
3cbee15b	166	kernel_base = KERNEL_LOAD_ADDR;
409dbce5 AJ	167	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
409dbce5 AJ	168	NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
52f163b7 BS	169	if (kernel_size < 0)
52f163b7 BS	170	kernel_size = load_aout(kernel_filename, kernel_base,
ca20cf32 BS	171	ram_size - kernel_base, bswap_needed,
ca20cf32 BS	172	TARGET_PAGE_SIZE);
52f163b7 BS	173	if (kernel_size < 0)
	174	kernel_size = load_image_targphys(kernel_filename,
	175	kernel_base,
	176	ram_size - kernel_base);
3cbee15b	177	if (kernel_size < 0) {
2ac71179	178	hw_error("qemu: could not load kernel '%s'\n",
3cbee15b JM	179	kernel_filename);
	180	exit(1);
	181	}
	182	/* load initrd */
	183	if (initrd_filename) {
b9e17a34	184	initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
dcac9679 PB	185	initrd_size = load_image_targphys(initrd_filename, initrd_base,
dcac9679 PB	186	ram_size - initrd_base);
3cbee15b	187	if (initrd_size < 0) {
2ac71179 PB	188	hw_error("qemu: could not load initial ram disk '%s'\n",
2ac71179 PB	189	initrd_filename);
3cbee15b JM	190	exit(1);
3cbee15b JM	191	}
b9e17a34	192	cmdline_base = round_page(initrd_base + initrd_size);
3cbee15b JM	193	} else {
	194	initrd_base = 0;
	195	initrd_size = 0;
b9e17a34	196	cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
3cbee15b	197	}
6ac0e82d	198	ppc_boot_device = 'm';
3cbee15b JM	199	} else {
	200	kernel_base = 0;
	201	kernel_size = 0;
	202	initrd_base = 0;
	203	initrd_size = 0;
28c5af54	204	ppc_boot_device = '\0';
0d913fdb	205	for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54	206	/* TOFIX: for now, the second IDE channel is not properly
0d913fdb	207	* used by OHW. The Mac floppy disk are not emulated.
28c5af54 JM	208	* For now, OHW cannot boot from the network.
	209	*/
	210	#if 0
0d913fdb JM	211	if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
0d913fdb JM	212	ppc_boot_device = boot_device[i];
28c5af54	213	break;
0d913fdb	214	}
28c5af54	215	#else
0d913fdb JM	216	if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
0d913fdb JM	217	ppc_boot_device = boot_device[i];
28c5af54	218	break;
0d913fdb	219	}
28c5af54 JM	220	#endif
	221	}
	222	if (ppc_boot_device == '\0') {
8a901def	223	fprintf(stderr, "No valid boot device for G3 Beige machine\n");
28c5af54 JM	224	exit(1);
28c5af54 JM	225	}
3cbee15b JM	226	}
3cbee15b JM	227
3cbee15b	228	/* Register 2 MB of ISA IO space */
7d52857e PB	229	memory_region_init_alias(isa, NULL, "isa_mmio",
	230	get_system_io(), 0, 0x00200000);
	231	memory_region_add_subregion(sysmem, 0xfe000000, isa);
3cbee15b JM	232
3cbee15b JM	233	/* XXX: we register only 1 output pin for heathrow PIC */
7267c094	234	heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
3cbee15b	235	heathrow_irqs[0] =
7267c094	236	g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
3cbee15b JM	237	/* Connect the heathrow PIC outputs to the 6xx bus */
	238	for (i = 0; i < smp_cpus; i++) {
	239	switch (PPC_INPUT(env)) {
	240	case PPC_FLAGS_INPUT_6xx:
	241	heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
	242	heathrow_irqs[i][0] =
	243	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	244	break;
	245	default:
2ac71179	246	hw_error("Bus model not supported on OldWorld Mac machine\n");
3cbee15b JM	247	}
	248	}
	249
	250	/* init basic PC hardware */
	251	if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
2ac71179	252	hw_error("Only 6xx bus is supported on heathrow machine\n");
3cbee15b	253	}
23c5e4ca	254	pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
aee97b84 AK	255	pci_bus = pci_grackle_init(0xfec00000, pic,
	256	get_system_memory(),
	257	get_system_io());
3e20ad3a	258	pci_vga_init(pci_bus);
aae9366a	259
b39491a8	260	escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
7fa9ae1a	261	serial_hds[1], ESCC_CLOCK, 4);
2c9b15ca	262	memory_region_init_alias(escc_bar, NULL, "escc-bar",
5b15f275	263	escc_mem, 0, memory_region_size(escc_mem));
aae9366a	264
cb457d76	265	for(i = 0; i < nb_nics; i++)
29b358f9	266	pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
0d913fdb	267
e4bcb14c	268
75717903	269	ide_drive_get(hd, MAX_IDE_BUS);
bd4524ed	270
d037834a	271	macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
07a7484e	272	dev = DEVICE(macio);
45fa67fb	273	qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
14eefd0e AG	274	qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
	275	qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
	276	qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
	277	qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
45fa67fb	278	macio_init(macio, pic_mem, escc_bar);
07a7484e	279
07a7484e	280	macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
14eefd0e	281	"ide[0]"));
07a7484e AF	282	macio_ide_init_drives(macio_ide, hd);
07a7484e AF	283
14eefd0e AG	284	macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
	285	"ide[1]"));
	286	macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
3cbee15b	287
293c867d AF	288	dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
	289	adb_bus = qdev_get_child_bus(dev, "adb.0");
	290	dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
2e4a7c9c	291	qdev_init_nofail(dev);
293c867d	292	dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
2e4a7c9c	293	qdev_init_nofail(dev);
45fa67fb	294
094b287f	295	if (usb_enabled(false)) {
afb9a60e	296	pci_create_simple(pci_bus, -1, "pci-ohci");
3cbee15b JM	297	}
	298
	299	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
	300	graphic_depth = 15;
	301
3cbee15b JM	302	/* No PCI init: the BIOS will do it */
3cbee15b JM	303
271dd5e0	304	fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
70db9222	305	fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
271dd5e0 BS	306	fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
	307	fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
	308	fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
513f789f BS	309	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
	310	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
	311	if (kernel_cmdline) {
b9e17a34 AG	312	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
b9e17a34 AG	313	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
513f789f BS	314	} else {
	315	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
	316	}
	317	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
	318	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
	319	fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
7f1aec5f LV	320
	321	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
	322	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
	323	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
	324
45024f09	325	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
dc333cd6 AG	326	if (kvm_enabled()) {
dc333cd6 AG	327	#ifdef CONFIG_KVM
45024f09 AG	328	uint8_t *hypercall;
45024f09 AG	329
dc333cd6	330	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
7267c094	331	hypercall = g_malloc(16);
45024f09 AG	332	kvmppc_get_hypercall(env, hypercall, 16);
	333	fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
	334	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
dc333cd6 AG	335	#endif
dc333cd6 AG	336	} else {
536d8cda	337	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ);
dc333cd6	338	}
a1014f25 AG	339	/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
a1014f25 AG	340	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000);
dc333cd6	341
513f789f	342	qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
3cbee15b JM	343	}
3cbee15b JM	344
f80f9ec9	345	static QEMUMachine heathrow_machine = {
4d7ca41e	346	.name = "g3beige",
4b32e168 AL	347	.desc = "Heathrow based PowerMAC",
4b32e168 AL	348	.init = ppc_heathrow_init,
3d878caa	349	.max_cpus = MAX_CPUS,
46214a27	350	#ifndef TARGET_PPC64
0c257437	351	.is_default = 1,
46214a27	352	#endif
c1654732	353	.default_boot_order = "cd", /* TOFIX "cad" when Mac floppy is implemented */
3cbee15b	354	};
f80f9ec9 AL	355
	356	static void heathrow_machine_init(void)
	357	{
	358	qemu_register_machine(&heathrow_machine);
	359	}
	360
	361	machine_init(heathrow_machine_init);