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Commit | Line | Data |
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ba7e5ac1 BZ |
1 | /* |
2 | * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator | |
3 | * | |
a8eda5ed | 4 | * Copyright (c) 2018-2021 BALATON Zoltan |
ba7e5ac1 BZ |
5 | * |
6 | * This work is licensed under the GNU GPL license version 2 or later. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
ba7e5ac1 BZ |
11 | #include "qemu/units.h" |
12 | #include "qapi/error.h" | |
13 | #include "hw/hw.h" | |
14 | #include "hw/ppc/ppc.h" | |
15 | #include "hw/sysbus.h" | |
16 | #include "hw/pci/pci_host.h" | |
17 | #include "hw/irq.h" | |
18 | #include "hw/pci-host/mv64361.h" | |
19 | #include "hw/isa/vt82c686.h" | |
20 | #include "hw/ide/pci.h" | |
21 | #include "hw/i2c/smbus_eeprom.h" | |
22 | #include "hw/qdev-properties.h" | |
23 | #include "sysemu/reset.h" | |
284c0486 | 24 | #include "sysemu/runstate.h" |
88adcbf2 | 25 | #include "sysemu/qtest.h" |
ba7e5ac1 BZ |
26 | #include "hw/boards.h" |
27 | #include "hw/loader.h" | |
28 | #include "hw/fw-path-provider.h" | |
29 | #include "elf.h" | |
30 | #include "qemu/log.h" | |
31 | #include "qemu/error-report.h" | |
32 | #include "sysemu/kvm.h" | |
33 | #include "kvm_ppc.h" | |
34 | #include "exec/address-spaces.h" | |
94cd1ffb BZ |
35 | #include "qom/qom-qobject.h" |
36 | #include "qapi/qmp/qdict.h" | |
ba7e5ac1 BZ |
37 | #include "trace.h" |
38 | #include "qemu/datadir.h" | |
39 | #include "sysemu/device_tree.h" | |
a6c9808a | 40 | #include "hw/ppc/vof.h" |
ba7e5ac1 | 41 | |
a6c9808a BZ |
42 | #include <libfdt.h> |
43 | ||
44 | #define PROM_FILENAME "vof.bin" | |
ba7e5ac1 BZ |
45 | #define PROM_ADDR 0xfff00000 |
46 | #define PROM_SIZE 0x80000 | |
47 | ||
a6c9808a | 48 | #define KVMPPC_HCALL_BASE 0xf000 |
5f2eb049 | 49 | #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) |
a6c9808a BZ |
50 | #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) |
51 | ||
52 | #define H_SUCCESS 0 | |
53 | #define H_PRIVILEGE -3 /* Caller not privileged */ | |
54 | #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ | |
55 | ||
ba7e5ac1 BZ |
56 | #define BUS_FREQ_HZ 133333333 |
57 | ||
d200ea14 | 58 | #define PCI0_CFG_ADDR 0xcf8 |
a6c9808a BZ |
59 | #define PCI0_MEM_BASE 0xc0000000 |
60 | #define PCI0_MEM_SIZE 0x20000000 | |
61 | #define PCI0_IO_BASE 0xf8000000 | |
62 | #define PCI0_IO_SIZE 0x10000 | |
63 | ||
d200ea14 | 64 | #define PCI1_CFG_ADDR 0xc78 |
a6c9808a BZ |
65 | #define PCI1_MEM_BASE 0x80000000 |
66 | #define PCI1_MEM_SIZE 0x40000000 | |
67 | #define PCI1_IO_BASE 0xfe000000 | |
68 | #define PCI1_IO_SIZE 0x10000 | |
69 | ||
a8eda5ed BZ |
70 | #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") |
71 | OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) | |
72 | ||
73 | struct Pegasos2MachineState { | |
74 | MachineState parent_obj; | |
75 | PowerPCCPU *cpu; | |
76 | DeviceState *mv; | |
a6c9808a BZ |
77 | Vof *vof; |
78 | void *fdt_blob; | |
79 | uint64_t kernel_addr; | |
80 | uint64_t kernel_entry; | |
81 | uint64_t kernel_size; | |
a8eda5ed BZ |
82 | }; |
83 | ||
a6c9808a BZ |
84 | static void *build_fdt(MachineState *machine, int *fdt_size); |
85 | ||
ba7e5ac1 BZ |
86 | static void pegasos2_cpu_reset(void *opaque) |
87 | { | |
88 | PowerPCCPU *cpu = opaque; | |
a6c9808a | 89 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); |
ba7e5ac1 BZ |
90 | |
91 | cpu_reset(CPU(cpu)); | |
92 | cpu->env.spr[SPR_HID1] = 7ULL << 28; | |
a6c9808a BZ |
93 | if (pm->vof) { |
94 | cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; | |
95 | cpu->env.nip = 0x100; | |
96 | } | |
ba7e5ac1 BZ |
97 | } |
98 | ||
99 | static void pegasos2_init(MachineState *machine) | |
100 | { | |
a8eda5ed BZ |
101 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); |
102 | CPUPPCState *env; | |
ba7e5ac1 | 103 | MemoryRegion *rom = g_new(MemoryRegion, 1); |
ba7e5ac1 BZ |
104 | PCIBus *pci_bus; |
105 | PCIDevice *dev; | |
106 | I2CBus *i2c_bus; | |
107 | const char *fwname = machine->firmware ?: PROM_FILENAME; | |
108 | char *filename; | |
109 | int sz; | |
110 | uint8_t *spd_data; | |
111 | ||
112 | /* init CPU */ | |
a8eda5ed BZ |
113 | pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
114 | env = &pm->cpu->env; | |
115 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
ba7e5ac1 BZ |
116 | error_report("Incompatible CPU, only 6xx bus supported"); |
117 | exit(1); | |
118 | } | |
119 | ||
120 | /* Set time-base frequency */ | |
a8eda5ed BZ |
121 | cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); |
122 | qemu_register_reset(pegasos2_cpu_reset, pm->cpu); | |
ba7e5ac1 BZ |
123 | |
124 | /* RAM */ | |
239fec24 BZ |
125 | if (machine->ram_size > 2 * GiB) { |
126 | error_report("RAM size more than 2 GiB is not supported"); | |
127 | exit(1); | |
128 | } | |
ba7e5ac1 BZ |
129 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
130 | ||
131 | /* allocate and load firmware */ | |
132 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); | |
133 | if (!filename) { | |
134 | error_report("Could not find firmware '%s'", fwname); | |
135 | exit(1); | |
136 | } | |
a6c9808a BZ |
137 | if (!machine->firmware && !pm->vof) { |
138 | pm->vof = g_malloc0(sizeof(*pm->vof)); | |
139 | } | |
ba7e5ac1 BZ |
140 | memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); |
141 | memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); | |
142 | sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, | |
143 | PPC_ELF_MACHINE, 0, 0); | |
144 | if (sz <= 0) { | |
a6c9808a | 145 | sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); |
ba7e5ac1 BZ |
146 | } |
147 | if (sz <= 0 || sz > PROM_SIZE) { | |
148 | error_report("Could not load firmware '%s'", filename); | |
149 | exit(1); | |
150 | } | |
151 | g_free(filename); | |
a6c9808a BZ |
152 | if (pm->vof) { |
153 | pm->vof->fw_size = sz; | |
154 | } | |
ba7e5ac1 BZ |
155 | |
156 | /* Marvell Discovery II system controller */ | |
a8eda5ed | 157 | pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, |
0f3e0c6f | 158 | qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT))); |
a8eda5ed | 159 | pci_bus = mv64361_get_pci_bus(pm->mv, 1); |
ba7e5ac1 BZ |
160 | |
161 | /* VIA VT8231 South Bridge (multifunction PCI device) */ | |
162 | /* VT8231 function 0: PCI-to-ISA Bridge */ | |
163 | dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true, | |
164 | TYPE_VT8231_ISA); | |
165 | qdev_connect_gpio_out(DEVICE(dev), 0, | |
a8eda5ed | 166 | qdev_get_gpio_in_named(pm->mv, "gpp", 31)); |
ba7e5ac1 BZ |
167 | |
168 | /* VT8231 function 1: IDE Controller */ | |
169 | dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide"); | |
170 | pci_ide_create_devs(dev); | |
171 | ||
172 | /* VT8231 function 2-3: USB Ports */ | |
173 | pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci"); | |
174 | pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci"); | |
175 | ||
176 | /* VT8231 function 4: Power Management Controller */ | |
177 | dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM); | |
178 | i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); | |
179 | spd_data = spd_data_generate(DDR, machine->ram_size); | |
180 | smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); | |
181 | ||
182 | /* VT8231 function 5-6: AC97 Audio & Modem */ | |
183 | pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97); | |
184 | pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97); | |
185 | ||
186 | /* other PC hardware */ | |
187 | pci_vga_init(pci_bus); | |
a6c9808a BZ |
188 | |
189 | if (machine->kernel_filename) { | |
190 | sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, | |
191 | &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, | |
192 | PPC_ELF_MACHINE, 0, 0); | |
193 | if (sz <= 0) { | |
194 | error_report("Could not load kernel '%s'", | |
195 | machine->kernel_filename); | |
196 | exit(1); | |
197 | } | |
198 | pm->kernel_size = sz; | |
199 | if (!pm->vof) { | |
200 | warn_report("Option -kernel may be ineffective with -bios."); | |
201 | } | |
88adcbf2 | 202 | } else if (pm->vof && !qtest_enabled()) { |
99173b67 | 203 | warn_report("Using Virtual OpenFirmware but no -kernel option."); |
a6c9808a | 204 | } |
99173b67 | 205 | |
6ebc0048 | 206 | if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { |
a6c9808a BZ |
207 | warn_report("Option -append may be ineffective with -bios."); |
208 | } | |
209 | } | |
210 | ||
bd20cde5 BZ |
211 | static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, |
212 | uint32_t addr, uint32_t len) | |
213 | { | |
214 | MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); | |
215 | uint64_t val = 0xffffffffULL; | |
216 | memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, | |
217 | MEMTXATTRS_UNSPECIFIED); | |
218 | return val; | |
219 | } | |
220 | ||
221 | static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, | |
222 | uint32_t len, uint32_t val) | |
223 | { | |
224 | MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); | |
225 | memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, | |
226 | MEMTXATTRS_UNSPECIFIED); | |
227 | } | |
228 | ||
229 | static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, | |
5f2eb049 BZ |
230 | uint32_t addr, uint32_t len) |
231 | { | |
d200ea14 | 232 | hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; |
bd20cde5 BZ |
233 | uint64_t val = 0xffffffffULL; |
234 | ||
235 | if (len <= 4) { | |
236 | pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); | |
237 | val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); | |
5f2eb049 BZ |
238 | } |
239 | return val; | |
240 | } | |
241 | ||
bd20cde5 BZ |
242 | static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, |
243 | uint32_t addr, uint32_t len, uint32_t val) | |
a6c9808a | 244 | { |
d200ea14 | 245 | hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; |
bd20cde5 BZ |
246 | |
247 | pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); | |
248 | pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); | |
a6c9808a BZ |
249 | } |
250 | ||
251 | static void pegasos2_machine_reset(MachineState *machine) | |
252 | { | |
253 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); | |
a6c9808a BZ |
254 | void *fdt; |
255 | uint64_t d[2]; | |
256 | int sz; | |
257 | ||
258 | qemu_devices_reset(); | |
259 | if (!pm->vof) { | |
260 | return; /* Firmware should set up machine so nothing to do */ | |
261 | } | |
262 | ||
263 | /* Otherwise, set up devices that board firmware would normally do */ | |
bd20cde5 BZ |
264 | pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); |
265 | pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); | |
266 | pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); | |
267 | pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); | |
268 | pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); | |
269 | pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | | |
a6c9808a | 270 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
bd20cde5 | 271 | pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | |
a6c9808a BZ |
272 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
273 | ||
bd20cde5 | 274 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | |
a6c9808a | 275 | PCI_INTERRUPT_LINE, 2, 0x9); |
bd20cde5 | 276 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | |
a6c9808a BZ |
277 | 0x50, 1, 0x2); |
278 | ||
bd20cde5 | 279 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 280 | PCI_INTERRUPT_LINE, 2, 0x109); |
bd20cde5 | 281 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 282 | PCI_CLASS_PROG, 1, 0xf); |
bd20cde5 | 283 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 284 | 0x40, 1, 0xb); |
bd20cde5 | 285 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 286 | 0x50, 4, 0x17171717); |
bd20cde5 | 287 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a BZ |
288 | PCI_COMMAND, 2, 0x87); |
289 | ||
bd20cde5 | 290 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | |
a6c9808a BZ |
291 | PCI_INTERRUPT_LINE, 2, 0x409); |
292 | ||
bd20cde5 | 293 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | |
a6c9808a BZ |
294 | PCI_INTERRUPT_LINE, 2, 0x409); |
295 | ||
bd20cde5 | 296 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 297 | PCI_INTERRUPT_LINE, 2, 0x9); |
bd20cde5 | 298 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 299 | 0x48, 4, 0xf00); |
bd20cde5 | 300 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 301 | 0x40, 4, 0x558020); |
bd20cde5 | 302 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a BZ |
303 | 0x90, 4, 0xd00); |
304 | ||
bd20cde5 | 305 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | |
a6c9808a BZ |
306 | PCI_INTERRUPT_LINE, 2, 0x309); |
307 | ||
bd20cde5 | 308 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | |
a6c9808a BZ |
309 | PCI_INTERRUPT_LINE, 2, 0x309); |
310 | ||
311 | /* Device tree and VOF set up */ | |
312 | vof_init(pm->vof, machine->ram_size, &error_fatal); | |
313 | if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { | |
314 | error_report("Memory allocation for stack failed"); | |
315 | exit(1); | |
316 | } | |
317 | if (pm->kernel_size && | |
318 | vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { | |
319 | error_report("Memory for kernel is in use"); | |
320 | exit(1); | |
321 | } | |
322 | fdt = build_fdt(machine, &sz); | |
323 | /* FIXME: VOF assumes entry is same as load address */ | |
324 | d[0] = cpu_to_be64(pm->kernel_entry); | |
325 | d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); | |
326 | qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); | |
327 | ||
328 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
329 | g_free(pm->fdt_blob); | |
330 | pm->fdt_blob = fdt; | |
331 | ||
332 | vof_build_dt(fdt, pm->vof); | |
333 | vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); | |
334 | pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); | |
335 | } | |
336 | ||
5f2eb049 BZ |
337 | enum pegasos2_rtas_tokens { |
338 | RTAS_RESTART_RTAS = 0, | |
339 | RTAS_NVRAM_FETCH = 1, | |
340 | RTAS_NVRAM_STORE = 2, | |
341 | RTAS_GET_TIME_OF_DAY = 3, | |
342 | RTAS_SET_TIME_OF_DAY = 4, | |
343 | RTAS_EVENT_SCAN = 6, | |
344 | RTAS_CHECK_EXCEPTION = 7, | |
345 | RTAS_READ_PCI_CONFIG = 8, | |
346 | RTAS_WRITE_PCI_CONFIG = 9, | |
347 | RTAS_DISPLAY_CHARACTER = 10, | |
348 | RTAS_SET_INDICATOR = 11, | |
349 | RTAS_POWER_OFF = 17, | |
350 | RTAS_SUSPEND = 18, | |
351 | RTAS_HIBERNATE = 19, | |
352 | RTAS_SYSTEM_REBOOT = 20, | |
353 | }; | |
354 | ||
355 | static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, | |
356 | target_ulong args_real) | |
357 | { | |
358 | AddressSpace *as = CPU(cpu)->as; | |
359 | uint32_t token = ldl_be_phys(as, args_real); | |
360 | uint32_t nargs = ldl_be_phys(as, args_real + 4); | |
361 | uint32_t nrets = ldl_be_phys(as, args_real + 8); | |
362 | uint32_t args = args_real + 12; | |
363 | uint32_t rets = args_real + 12 + nargs * 4; | |
364 | ||
365 | if (nrets < 1) { | |
366 | qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); | |
367 | return H_PARAMETER; | |
368 | } | |
369 | switch (token) { | |
94cd1ffb BZ |
370 | case RTAS_GET_TIME_OF_DAY: |
371 | { | |
372 | QObject *qo = object_property_get_qobject(qdev_get_machine(), | |
373 | "rtc-time", &error_fatal); | |
374 | QDict *qd = qobject_to(QDict, qo); | |
375 | ||
376 | if (nargs != 0 || nrets != 8 || !qd) { | |
377 | stl_be_phys(as, rets, -1); | |
378 | qobject_unref(qo); | |
379 | return H_PARAMETER; | |
380 | } | |
381 | ||
382 | stl_be_phys(as, rets, 0); | |
383 | stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); | |
384 | stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); | |
385 | stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); | |
386 | stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); | |
387 | stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); | |
388 | stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); | |
389 | stl_be_phys(as, rets + 28, 0); | |
390 | qobject_unref(qo); | |
391 | return H_SUCCESS; | |
392 | } | |
5f2eb049 BZ |
393 | case RTAS_READ_PCI_CONFIG: |
394 | { | |
395 | uint32_t addr, len, val; | |
396 | ||
397 | if (nargs != 2 || nrets != 2) { | |
398 | stl_be_phys(as, rets, -1); | |
399 | return H_PARAMETER; | |
400 | } | |
401 | addr = ldl_be_phys(as, args); | |
402 | len = ldl_be_phys(as, args + 4); | |
bd20cde5 | 403 | val = pegasos2_pci_config_read(pm, !(addr >> 24), |
5f2eb049 BZ |
404 | addr & 0x0fffffff, len); |
405 | stl_be_phys(as, rets, 0); | |
406 | stl_be_phys(as, rets + 4, val); | |
407 | return H_SUCCESS; | |
408 | } | |
409 | case RTAS_WRITE_PCI_CONFIG: | |
410 | { | |
411 | uint32_t addr, len, val; | |
412 | ||
413 | if (nargs != 3 || nrets != 1) { | |
414 | stl_be_phys(as, rets, -1); | |
415 | return H_PARAMETER; | |
416 | } | |
417 | addr = ldl_be_phys(as, args); | |
418 | len = ldl_be_phys(as, args + 4); | |
419 | val = ldl_be_phys(as, args + 8); | |
bd20cde5 | 420 | pegasos2_pci_config_write(pm, !(addr >> 24), |
5f2eb049 BZ |
421 | addr & 0x0fffffff, len, val); |
422 | stl_be_phys(as, rets, 0); | |
423 | return H_SUCCESS; | |
424 | } | |
425 | case RTAS_DISPLAY_CHARACTER: | |
426 | if (nargs != 1 || nrets != 1) { | |
427 | stl_be_phys(as, rets, -1); | |
428 | return H_PARAMETER; | |
429 | } | |
430 | qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); | |
431 | stl_be_phys(as, rets, 0); | |
432 | return H_SUCCESS; | |
284c0486 BZ |
433 | case RTAS_POWER_OFF: |
434 | { | |
435 | if (nargs != 2 || nrets != 1) { | |
436 | stl_be_phys(as, rets, -1); | |
437 | return H_PARAMETER; | |
438 | } | |
439 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
440 | stl_be_phys(as, rets, 0); | |
441 | return H_SUCCESS; | |
442 | } | |
5f2eb049 BZ |
443 | default: |
444 | qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", | |
445 | token, nargs, nrets); | |
446 | stl_be_phys(as, rets, 0); | |
447 | return H_SUCCESS; | |
448 | } | |
449 | } | |
450 | ||
7cebc5db NP |
451 | static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu) |
452 | { | |
453 | return false; | |
454 | } | |
455 | ||
a6c9808a BZ |
456 | static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) |
457 | { | |
458 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); | |
459 | CPUPPCState *env = &cpu->env; | |
460 | ||
461 | /* The TCG path should also be holding the BQL at this point */ | |
462 | g_assert(qemu_mutex_iothread_locked()); | |
463 | ||
d41ccf6e | 464 | if (FIELD_EX64(env->msr, MSR, PR)) { |
a6c9808a BZ |
465 | qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); |
466 | env->gpr[3] = H_PRIVILEGE; | |
5f2eb049 BZ |
467 | } else if (env->gpr[3] == KVMPPC_H_RTAS) { |
468 | env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); | |
a6c9808a BZ |
469 | } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { |
470 | int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, | |
471 | env->gpr[4]); | |
472 | env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); | |
473 | } else { | |
474 | qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx | |
475 | "\n", env->gpr[3]); | |
476 | env->gpr[3] = -1; | |
477 | } | |
478 | } | |
479 | ||
480 | static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) | |
481 | { | |
482 | } | |
483 | ||
484 | static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) | |
485 | { | |
486 | return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; | |
ba7e5ac1 BZ |
487 | } |
488 | ||
a312aaeb BZ |
489 | static bool pegasos2_setprop(MachineState *ms, const char *path, |
490 | const char *propname, void *val, int vallen) | |
491 | { | |
492 | return true; | |
493 | } | |
494 | ||
a8eda5ed | 495 | static void pegasos2_machine_class_init(ObjectClass *oc, void *data) |
ba7e5ac1 | 496 | { |
a8eda5ed | 497 | MachineClass *mc = MACHINE_CLASS(oc); |
a6c9808a | 498 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
a312aaeb | 499 | VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); |
a8eda5ed | 500 | |
ba7e5ac1 BZ |
501 | mc->desc = "Genesi/bPlan Pegasos II"; |
502 | mc->init = pegasos2_init; | |
a6c9808a | 503 | mc->reset = pegasos2_machine_reset; |
ba7e5ac1 BZ |
504 | mc->block_default_type = IF_IDE; |
505 | mc->default_boot_order = "cd"; | |
506 | mc->default_display = "std"; | |
507 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); | |
508 | mc->default_ram_id = "pegasos2.ram"; | |
509 | mc->default_ram_size = 512 * MiB; | |
a6c9808a | 510 | |
7cebc5db | 511 | vhc->cpu_in_nested = pegasos2_cpu_in_nested; |
a6c9808a BZ |
512 | vhc->hypercall = pegasos2_hypercall; |
513 | vhc->cpu_exec_enter = vhyp_nop; | |
514 | vhc->cpu_exec_exit = vhyp_nop; | |
515 | vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; | |
a312aaeb BZ |
516 | |
517 | vmc->setprop = pegasos2_setprop; | |
ba7e5ac1 BZ |
518 | } |
519 | ||
a8eda5ed BZ |
520 | static const TypeInfo pegasos2_machine_info = { |
521 | .name = TYPE_PEGASOS2_MACHINE, | |
522 | .parent = TYPE_MACHINE, | |
523 | .class_init = pegasos2_machine_class_init, | |
524 | .instance_size = sizeof(Pegasos2MachineState), | |
a6c9808a BZ |
525 | .interfaces = (InterfaceInfo[]) { |
526 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, | |
a312aaeb | 527 | { TYPE_VOF_MACHINE_IF }, |
a6c9808a BZ |
528 | { } |
529 | }, | |
a8eda5ed BZ |
530 | }; |
531 | ||
532 | static void pegasos2_machine_register_types(void) | |
533 | { | |
534 | type_register_static(&pegasos2_machine_info); | |
535 | } | |
536 | ||
537 | type_init(pegasos2_machine_register_types) | |
a6c9808a BZ |
538 | |
539 | /* FDT creation for passing to firmware */ | |
540 | ||
541 | typedef struct { | |
542 | void *fdt; | |
543 | const char *path; | |
544 | } FDTInfo; | |
545 | ||
546 | /* We do everything in reverse order so it comes out right in the tree */ | |
547 | ||
548 | static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
549 | { | |
550 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); | |
551 | } | |
552 | ||
553 | static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
554 | { | |
555 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); | |
556 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); | |
557 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); | |
558 | } | |
559 | ||
560 | static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
561 | { | |
562 | GString *name = g_string_sized_new(64); | |
563 | uint32_t cells[3]; | |
564 | ||
565 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); | |
566 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); | |
567 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); | |
568 | qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); | |
569 | ||
570 | /* addional devices */ | |
571 | g_string_printf(name, "%s/lpt@i3bc", fi->path); | |
572 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
573 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
574 | cells[0] = cpu_to_be32(7); | |
575 | cells[1] = 0; | |
576 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
577 | cells, 2 * sizeof(cells[0])); | |
578 | cells[0] = cpu_to_be32(1); | |
579 | cells[1] = cpu_to_be32(0x3bc); | |
580 | cells[2] = cpu_to_be32(8); | |
581 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
582 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); | |
583 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); | |
584 | ||
585 | g_string_printf(name, "%s/fdc@i3f0", fi->path); | |
586 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
587 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
588 | cells[0] = cpu_to_be32(6); | |
589 | cells[1] = 0; | |
590 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
591 | cells, 2 * sizeof(cells[0])); | |
592 | cells[0] = cpu_to_be32(1); | |
593 | cells[1] = cpu_to_be32(0x3f0); | |
594 | cells[2] = cpu_to_be32(8); | |
595 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
596 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); | |
597 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); | |
598 | ||
599 | g_string_printf(name, "%s/timer@i40", fi->path); | |
600 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
601 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
602 | cells[0] = cpu_to_be32(1); | |
603 | cells[1] = cpu_to_be32(0x40); | |
604 | cells[2] = cpu_to_be32(8); | |
605 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
606 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); | |
607 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); | |
608 | ||
609 | g_string_printf(name, "%s/rtc@i70", fi->path); | |
610 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
611 | qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); | |
612 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
613 | cells[0] = cpu_to_be32(8); | |
614 | cells[1] = 0; | |
615 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
616 | cells, 2 * sizeof(cells[0])); | |
617 | cells[0] = cpu_to_be32(1); | |
618 | cells[1] = cpu_to_be32(0x70); | |
619 | cells[2] = cpu_to_be32(2); | |
620 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
621 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); | |
622 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); | |
623 | ||
624 | g_string_printf(name, "%s/keyboard@i60", fi->path); | |
625 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
626 | cells[0] = cpu_to_be32(1); | |
627 | cells[1] = 0; | |
628 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
629 | cells, 2 * sizeof(cells[0])); | |
630 | cells[0] = cpu_to_be32(1); | |
631 | cells[1] = cpu_to_be32(0x60); | |
632 | cells[2] = cpu_to_be32(5); | |
633 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
634 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); | |
635 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); | |
636 | ||
637 | g_string_printf(name, "%s/8042@i60", fi->path); | |
638 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
639 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); | |
640 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); | |
641 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); | |
642 | qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); | |
643 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
644 | cells[0] = cpu_to_be32(1); | |
645 | cells[1] = cpu_to_be32(0x60); | |
646 | cells[2] = cpu_to_be32(5); | |
647 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
648 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); | |
649 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); | |
650 | ||
651 | g_string_printf(name, "%s/serial@i2f8", fi->path); | |
652 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
653 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
654 | cells[0] = cpu_to_be32(3); | |
655 | cells[1] = 0; | |
656 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
657 | cells, 2 * sizeof(cells[0])); | |
658 | cells[0] = cpu_to_be32(1); | |
659 | cells[1] = cpu_to_be32(0x2f8); | |
660 | cells[2] = cpu_to_be32(8); | |
661 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
662 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); | |
663 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); | |
664 | ||
665 | g_string_free(name, TRUE); | |
666 | } | |
667 | ||
668 | static struct { | |
669 | const char *id; | |
670 | const char *name; | |
671 | void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); | |
672 | } device_map[] = { | |
673 | { "pci11ab,6460", "host", NULL }, | |
674 | { "pci1106,8231", "isa", dt_isa }, | |
675 | { "pci1106,571", "ide", dt_ide }, | |
676 | { "pci1106,3044", "firewire", NULL }, | |
677 | { "pci1106,3038", "usb", dt_usb }, | |
678 | { "pci1106,8235", "other", NULL }, | |
679 | { "pci1106,3058", "sound", NULL }, | |
680 | { NULL, NULL } | |
681 | }; | |
682 | ||
683 | static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) | |
684 | { | |
685 | FDTInfo *fi = opaque; | |
686 | GString *node = g_string_new(NULL); | |
687 | uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; | |
688 | int i, j; | |
689 | const char *name = NULL; | |
690 | g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", | |
691 | pci_get_word(&d->config[PCI_VENDOR_ID]), | |
692 | pci_get_word(&d->config[PCI_DEVICE_ID])); | |
693 | ||
694 | for (i = 0; device_map[i].id; i++) { | |
695 | if (!strcmp(pn, device_map[i].id)) { | |
696 | name = device_map[i].name; | |
697 | break; | |
698 | } | |
699 | } | |
700 | g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), | |
701 | PCI_SLOT(d->devfn)); | |
702 | if (PCI_FUNC(d->devfn)) { | |
703 | g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); | |
704 | } | |
705 | ||
706 | qemu_fdt_add_subnode(fi->fdt, node->str); | |
707 | if (device_map[i].dtf) { | |
708 | FDTInfo cfi = { fi->fdt, node->str }; | |
709 | device_map[i].dtf(bus, d, &cfi); | |
710 | } | |
711 | cells[0] = cpu_to_be32(d->devfn << 8); | |
712 | cells[1] = 0; | |
713 | cells[2] = 0; | |
714 | cells[3] = 0; | |
715 | cells[4] = 0; | |
716 | j = 5; | |
717 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
718 | if (!d->io_regions[i].size) { | |
719 | continue; | |
720 | } | |
721 | cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); | |
722 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
723 | cells[j] |= cpu_to_be32(1 << 24); | |
724 | } else { | |
725 | cells[j] |= cpu_to_be32(2 << 24); | |
726 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
727 | cells[j] |= cpu_to_be32(4 << 28); | |
728 | } | |
729 | } | |
730 | cells[j + 1] = 0; | |
731 | cells[j + 2] = 0; | |
732 | cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); | |
733 | cells[j + 4] = cpu_to_be32(d->io_regions[i].size); | |
734 | j += 5; | |
735 | } | |
736 | qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); | |
737 | qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); | |
738 | if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { | |
739 | qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", | |
740 | pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); | |
741 | } | |
742 | /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ | |
743 | qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", | |
744 | pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); | |
745 | qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", | |
746 | pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); | |
747 | cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); | |
748 | qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); | |
e7dfb29e | 749 | qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); |
a6c9808a BZ |
750 | qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", |
751 | pci_get_word(&d->config[PCI_DEVICE_ID])); | |
752 | qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", | |
753 | pci_get_word(&d->config[PCI_VENDOR_ID])); | |
754 | ||
755 | g_string_free(node, TRUE); | |
756 | } | |
757 | ||
758 | static void *build_fdt(MachineState *machine, int *fdt_size) | |
759 | { | |
760 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); | |
761 | PowerPCCPU *cpu = pm->cpu; | |
762 | PCIBus *pci_bus; | |
763 | FDTInfo fi; | |
764 | uint32_t cells[16]; | |
765 | void *fdt = create_device_tree(fdt_size); | |
766 | ||
767 | fi.fdt = fdt; | |
768 | ||
769 | /* root node */ | |
770 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", | |
771 | "Pegasos CHRP PowerPC System"); | |
772 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); | |
773 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); | |
774 | qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); | |
775 | qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); | |
776 | qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); | |
777 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); | |
778 | qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); | |
779 | ||
780 | /* pci@c0000000 */ | |
781 | qemu_fdt_add_subnode(fdt, "/pci@c0000000"); | |
782 | cells[0] = 0; | |
783 | cells[1] = 0; | |
784 | qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", | |
785 | cells, 2 * sizeof(cells[0])); | |
786 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); | |
787 | cells[0] = cpu_to_be32(PCI0_MEM_BASE); | |
788 | cells[1] = cpu_to_be32(PCI0_MEM_SIZE); | |
789 | qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); | |
790 | cells[0] = cpu_to_be32(0x01000000); | |
791 | cells[1] = 0; | |
792 | cells[2] = 0; | |
793 | cells[3] = cpu_to_be32(PCI0_IO_BASE); | |
794 | cells[4] = 0; | |
795 | cells[5] = cpu_to_be32(PCI0_IO_SIZE); | |
796 | cells[6] = cpu_to_be32(0x02000000); | |
797 | cells[7] = 0; | |
798 | cells[8] = cpu_to_be32(PCI0_MEM_BASE); | |
799 | cells[9] = cpu_to_be32(PCI0_MEM_BASE); | |
800 | cells[10] = 0; | |
801 | cells[11] = cpu_to_be32(PCI0_MEM_SIZE); | |
802 | qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", | |
803 | cells, 12 * sizeof(cells[0])); | |
804 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); | |
805 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); | |
806 | qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); | |
807 | qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); | |
808 | ||
809 | fi.path = "/pci@c0000000"; | |
810 | pci_bus = mv64361_get_pci_bus(pm->mv, 0); | |
811 | pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); | |
812 | ||
813 | /* pci@80000000 */ | |
814 | qemu_fdt_add_subnode(fdt, "/pci@80000000"); | |
815 | cells[0] = 0; | |
816 | cells[1] = 0; | |
817 | qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", | |
818 | cells, 2 * sizeof(cells[0])); | |
819 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); | |
820 | cells[0] = cpu_to_be32(PCI1_MEM_BASE); | |
821 | cells[1] = cpu_to_be32(PCI1_MEM_SIZE); | |
822 | qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); | |
823 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", | |
824 | 0xf1000cb4); | |
825 | cells[0] = cpu_to_be32(0x01000000); | |
826 | cells[1] = 0; | |
827 | cells[2] = 0; | |
828 | cells[3] = cpu_to_be32(PCI1_IO_BASE); | |
829 | cells[4] = 0; | |
830 | cells[5] = cpu_to_be32(PCI1_IO_SIZE); | |
831 | cells[6] = cpu_to_be32(0x02000000); | |
832 | cells[7] = 0; | |
833 | cells[8] = cpu_to_be32(PCI1_MEM_BASE); | |
834 | cells[9] = cpu_to_be32(PCI1_MEM_BASE); | |
835 | cells[10] = 0; | |
836 | cells[11] = cpu_to_be32(PCI1_MEM_SIZE); | |
837 | qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", | |
838 | cells, 12 * sizeof(cells[0])); | |
839 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); | |
840 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); | |
841 | qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); | |
842 | qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); | |
843 | ||
844 | fi.path = "/pci@80000000"; | |
845 | pci_bus = mv64361_get_pci_bus(pm->mv, 1); | |
846 | pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); | |
847 | ||
848 | qemu_fdt_add_subnode(fdt, "/failsafe"); | |
849 | qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); | |
850 | qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); | |
851 | ||
5f2eb049 BZ |
852 | qemu_fdt_add_subnode(fdt, "/rtas"); |
853 | qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); | |
854 | qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); | |
855 | qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); | |
856 | qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); | |
857 | qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); | |
858 | qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", | |
859 | RTAS_DISPLAY_CHARACTER); | |
860 | qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", | |
861 | RTAS_WRITE_PCI_CONFIG); | |
862 | qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", | |
863 | RTAS_READ_PCI_CONFIG); | |
864 | /* Pegasos2 firmware misspells check-exception and guests use that */ | |
865 | qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", | |
866 | RTAS_CHECK_EXCEPTION); | |
867 | qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); | |
868 | qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", | |
869 | RTAS_SET_TIME_OF_DAY); | |
870 | qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", | |
871 | RTAS_GET_TIME_OF_DAY); | |
872 | qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); | |
873 | qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); | |
874 | qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); | |
875 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); | |
876 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); | |
877 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); | |
878 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); | |
879 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); | |
880 | ||
a6c9808a BZ |
881 | /* cpus */ |
882 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
883 | qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); | |
884 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
885 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
886 | qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); | |
887 | ||
888 | /* FIXME Get CPU name from CPU object */ | |
889 | const char *cp = "/cpus/PowerPC,G4"; | |
890 | qemu_fdt_add_subnode(fdt, cp); | |
891 | qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); | |
892 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); | |
893 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", | |
894 | cpu->env.dcache_line_size); | |
895 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", | |
896 | cpu->env.dcache_line_size); | |
897 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); | |
898 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", | |
899 | cpu->env.icache_line_size); | |
900 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", | |
901 | cpu->env.icache_line_size); | |
902 | if (cpu->env.id_tlbs) { | |
903 | qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); | |
904 | qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); | |
905 | qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); | |
906 | qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); | |
907 | qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); | |
908 | } | |
909 | qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); | |
910 | qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); | |
911 | qemu_fdt_setprop_string(fdt, cp, "state", "running"); | |
912 | if (cpu->env.insns_flags & PPC_ALTIVEC) { | |
913 | qemu_fdt_setprop_string(fdt, cp, "altivec", ""); | |
914 | qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); | |
915 | } | |
916 | /* | |
917 | * FIXME What flags do data-streams, external-control and | |
918 | * performance-monitor depend on? | |
919 | */ | |
920 | qemu_fdt_setprop_string(fdt, cp, "external-control", ""); | |
921 | if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { | |
922 | qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); | |
923 | } | |
924 | qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); | |
925 | if (cpu->env.insns_flags & PPC_FLOAT_FRES) { | |
926 | qemu_fdt_setprop_string(fdt, cp, "graphics", ""); | |
927 | } | |
928 | qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); | |
929 | qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", | |
930 | cpu->env.tb_env->tb_freq); | |
931 | qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); | |
932 | qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); | |
933 | qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); | |
934 | cells[0] = 0; | |
935 | cells[1] = 0; | |
936 | qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); | |
937 | qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); | |
938 | qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); | |
939 | ||
940 | /* memory */ | |
941 | qemu_fdt_add_subnode(fdt, "/memory@0"); | |
942 | cells[0] = 0; | |
943 | cells[1] = cpu_to_be32(machine->ram_size); | |
944 | qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); | |
945 | qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); | |
946 | qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); | |
947 | ||
948 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
949 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", | |
950 | machine->kernel_cmdline ?: ""); | |
951 | qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); | |
952 | ||
953 | qemu_fdt_add_subnode(fdt, "/openprom"); | |
954 | qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); | |
955 | ||
956 | return fdt; | |
957 | } |