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Commit | Line | Data |
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ba7e5ac1 BZ |
1 | /* |
2 | * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator | |
3 | * | |
a8eda5ed | 4 | * Copyright (c) 2018-2021 BALATON Zoltan |
ba7e5ac1 BZ |
5 | * |
6 | * This work is licensed under the GNU GPL license version 2 or later. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
ba7e5ac1 BZ |
11 | #include "qemu/units.h" |
12 | #include "qapi/error.h" | |
ba7e5ac1 BZ |
13 | #include "hw/ppc/ppc.h" |
14 | #include "hw/sysbus.h" | |
15 | #include "hw/pci/pci_host.h" | |
16 | #include "hw/irq.h" | |
17 | #include "hw/pci-host/mv64361.h" | |
18 | #include "hw/isa/vt82c686.h" | |
19 | #include "hw/ide/pci.h" | |
20 | #include "hw/i2c/smbus_eeprom.h" | |
21 | #include "hw/qdev-properties.h" | |
22 | #include "sysemu/reset.h" | |
284c0486 | 23 | #include "sysemu/runstate.h" |
88adcbf2 | 24 | #include "sysemu/qtest.h" |
ba7e5ac1 BZ |
25 | #include "hw/boards.h" |
26 | #include "hw/loader.h" | |
27 | #include "hw/fw-path-provider.h" | |
28 | #include "elf.h" | |
29 | #include "qemu/log.h" | |
30 | #include "qemu/error-report.h" | |
31 | #include "sysemu/kvm.h" | |
32 | #include "kvm_ppc.h" | |
33 | #include "exec/address-spaces.h" | |
94cd1ffb BZ |
34 | #include "qom/qom-qobject.h" |
35 | #include "qapi/qmp/qdict.h" | |
ba7e5ac1 BZ |
36 | #include "trace.h" |
37 | #include "qemu/datadir.h" | |
38 | #include "sysemu/device_tree.h" | |
a6c9808a | 39 | #include "hw/ppc/vof.h" |
ba7e5ac1 | 40 | |
a6c9808a BZ |
41 | #include <libfdt.h> |
42 | ||
43 | #define PROM_FILENAME "vof.bin" | |
ba7e5ac1 BZ |
44 | #define PROM_ADDR 0xfff00000 |
45 | #define PROM_SIZE 0x80000 | |
46 | ||
ebe0e9bb BZ |
47 | #define INITRD_MIN_ADDR 0x600000 |
48 | ||
a6c9808a | 49 | #define KVMPPC_HCALL_BASE 0xf000 |
5f2eb049 | 50 | #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) |
a6c9808a BZ |
51 | #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) |
52 | ||
53 | #define H_SUCCESS 0 | |
54 | #define H_PRIVILEGE -3 /* Caller not privileged */ | |
55 | #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ | |
56 | ||
ba7e5ac1 BZ |
57 | #define BUS_FREQ_HZ 133333333 |
58 | ||
d200ea14 | 59 | #define PCI0_CFG_ADDR 0xcf8 |
a6c9808a BZ |
60 | #define PCI0_MEM_BASE 0xc0000000 |
61 | #define PCI0_MEM_SIZE 0x20000000 | |
62 | #define PCI0_IO_BASE 0xf8000000 | |
63 | #define PCI0_IO_SIZE 0x10000 | |
64 | ||
d200ea14 | 65 | #define PCI1_CFG_ADDR 0xc78 |
a6c9808a BZ |
66 | #define PCI1_MEM_BASE 0x80000000 |
67 | #define PCI1_MEM_SIZE 0x40000000 | |
68 | #define PCI1_IO_BASE 0xfe000000 | |
69 | #define PCI1_IO_SIZE 0x10000 | |
70 | ||
a8eda5ed BZ |
71 | #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") |
72 | OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) | |
73 | ||
74 | struct Pegasos2MachineState { | |
75 | MachineState parent_obj; | |
76 | PowerPCCPU *cpu; | |
77 | DeviceState *mv; | |
fb27a3e9 BZ |
78 | qemu_irq mv_pirq[PCI_NUM_PINS]; |
79 | qemu_irq via_pirq[PCI_NUM_PINS]; | |
a6c9808a BZ |
80 | Vof *vof; |
81 | void *fdt_blob; | |
82 | uint64_t kernel_addr; | |
83 | uint64_t kernel_entry; | |
84 | uint64_t kernel_size; | |
ebe0e9bb BZ |
85 | uint64_t initrd_addr; |
86 | uint64_t initrd_size; | |
a8eda5ed BZ |
87 | }; |
88 | ||
a6c9808a BZ |
89 | static void *build_fdt(MachineState *machine, int *fdt_size); |
90 | ||
ba7e5ac1 BZ |
91 | static void pegasos2_cpu_reset(void *opaque) |
92 | { | |
93 | PowerPCCPU *cpu = opaque; | |
a6c9808a | 94 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); |
ba7e5ac1 BZ |
95 | |
96 | cpu_reset(CPU(cpu)); | |
97 | cpu->env.spr[SPR_HID1] = 7ULL << 28; | |
a6c9808a BZ |
98 | if (pm->vof) { |
99 | cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; | |
100 | cpu->env.nip = 0x100; | |
101 | } | |
ba7e5ac1 BZ |
102 | } |
103 | ||
fb27a3e9 BZ |
104 | static void pegasos2_pci_irq(void *opaque, int n, int level) |
105 | { | |
106 | Pegasos2MachineState *pm = opaque; | |
107 | ||
108 | /* PCI interrupt lines are connected to both MV64361 and VT8231 */ | |
109 | qemu_set_irq(pm->mv_pirq[n], level); | |
110 | qemu_set_irq(pm->via_pirq[n], level); | |
111 | } | |
112 | ||
ba7e5ac1 BZ |
113 | static void pegasos2_init(MachineState *machine) |
114 | { | |
a8eda5ed BZ |
115 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); |
116 | CPUPPCState *env; | |
ba7e5ac1 | 117 | MemoryRegion *rom = g_new(MemoryRegion, 1); |
ba7e5ac1 | 118 | PCIBus *pci_bus; |
65133e33 BZ |
119 | Object *via; |
120 | PCIDevice *dev; | |
ba7e5ac1 BZ |
121 | I2CBus *i2c_bus; |
122 | const char *fwname = machine->firmware ?: PROM_FILENAME; | |
123 | char *filename; | |
ebe0e9bb BZ |
124 | int i; |
125 | ssize_t sz; | |
ba7e5ac1 BZ |
126 | uint8_t *spd_data; |
127 | ||
128 | /* init CPU */ | |
a8eda5ed BZ |
129 | pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
130 | env = &pm->cpu->env; | |
131 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
ba7e5ac1 BZ |
132 | error_report("Incompatible CPU, only 6xx bus supported"); |
133 | exit(1); | |
134 | } | |
135 | ||
136 | /* Set time-base frequency */ | |
a8eda5ed BZ |
137 | cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); |
138 | qemu_register_reset(pegasos2_cpu_reset, pm->cpu); | |
ba7e5ac1 BZ |
139 | |
140 | /* RAM */ | |
239fec24 BZ |
141 | if (machine->ram_size > 2 * GiB) { |
142 | error_report("RAM size more than 2 GiB is not supported"); | |
143 | exit(1); | |
144 | } | |
ba7e5ac1 BZ |
145 | memory_region_add_subregion(get_system_memory(), 0, machine->ram); |
146 | ||
147 | /* allocate and load firmware */ | |
148 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); | |
149 | if (!filename) { | |
150 | error_report("Could not find firmware '%s'", fwname); | |
151 | exit(1); | |
152 | } | |
a6c9808a BZ |
153 | if (!machine->firmware && !pm->vof) { |
154 | pm->vof = g_malloc0(sizeof(*pm->vof)); | |
155 | } | |
ba7e5ac1 BZ |
156 | memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); |
157 | memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); | |
158 | sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, | |
159 | PPC_ELF_MACHINE, 0, 0); | |
160 | if (sz <= 0) { | |
a6c9808a | 161 | sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); |
ba7e5ac1 BZ |
162 | } |
163 | if (sz <= 0 || sz > PROM_SIZE) { | |
164 | error_report("Could not load firmware '%s'", filename); | |
165 | exit(1); | |
166 | } | |
167 | g_free(filename); | |
a6c9808a BZ |
168 | if (pm->vof) { |
169 | pm->vof->fw_size = sz; | |
170 | } | |
ba7e5ac1 BZ |
171 | |
172 | /* Marvell Discovery II system controller */ | |
a8eda5ed | 173 | pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, |
0f3e0c6f | 174 | qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT))); |
fb27a3e9 BZ |
175 | for (i = 0; i < PCI_NUM_PINS; i++) { |
176 | pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); | |
177 | } | |
a8eda5ed | 178 | pci_bus = mv64361_get_pci_bus(pm->mv, 1); |
fb27a3e9 | 179 | pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); |
ba7e5ac1 BZ |
180 | |
181 | /* VIA VT8231 South Bridge (multifunction PCI device) */ | |
65133e33 BZ |
182 | via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), |
183 | true, TYPE_VT8231_ISA)); | |
fb27a3e9 BZ |
184 | for (i = 0; i < PCI_NUM_PINS; i++) { |
185 | pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i); | |
186 | } | |
ff9105da | 187 | object_property_add_alias(OBJECT(machine), "rtc-time", |
65133e33 | 188 | object_resolve_path_component(via, "rtc"), |
ff9105da | 189 | "date"); |
9eb6abbf | 190 | qdev_connect_gpio_out(DEVICE(via), 0, |
a8eda5ed | 191 | qdev_get_gpio_in_named(pm->mv, "gpp", 31)); |
ba7e5ac1 | 192 | |
65133e33 | 193 | dev = PCI_DEVICE(object_resolve_path_component(via, "ide")); |
ba7e5ac1 BZ |
194 | pci_ide_create_devs(dev); |
195 | ||
65133e33 | 196 | dev = PCI_DEVICE(object_resolve_path_component(via, "pm")); |
ba7e5ac1 BZ |
197 | i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); |
198 | spd_data = spd_data_generate(DDR, machine->ram_size); | |
199 | smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); | |
200 | ||
ba7e5ac1 BZ |
201 | /* other PC hardware */ |
202 | pci_vga_init(pci_bus); | |
a6c9808a BZ |
203 | |
204 | if (machine->kernel_filename) { | |
205 | sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, | |
206 | &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, | |
207 | PPC_ELF_MACHINE, 0, 0); | |
208 | if (sz <= 0) { | |
209 | error_report("Could not load kernel '%s'", | |
210 | machine->kernel_filename); | |
211 | exit(1); | |
212 | } | |
213 | pm->kernel_size = sz; | |
214 | if (!pm->vof) { | |
215 | warn_report("Option -kernel may be ineffective with -bios."); | |
216 | } | |
88adcbf2 | 217 | } else if (pm->vof && !qtest_enabled()) { |
99173b67 | 218 | warn_report("Using Virtual OpenFirmware but no -kernel option."); |
a6c9808a | 219 | } |
99173b67 | 220 | |
ebe0e9bb BZ |
221 | if (machine->initrd_filename) { |
222 | pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB; | |
223 | pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4); | |
224 | pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR); | |
225 | sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr, | |
226 | machine->ram_size - pm->initrd_addr); | |
227 | if (sz <= 0) { | |
228 | error_report("Could not load initrd '%s'", | |
229 | machine->initrd_filename); | |
230 | exit(1); | |
231 | } | |
232 | pm->initrd_size = sz; | |
233 | } | |
234 | ||
6ebc0048 | 235 | if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { |
a6c9808a BZ |
236 | warn_report("Option -append may be ineffective with -bios."); |
237 | } | |
238 | } | |
239 | ||
bd20cde5 BZ |
240 | static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, |
241 | uint32_t addr, uint32_t len) | |
242 | { | |
243 | MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); | |
244 | uint64_t val = 0xffffffffULL; | |
245 | memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, | |
246 | MEMTXATTRS_UNSPECIFIED); | |
247 | return val; | |
248 | } | |
249 | ||
250 | static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, | |
251 | uint32_t len, uint32_t val) | |
252 | { | |
253 | MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); | |
254 | memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, | |
255 | MEMTXATTRS_UNSPECIFIED); | |
256 | } | |
257 | ||
258 | static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, | |
5f2eb049 BZ |
259 | uint32_t addr, uint32_t len) |
260 | { | |
d200ea14 | 261 | hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; |
bd20cde5 BZ |
262 | uint64_t val = 0xffffffffULL; |
263 | ||
264 | if (len <= 4) { | |
265 | pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); | |
266 | val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); | |
5f2eb049 BZ |
267 | } |
268 | return val; | |
269 | } | |
270 | ||
bd20cde5 BZ |
271 | static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, |
272 | uint32_t addr, uint32_t len, uint32_t val) | |
a6c9808a | 273 | { |
d200ea14 | 274 | hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; |
bd20cde5 BZ |
275 | |
276 | pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); | |
277 | pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); | |
a6c9808a BZ |
278 | } |
279 | ||
7966d70f | 280 | static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason) |
a6c9808a BZ |
281 | { |
282 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); | |
a6c9808a BZ |
283 | void *fdt; |
284 | uint64_t d[2]; | |
285 | int sz; | |
286 | ||
7966d70f | 287 | qemu_devices_reset(reason); |
a6c9808a BZ |
288 | if (!pm->vof) { |
289 | return; /* Firmware should set up machine so nothing to do */ | |
290 | } | |
291 | ||
292 | /* Otherwise, set up devices that board firmware would normally do */ | |
bd20cde5 BZ |
293 | pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); |
294 | pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); | |
295 | pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); | |
296 | pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); | |
297 | pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); | |
298 | pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | | |
a6c9808a | 299 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
bd20cde5 | 300 | pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | |
a6c9808a BZ |
301 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
302 | ||
bd20cde5 | 303 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | |
a6c9808a | 304 | PCI_INTERRUPT_LINE, 2, 0x9); |
bd20cde5 | 305 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | |
a6c9808a | 306 | 0x50, 1, 0x2); |
fb27a3e9 BZ |
307 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | |
308 | 0x55, 1, 0x90); | |
309 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | | |
310 | 0x56, 1, 0x99); | |
311 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | | |
312 | 0x57, 1, 0x90); | |
a6c9808a | 313 | |
bd20cde5 | 314 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 315 | PCI_INTERRUPT_LINE, 2, 0x109); |
bd20cde5 | 316 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 317 | PCI_CLASS_PROG, 1, 0xf); |
bd20cde5 | 318 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 319 | 0x40, 1, 0xb); |
bd20cde5 | 320 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a | 321 | 0x50, 4, 0x17171717); |
bd20cde5 | 322 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | |
a6c9808a BZ |
323 | PCI_COMMAND, 2, 0x87); |
324 | ||
bd20cde5 | 325 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | |
a6c9808a BZ |
326 | PCI_INTERRUPT_LINE, 2, 0x409); |
327 | ||
bd20cde5 | 328 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | |
a6c9808a BZ |
329 | PCI_INTERRUPT_LINE, 2, 0x409); |
330 | ||
bd20cde5 | 331 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 332 | PCI_INTERRUPT_LINE, 2, 0x9); |
bd20cde5 | 333 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 334 | 0x48, 4, 0xf00); |
bd20cde5 | 335 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a | 336 | 0x40, 4, 0x558020); |
bd20cde5 | 337 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | |
a6c9808a BZ |
338 | 0x90, 4, 0xd00); |
339 | ||
bd20cde5 | 340 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | |
a6c9808a BZ |
341 | PCI_INTERRUPT_LINE, 2, 0x309); |
342 | ||
bd20cde5 | 343 | pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | |
a6c9808a BZ |
344 | PCI_INTERRUPT_LINE, 2, 0x309); |
345 | ||
346 | /* Device tree and VOF set up */ | |
347 | vof_init(pm->vof, machine->ram_size, &error_fatal); | |
348 | if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { | |
349 | error_report("Memory allocation for stack failed"); | |
350 | exit(1); | |
351 | } | |
352 | if (pm->kernel_size && | |
353 | vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { | |
354 | error_report("Memory for kernel is in use"); | |
355 | exit(1); | |
356 | } | |
ebe0e9bb BZ |
357 | if (pm->initrd_size && |
358 | vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) { | |
359 | error_report("Memory for initrd is in use"); | |
360 | exit(1); | |
361 | } | |
a6c9808a BZ |
362 | fdt = build_fdt(machine, &sz); |
363 | /* FIXME: VOF assumes entry is same as load address */ | |
364 | d[0] = cpu_to_be64(pm->kernel_entry); | |
365 | d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); | |
366 | qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); | |
367 | ||
368 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
369 | g_free(pm->fdt_blob); | |
370 | pm->fdt_blob = fdt; | |
371 | ||
372 | vof_build_dt(fdt, pm->vof); | |
373 | vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); | |
8d55f876 DHB |
374 | |
375 | /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ | |
376 | machine->fdt = fdt; | |
377 | ||
a6c9808a BZ |
378 | pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); |
379 | } | |
380 | ||
5f2eb049 BZ |
381 | enum pegasos2_rtas_tokens { |
382 | RTAS_RESTART_RTAS = 0, | |
383 | RTAS_NVRAM_FETCH = 1, | |
384 | RTAS_NVRAM_STORE = 2, | |
385 | RTAS_GET_TIME_OF_DAY = 3, | |
386 | RTAS_SET_TIME_OF_DAY = 4, | |
387 | RTAS_EVENT_SCAN = 6, | |
388 | RTAS_CHECK_EXCEPTION = 7, | |
389 | RTAS_READ_PCI_CONFIG = 8, | |
390 | RTAS_WRITE_PCI_CONFIG = 9, | |
391 | RTAS_DISPLAY_CHARACTER = 10, | |
392 | RTAS_SET_INDICATOR = 11, | |
393 | RTAS_POWER_OFF = 17, | |
394 | RTAS_SUSPEND = 18, | |
395 | RTAS_HIBERNATE = 19, | |
396 | RTAS_SYSTEM_REBOOT = 20, | |
397 | }; | |
398 | ||
399 | static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, | |
400 | target_ulong args_real) | |
401 | { | |
402 | AddressSpace *as = CPU(cpu)->as; | |
403 | uint32_t token = ldl_be_phys(as, args_real); | |
404 | uint32_t nargs = ldl_be_phys(as, args_real + 4); | |
405 | uint32_t nrets = ldl_be_phys(as, args_real + 8); | |
406 | uint32_t args = args_real + 12; | |
407 | uint32_t rets = args_real + 12 + nargs * 4; | |
408 | ||
409 | if (nrets < 1) { | |
410 | qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); | |
411 | return H_PARAMETER; | |
412 | } | |
413 | switch (token) { | |
94cd1ffb BZ |
414 | case RTAS_GET_TIME_OF_DAY: |
415 | { | |
416 | QObject *qo = object_property_get_qobject(qdev_get_machine(), | |
417 | "rtc-time", &error_fatal); | |
418 | QDict *qd = qobject_to(QDict, qo); | |
419 | ||
420 | if (nargs != 0 || nrets != 8 || !qd) { | |
421 | stl_be_phys(as, rets, -1); | |
422 | qobject_unref(qo); | |
423 | return H_PARAMETER; | |
424 | } | |
425 | ||
426 | stl_be_phys(as, rets, 0); | |
427 | stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); | |
428 | stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); | |
429 | stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); | |
430 | stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); | |
431 | stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); | |
432 | stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); | |
433 | stl_be_phys(as, rets + 28, 0); | |
434 | qobject_unref(qo); | |
435 | return H_SUCCESS; | |
436 | } | |
5f2eb049 BZ |
437 | case RTAS_READ_PCI_CONFIG: |
438 | { | |
439 | uint32_t addr, len, val; | |
440 | ||
441 | if (nargs != 2 || nrets != 2) { | |
442 | stl_be_phys(as, rets, -1); | |
443 | return H_PARAMETER; | |
444 | } | |
445 | addr = ldl_be_phys(as, args); | |
446 | len = ldl_be_phys(as, args + 4); | |
bd20cde5 | 447 | val = pegasos2_pci_config_read(pm, !(addr >> 24), |
5f2eb049 BZ |
448 | addr & 0x0fffffff, len); |
449 | stl_be_phys(as, rets, 0); | |
450 | stl_be_phys(as, rets + 4, val); | |
451 | return H_SUCCESS; | |
452 | } | |
453 | case RTAS_WRITE_PCI_CONFIG: | |
454 | { | |
455 | uint32_t addr, len, val; | |
456 | ||
457 | if (nargs != 3 || nrets != 1) { | |
458 | stl_be_phys(as, rets, -1); | |
459 | return H_PARAMETER; | |
460 | } | |
461 | addr = ldl_be_phys(as, args); | |
462 | len = ldl_be_phys(as, args + 4); | |
463 | val = ldl_be_phys(as, args + 8); | |
bd20cde5 | 464 | pegasos2_pci_config_write(pm, !(addr >> 24), |
5f2eb049 BZ |
465 | addr & 0x0fffffff, len, val); |
466 | stl_be_phys(as, rets, 0); | |
467 | return H_SUCCESS; | |
468 | } | |
469 | case RTAS_DISPLAY_CHARACTER: | |
470 | if (nargs != 1 || nrets != 1) { | |
471 | stl_be_phys(as, rets, -1); | |
472 | return H_PARAMETER; | |
473 | } | |
474 | qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); | |
475 | stl_be_phys(as, rets, 0); | |
476 | return H_SUCCESS; | |
284c0486 BZ |
477 | case RTAS_POWER_OFF: |
478 | { | |
479 | if (nargs != 2 || nrets != 1) { | |
480 | stl_be_phys(as, rets, -1); | |
481 | return H_PARAMETER; | |
482 | } | |
483 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
484 | stl_be_phys(as, rets, 0); | |
485 | return H_SUCCESS; | |
486 | } | |
5f2eb049 BZ |
487 | default: |
488 | qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", | |
489 | token, nargs, nrets); | |
490 | stl_be_phys(as, rets, 0); | |
491 | return H_SUCCESS; | |
492 | } | |
493 | } | |
494 | ||
7cebc5db NP |
495 | static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu) |
496 | { | |
497 | return false; | |
498 | } | |
499 | ||
a6c9808a BZ |
500 | static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) |
501 | { | |
502 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); | |
503 | CPUPPCState *env = &cpu->env; | |
504 | ||
505 | /* The TCG path should also be holding the BQL at this point */ | |
506 | g_assert(qemu_mutex_iothread_locked()); | |
507 | ||
d41ccf6e | 508 | if (FIELD_EX64(env->msr, MSR, PR)) { |
a6c9808a BZ |
509 | qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); |
510 | env->gpr[3] = H_PRIVILEGE; | |
5f2eb049 BZ |
511 | } else if (env->gpr[3] == KVMPPC_H_RTAS) { |
512 | env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); | |
a6c9808a BZ |
513 | } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { |
514 | int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, | |
515 | env->gpr[4]); | |
516 | env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); | |
517 | } else { | |
518 | qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx | |
519 | "\n", env->gpr[3]); | |
520 | env->gpr[3] = -1; | |
521 | } | |
522 | } | |
523 | ||
524 | static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) | |
525 | { | |
526 | } | |
527 | ||
528 | static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) | |
529 | { | |
530 | return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; | |
ba7e5ac1 BZ |
531 | } |
532 | ||
a312aaeb BZ |
533 | static bool pegasos2_setprop(MachineState *ms, const char *path, |
534 | const char *propname, void *val, int vallen) | |
535 | { | |
536 | return true; | |
537 | } | |
538 | ||
a8eda5ed | 539 | static void pegasos2_machine_class_init(ObjectClass *oc, void *data) |
ba7e5ac1 | 540 | { |
a8eda5ed | 541 | MachineClass *mc = MACHINE_CLASS(oc); |
a6c9808a | 542 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
a312aaeb | 543 | VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); |
a8eda5ed | 544 | |
ba7e5ac1 BZ |
545 | mc->desc = "Genesi/bPlan Pegasos II"; |
546 | mc->init = pegasos2_init; | |
a6c9808a | 547 | mc->reset = pegasos2_machine_reset; |
ba7e5ac1 BZ |
548 | mc->block_default_type = IF_IDE; |
549 | mc->default_boot_order = "cd"; | |
550 | mc->default_display = "std"; | |
56b8bfe9 | 551 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2"); |
ba7e5ac1 BZ |
552 | mc->default_ram_id = "pegasos2.ram"; |
553 | mc->default_ram_size = 512 * MiB; | |
a6c9808a | 554 | |
7cebc5db | 555 | vhc->cpu_in_nested = pegasos2_cpu_in_nested; |
a6c9808a BZ |
556 | vhc->hypercall = pegasos2_hypercall; |
557 | vhc->cpu_exec_enter = vhyp_nop; | |
558 | vhc->cpu_exec_exit = vhyp_nop; | |
559 | vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; | |
a312aaeb BZ |
560 | |
561 | vmc->setprop = pegasos2_setprop; | |
ba7e5ac1 BZ |
562 | } |
563 | ||
a8eda5ed BZ |
564 | static const TypeInfo pegasos2_machine_info = { |
565 | .name = TYPE_PEGASOS2_MACHINE, | |
566 | .parent = TYPE_MACHINE, | |
567 | .class_init = pegasos2_machine_class_init, | |
568 | .instance_size = sizeof(Pegasos2MachineState), | |
a6c9808a BZ |
569 | .interfaces = (InterfaceInfo[]) { |
570 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, | |
a312aaeb | 571 | { TYPE_VOF_MACHINE_IF }, |
a6c9808a BZ |
572 | { } |
573 | }, | |
a8eda5ed BZ |
574 | }; |
575 | ||
576 | static void pegasos2_machine_register_types(void) | |
577 | { | |
578 | type_register_static(&pegasos2_machine_info); | |
579 | } | |
580 | ||
581 | type_init(pegasos2_machine_register_types) | |
a6c9808a BZ |
582 | |
583 | /* FDT creation for passing to firmware */ | |
584 | ||
585 | typedef struct { | |
586 | void *fdt; | |
587 | const char *path; | |
588 | } FDTInfo; | |
589 | ||
590 | /* We do everything in reverse order so it comes out right in the tree */ | |
591 | ||
592 | static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
593 | { | |
594 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); | |
595 | } | |
596 | ||
597 | static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
598 | { | |
599 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); | |
600 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); | |
601 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); | |
602 | } | |
603 | ||
604 | static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) | |
605 | { | |
606 | GString *name = g_string_sized_new(64); | |
607 | uint32_t cells[3]; | |
608 | ||
609 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); | |
610 | qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); | |
611 | qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); | |
612 | qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); | |
613 | ||
c0091740 | 614 | /* additional devices */ |
a6c9808a BZ |
615 | g_string_printf(name, "%s/lpt@i3bc", fi->path); |
616 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
617 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
618 | cells[0] = cpu_to_be32(7); | |
619 | cells[1] = 0; | |
620 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
621 | cells, 2 * sizeof(cells[0])); | |
622 | cells[0] = cpu_to_be32(1); | |
623 | cells[1] = cpu_to_be32(0x3bc); | |
624 | cells[2] = cpu_to_be32(8); | |
625 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
626 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); | |
627 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); | |
628 | ||
629 | g_string_printf(name, "%s/fdc@i3f0", fi->path); | |
630 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
631 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
632 | cells[0] = cpu_to_be32(6); | |
633 | cells[1] = 0; | |
634 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
635 | cells, 2 * sizeof(cells[0])); | |
636 | cells[0] = cpu_to_be32(1); | |
637 | cells[1] = cpu_to_be32(0x3f0); | |
638 | cells[2] = cpu_to_be32(8); | |
639 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
640 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); | |
641 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); | |
642 | ||
643 | g_string_printf(name, "%s/timer@i40", fi->path); | |
644 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
645 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
646 | cells[0] = cpu_to_be32(1); | |
647 | cells[1] = cpu_to_be32(0x40); | |
648 | cells[2] = cpu_to_be32(8); | |
649 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
650 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); | |
651 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); | |
652 | ||
653 | g_string_printf(name, "%s/rtc@i70", fi->path); | |
654 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
655 | qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); | |
656 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
657 | cells[0] = cpu_to_be32(8); | |
658 | cells[1] = 0; | |
659 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
660 | cells, 2 * sizeof(cells[0])); | |
661 | cells[0] = cpu_to_be32(1); | |
662 | cells[1] = cpu_to_be32(0x70); | |
663 | cells[2] = cpu_to_be32(2); | |
664 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
665 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); | |
666 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); | |
667 | ||
668 | g_string_printf(name, "%s/keyboard@i60", fi->path); | |
669 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
670 | cells[0] = cpu_to_be32(1); | |
671 | cells[1] = 0; | |
672 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
673 | cells, 2 * sizeof(cells[0])); | |
674 | cells[0] = cpu_to_be32(1); | |
675 | cells[1] = cpu_to_be32(0x60); | |
676 | cells[2] = cpu_to_be32(5); | |
677 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
678 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); | |
679 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); | |
680 | ||
681 | g_string_printf(name, "%s/8042@i60", fi->path); | |
682 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
683 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); | |
684 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); | |
685 | qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); | |
686 | qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); | |
687 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
688 | cells[0] = cpu_to_be32(1); | |
689 | cells[1] = cpu_to_be32(0x60); | |
690 | cells[2] = cpu_to_be32(5); | |
691 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
692 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); | |
693 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); | |
694 | ||
695 | g_string_printf(name, "%s/serial@i2f8", fi->path); | |
696 | qemu_fdt_add_subnode(fi->fdt, name->str); | |
697 | qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); | |
698 | cells[0] = cpu_to_be32(3); | |
699 | cells[1] = 0; | |
700 | qemu_fdt_setprop(fi->fdt, name->str, "interrupts", | |
701 | cells, 2 * sizeof(cells[0])); | |
702 | cells[0] = cpu_to_be32(1); | |
703 | cells[1] = cpu_to_be32(0x2f8); | |
704 | cells[2] = cpu_to_be32(8); | |
705 | qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); | |
706 | qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); | |
707 | qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); | |
708 | ||
709 | g_string_free(name, TRUE); | |
710 | } | |
711 | ||
712 | static struct { | |
713 | const char *id; | |
714 | const char *name; | |
715 | void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); | |
716 | } device_map[] = { | |
717 | { "pci11ab,6460", "host", NULL }, | |
718 | { "pci1106,8231", "isa", dt_isa }, | |
719 | { "pci1106,571", "ide", dt_ide }, | |
720 | { "pci1106,3044", "firewire", NULL }, | |
721 | { "pci1106,3038", "usb", dt_usb }, | |
722 | { "pci1106,8235", "other", NULL }, | |
723 | { "pci1106,3058", "sound", NULL }, | |
724 | { NULL, NULL } | |
725 | }; | |
726 | ||
727 | static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) | |
728 | { | |
729 | FDTInfo *fi = opaque; | |
730 | GString *node = g_string_new(NULL); | |
731 | uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; | |
732 | int i, j; | |
733 | const char *name = NULL; | |
734 | g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", | |
735 | pci_get_word(&d->config[PCI_VENDOR_ID]), | |
736 | pci_get_word(&d->config[PCI_DEVICE_ID])); | |
737 | ||
738 | for (i = 0; device_map[i].id; i++) { | |
739 | if (!strcmp(pn, device_map[i].id)) { | |
740 | name = device_map[i].name; | |
741 | break; | |
742 | } | |
743 | } | |
744 | g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), | |
745 | PCI_SLOT(d->devfn)); | |
746 | if (PCI_FUNC(d->devfn)) { | |
747 | g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); | |
748 | } | |
749 | ||
750 | qemu_fdt_add_subnode(fi->fdt, node->str); | |
751 | if (device_map[i].dtf) { | |
752 | FDTInfo cfi = { fi->fdt, node->str }; | |
753 | device_map[i].dtf(bus, d, &cfi); | |
754 | } | |
755 | cells[0] = cpu_to_be32(d->devfn << 8); | |
756 | cells[1] = 0; | |
757 | cells[2] = 0; | |
758 | cells[3] = 0; | |
759 | cells[4] = 0; | |
760 | j = 5; | |
761 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
762 | if (!d->io_regions[i].size) { | |
763 | continue; | |
764 | } | |
765 | cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); | |
766 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { | |
767 | cells[j] |= cpu_to_be32(1 << 24); | |
768 | } else { | |
769 | cells[j] |= cpu_to_be32(2 << 24); | |
770 | if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
771 | cells[j] |= cpu_to_be32(4 << 28); | |
772 | } | |
773 | } | |
774 | cells[j + 1] = 0; | |
775 | cells[j + 2] = 0; | |
776 | cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); | |
777 | cells[j + 4] = cpu_to_be32(d->io_regions[i].size); | |
778 | j += 5; | |
779 | } | |
780 | qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); | |
781 | qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); | |
782 | if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { | |
783 | qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", | |
784 | pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); | |
785 | } | |
786 | /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ | |
787 | qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", | |
788 | pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); | |
789 | qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", | |
790 | pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); | |
791 | cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); | |
792 | qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); | |
e7dfb29e | 793 | qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); |
a6c9808a BZ |
794 | qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", |
795 | pci_get_word(&d->config[PCI_DEVICE_ID])); | |
796 | qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", | |
797 | pci_get_word(&d->config[PCI_VENDOR_ID])); | |
798 | ||
799 | g_string_free(node, TRUE); | |
800 | } | |
801 | ||
802 | static void *build_fdt(MachineState *machine, int *fdt_size) | |
803 | { | |
804 | Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); | |
805 | PowerPCCPU *cpu = pm->cpu; | |
806 | PCIBus *pci_bus; | |
807 | FDTInfo fi; | |
808 | uint32_t cells[16]; | |
809 | void *fdt = create_device_tree(fdt_size); | |
810 | ||
811 | fi.fdt = fdt; | |
812 | ||
813 | /* root node */ | |
814 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", | |
815 | "Pegasos CHRP PowerPC System"); | |
816 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); | |
817 | qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); | |
818 | qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); | |
819 | qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); | |
820 | qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); | |
821 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); | |
822 | qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); | |
823 | ||
824 | /* pci@c0000000 */ | |
825 | qemu_fdt_add_subnode(fdt, "/pci@c0000000"); | |
826 | cells[0] = 0; | |
827 | cells[1] = 0; | |
828 | qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", | |
829 | cells, 2 * sizeof(cells[0])); | |
830 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); | |
831 | cells[0] = cpu_to_be32(PCI0_MEM_BASE); | |
832 | cells[1] = cpu_to_be32(PCI0_MEM_SIZE); | |
833 | qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); | |
834 | cells[0] = cpu_to_be32(0x01000000); | |
835 | cells[1] = 0; | |
836 | cells[2] = 0; | |
837 | cells[3] = cpu_to_be32(PCI0_IO_BASE); | |
838 | cells[4] = 0; | |
839 | cells[5] = cpu_to_be32(PCI0_IO_SIZE); | |
840 | cells[6] = cpu_to_be32(0x02000000); | |
841 | cells[7] = 0; | |
842 | cells[8] = cpu_to_be32(PCI0_MEM_BASE); | |
843 | cells[9] = cpu_to_be32(PCI0_MEM_BASE); | |
844 | cells[10] = 0; | |
845 | cells[11] = cpu_to_be32(PCI0_MEM_SIZE); | |
846 | qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", | |
847 | cells, 12 * sizeof(cells[0])); | |
848 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); | |
849 | qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); | |
850 | qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); | |
851 | qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); | |
852 | ||
853 | fi.path = "/pci@c0000000"; | |
854 | pci_bus = mv64361_get_pci_bus(pm->mv, 0); | |
855 | pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); | |
856 | ||
857 | /* pci@80000000 */ | |
858 | qemu_fdt_add_subnode(fdt, "/pci@80000000"); | |
859 | cells[0] = 0; | |
860 | cells[1] = 0; | |
861 | qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", | |
862 | cells, 2 * sizeof(cells[0])); | |
863 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); | |
864 | cells[0] = cpu_to_be32(PCI1_MEM_BASE); | |
865 | cells[1] = cpu_to_be32(PCI1_MEM_SIZE); | |
866 | qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); | |
867 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", | |
868 | 0xf1000cb4); | |
869 | cells[0] = cpu_to_be32(0x01000000); | |
870 | cells[1] = 0; | |
871 | cells[2] = 0; | |
872 | cells[3] = cpu_to_be32(PCI1_IO_BASE); | |
873 | cells[4] = 0; | |
874 | cells[5] = cpu_to_be32(PCI1_IO_SIZE); | |
875 | cells[6] = cpu_to_be32(0x02000000); | |
876 | cells[7] = 0; | |
877 | cells[8] = cpu_to_be32(PCI1_MEM_BASE); | |
878 | cells[9] = cpu_to_be32(PCI1_MEM_BASE); | |
879 | cells[10] = 0; | |
880 | cells[11] = cpu_to_be32(PCI1_MEM_SIZE); | |
881 | qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", | |
882 | cells, 12 * sizeof(cells[0])); | |
883 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); | |
884 | qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); | |
885 | qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); | |
886 | qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); | |
887 | ||
888 | fi.path = "/pci@80000000"; | |
889 | pci_bus = mv64361_get_pci_bus(pm->mv, 1); | |
890 | pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); | |
891 | ||
892 | qemu_fdt_add_subnode(fdt, "/failsafe"); | |
893 | qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); | |
894 | qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); | |
895 | ||
5f2eb049 BZ |
896 | qemu_fdt_add_subnode(fdt, "/rtas"); |
897 | qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); | |
898 | qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); | |
899 | qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); | |
900 | qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); | |
901 | qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); | |
902 | qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", | |
903 | RTAS_DISPLAY_CHARACTER); | |
904 | qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", | |
905 | RTAS_WRITE_PCI_CONFIG); | |
906 | qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", | |
907 | RTAS_READ_PCI_CONFIG); | |
908 | /* Pegasos2 firmware misspells check-exception and guests use that */ | |
909 | qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", | |
910 | RTAS_CHECK_EXCEPTION); | |
911 | qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); | |
912 | qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", | |
913 | RTAS_SET_TIME_OF_DAY); | |
914 | qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", | |
915 | RTAS_GET_TIME_OF_DAY); | |
916 | qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); | |
917 | qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); | |
918 | qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); | |
919 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); | |
920 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); | |
921 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); | |
922 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); | |
923 | qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); | |
924 | ||
a6c9808a BZ |
925 | /* cpus */ |
926 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
927 | qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); | |
928 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); | |
929 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); | |
930 | qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); | |
931 | ||
932 | /* FIXME Get CPU name from CPU object */ | |
933 | const char *cp = "/cpus/PowerPC,G4"; | |
934 | qemu_fdt_add_subnode(fdt, cp); | |
935 | qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); | |
936 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); | |
937 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", | |
938 | cpu->env.dcache_line_size); | |
939 | qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", | |
940 | cpu->env.dcache_line_size); | |
941 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); | |
942 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", | |
943 | cpu->env.icache_line_size); | |
944 | qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", | |
945 | cpu->env.icache_line_size); | |
946 | if (cpu->env.id_tlbs) { | |
947 | qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); | |
948 | qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); | |
949 | qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); | |
950 | qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); | |
951 | qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); | |
952 | } | |
953 | qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); | |
954 | qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); | |
955 | qemu_fdt_setprop_string(fdt, cp, "state", "running"); | |
956 | if (cpu->env.insns_flags & PPC_ALTIVEC) { | |
957 | qemu_fdt_setprop_string(fdt, cp, "altivec", ""); | |
958 | qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); | |
959 | } | |
960 | /* | |
961 | * FIXME What flags do data-streams, external-control and | |
962 | * performance-monitor depend on? | |
963 | */ | |
964 | qemu_fdt_setprop_string(fdt, cp, "external-control", ""); | |
965 | if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { | |
966 | qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); | |
967 | } | |
968 | qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); | |
969 | if (cpu->env.insns_flags & PPC_FLOAT_FRES) { | |
970 | qemu_fdt_setprop_string(fdt, cp, "graphics", ""); | |
971 | } | |
972 | qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); | |
973 | qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", | |
974 | cpu->env.tb_env->tb_freq); | |
975 | qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); | |
976 | qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); | |
977 | qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); | |
978 | cells[0] = 0; | |
979 | cells[1] = 0; | |
980 | qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); | |
981 | qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); | |
982 | qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); | |
983 | ||
984 | /* memory */ | |
985 | qemu_fdt_add_subnode(fdt, "/memory@0"); | |
986 | cells[0] = 0; | |
987 | cells[1] = cpu_to_be32(machine->ram_size); | |
988 | qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); | |
989 | qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); | |
990 | qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); | |
991 | ||
992 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
ebe0e9bb BZ |
993 | if (pm->initrd_addr && pm->initrd_size) { |
994 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", | |
995 | pm->initrd_addr + pm->initrd_size); | |
996 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
997 | pm->initrd_addr); | |
998 | } | |
a6c9808a BZ |
999 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
1000 | machine->kernel_cmdline ?: ""); | |
1001 | qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); | |
1002 | ||
1003 | qemu_fdt_add_subnode(fdt, "/openprom"); | |
1004 | qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); | |
1005 | ||
1006 | return fdt; | |
1007 | } |