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hw: Remove unnecessary DEVICE() cast
[mirror_qemu.git] / hw / ppc / pnv.c
CommitLineData
9e933f4a
BH		 1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
fc6b3cf9 22#include "qemu/units.h"
9e933f4a
BH		 23#include "qapi/error.h"
24#include "sysemu/sysemu.h"
25#include "sysemu/numa.h"
71e8a915 26#include "sysemu/reset.h"
54d31236 27#include "sysemu/runstate.h"
d2528bdc 28#include "sysemu/cpus.h"
8d409261 29#include "sysemu/device_tree.h"
01b552b0 30#include "sysemu/hw_accel.h"
fcf5ef2a 31#include "target/ppc/cpu.h"
9e933f4a
BH		 32#include "qemu/log.h"
33#include "hw/ppc/fdt.h"
34#include "hw/ppc/ppc.h"
35#include "hw/ppc/pnv.h"
d2fd9612 36#include "hw/ppc/pnv_core.h"
9e933f4a 37#include "hw/loader.h"
01b552b0 38#include "hw/nmi.h"
9e933f4a 39#include "exec/address-spaces.h"
e997040e 40#include "qapi/visitor.h"
47fea43a
CLG		 41#include "monitor/monitor.h"
42#include "hw/intc/intc.h"
aeaef83d 43#include "hw/ipmi/ipmi.h"
58969eee 44#include "target/ppc/mmu-hash64.h"
4f9924c4 45#include "hw/pci/msi.h"
9e933f4a 46
36fc6f08 47#include "hw/ppc/xics.h"
a27bd6c7 48#include "hw/qdev-properties.h"
967b7523 49#include "hw/ppc/pnv_xscom.h"
35dde576 50#include "hw/ppc/pnv_pnor.h"
967b7523 51
3495b6b6 52#include "hw/isa/isa.h"
12e9493d 53#include "hw/boards.h"
3495b6b6 54#include "hw/char/serial.h"
bcdb9064 55#include "hw/rtc/mc146818rtc.h"
3495b6b6 56
9e933f4a
BH		 57#include <libfdt.h>
58
b268a616 59#define FDT_MAX_SIZE (1 * MiB)
9e933f4a
BH		 60
61#define FW_FILE_NAME "skiboot.lid"
62#define FW_LOAD_ADDR 0x0
b268a616 63#define FW_MAX_SIZE (4 * MiB)
9e933f4a
BH		 64
65#define KERNEL_LOAD_ADDR 0x20000000
b45b56ba 66#define KERNEL_MAX_SIZE (256 * MiB)
fef592f9 67#define INITRD_LOAD_ADDR 0x60000000
584ea7e7 68#define INITRD_MAX_SIZE (256 * MiB)
9e933f4a 69
40abf43f
IM		 70static const char *pnv_chip_core_typename(const PnvChip *o)
71{
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78}
79
9e933f4a
BH		 80/*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85#define MAX_CPUS 2048
86
87/*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
b168a138 92static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
9e933f4a
BH		 93{
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109}
110
d2fd9612
CLG		 111static int get_cpus_node(void *fdt)
112{
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
a4f3885c 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
d2fd9612
CLG		 117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124}
125
126/*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
b168a138 133static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
d2fd9612 134{
08304a86
DG		 135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
d2fd9612 137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
8bd9530e 138 int smt_threads = CPU_CORE(pc)->nr_threads;
d2fd9612
CLG		 139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
3dc6f869 183 warn_report("Unknown L1 dcache size for cpu");
d2fd9612
CLG		 184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
3dc6f869 189 warn_report("Unknown L1 icache size for cpu");
d2fd9612
CLG		 190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
59b7c1c2
B		 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
d2fd9612
CLG		 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (env->spr_cb[SPR_PURR].oea_read) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
58969eee 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
d2fd9612
CLG		 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
59b7c1c2
B		 208 /*
209 * Advertise VMX/VSX (vector extensions) if available
d2fd9612
CLG		 210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
59b7c1c2
B		 212 * 2 == VSX available
213 */
d2fd9612
CLG		 214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
59b7c1c2
B		 220 /*
221 * Advertise DFP (Decimal Floating Point) if available
d2fd9612 222 * 0 / no property == no DFP
59b7c1c2
B		 223 * 1 == DFP available
224 */
d2fd9612
CLG		 225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
644a2c99
DG		 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
d2fd9612
CLG		 231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
d2fd9612
CLG		 239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245}
246
b168a138
CLG		 247static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
bf5615e7
CLG		 249{
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282}
283
eb859a27 284static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
e997040e 285{
c396c58a 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
d2fd9612
CLG		 287 int i;
288
3f5b45ca
GK		 289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
c396c58a
GK		 291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
967b7523 293
d2fd9612 294 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 295 PnvCore *pnv_core = chip->cores[i];
d2fd9612 296
b168a138 297 pnv_dt_core(chip, pnv_core, fdt);
bf5615e7
CLG		 298
299 /* Interrupt Control Presenters (ICP). One per core. */
b168a138 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
d2fd9612
CLG		 301 }
302
e997040e 303 if (chip->ram_size) {
b168a138 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
e997040e
CLG		 305 }
306}
307
eb859a27
CLG		 308static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309{
c396c58a 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
eb859a27
CLG		 311 int i;
312
3f5b45ca
GK		 313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
c396c58a
GK		 315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
eb859a27
CLG		 317
318 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 319 PnvCore *pnv_core = chip->cores[i];
eb859a27
CLG		 320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
15376c66 327
2661f6ab 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
eb859a27
CLG		 329}
330
2b548a42
CLG		 331static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332{
c396c58a 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
2b548a42
CLG		 334 int i;
335
3f5b45ca
GK		 336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
c396c58a
GK		 338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
2b548a42
CLG		 340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
2661f6ab
CLG		 350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
2b548a42
CLG		 352}
353
b168a138 354static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
c5ffdcae
CLG		 355{
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372}
373
b168a138 374static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cb228f5a
CLG		 375{
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 char *name;
384 int node;
385
386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
387 node = fdt_add_subnode(fdt, lpc_off, name);
388 _FDT(node);
389 g_free(name);
390
391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
392 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
393 sizeof(compatible))));
394
395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
399 fdt_get_phandle(fdt, lpc_off))));
400
401 /* This is needed by Linux */
402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
403}
404
b168a138 405static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
04f6c8b2
CLG		 406{
407 const char compatible[] = "bt\0ipmi-bt";
408 uint32_t io_base;
409 uint32_t io_regs[] = {
410 cpu_to_be32(1),
411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
412 cpu_to_be32(3)
413 };
414 uint32_t irq;
415 char *name;
416 int node;
417
418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
419 io_regs[1] = cpu_to_be32(io_base);
420
421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
422
423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
424 node = fdt_add_subnode(fdt, lpc_off, name);
425 _FDT(node);
426 g_free(name);
427
7032d92a
CLG		 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
429 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
430 sizeof(compatible))));
04f6c8b2
CLG		 431
432 /* Mark it as reserved to avoid Linux trying to claim it */
433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
436 fdt_get_phandle(fdt, lpc_off))));
437}
438
e7a3fee3
CLG		 439typedef struct ForeachPopulateArgs {
440 void *fdt;
441 int offset;
442} ForeachPopulateArgs;
443
b168a138 444static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
e7a3fee3 445{
c5ffdcae
CLG		 446 ForeachPopulateArgs *args = opaque;
447 ISADevice *d = ISA_DEVICE(dev);
448
449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
b168a138 450 pnv_dt_rtc(d, args->fdt, args->offset);
cb228f5a 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
b168a138 452 pnv_dt_serial(d, args->fdt, args->offset);
04f6c8b2 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
b168a138 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
c5ffdcae
CLG		 455 } else {
456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
457 d->ioport_id);
458 }
459
e7a3fee3
CLG		 460 return 0;
461}
462
59b7c1c2
B		 463/*
464 * The default LPC bus of a multichip system is on chip 0. It's
bb7ab95c
CLG		 465 * recognized by the firmware (skiboot) using a "primary" property.
466 */
467static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
468{
64d011d5 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
e7a3fee3
CLG		 470 ForeachPopulateArgs args = {
471 .fdt = fdt,
bb7ab95c 472 .offset = isa_offset,
e7a3fee3 473 };
f47a08d1 474 uint32_t phandle;
e7a3fee3 475
bb7ab95c
CLG		 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
477
f47a08d1
CLG		 478 phandle = qemu_fdt_alloc_phandle(fdt);
479 assert(phandle > 0);
480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
481
59b7c1c2
B		 482 /*
483 * ISA devices are not necessarily parented to the ISA bus so we
484 * can not use object_child_foreach()
485 */
bb7ab95c
CLG		 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
487 &args);
e7a3fee3
CLG		 488}
489
7a90c6a1 490static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
e5694793
CLG		 491{
492 int off;
493
494 off = fdt_add_subnode(fdt, 0, "ibm,opal");
495 off = fdt_add_subnode(fdt, off, "power-mgt");
496
497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
498}
499
b168a138 500static void *pnv_dt_create(MachineState *machine)
9e933f4a 501{
d76f2da7 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
b168a138 503 PnvMachineState *pnv = PNV_MACHINE(machine);
9e933f4a
BH		 504 void *fdt;
505 char *buf;
506 int off;
e997040e 507 int i;
9e933f4a
BH		 508
509 fdt = g_malloc0(FDT_MAX_SIZE);
510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
511
ccb099b3
CLG		 512 /* /qemu node */
513 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
514
9e933f4a
BH		 515 /* Root node */
516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
518 _FDT((fdt_setprop_string(fdt, 0, "model",
519 "IBM PowerNV (emulated by qemu)")));
d76f2da7 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
9e933f4a
BH		 521
522 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
524 if (qemu_uuid_set) {
525 _FDT((fdt_property_string(fdt, "system-id", buf)));
526 }
527 g_free(buf);
528
529 off = fdt_add_subnode(fdt, 0, "chosen");
530 if (machine->kernel_cmdline) {
531 _FDT((fdt_setprop_string(fdt, off, "bootargs",
532 machine->kernel_cmdline)));
533 }
534
535 if (pnv->initrd_size) {
536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
538
539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
540 &start_prop, sizeof(start_prop))));
541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
542 &end_prop, sizeof(end_prop))));
543 }
544
e997040e
CLG		 545 /* Populate device tree for each chip */
546 for (i = 0; i < pnv->num_chips; i++) {
eb859a27 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
e997040e 548 }
e7a3fee3
CLG		 549
550 /* Populate ISA devices on chip 0 */
bb7ab95c 551 pnv_dt_isa(pnv, fdt);
aeaef83d
CLG		 552
553 if (pnv->bmc) {
b168a138 554 pnv_dt_bmc_sensors(pnv->bmc, fdt);
aeaef83d
CLG		 555 }
556
7a90c6a1
GK		 557 /* Create an extra node for power management on machines that support it */
558 if (pmc->dt_power_mgt) {
559 pmc->dt_power_mgt(pnv, fdt);
e5694793
CLG		 560 }
561
9e933f4a
BH		 562 return fdt;
563}
564
bce0b691
CLG		 565static void pnv_powerdown_notify(Notifier *n, void *opaque)
566{
8f06e370 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
bce0b691
CLG		 568
569 if (pnv->bmc) {
570 pnv_bmc_powerdown(pnv->bmc);
571 }
572}
573
a0628599 574static void pnv_reset(MachineState *machine)
9e933f4a 575{
25f3170b
CLG		 576 PnvMachineState *pnv = PNV_MACHINE(machine);
577 IPMIBmc *bmc;
9e933f4a
BH		 578 void *fdt;
579
580 qemu_devices_reset();
581
25f3170b
CLG		 582 /*
583 * The machine should provide by default an internal BMC simulator.
584 * If not, try to use the BMC device that was provided on the command
585 * line.
586 */
587 bmc = pnv_bmc_find(&error_fatal);
588 if (!pnv->bmc) {
589 if (!bmc) {
590 warn_report("machine has no BMC device. Use '-device "
591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
592 "to define one");
593 } else {
594 pnv_bmc_set_pnor(bmc, pnv->pnor);
595 pnv->bmc = bmc;
596 }
597 }
598
b168a138 599 fdt = pnv_dt_create(machine);
9e933f4a
BH		 600
601 /* Pack resulting tree */
602 _FDT((fdt_pack(fdt)));
603
8d409261 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
9e933f4a 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
b2fb7a43
PN		 606
607 g_free(fdt);
9e933f4a
BH		 608}
609
04026890 610static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
3495b6b6 611{
77864267
CLG		 612 Pnv8Chip *chip8 = PNV8_CHIP(chip);
613 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
04026890 614}
3495b6b6 615
04026890
CLG		 616static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
617{
77864267
CLG		 618 Pnv8Chip *chip8 = PNV8_CHIP(chip);
619 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
04026890 620}
3495b6b6 621
04026890
CLG		 622static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
623{
15376c66
CLG		 624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
04026890 626}
3495b6b6 627
2b548a42
CLG		 628static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
629{
2661f6ab
CLG		 630 Pnv10Chip *chip10 = PNV10_CHIP(chip);
631 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
2b548a42
CLG		 632}
633
04026890
CLG		 634static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
635{
636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
3495b6b6
CLG		 637}
638
d8e4aad5
CLG		 639static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
640{
641 Pnv8Chip *chip8 = PNV8_CHIP(chip);
9ae1329e 642 int i;
d8e4aad5
CLG		 643
644 ics_pic_print_info(&chip8->psi.ics, mon);
9ae1329e
CLG		 645 for (i = 0; i < chip->num_phbs; i++) {
646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
647 ics_pic_print_info(&chip8->phbs[i].lsis, mon);
648 }
d8e4aad5
CLG		 649}
650
651static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
652{
653 Pnv9Chip *chip9 = PNV9_CHIP(chip);
4f9924c4 654 int i, j;
d8e4aad5
CLG		 655
656 pnv_xive_pic_print_info(&chip9->xive, mon);
c38536bc 657 pnv_psi_pic_print_info(&chip9->psi, mon);
4f9924c4
BH		 658
659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
660 PnvPhb4PecState *pec = &chip9->pecs[i];
661 for (j = 0; j < pec->num_stacks; j++) {
662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
663 }
664 }
d8e4aad5
CLG		 665}
666
c4b2c40c
GK		 667static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
668 uint32_t core_id)
669{
670 return PNV_XSCOM_EX_BASE(core_id);
671}
672
673static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
674 uint32_t core_id)
675{
676 return PNV9_XSCOM_EC_BASE(core_id);
677}
678
679static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
680 uint32_t core_id)
681{
682 return PNV10_XSCOM_EC_BASE(core_id);
683}
684
f30c843c
CLG		 685static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
686{
687 PowerPCCPUClass *ppc_default =
688 POWERPC_CPU_CLASS(object_class_by_name(default_type));
689 PowerPCCPUClass *ppc =
690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
691
692 return ppc_default->pvr_match(ppc_default, ppc->pvr);
693}
694
e2392d43
CLG		 695static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
696{
697 Object *obj;
698
699 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
700 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
701 object_property_set_int(obj, irq, "irq", &error_fatal);
702 object_property_set_bool(obj, true, "realized", &error_fatal);
703}
704
2b548a42
CLG		 705static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
706{
8b50ce85
CLG		 707 Pnv10Chip *chip10 = PNV10_CHIP(chip);
708
709 pnv_psi_pic_print_info(&chip10->psi, mon);
2b548a42
CLG		 710}
711
b168a138 712static void pnv_init(MachineState *machine)
9e933f4a 713{
b168a138 714 PnvMachineState *pnv = PNV_MACHINE(machine);
f30c843c 715 MachineClass *mc = MACHINE_GET_CLASS(machine);
9e933f4a
BH		 716 char *fw_filename;
717 long fw_size;
e997040e
CLG		 718 int i;
719 char *chip_typename;
35dde576
CLG		 720 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
721 DeviceState *dev;
9e933f4a
BH		 722
723 /* allocate RAM */
d23b6caa 724 if (machine->ram_size < (1 * GiB)) {
3dc6f869 725 warn_report("skiboot may not work with < 1GB of RAM");
9e933f4a 726 }
173a36d8 727 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
9e933f4a 728
35dde576
CLG		 729 /*
730 * Create our simple PNOR device
731 */
732 dev = qdev_create(NULL, TYPE_PNV_PNOR);
733 if (pnor) {
734 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
735 &error_abort);
736 }
737 qdev_init_nofail(dev);
738 pnv->pnor = PNV_PNOR(dev);
739
9e933f4a
BH		 740 /* load skiboot firmware */
741 if (bios_name == NULL) {
742 bios_name = FW_FILE_NAME;
743 }
744
745 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
15fcedb2
CLG		 746 if (!fw_filename) {
747 error_report("Could not find OPAL firmware '%s'", bios_name);
748 exit(1);
749 }
9e933f4a 750
08c3f3a7 751 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
9e933f4a 752 if (fw_size < 0) {
15fcedb2 753 error_report("Could not load OPAL firmware '%s'", fw_filename);
9e933f4a
BH		 754 exit(1);
755 }
756 g_free(fw_filename);
757
758 /* load kernel */
759 if (machine->kernel_filename) {
760 long kernel_size;
761
762 kernel_size = load_image_targphys(machine->kernel_filename,
b45b56ba 763 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
9e933f4a 764 if (kernel_size < 0) {
802fc7ab 765 error_report("Could not load kernel '%s'",
7c6e8797 766 machine->kernel_filename);
9e933f4a
BH		 767 exit(1);
768 }
769 }
770
771 /* load initrd */
772 if (machine->initrd_filename) {
773 pnv->initrd_base = INITRD_LOAD_ADDR;
774 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
584ea7e7 775 pnv->initrd_base, INITRD_MAX_SIZE);
9e933f4a 776 if (pnv->initrd_size < 0) {
802fc7ab 777 error_report("Could not load initial ram disk '%s'",
9e933f4a
BH		 778 machine->initrd_filename);
779 exit(1);
780 }
781 }
e997040e 782
4f9924c4
BH		 783 /* MSIs are supported on this platform */
784 msi_nonbroken = true;
785
f30c843c
CLG		 786 /*
787 * Check compatibility of the specified CPU with the machine
788 * default.
789 */
790 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
791 error_report("invalid CPU model '%s' for %s machine",
792 machine->cpu_type, mc->name);
793 exit(1);
794 }
795
e997040e 796 /* Create the processor chips */
4a12c699 797 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
7fd544d8 798 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
4a12c699 799 i, machine->cpu_type);
e997040e 800 if (!object_class_by_name(chip_typename)) {
f30c843c
CLG		 801 error_report("invalid chip model '%.*s' for %s machine",
802 i, machine->cpu_type, mc->name);
e997040e
CLG		 803 exit(1);
804 }
805
e44acde2
GK		 806 pnv->num_chips =
807 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
808 /*
809 * TODO: should we decide on how many chips we can create based
810 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
811 */
812 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
813 error_report("invalid number of chips: '%d'", pnv->num_chips);
814 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
815 exit(1);
816 }
817
e997040e
CLG		 818 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
819 for (i = 0; i < pnv->num_chips; i++) {
820 char chip_name[32];
821 Object *chip = object_new(chip_typename);
822
823 pnv->chips[i] = PNV_CHIP(chip);
824
59b7c1c2
B		 825 /*
826 * TODO: put all the memory in one node on chip 0 until we find a
e997040e
CLG		 827 * way to specify different ranges for each chip
828 */
829 if (i == 0) {
830 object_property_set_int(chip, machine->ram_size, "ram-size",
831 &error_fatal);
832 }
833
834 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
d2623129 835 object_property_add_child(OBJECT(pnv), chip_name, chip);
e997040e
CLG		 836 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
837 &error_fatal);
fe6b6346
LX		 838 object_property_set_int(chip, machine->smp.cores,
839 "nr-cores", &error_fatal);
764f9b25
GK		 840 object_property_set_int(chip, machine->smp.threads,
841 "nr-threads", &error_fatal);
245cdb7f
CLG		 842 /*
843 * The POWER8 machine use the XICS interrupt interface.
844 * Propagate the XICS fabric to the chip and its controllers.
845 */
846 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
847 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
848 }
d1214b81
GK		 849 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
850 object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
851 &error_abort);
852 }
e997040e
CLG		 853 object_property_set_bool(chip, true, "realized", &error_fatal);
854 }
855 g_free(chip_typename);
3495b6b6
CLG		 856
857 /* Instantiate ISA bus on chip 0 */
04026890 858 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
3495b6b6
CLG		 859
860 /* Create serial port */
def337ff 861 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
3495b6b6
CLG		 862
863 /* Create an RTC ISA device too */
6c646a11 864 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
bce0b691 865
25f3170b
CLG		 866 /*
867 * Create the machine BMC simulator and the IPMI BT device for
868 * communication with the BMC
869 */
870 if (defaults_enabled()) {
871 pnv->bmc = pnv_bmc_create(pnv->pnor);
872 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
873 }
e2392d43 874
59b7c1c2
B		 875 /*
876 * OpenPOWER systems use a IPMI SEL Event message to notify the
877 * host to powerdown
878 */
bce0b691
CLG		 879 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
880 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
e997040e
CLG		 881}
882
631adaff
CLG		 883/*
884 * 0:21 Reserved - Read as zeros
885 * 22:24 Chip ID
886 * 25:28 Core number
887 * 29:31 Thread ID
888 */
889static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
890{
891 return (chip->chip_id << 7) | (core_id << 3);
892}
893
8fa1f4ef
CLG		 894static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
895 Error **errp)
d35aefa9 896{
245cdb7f 897 Pnv8Chip *chip8 = PNV8_CHIP(chip);
8fa1f4ef
CLG		 898 Error *local_err = NULL;
899 Object *obj;
8907fc25 900 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8fa1f4ef 901
245cdb7f 902 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
8fa1f4ef
CLG		 903 if (local_err) {
904 error_propagate(errp, local_err);
905 return;
906 }
907
956b8f46 908 pnv_cpu->intc = obj;
d35aefa9
CLG		 909}
910
0990ce6a 911
d49e8a9b
CLG		 912static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
913{
914 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
915
916 icp_reset(ICP(pnv_cpu->intc));
917}
918
0990ce6a
GK		 919static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
920{
921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
922
923 icp_destroy(ICP(pnv_cpu->intc));
924 pnv_cpu->intc = NULL;
925}
926
85913070
GK		 927static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
928 Monitor *mon)
929{
930 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
931}
932
631adaff
CLG		 933/*
934 * 0:48 Reserved - Read as zeroes
935 * 49:52 Node ID
936 * 53:55 Chip ID
937 * 56 Reserved - Read as zero
938 * 57:61 Core number
939 * 62:63 Thread ID
940 *
941 * We only care about the lower bits. uint32_t is fine for the moment.
942 */
943static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
944{
945 return (chip->chip_id << 8) | (core_id << 2);
946}
947
2b548a42
CLG		 948static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
949{
950 return (chip->chip_id << 8) | (core_id << 2);
951}
952
8fa1f4ef
CLG		 953static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
954 Error **errp)
d35aefa9 955{
2dfa91a2
CLG		 956 Pnv9Chip *chip9 = PNV9_CHIP(chip);
957 Error *local_err = NULL;
958 Object *obj;
959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
960
961 /*
962 * The core creates its interrupt presenter but the XIVE interrupt
963 * controller object is initialized afterwards. Hopefully, it's
964 * only used at runtime.
965 */
47950946
CLG		 966 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
967 &local_err);
2dfa91a2
CLG		 968 if (local_err) {
969 error_propagate(errp, local_err);
970 return;
971 }
972
973 pnv_cpu->intc = obj;
d35aefa9
CLG		 974}
975
d49e8a9b
CLG		 976static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
977{
978 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
979
980 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
981}
982
0990ce6a
GK		 983static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
984{
985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
986
987 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
988 pnv_cpu->intc = NULL;
989}
990
85913070
GK		 991static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
992 Monitor *mon)
993{
994 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
995}
996
2b548a42
CLG		 997static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
998 Error **errp)
999{
1000 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1001
1002 /* Will be defined when the interrupt controller is */
1003 pnv_cpu->intc = NULL;
1004}
1005
1006static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1007{
1008 ;
1009}
1010
1011static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1012{
1013 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1014
1015 pnv_cpu->intc = NULL;
1016}
1017
85913070
GK		 1018static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1019 Monitor *mon)
1020{
1021}
1022
59b7c1c2
B		 1023/*
1024 * Allowed core identifiers on a POWER8 Processor Chip :
397a79e7
CLG		 1025 *
1026 * <EX0 reserved>
1027 * EX1 - Venice only
1028 * EX2 - Venice only
1029 * EX3 - Venice only
1030 * EX4
1031 * EX5
1032 * EX6
1033 * <EX7,8 reserved> <reserved>
1034 * EX9 - Venice only
1035 * EX10 - Venice only
1036 * EX11 - Venice only
1037 * EX12
1038 * EX13
1039 * EX14
1040 * <EX15 reserved>
1041 */
1042#define POWER8E_CORE_MASK (0x7070ull)
1043#define POWER8_CORE_MASK (0x7e7eull)
1044
1045/*
09279d7e 1046 * POWER9 has 24 cores, ids starting at 0x0
397a79e7 1047 */
09279d7e 1048#define POWER9_CORE_MASK (0xffffffffffffffull)
397a79e7 1049
2b548a42
CLG		 1050
1051#define POWER10_CORE_MASK (0xffffffffffffffull)
1052
77864267
CLG		 1053static void pnv_chip_power8_instance_init(Object *obj)
1054{
9ae1329e 1055 PnvChip *chip = PNV_CHIP(obj);
77864267 1056 Pnv8Chip *chip8 = PNV8_CHIP(obj);
9ae1329e
CLG		 1057 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1058 int i;
77864267 1059
245cdb7f
CLG		 1060 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1061 (Object **)&chip8->xics,
1062 object_property_allow_set_link,
d2623129 1063 OBJ_PROP_LINK_STRONG);
245cdb7f 1064
f6d4dca8 1065 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
ae856055 1066 TYPE_PNV8_PSI, &error_abort, NULL);
77864267 1067
f6d4dca8 1068 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
82514be2 1069 TYPE_PNV8_LPC, &error_abort, NULL);
77864267 1070
f6d4dca8 1071 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
3233838c 1072 TYPE_PNV8_OCC, &error_abort, NULL);
3887d241
B		 1073
1074 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1075 TYPE_PNV8_HOMER, &error_abort, NULL);
9ae1329e
CLG		 1076
1077 for (i = 0; i < pcc->num_phbs; i++) {
1078 object_initialize_child(obj, "phb[*]", &chip8->phbs[i],
1079 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3,
1080 &error_abort, NULL);
1081 }
1082
1083 /*
1084 * Number of PHBs is the chip default
1085 */
1086 chip->num_phbs = pcc->num_phbs;
77864267
CLG		 1087}
1088
1089static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1090 {
1091 PnvChip *chip = PNV_CHIP(chip8);
1092 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
77864267
CLG		 1093 int i, j;
1094 char *name;
77864267
CLG		 1095
1096 name = g_strdup_printf("icp-%x", chip->chip_id);
1097 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1098 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1099 g_free(name);
1100
1101 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1102
1103 /* Map the ICP registers for each thread */
1104 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 1105 PnvCore *pnv_core = chip->cores[i];
77864267
CLG		 1106 int core_hwid = CPU_CORE(pnv_core)->core_id;
1107
1108 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1109 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
245cdb7f 1110 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
77864267
CLG		 1111
1112 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1113 &icp->mmio);
1114 }
1115 }
1116}
1117
1118static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1119{
1120 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1121 PnvChip *chip = PNV_CHIP(dev);
1122 Pnv8Chip *chip8 = PNV8_CHIP(dev);
ae856055 1123 Pnv8Psi *psi8 = &chip8->psi;
77864267 1124 Error *local_err = NULL;
9ae1329e 1125 int i;
77864267 1126
245cdb7f
CLG		 1127 assert(chip8->xics);
1128
709044fd
CLG		 1129 /* XSCOM bridge is first */
1130 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1131 if (local_err) {
1132 error_propagate(errp, local_err);
1133 return;
1134 }
1135 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1136
77864267
CLG		 1137 pcc->parent_realize(dev, &local_err);
1138 if (local_err) {
1139 error_propagate(errp, local_err);
1140 return;
1141 }
1142
1143 /* Processor Service Interface (PSI) Host Bridge */
1144 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1145 "bar", &error_fatal);
245cdb7f 1146 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
34bdca8f 1147 ICS_PROP_XICS, &error_abort);
77864267
CLG		 1148 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1149 if (local_err) {
1150 error_propagate(errp, local_err);
1151 return;
1152 }
ae856055
CLG		 1153 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1154 &PNV_PSI(psi8)->xscom_regs);
77864267
CLG		 1155
1156 /* Create LPC controller */
b63f3893
GK		 1157 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1158 &error_abort);
77864267
CLG		 1159 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1160 &error_fatal);
1161 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1162
64d011d5
CLG		 1163 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1164 (uint64_t) PNV_XSCOM_BASE(chip),
1165 PNV_XSCOM_LPC_BASE);
1166
59b7c1c2
B		 1167 /*
1168 * Interrupt Management Area. This is the memory region holding
1169 * all the Interrupt Control Presenter (ICP) registers
1170 */
77864267
CLG		 1171 pnv_chip_icp_realize(chip8, &local_err);
1172 if (local_err) {
1173 error_propagate(errp, local_err);
1174 return;
1175 }
1176
1177 /* Create the simplified OCC model */
ee3d2713
GK		 1178 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1179 &error_abort);
77864267
CLG		 1180 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1181 if (local_err) {
1182 error_propagate(errp, local_err);
1183 return;
1184 }
1185 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
f3db8266
B		 1186
1187 /* OCC SRAM model */
3a1b70b6 1188 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
f3db8266 1189 &chip8->occ.sram_regs);
3887d241
B		 1190
1191 /* HOMER */
f2582acf
GK		 1192 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1193 &error_abort);
3887d241
B		 1194 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1195 &local_err);
1196 if (local_err) {
1197 error_propagate(errp, local_err);
1198 return;
1199 }
8f092316
CLG		 1200 /* Homer Xscom region */
1201 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1202
1203 /* Homer mmio region */
3887d241
B		 1204 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1205 &chip8->homer.regs);
9ae1329e
CLG		 1206
1207 /* PHB3 controllers */
1208 for (i = 0; i < chip->num_phbs; i++) {
1209 PnvPHB3 *phb = &chip8->phbs[i];
1210 PnvPBCQState *pbcq = &phb->pbcq;
1211
1212 object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
1213 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
1214 &error_fatal);
1215 object_property_set_bool(OBJECT(phb), true, "realized", &local_err);
1216 if (local_err) {
1217 error_propagate(errp, local_err);
1218 return;
1219 }
1220 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default());
1221
1222 /* Populate the XSCOM address space. */
1223 pnv_xscom_add_subregion(chip,
1224 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
1225 &pbcq->xscom_nest_regs);
1226 pnv_xscom_add_subregion(chip,
1227 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
1228 &pbcq->xscom_pci_regs);
1229 pnv_xscom_add_subregion(chip,
1230 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
1231 &pbcq->xscom_spci_regs);
1232 }
77864267
CLG		 1233}
1234
70c059e9
GK		 1235static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1236{
1237 addr &= (PNV_XSCOM_SIZE - 1);
1238 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1239}
1240
e997040e
CLG		 1241static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1242{
1243 DeviceClass *dc = DEVICE_CLASS(klass);
1244 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1245
e997040e 1246 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
397a79e7 1247 k->cores_mask = POWER8E_CORE_MASK;
9ae1329e 1248 k->num_phbs = 3;
631adaff 1249 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1250 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1251 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1252 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1253 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1254 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1255 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1256 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1257 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1258 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1259 dc->desc = "PowerNV Chip POWER8E";
77864267
CLG		 1260
1261 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1262 &k->parent_realize);
e997040e
CLG		 1263}
1264
e997040e
CLG		 1265static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1266{
1267 DeviceClass *dc = DEVICE_CLASS(klass);
1268 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1269
e997040e 1270 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
397a79e7 1271 k->cores_mask = POWER8_CORE_MASK;
9ae1329e 1272 k->num_phbs = 3;
631adaff 1273 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1274 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1275 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1276 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1277 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1278 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1279 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1280 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1281 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1282 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1283 dc->desc = "PowerNV Chip POWER8";
77864267
CLG		 1284
1285 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1286 &k->parent_realize);
e997040e
CLG		 1287}
1288
e997040e
CLG		 1289static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1290{
1291 DeviceClass *dc = DEVICE_CLASS(klass);
1292 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1293
e997040e 1294 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
397a79e7 1295 k->cores_mask = POWER8_CORE_MASK;
9ae1329e 1296 k->num_phbs = 3;
631adaff 1297 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1298 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1299 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1300 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1301 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1302 k->isa_create = pnv_chip_power8nvl_isa_create;
eb859a27 1303 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1304 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1305 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1306 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1307 dc->desc = "PowerNV Chip POWER8NVL";
77864267
CLG		 1308
1309 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1310 &k->parent_realize);
1311}
1312
1313static void pnv_chip_power9_instance_init(Object *obj)
1314{
4f9924c4 1315 PnvChip *chip = PNV_CHIP(obj);
2dfa91a2 1316 Pnv9Chip *chip9 = PNV9_CHIP(obj);
4f9924c4
BH		 1317 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1318 int i;
2dfa91a2
CLG		 1319
1320 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1321 TYPE_PNV_XIVE, &error_abort, NULL);
d1214b81 1322 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
d2623129 1323 "xive-fabric");
c38536bc
CLG		 1324
1325 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1326 TYPE_PNV9_PSI, &error_abort, NULL);
15376c66
CLG		 1327
1328 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1329 TYPE_PNV9_LPC, &error_abort, NULL);
6598a70d
CLG		 1330
1331 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1332 TYPE_PNV9_OCC, &error_abort, NULL);
3887d241
B		 1333
1334 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1335 TYPE_PNV9_HOMER, &error_abort, NULL);
4f9924c4
BH		 1336
1337 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1338 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1339 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC,
1340 &error_abort, NULL);
1341 }
1342
1343 /*
1344 * Number of PHBs is the chip default
1345 */
1346 chip->num_phbs = pcc->num_phbs;
77864267
CLG		 1347}
1348
5dad902c
CLG		 1349static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1350{
1351 PnvChip *chip = PNV_CHIP(chip9);
5dad902c
CLG		 1352 int i;
1353
1354 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1355 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1356
1357 for (i = 0; i < chip9->nr_quads; i++) {
1358 char eq_name[32];
1359 PnvQuad *eq = &chip9->quads[i];
4fa28f23 1360 PnvCore *pnv_core = chip->cores[i * 4];
5dad902c
CLG		 1361 int core_id = CPU_CORE(pnv_core)->core_id;
1362
5dad902c 1363 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
bc4c406c
PMD		 1364 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1365 TYPE_PNV_QUAD, &error_fatal, NULL);
5dad902c 1366
5dad902c
CLG		 1367 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1368 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
5dad902c
CLG		 1369
1370 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1371 &eq->xscom_regs);
1372 }
1373}
1374
4f9924c4
BH		 1375static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
1376{
1377 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1378 Error *local_err = NULL;
1379 int i, j;
1380 int phb_id = 0;
1381
1382 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1383 PnvPhb4PecState *pec = &chip9->pecs[i];
1384 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1385 uint32_t pec_nest_base;
1386 uint32_t pec_pci_base;
1387
1388 object_property_set_int(OBJECT(pec), i, "index", &error_fatal);
1389 /*
1390 * PEC0 -> 1 stack
1391 * PEC1 -> 2 stacks
1392 * PEC2 -> 3 stacks
1393 */
1394 object_property_set_int(OBJECT(pec), i + 1, "num-stacks",
1395 &error_fatal);
1396 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id",
1397 &error_fatal);
1398 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()),
1399 "system-memory", &error_abort);
1400 object_property_set_bool(OBJECT(pec), true, "realized", &local_err);
1401 if (local_err) {
1402 error_propagate(errp, local_err);
1403 return;
1404 }
1405
1406 pec_nest_base = pecc->xscom_nest_base(pec);
1407 pec_pci_base = pecc->xscom_pci_base(pec);
1408
1409 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1410 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1411
1412 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
1413 j++, phb_id++) {
1414 PnvPhb4PecStack *stack = &pec->stacks[j];
1415 Object *obj = OBJECT(&stack->phb);
1416
1417 object_property_set_int(obj, phb_id, "index", &error_fatal);
1418 object_property_set_int(obj, chip->chip_id, "chip-id",
1419 &error_fatal);
1420 object_property_set_int(obj, PNV_PHB4_VERSION, "version",
1421 &error_fatal);
1422 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id",
1423 &error_fatal);
1424 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort);
1425 object_property_set_bool(obj, true, "realized", &local_err);
1426 if (local_err) {
1427 error_propagate(errp, local_err);
1428 return;
1429 }
1430 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default());
1431
1432 /* Populate the XSCOM address space. */
1433 pnv_xscom_add_subregion(chip,
1434 pec_nest_base + 0x40 * (stack->stack_no + 1),
1435 &stack->nest_regs_mr);
1436 pnv_xscom_add_subregion(chip,
1437 pec_pci_base + 0x40 * (stack->stack_no + 1),
1438 &stack->pci_regs_mr);
1439 pnv_xscom_add_subregion(chip,
1440 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1441 0x40 * stack->stack_no,
1442 &stack->phb_regs_mr);
1443 }
1444 }
1445}
1446
77864267
CLG		 1447static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1448{
1449 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2dfa91a2
CLG		 1450 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1451 PnvChip *chip = PNV_CHIP(dev);
c38536bc 1452 Pnv9Psi *psi9 = &chip9->psi;
77864267
CLG		 1453 Error *local_err = NULL;
1454
709044fd
CLG		 1455 /* XSCOM bridge is first */
1456 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1457 if (local_err) {
1458 error_propagate(errp, local_err);
1459 return;
1460 }
1461 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1462
77864267
CLG		 1463 pcc->parent_realize(dev, &local_err);
1464 if (local_err) {
1465 error_propagate(errp, local_err);
1466 return;
1467 }
2dfa91a2 1468
5dad902c
CLG		 1469 pnv_chip_quad_realize(chip9, &local_err);
1470 if (local_err) {
1471 error_propagate(errp, local_err);
1472 return;
1473 }
1474
2dfa91a2
CLG		 1475 /* XIVE interrupt controller (POWER9) */
1476 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1477 "ic-bar", &error_fatal);
1478 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1479 "vc-bar", &error_fatal);
1480 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1481 "pc-bar", &error_fatal);
1482 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1483 "tm-bar", &error_fatal);
7ae54cc3
GK		 1484 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1485 &error_abort);
2dfa91a2
CLG		 1486 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1487 &local_err);
1488 if (local_err) {
1489 error_propagate(errp, local_err);
1490 return;
1491 }
1492 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1493 &chip9->xive.xscom_regs);
c38536bc
CLG		 1494
1495 /* Processor Service Interface (PSI) Host Bridge */
1496 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1497 "bar", &error_fatal);
1498 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1499 if (local_err) {
1500 error_propagate(errp, local_err);
1501 return;
1502 }
1503 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1504 &PNV_PSI(psi9)->xscom_regs);
15376c66
CLG		 1505
1506 /* LPC */
b63f3893
GK		 1507 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1508 &error_abort);
15376c66
CLG		 1509 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1510 if (local_err) {
1511 error_propagate(errp, local_err);
1512 return;
1513 }
1514 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1515 &chip9->lpc.xscom_regs);
1516
1517 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1518 (uint64_t) PNV9_LPCM_BASE(chip));
6598a70d
CLG		 1519
1520 /* Create the simplified OCC model */
ee3d2713
GK		 1521 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1522 &error_abort);
6598a70d
CLG		 1523 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1524 if (local_err) {
1525 error_propagate(errp, local_err);
1526 return;
1527 }
1528 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
f3db8266
B		 1529
1530 /* OCC SRAM model */
3a1b70b6 1531 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
f3db8266 1532 &chip9->occ.sram_regs);
3887d241
B		 1533
1534 /* HOMER */
f2582acf
GK		 1535 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1536 &error_abort);
3887d241
B		 1537 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1538 &local_err);
1539 if (local_err) {
1540 error_propagate(errp, local_err);
1541 return;
1542 }
8f092316
CLG		 1543 /* Homer Xscom region */
1544 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1545
1546 /* Homer mmio region */
3887d241
B		 1547 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1548 &chip9->homer.regs);
4f9924c4
BH		 1549
1550 /* PHBs */
1551 pnv_chip_power9_phb_realize(chip, &local_err);
1552 if (local_err) {
1553 error_propagate(errp, local_err);
1554 return;
1555 }
e997040e
CLG		 1556}
1557
70c059e9
GK		 1558static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1559{
1560 addr &= (PNV9_XSCOM_SIZE - 1);
1561 return addr >> 3;
1562}
1563
e997040e
CLG		 1564static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1565{
1566 DeviceClass *dc = DEVICE_CLASS(klass);
1567 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1568
83028a2b 1569 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
397a79e7 1570 k->cores_mask = POWER9_CORE_MASK;
631adaff 1571 k->core_pir = pnv_chip_core_pir_p9;
d35aefa9 1572 k->intc_create = pnv_chip_power9_intc_create;
d49e8a9b 1573 k->intc_reset = pnv_chip_power9_intc_reset;
0990ce6a 1574 k->intc_destroy = pnv_chip_power9_intc_destroy;
85913070 1575 k->intc_print_info = pnv_chip_power9_intc_print_info;
04026890 1576 k->isa_create = pnv_chip_power9_isa_create;
eb859a27 1577 k->dt_populate = pnv_chip_power9_dt_populate;
d8e4aad5 1578 k->pic_print_info = pnv_chip_power9_pic_print_info;
c4b2c40c 1579 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
70c059e9 1580 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
e997040e 1581 dc->desc = "PowerNV Chip POWER9";
4f9924c4 1582 k->num_phbs = 6;
77864267
CLG		 1583
1584 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1585 &k->parent_realize);
e997040e
CLG		 1586}
1587
2b548a42
CLG		 1588static void pnv_chip_power10_instance_init(Object *obj)
1589{
8b50ce85
CLG		 1590 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1591
1592 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1593 TYPE_PNV10_PSI, &error_abort, NULL);
2661f6ab
CLG		 1594 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1595 TYPE_PNV10_LPC, &error_abort, NULL);
2b548a42
CLG		 1596}
1597
1598static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1599{
1600 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1601 PnvChip *chip = PNV_CHIP(dev);
8b50ce85 1602 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2b548a42
CLG		 1603 Error *local_err = NULL;
1604
1605 /* XSCOM bridge is first */
1606 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1607 if (local_err) {
1608 error_propagate(errp, local_err);
1609 return;
1610 }
1611 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1612
1613 pcc->parent_realize(dev, &local_err);
1614 if (local_err) {
1615 error_propagate(errp, local_err);
1616 return;
1617 }
8b50ce85
CLG		 1618
1619 /* Processor Service Interface (PSI) Host Bridge */
1620 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1621 "bar", &error_fatal);
1622 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1623 &local_err);
1624 if (local_err) {
1625 error_propagate(errp, local_err);
1626 return;
1627 }
1628 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1629 &PNV_PSI(&chip10->psi)->xscom_regs);
2661f6ab
CLG		 1630
1631 /* LPC */
1632 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1633 &error_abort);
1634 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1635 &local_err);
1636 if (local_err) {
1637 error_propagate(errp, local_err);
1638 return;
1639 }
1640 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1641 &chip10->lpc.xscom_regs);
1642
1643 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1644 (uint64_t) PNV10_LPCM_BASE(chip));
2b548a42
CLG		 1645}
1646
70c059e9
GK		 1647static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1648{
1649 addr &= (PNV10_XSCOM_SIZE - 1);
1650 return addr >> 3;
1651}
1652
2b548a42
CLG		 1653static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1654{
1655 DeviceClass *dc = DEVICE_CLASS(klass);
1656 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1657
2b548a42
CLG		 1658 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1659 k->cores_mask = POWER10_CORE_MASK;
1660 k->core_pir = pnv_chip_core_pir_p10;
1661 k->intc_create = pnv_chip_power10_intc_create;
1662 k->intc_reset = pnv_chip_power10_intc_reset;
1663 k->intc_destroy = pnv_chip_power10_intc_destroy;
85913070 1664 k->intc_print_info = pnv_chip_power10_intc_print_info;
2b548a42
CLG		 1665 k->isa_create = pnv_chip_power10_isa_create;
1666 k->dt_populate = pnv_chip_power10_dt_populate;
1667 k->pic_print_info = pnv_chip_power10_pic_print_info;
c4b2c40c 1668 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
70c059e9 1669 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2b548a42
CLG		 1670 dc->desc = "PowerNV Chip POWER10";
1671
1672 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1673 &k->parent_realize);
1674}
1675
397a79e7
CLG		 1676static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1677{
1678 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1679 int cores_max;
1680
1681 /*
1682 * No custom mask for this chip, let's use the default one from *
1683 * the chip class
1684 */
1685 if (!chip->cores_mask) {
1686 chip->cores_mask = pcc->cores_mask;
1687 }
1688
1689 /* filter alien core ids ! some are reserved */
1690 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1691 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1692 chip->cores_mask);
1693 return;
1694 }
1695 chip->cores_mask &= pcc->cores_mask;
1696
1697 /* now that we have a sane layout, let check the number of cores */
27d9ffd4 1698 cores_max = ctpop64(chip->cores_mask);
397a79e7
CLG		 1699 if (chip->nr_cores > cores_max) {
1700 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1701 cores_max);
1702 return;
1703 }
1704}
1705
51c04728 1706static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
e997040e 1707{
397a79e7 1708 Error *error = NULL;
d2fd9612 1709 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
40abf43f 1710 const char *typename = pnv_chip_core_typename(chip);
d2fd9612 1711 int i, core_hwid;
08c3f3a7 1712 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
d2fd9612
CLG		 1713
1714 if (!object_class_by_name(typename)) {
1715 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1716 return;
1717 }
397a79e7 1718
d2fd9612 1719 /* Cores */
397a79e7
CLG		 1720 pnv_chip_core_sanitize(chip, &error);
1721 if (error) {
1722 error_propagate(errp, error);
1723 return;
1724 }
d2fd9612 1725
4fa28f23 1726 chip->cores = g_new0(PnvCore *, chip->nr_cores);
d2fd9612
CLG		 1727
1728 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1729 && (i < chip->nr_cores); core_hwid++) {
1730 char core_name[32];
4fa28f23 1731 PnvCore *pnv_core;
c035851a 1732 uint64_t xscom_core_base;
d2fd9612
CLG		 1733
1734 if (!(chip->cores_mask & (1ull << core_hwid))) {
1735 continue;
1736 }
1737
4fa28f23
GK		 1738 pnv_core = PNV_CORE(object_new(typename));
1739
d2fd9612 1740 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
d2623129 1741 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
4fa28f23 1742 chip->cores[i] = pnv_core;
764f9b25
GK		 1743 object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
1744 "nr-threads", &error_fatal);
d2fd9612
CLG		 1745 object_property_set_int(OBJECT(pnv_core), core_hwid,
1746 CPU_CORE_PROP_CORE_ID, &error_fatal);
1747 object_property_set_int(OBJECT(pnv_core),
1748 pcc->core_pir(chip, core_hwid),
1749 "pir", &error_fatal);
08c3f3a7
CLG		 1750 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr,
1751 "hrmor", &error_fatal);
158e17a6
GK		 1752 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1753 &error_abort);
d2fd9612
CLG		 1754 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1755 &error_fatal);
24ece072
CLG		 1756
1757 /* Each core has an XSCOM MMIO region */
c4b2c40c 1758 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
c035851a
CLG		 1759
1760 pnv_xscom_add_subregion(chip, xscom_core_base,
4fa28f23 1761 &pnv_core->xscom_regs);
d2fd9612
CLG		 1762 i++;
1763 }
51c04728
CLG		 1764}
1765
1766static void pnv_chip_realize(DeviceState *dev, Error **errp)
1767{
1768 PnvChip *chip = PNV_CHIP(dev);
1769 Error *error = NULL;
1770
51c04728
CLG		 1771 /* Cores */
1772 pnv_chip_core_realize(chip, &error);
1773 if (error) {
1774 error_propagate(errp, error);
1775 return;
1776 }
e997040e
CLG		 1777}
1778
1779static Property pnv_chip_properties[] = {
1780 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1781 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1782 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
397a79e7
CLG		 1783 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1784 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
764f9b25 1785 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
4f9924c4 1786 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0),
e997040e
CLG		 1787 DEFINE_PROP_END_OF_LIST(),
1788};
1789
1790static void pnv_chip_class_init(ObjectClass *klass, void *data)
1791{
1792 DeviceClass *dc = DEVICE_CLASS(klass);
1793
9d169fb3 1794 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
e997040e 1795 dc->realize = pnv_chip_realize;
4f67d30b 1796 device_class_set_props(dc, pnv_chip_properties);
e997040e
CLG		 1797 dc->desc = "PowerNV Chip";
1798}
1799
119eaa9d
CLG		 1800PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1801{
1802 int i, j;
1803
1804 for (i = 0; i < chip->nr_cores; i++) {
1805 PnvCore *pc = chip->cores[i];
1806 CPUCore *cc = CPU_CORE(pc);
1807
1808 for (j = 0; j < cc->nr_threads; j++) {
1809 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1810 return pc->threads[j];
1811 }
1812 }
1813 }
1814 return NULL;
1815}
1816
54f59d78
CLG		 1817static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1818{
b168a138 1819 PnvMachineState *pnv = PNV_MACHINE(xi);
9ae1329e 1820 int i, j;
54f59d78
CLG		 1821
1822 for (i = 0; i < pnv->num_chips; i++) {
9ae1329e 1823 PnvChip *chip = pnv->chips[i];
77864267
CLG		 1824 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1825
1826 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1827 return &chip8->psi.ics;
54f59d78 1828 }
9ae1329e
CLG		 1829 for (j = 0; j < chip->num_phbs; j++) {
1830 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
1831 return &chip8->phbs[j].lsis;
1832 }
1833 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
1834 return ICS(&chip8->phbs[j].msis);
1835 }
1836 }
54f59d78
CLG		 1837 }
1838 return NULL;
1839}
1840
1841static void pnv_ics_resend(XICSFabric *xi)
1842{
b168a138 1843 PnvMachineState *pnv = PNV_MACHINE(xi);
9ae1329e 1844 int i, j;
54f59d78
CLG		 1845
1846 for (i = 0; i < pnv->num_chips; i++) {
9ae1329e 1847 PnvChip *chip = pnv->chips[i];
77864267 1848 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
9ae1329e 1849
77864267 1850 ics_resend(&chip8->psi.ics);
9ae1329e
CLG		 1851 for (j = 0; j < chip->num_phbs; j++) {
1852 ics_resend(&chip8->phbs[j].lsis);
1853 ics_resend(ICS(&chip8->phbs[j].msis));
1854 }
54f59d78
CLG		 1855 }
1856}
1857
36fc6f08
CLG		 1858static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1859{
1860 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1861
956b8f46 1862 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
36fc6f08
CLG		 1863}
1864
47fea43a
CLG		 1865static void pnv_pic_print_info(InterruptStatsProvider *obj,
1866 Monitor *mon)
1867{
b168a138 1868 PnvMachineState *pnv = PNV_MACHINE(obj);
54f59d78 1869 int i;
47fea43a
CLG		 1870 CPUState *cs;
1871
1872 CPU_FOREACH(cs) {
1873 PowerPCCPU *cpu = POWERPC_CPU(cs);
1874
85913070
GK		 1875 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1876 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1877 mon);
47fea43a 1878 }
54f59d78
CLG		 1879
1880 for (i = 0; i < pnv->num_chips; i++) {
d8e4aad5 1881 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
54f59d78 1882 }
47fea43a
CLG		 1883}
1884
c722579e
CLG		 1885static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1886 uint8_t nvt_blk, uint32_t nvt_idx,
1887 bool cam_ignore, uint8_t priority,
1888 uint32_t logic_serv,
1889 XiveTCTXMatch *match)
1890{
1891 PnvMachineState *pnv = PNV_MACHINE(xfb);
1892 int total_count = 0;
1893 int i;
1894
1895 for (i = 0; i < pnv->num_chips; i++) {
1896 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1897 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1898 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1899 int count;
1900
1901 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1902 priority, logic_serv, match);
1903
1904 if (count < 0) {
1905 return count;
1906 }
1907
1908 total_count += count;
1909 }
1910
1911 return total_count;
1912}
1913
f30c843c 1914static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
9e933f4a
BH		 1915{
1916 MachineClass *mc = MACHINE_CLASS(oc);
36fc6f08 1917 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
d76f2da7
GK		 1918 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1919 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
f30c843c
CLG		 1920
1921 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1922 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1923
1924 xic->icp_get = pnv_icp_get;
1925 xic->ics_get = pnv_ics_get;
1926 xic->ics_resend = pnv_ics_resend;
d76f2da7
GK		 1927
1928 pmc->compat = compat;
1929 pmc->compat_size = sizeof(compat);
f30c843c
CLG		 1930}
1931
1932static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1933{
1934 MachineClass *mc = MACHINE_CLASS(oc);
c722579e 1935 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
d76f2da7
GK		 1936 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1937 static const char compat[] = "qemu,powernv9\0ibm,powernv";
f30c843c
CLG		 1938
1939 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1940 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
c722579e 1941 xfc->match_nvt = pnv_match_nvt;
f30c843c
CLG		 1942
1943 mc->alias = "powernv";
d76f2da7
GK		 1944
1945 pmc->compat = compat;
1946 pmc->compat_size = sizeof(compat);
7a90c6a1 1947 pmc->dt_power_mgt = pnv_dt_power_mgt;
f30c843c
CLG		 1948}
1949
2b548a42
CLG		 1950static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1951{
1952 MachineClass *mc = MACHINE_CLASS(oc);
d76f2da7
GK		 1953 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1954 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2b548a42
CLG		 1955
1956 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1957 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
d76f2da7
GK		 1958
1959 pmc->compat = compat;
1960 pmc->compat_size = sizeof(compat);
7a90c6a1 1961 pmc->dt_power_mgt = pnv_dt_power_mgt;
2b548a42
CLG		 1962}
1963
08c3f3a7
CLG		 1964static bool pnv_machine_get_hb(Object *obj, Error **errp)
1965{
1966 PnvMachineState *pnv = PNV_MACHINE(obj);
1967
1968 return !!pnv->fw_load_addr;
1969}
1970
1971static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
1972{
1973 PnvMachineState *pnv = PNV_MACHINE(obj);
1974
1975 if (value) {
1976 pnv->fw_load_addr = 0x8000000;
1977 }
1978}
1979
01b552b0
NP		 1980static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
1981{
1982 PowerPCCPU *cpu = POWERPC_CPU(cs);
1983 CPUPPCState *env = &cpu->env;
1984
1985 cpu_synchronize_state(cs);
1986 ppc_cpu_do_system_reset(cs);
1987 /*
1988 * SRR1[42:45] is set to 0100 which the ISA defines as implementation
1989 * dependent. POWER processors use this for xscom triggered interrupts,
1990 * which come from the BMC or NMI IPIs.
1991 */
1992 env->spr[SPR_SRR1] |= PPC_BIT(43);
1993}
1994
1995static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
1996{
1997 CPUState *cs;
1998
1999 CPU_FOREACH(cs) {
2000 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2001 }
2002}
2003
f30c843c
CLG		 2004static void pnv_machine_class_init(ObjectClass *oc, void *data)
2005{
2006 MachineClass *mc = MACHINE_CLASS(oc);
47fea43a 2007 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
01b552b0 2008 NMIClass *nc = NMI_CLASS(oc);
9e933f4a
BH		 2009
2010 mc->desc = "IBM PowerNV (Non-Virtualized)";
b168a138
CLG		 2011 mc->init = pnv_init;
2012 mc->reset = pnv_reset;
9e933f4a 2013 mc->max_cpus = MAX_CPUS;
59b7c1c2
B		 2014 /* Pnv provides a AHCI device for storage */
2015 mc->block_default_type = IF_IDE;
9e933f4a
BH		 2016 mc->no_parallel = 1;
2017 mc->default_boot_order = NULL;
f1d18b0a
JS		 2018 /*
2019 * RAM defaults to less than 2048 for 32-bit hosts, and large
2020 * enough to fit the maximum initrd size at it's load address
2021 */
2022 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
173a36d8 2023 mc->default_ram_id = "pnv.ram";
47fea43a 2024 ispc->print_info = pnv_pic_print_info;
01b552b0 2025 nc->nmi_monitor_handler = pnv_nmi;
08c3f3a7
CLG		 2026
2027 object_class_property_add_bool(oc, "hb-mode",
d2623129 2028 pnv_machine_get_hb, pnv_machine_set_hb);
08c3f3a7 2029 object_class_property_set_description(oc, "hb-mode",
7eecec7d 2030 "Use a hostboot like boot loader");
9e933f4a
BH		 2031}
2032
77864267
CLG		 2033#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2034 { \
2035 .name = type, \
2036 .class_init = class_initfn, \
2037 .parent = TYPE_PNV8_CHIP, \
2038 }
2039
2040#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2041 { \
2042 .name = type, \
2043 .class_init = class_initfn, \
2044 .parent = TYPE_PNV9_CHIP, \
beba5c0f
IM		 2045 }
2046
2b548a42
CLG		 2047#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2048 { \
2049 .name = type, \
2050 .class_init = class_initfn, \
2051 .parent = TYPE_PNV10_CHIP, \
2052 }
2053
beba5c0f 2054static const TypeInfo types[] = {
2b548a42
CLG		 2055 {
2056 .name = MACHINE_TYPE_NAME("powernv10"),
2057 .parent = TYPE_PNV_MACHINE,
2058 .class_init = pnv_machine_power10_class_init,
2059 },
1aba8716
CLG		 2060 {
2061 .name = MACHINE_TYPE_NAME("powernv9"),
2062 .parent = TYPE_PNV_MACHINE,
2063 .class_init = pnv_machine_power9_class_init,
c722579e
CLG		 2064 .interfaces = (InterfaceInfo[]) {
2065 { TYPE_XIVE_FABRIC },
2066 { },
2067 },
1aba8716
CLG		 2068 },
2069 {
2070 .name = MACHINE_TYPE_NAME("powernv8"),
2071 .parent = TYPE_PNV_MACHINE,
2072 .class_init = pnv_machine_power8_class_init,
2073 .interfaces = (InterfaceInfo[]) {
2074 { TYPE_XICS_FABRIC },
2075 { },
2076 },
2077 },
beba5c0f 2078 {
b168a138 2079 .name = TYPE_PNV_MACHINE,
beba5c0f 2080 .parent = TYPE_MACHINE,
f30c843c 2081 .abstract = true,
beba5c0f 2082 .instance_size = sizeof(PnvMachineState),
b168a138 2083 .class_init = pnv_machine_class_init,
d76f2da7 2084 .class_size = sizeof(PnvMachineClass),
beba5c0f 2085 .interfaces = (InterfaceInfo[]) {
beba5c0f 2086 { TYPE_INTERRUPT_STATS_PROVIDER },
01b552b0 2087 { TYPE_NMI },
beba5c0f
IM		 2088 { },
2089 },
36fc6f08 2090 },
beba5c0f
IM		 2091 {
2092 .name = TYPE_PNV_CHIP,
2093 .parent = TYPE_SYS_BUS_DEVICE,
2094 .class_init = pnv_chip_class_init,
beba5c0f
IM		 2095 .instance_size = sizeof(PnvChip),
2096 .class_size = sizeof(PnvChipClass),
2097 .abstract = true,
2098 },
77864267 2099
2b548a42
CLG		 2100 /*
2101 * P10 chip and variants
2102 */
2103 {
2104 .name = TYPE_PNV10_CHIP,
2105 .parent = TYPE_PNV_CHIP,
2106 .instance_init = pnv_chip_power10_instance_init,
2107 .instance_size = sizeof(Pnv10Chip),
2108 },
2109 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2110
77864267
CLG		 2111 /*
2112 * P9 chip and variants
2113 */
2114 {
2115 .name = TYPE_PNV9_CHIP,
2116 .parent = TYPE_PNV_CHIP,
2117 .instance_init = pnv_chip_power9_instance_init,
2118 .instance_size = sizeof(Pnv9Chip),
2119 },
2120 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2121
2122 /*
2123 * P8 chip and variants
2124 */
2125 {
2126 .name = TYPE_PNV8_CHIP,
2127 .parent = TYPE_PNV_CHIP,
2128 .instance_init = pnv_chip_power8_instance_init,
2129 .instance_size = sizeof(Pnv8Chip),
2130 },
2131 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2132 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2133 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2134 pnv_chip_power8nvl_class_init),
9e933f4a
BH		 2135};
2136
beba5c0f 2137DEFINE_TYPES(types)
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