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ppc/pnv: Introduce PnvChipClass::xscom_pcba() method
[mirror_qemu.git] / hw / ppc / pnv.c
CommitLineData
9e933f4a
BH		 1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
fc6b3cf9 22#include "qemu/units.h"
9e933f4a
BH		 23#include "qapi/error.h"
24#include "sysemu/sysemu.h"
25#include "sysemu/numa.h"
71e8a915 26#include "sysemu/reset.h"
54d31236 27#include "sysemu/runstate.h"
d2528bdc 28#include "sysemu/cpus.h"
8d409261 29#include "sysemu/device_tree.h"
fcf5ef2a 30#include "target/ppc/cpu.h"
9e933f4a
BH		 31#include "qemu/log.h"
32#include "hw/ppc/fdt.h"
33#include "hw/ppc/ppc.h"
34#include "hw/ppc/pnv.h"
d2fd9612 35#include "hw/ppc/pnv_core.h"
9e933f4a
BH		 36#include "hw/loader.h"
37#include "exec/address-spaces.h"
e997040e 38#include "qapi/visitor.h"
47fea43a
CLG		 39#include "monitor/monitor.h"
40#include "hw/intc/intc.h"
aeaef83d 41#include "hw/ipmi/ipmi.h"
58969eee 42#include "target/ppc/mmu-hash64.h"
9e933f4a 43
36fc6f08 44#include "hw/ppc/xics.h"
a27bd6c7 45#include "hw/qdev-properties.h"
967b7523 46#include "hw/ppc/pnv_xscom.h"
35dde576 47#include "hw/ppc/pnv_pnor.h"
967b7523 48
3495b6b6 49#include "hw/isa/isa.h"
12e9493d 50#include "hw/boards.h"
3495b6b6 51#include "hw/char/serial.h"
bcdb9064 52#include "hw/rtc/mc146818rtc.h"
3495b6b6 53
9e933f4a
BH		 54#include <libfdt.h>
55
b268a616 56#define FDT_MAX_SIZE (1 * MiB)
9e933f4a
BH		 57
58#define FW_FILE_NAME "skiboot.lid"
59#define FW_LOAD_ADDR 0x0
b268a616 60#define FW_MAX_SIZE (4 * MiB)
9e933f4a
BH		 61
62#define KERNEL_LOAD_ADDR 0x20000000
b45b56ba 63#define KERNEL_MAX_SIZE (256 * MiB)
fef592f9 64#define INITRD_LOAD_ADDR 0x60000000
584ea7e7 65#define INITRD_MAX_SIZE (256 * MiB)
9e933f4a 66
40abf43f
IM		 67static const char *pnv_chip_core_typename(const PnvChip *o)
68{
69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
72 const char *core_type = object_class_get_name(object_class_by_name(s));
73 g_free(s);
74 return core_type;
75}
76
9e933f4a
BH		 77/*
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
80 * Let's make it 2^11
81 */
82#define MAX_CPUS 2048
83
84/*
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
87 * per chip.
88 */
b168a138 89static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
9e933f4a
BH		 90{
91 char *mem_name;
92 uint64_t mem_reg_property[2];
93 int off;
94
95 mem_reg_property[0] = cpu_to_be64(start);
96 mem_reg_property[1] = cpu_to_be64(size);
97
98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
99 off = fdt_add_subnode(fdt, 0, mem_name);
100 g_free(mem_name);
101
102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
104 sizeof(mem_reg_property))));
105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
106}
107
d2fd9612
CLG		 108static int get_cpus_node(void *fdt)
109{
110 int cpus_offset = fdt_path_offset(fdt, "/cpus");
111
112 if (cpus_offset < 0) {
a4f3885c 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
d2fd9612
CLG		 114 if (cpus_offset) {
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
117 }
118 }
119 _FDT(cpus_offset);
120 return cpus_offset;
121}
122
123/*
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
128 * servers.
129 */
b168a138 130static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
d2fd9612 131{
08304a86
DG		 132 PowerPCCPU *cpu = pc->threads[0];
133 CPUState *cs = CPU(cpu);
d2fd9612 134 DeviceClass *dc = DEVICE_GET_CLASS(cs);
8bd9530e 135 int smt_threads = CPU_CORE(pc)->nr_threads;
d2fd9612
CLG		 136 CPUPPCState *env = &cpu->env;
137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
138 uint32_t servers_prop[smt_threads];
139 int i;
140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
143 uint32_t cpufreq = 1000000000;
144 uint32_t page_sizes_prop[64];
145 size_t page_sizes_prop_size;
146 const uint8_t pa_features[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
151 int offset;
152 char *nodename;
153 int cpus_offset = get_cpus_node(fdt);
154
155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
156 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
157 _FDT(offset);
158 g_free(nodename);
159
160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
161
162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
168 env->dcache_line_size)));
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
170 env->dcache_line_size)));
171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
172 env->icache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
174 env->icache_line_size)));
175
176 if (pcc->l1_dcache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
178 pcc->l1_dcache_size)));
179 } else {
3dc6f869 180 warn_report("Unknown L1 dcache size for cpu");
d2fd9612
CLG		 181 }
182 if (pcc->l1_icache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
184 pcc->l1_icache_size)));
185 } else {
3dc6f869 186 warn_report("Unknown L1 icache size for cpu");
d2fd9612
CLG		 187 }
188
189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
59b7c1c2
B		 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
192 cpu->hash64_opts->slb_size)));
d2fd9612
CLG		 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
195
196 if (env->spr_cb[SPR_PURR].oea_read) {
197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
198 }
199
58969eee 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
d2fd9612
CLG		 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
202 segs, sizeof(segs))));
203 }
204
59b7c1c2
B		 205 /*
206 * Advertise VMX/VSX (vector extensions) if available
d2fd9612
CLG		 207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
59b7c1c2
B		 209 * 2 == VSX available
210 */
d2fd9612
CLG		 211 if (env->insns_flags & PPC_ALTIVEC) {
212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
213
214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
215 }
216
59b7c1c2
B		 217 /*
218 * Advertise DFP (Decimal Floating Point) if available
d2fd9612 219 * 0 / no property == no DFP
59b7c1c2
B		 220 * 1 == DFP available
221 */
d2fd9612
CLG		 222 if (env->insns_flags2 & PPC2_DFP) {
223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
224 }
225
644a2c99
DG		 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
227 sizeof(page_sizes_prop));
d2fd9612
CLG		 228 if (page_sizes_prop_size) {
229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
230 page_sizes_prop, page_sizes_prop_size)));
231 }
232
233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
234 pa_features, sizeof(pa_features))));
235
d2fd9612
CLG		 236 /* Build interrupt servers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(pc->pir + i);
239 }
240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
241 servers_prop, sizeof(servers_prop))));
242}
243
b168a138
CLG		 244static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
245 uint32_t nr_threads)
bf5615e7
CLG		 246{
247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
248 char *name;
249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange[2], i, rsize;
251 uint64_t *reg;
252 int offset;
253
254 irange[0] = cpu_to_be32(pir);
255 irange[1] = cpu_to_be32(nr_threads);
256
257 rsize = sizeof(uint64_t) * 2 * nr_threads;
258 reg = g_malloc(rsize);
259 for (i = 0; i < nr_threads; i++) {
260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
261 reg[i * 2 + 1] = cpu_to_be64(0x1000);
262 }
263
264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
265 offset = fdt_add_subnode(fdt, 0, name);
266 _FDT(offset);
267 g_free(name);
268
269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
271 _FDT((fdt_setprop_string(fdt, offset, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
275 irange, sizeof(irange))));
276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
278 g_free(reg);
279}
280
eb859a27 281static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
e997040e 282{
c396c58a 283 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
d2fd9612
CLG		 284 int i;
285
3f5b45ca
GK		 286 pnv_dt_xscom(chip, fdt, 0,
287 cpu_to_be64(PNV_XSCOM_BASE(chip)),
c396c58a
GK		 288 cpu_to_be64(PNV_XSCOM_SIZE),
289 compat, sizeof(compat));
967b7523 290
d2fd9612 291 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 292 PnvCore *pnv_core = chip->cores[i];
d2fd9612 293
b168a138 294 pnv_dt_core(chip, pnv_core, fdt);
bf5615e7
CLG		 295
296 /* Interrupt Control Presenters (ICP). One per core. */
b168a138 297 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
d2fd9612
CLG		 298 }
299
e997040e 300 if (chip->ram_size) {
b168a138 301 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
e997040e
CLG		 302 }
303}
304
eb859a27
CLG		 305static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
306{
c396c58a 307 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
eb859a27
CLG		 308 int i;
309
3f5b45ca
GK		 310 pnv_dt_xscom(chip, fdt, 0,
311 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
c396c58a
GK		 312 cpu_to_be64(PNV9_XSCOM_SIZE),
313 compat, sizeof(compat));
eb859a27
CLG		 314
315 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 316 PnvCore *pnv_core = chip->cores[i];
eb859a27
CLG		 317
318 pnv_dt_core(chip, pnv_core, fdt);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
15376c66 324
2661f6ab 325 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
eb859a27
CLG		 326}
327
2b548a42
CLG		 328static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
329{
c396c58a 330 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
2b548a42
CLG		 331 int i;
332
3f5b45ca
GK		 333 pnv_dt_xscom(chip, fdt, 0,
334 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
c396c58a
GK		 335 cpu_to_be64(PNV10_XSCOM_SIZE),
336 compat, sizeof(compat));
2b548a42
CLG		 337
338 for (i = 0; i < chip->nr_cores; i++) {
339 PnvCore *pnv_core = chip->cores[i];
340
341 pnv_dt_core(chip, pnv_core, fdt);
342 }
343
344 if (chip->ram_size) {
345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
346 }
2661f6ab
CLG		 347
348 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
2b548a42
CLG		 349}
350
b168a138 351static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
c5ffdcae
CLG		 352{
353 uint32_t io_base = d->ioport_id;
354 uint32_t io_regs[] = {
355 cpu_to_be32(1),
356 cpu_to_be32(io_base),
357 cpu_to_be32(2)
358 };
359 char *name;
360 int node;
361
362 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
363 node = fdt_add_subnode(fdt, lpc_off, name);
364 _FDT(node);
365 g_free(name);
366
367 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
368 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
369}
370
b168a138 371static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cb228f5a
CLG		 372{
373 const char compatible[] = "ns16550\0pnpPNP,501";
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(8)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
390 sizeof(compatible))));
391
392 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
393 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
396 fdt_get_phandle(fdt, lpc_off))));
397
398 /* This is needed by Linux */
399 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
400}
401
b168a138 402static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
04f6c8b2
CLG		 403{
404 const char compatible[] = "bt\0ipmi-bt";
405 uint32_t io_base;
406 uint32_t io_regs[] = {
407 cpu_to_be32(1),
408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
409 cpu_to_be32(3)
410 };
411 uint32_t irq;
412 char *name;
413 int node;
414
415 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
416 io_regs[1] = cpu_to_be32(io_base);
417
418 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
419
420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
421 node = fdt_add_subnode(fdt, lpc_off, name);
422 _FDT(node);
423 g_free(name);
424
7032d92a
CLG		 425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
426 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
427 sizeof(compatible))));
04f6c8b2
CLG		 428
429 /* Mark it as reserved to avoid Linux trying to claim it */
430 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
433 fdt_get_phandle(fdt, lpc_off))));
434}
435
e7a3fee3
CLG		 436typedef struct ForeachPopulateArgs {
437 void *fdt;
438 int offset;
439} ForeachPopulateArgs;
440
b168a138 441static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
e7a3fee3 442{
c5ffdcae
CLG		 443 ForeachPopulateArgs *args = opaque;
444 ISADevice *d = ISA_DEVICE(dev);
445
446 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
b168a138 447 pnv_dt_rtc(d, args->fdt, args->offset);
cb228f5a 448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
b168a138 449 pnv_dt_serial(d, args->fdt, args->offset);
04f6c8b2 450 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
b168a138 451 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
c5ffdcae
CLG		 452 } else {
453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
454 d->ioport_id);
455 }
456
e7a3fee3
CLG		 457 return 0;
458}
459
59b7c1c2
B		 460/*
461 * The default LPC bus of a multichip system is on chip 0. It's
bb7ab95c
CLG		 462 * recognized by the firmware (skiboot) using a "primary" property.
463 */
464static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
465{
64d011d5 466 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
e7a3fee3
CLG		 467 ForeachPopulateArgs args = {
468 .fdt = fdt,
bb7ab95c 469 .offset = isa_offset,
e7a3fee3 470 };
f47a08d1 471 uint32_t phandle;
e7a3fee3 472
bb7ab95c
CLG		 473 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
474
f47a08d1
CLG		 475 phandle = qemu_fdt_alloc_phandle(fdt);
476 assert(phandle > 0);
477 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
478
59b7c1c2
B		 479 /*
480 * ISA devices are not necessarily parented to the ISA bus so we
481 * can not use object_child_foreach()
482 */
bb7ab95c
CLG		 483 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
484 &args);
e7a3fee3
CLG		 485}
486
7a90c6a1 487static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
e5694793
CLG		 488{
489 int off;
490
491 off = fdt_add_subnode(fdt, 0, "ibm,opal");
492 off = fdt_add_subnode(fdt, off, "power-mgt");
493
494 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
495}
496
b168a138 497static void *pnv_dt_create(MachineState *machine)
9e933f4a 498{
d76f2da7 499 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
b168a138 500 PnvMachineState *pnv = PNV_MACHINE(machine);
9e933f4a
BH		 501 void *fdt;
502 char *buf;
503 int off;
e997040e 504 int i;
9e933f4a
BH		 505
506 fdt = g_malloc0(FDT_MAX_SIZE);
507 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
508
ccb099b3
CLG		 509 /* /qemu node */
510 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
511
9e933f4a
BH		 512 /* Root node */
513 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
514 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
515 _FDT((fdt_setprop_string(fdt, 0, "model",
516 "IBM PowerNV (emulated by qemu)")));
d76f2da7 517 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
9e933f4a
BH		 518
519 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
521 if (qemu_uuid_set) {
522 _FDT((fdt_property_string(fdt, "system-id", buf)));
523 }
524 g_free(buf);
525
526 off = fdt_add_subnode(fdt, 0, "chosen");
527 if (machine->kernel_cmdline) {
528 _FDT((fdt_setprop_string(fdt, off, "bootargs",
529 machine->kernel_cmdline)));
530 }
531
532 if (pnv->initrd_size) {
533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
535
536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
537 &start_prop, sizeof(start_prop))));
538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
539 &end_prop, sizeof(end_prop))));
540 }
541
e997040e
CLG		 542 /* Populate device tree for each chip */
543 for (i = 0; i < pnv->num_chips; i++) {
eb859a27 544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
e997040e 545 }
e7a3fee3
CLG		 546
547 /* Populate ISA devices on chip 0 */
bb7ab95c 548 pnv_dt_isa(pnv, fdt);
aeaef83d
CLG		 549
550 if (pnv->bmc) {
b168a138 551 pnv_dt_bmc_sensors(pnv->bmc, fdt);
aeaef83d
CLG		 552 }
553
7a90c6a1
GK		 554 /* Create an extra node for power management on machines that support it */
555 if (pmc->dt_power_mgt) {
556 pmc->dt_power_mgt(pnv, fdt);
e5694793
CLG		 557 }
558
9e933f4a
BH		 559 return fdt;
560}
561
bce0b691
CLG		 562static void pnv_powerdown_notify(Notifier *n, void *opaque)
563{
b168a138 564 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
bce0b691
CLG		 565
566 if (pnv->bmc) {
567 pnv_bmc_powerdown(pnv->bmc);
568 }
569}
570
a0628599 571static void pnv_reset(MachineState *machine)
9e933f4a 572{
9e933f4a
BH		 573 void *fdt;
574
575 qemu_devices_reset();
576
b168a138 577 fdt = pnv_dt_create(machine);
9e933f4a
BH		 578
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt)));
581
8d409261 582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
9e933f4a
BH		 583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
584}
585
04026890 586static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
3495b6b6 587{
77864267
CLG		 588 Pnv8Chip *chip8 = PNV8_CHIP(chip);
589 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
04026890 590}
3495b6b6 591
04026890
CLG		 592static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
593{
77864267
CLG		 594 Pnv8Chip *chip8 = PNV8_CHIP(chip);
595 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
04026890 596}
3495b6b6 597
04026890
CLG		 598static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
599{
15376c66
CLG		 600 Pnv9Chip *chip9 = PNV9_CHIP(chip);
601 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
04026890 602}
3495b6b6 603
2b548a42
CLG		 604static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
605{
2661f6ab
CLG		 606 Pnv10Chip *chip10 = PNV10_CHIP(chip);
607 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
2b548a42
CLG		 608}
609
04026890
CLG		 610static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
611{
612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
3495b6b6
CLG		 613}
614
d8e4aad5
CLG		 615static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
616{
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618
619 ics_pic_print_info(&chip8->psi.ics, mon);
620}
621
622static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
623{
624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625
626 pnv_xive_pic_print_info(&chip9->xive, mon);
c38536bc 627 pnv_psi_pic_print_info(&chip9->psi, mon);
d8e4aad5
CLG		 628}
629
c4b2c40c
GK		 630static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
631 uint32_t core_id)
632{
633 return PNV_XSCOM_EX_BASE(core_id);
634}
635
636static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
637 uint32_t core_id)
638{
639 return PNV9_XSCOM_EC_BASE(core_id);
640}
641
642static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
643 uint32_t core_id)
644{
645 return PNV10_XSCOM_EC_BASE(core_id);
646}
647
f30c843c
CLG		 648static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
649{
650 PowerPCCPUClass *ppc_default =
651 POWERPC_CPU_CLASS(object_class_by_name(default_type));
652 PowerPCCPUClass *ppc =
653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
654
655 return ppc_default->pvr_match(ppc_default, ppc->pvr);
656}
657
e2392d43
CLG		 658static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
659{
660 Object *obj;
661
662 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
663 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
664 object_property_set_int(obj, irq, "irq", &error_fatal);
665 object_property_set_bool(obj, true, "realized", &error_fatal);
666}
667
2b548a42
CLG		 668static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
669{
8b50ce85
CLG		 670 Pnv10Chip *chip10 = PNV10_CHIP(chip);
671
672 pnv_psi_pic_print_info(&chip10->psi, mon);
2b548a42
CLG		 673}
674
b168a138 675static void pnv_init(MachineState *machine)
9e933f4a 676{
b168a138 677 PnvMachineState *pnv = PNV_MACHINE(machine);
f30c843c 678 MachineClass *mc = MACHINE_GET_CLASS(machine);
9e933f4a
BH		 679 MemoryRegion *ram;
680 char *fw_filename;
681 long fw_size;
e997040e
CLG		 682 int i;
683 char *chip_typename;
35dde576
CLG		 684 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
685 DeviceState *dev;
9e933f4a
BH		 686
687 /* allocate RAM */
d23b6caa 688 if (machine->ram_size < (1 * GiB)) {
3dc6f869 689 warn_report("skiboot may not work with < 1GB of RAM");
9e933f4a
BH		 690 }
691
692 ram = g_new(MemoryRegion, 1);
b168a138 693 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
9e933f4a
BH		 694 machine->ram_size);
695 memory_region_add_subregion(get_system_memory(), 0, ram);
696
35dde576
CLG		 697 /*
698 * Create our simple PNOR device
699 */
700 dev = qdev_create(NULL, TYPE_PNV_PNOR);
701 if (pnor) {
702 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
703 &error_abort);
704 }
705 qdev_init_nofail(dev);
706 pnv->pnor = PNV_PNOR(dev);
707
9e933f4a
BH		 708 /* load skiboot firmware */
709 if (bios_name == NULL) {
710 bios_name = FW_FILE_NAME;
711 }
712
713 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
15fcedb2
CLG		 714 if (!fw_filename) {
715 error_report("Could not find OPAL firmware '%s'", bios_name);
716 exit(1);
717 }
9e933f4a
BH		 718
719 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
720 if (fw_size < 0) {
15fcedb2 721 error_report("Could not load OPAL firmware '%s'", fw_filename);
9e933f4a
BH		 722 exit(1);
723 }
724 g_free(fw_filename);
725
726 /* load kernel */
727 if (machine->kernel_filename) {
728 long kernel_size;
729
730 kernel_size = load_image_targphys(machine->kernel_filename,
b45b56ba 731 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
9e933f4a 732 if (kernel_size < 0) {
802fc7ab 733 error_report("Could not load kernel '%s'",
7c6e8797 734 machine->kernel_filename);
9e933f4a
BH		 735 exit(1);
736 }
737 }
738
739 /* load initrd */
740 if (machine->initrd_filename) {
741 pnv->initrd_base = INITRD_LOAD_ADDR;
742 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
584ea7e7 743 pnv->initrd_base, INITRD_MAX_SIZE);
9e933f4a 744 if (pnv->initrd_size < 0) {
802fc7ab 745 error_report("Could not load initial ram disk '%s'",
9e933f4a
BH		 746 machine->initrd_filename);
747 exit(1);
748 }
749 }
e997040e 750
f30c843c
CLG		 751 /*
752 * Check compatibility of the specified CPU with the machine
753 * default.
754 */
755 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
756 error_report("invalid CPU model '%s' for %s machine",
757 machine->cpu_type, mc->name);
758 exit(1);
759 }
760
e997040e 761 /* Create the processor chips */
4a12c699 762 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
7fd544d8 763 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
4a12c699 764 i, machine->cpu_type);
e997040e 765 if (!object_class_by_name(chip_typename)) {
f30c843c
CLG		 766 error_report("invalid chip model '%.*s' for %s machine",
767 i, machine->cpu_type, mc->name);
e997040e
CLG		 768 exit(1);
769 }
770
771 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
772 for (i = 0; i < pnv->num_chips; i++) {
773 char chip_name[32];
774 Object *chip = object_new(chip_typename);
775
776 pnv->chips[i] = PNV_CHIP(chip);
777
59b7c1c2
B		 778 /*
779 * TODO: put all the memory in one node on chip 0 until we find a
e997040e
CLG		 780 * way to specify different ranges for each chip
781 */
782 if (i == 0) {
783 object_property_set_int(chip, machine->ram_size, "ram-size",
784 &error_fatal);
785 }
786
787 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
788 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
789 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
790 &error_fatal);
fe6b6346
LX		 791 object_property_set_int(chip, machine->smp.cores,
792 "nr-cores", &error_fatal);
e997040e
CLG		 793 object_property_set_bool(chip, true, "realized", &error_fatal);
794 }
795 g_free(chip_typename);
3495b6b6 796
e2392d43
CLG		 797 /* Create the machine BMC simulator */
798 pnv->bmc = pnv_bmc_create();
799
3495b6b6 800 /* Instantiate ISA bus on chip 0 */
04026890 801 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
3495b6b6
CLG		 802
803 /* Create serial port */
def337ff 804 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
3495b6b6
CLG		 805
806 /* Create an RTC ISA device too */
6c646a11 807 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
bce0b691 808
e2392d43
CLG		 809 /* Create the IPMI BT device for communication with the BMC */
810 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
811
59b7c1c2
B		 812 /*
813 * OpenPOWER systems use a IPMI SEL Event message to notify the
814 * host to powerdown
815 */
bce0b691
CLG		 816 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
817 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
e997040e
CLG		 818}
819
631adaff
CLG		 820/*
821 * 0:21 Reserved - Read as zeros
822 * 22:24 Chip ID
823 * 25:28 Core number
824 * 29:31 Thread ID
825 */
826static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
827{
828 return (chip->chip_id << 7) | (core_id << 3);
829}
830
8fa1f4ef
CLG		 831static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
832 Error **errp)
d35aefa9 833{
8fa1f4ef
CLG		 834 Error *local_err = NULL;
835 Object *obj;
8907fc25 836 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8fa1f4ef
CLG		 837
838 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
839 &local_err);
840 if (local_err) {
841 error_propagate(errp, local_err);
842 return;
843 }
844
956b8f46 845 pnv_cpu->intc = obj;
d35aefa9
CLG		 846}
847
0990ce6a 848
d49e8a9b
CLG		 849static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
850{
851 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
852
853 icp_reset(ICP(pnv_cpu->intc));
854}
855
0990ce6a
GK		 856static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
857{
858 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
859
860 icp_destroy(ICP(pnv_cpu->intc));
861 pnv_cpu->intc = NULL;
862}
863
85913070
GK		 864static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
865 Monitor *mon)
866{
867 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
868}
869
631adaff
CLG		 870/*
871 * 0:48 Reserved - Read as zeroes
872 * 49:52 Node ID
873 * 53:55 Chip ID
874 * 56 Reserved - Read as zero
875 * 57:61 Core number
876 * 62:63 Thread ID
877 *
878 * We only care about the lower bits. uint32_t is fine for the moment.
879 */
880static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
881{
882 return (chip->chip_id << 8) | (core_id << 2);
883}
884
2b548a42
CLG		 885static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
886{
887 return (chip->chip_id << 8) | (core_id << 2);
888}
889
8fa1f4ef
CLG		 890static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
891 Error **errp)
d35aefa9 892{
2dfa91a2
CLG		 893 Pnv9Chip *chip9 = PNV9_CHIP(chip);
894 Error *local_err = NULL;
895 Object *obj;
896 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
897
898 /*
899 * The core creates its interrupt presenter but the XIVE interrupt
900 * controller object is initialized afterwards. Hopefully, it's
901 * only used at runtime.
902 */
26aa5b1e 903 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
2dfa91a2
CLG		 904 if (local_err) {
905 error_propagate(errp, local_err);
906 return;
907 }
908
909 pnv_cpu->intc = obj;
d35aefa9
CLG		 910}
911
d49e8a9b
CLG		 912static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
913{
914 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
915
916 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
917}
918
0990ce6a
GK		 919static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
920{
921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
922
923 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
924 pnv_cpu->intc = NULL;
925}
926
85913070
GK		 927static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
928 Monitor *mon)
929{
930 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
931}
932
2b548a42
CLG		 933static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
934 Error **errp)
935{
936 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
937
938 /* Will be defined when the interrupt controller is */
939 pnv_cpu->intc = NULL;
940}
941
942static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
943{
944 ;
945}
946
947static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
948{
949 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
950
951 pnv_cpu->intc = NULL;
952}
953
85913070
GK		 954static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
955 Monitor *mon)
956{
957}
958
59b7c1c2
B		 959/*
960 * Allowed core identifiers on a POWER8 Processor Chip :
397a79e7
CLG		 961 *
962 * <EX0 reserved>
963 * EX1 - Venice only
964 * EX2 - Venice only
965 * EX3 - Venice only
966 * EX4
967 * EX5
968 * EX6
969 * <EX7,8 reserved> <reserved>
970 * EX9 - Venice only
971 * EX10 - Venice only
972 * EX11 - Venice only
973 * EX12
974 * EX13
975 * EX14
976 * <EX15 reserved>
977 */
978#define POWER8E_CORE_MASK (0x7070ull)
979#define POWER8_CORE_MASK (0x7e7eull)
980
981/*
09279d7e 982 * POWER9 has 24 cores, ids starting at 0x0
397a79e7 983 */
09279d7e 984#define POWER9_CORE_MASK (0xffffffffffffffull)
397a79e7 985
2b548a42
CLG		 986
987#define POWER10_CORE_MASK (0xffffffffffffffull)
988
77864267
CLG		 989static void pnv_chip_power8_instance_init(Object *obj)
990{
991 Pnv8Chip *chip8 = PNV8_CHIP(obj);
992
f6d4dca8 993 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
ae856055 994 TYPE_PNV8_PSI, &error_abort, NULL);
77864267
CLG		 995 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
996 OBJECT(qdev_get_machine()), &error_abort);
997
f6d4dca8 998 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
82514be2 999 TYPE_PNV8_LPC, &error_abort, NULL);
77864267 1000
f6d4dca8 1001 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
3233838c 1002 TYPE_PNV8_OCC, &error_abort, NULL);
3887d241
B		 1003
1004 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1005 TYPE_PNV8_HOMER, &error_abort, NULL);
77864267
CLG		 1006}
1007
1008static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1009 {
1010 PnvChip *chip = PNV_CHIP(chip8);
1011 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
77864267
CLG		 1012 int i, j;
1013 char *name;
1014 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
1015
1016 name = g_strdup_printf("icp-%x", chip->chip_id);
1017 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1018 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1019 g_free(name);
1020
1021 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1022
1023 /* Map the ICP registers for each thread */
1024 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 1025 PnvCore *pnv_core = chip->cores[i];
77864267
CLG		 1026 int core_hwid = CPU_CORE(pnv_core)->core_id;
1027
1028 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1029 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1030 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
1031
1032 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1033 &icp->mmio);
1034 }
1035 }
1036}
1037
1038static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1039{
1040 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1041 PnvChip *chip = PNV_CHIP(dev);
1042 Pnv8Chip *chip8 = PNV8_CHIP(dev);
ae856055 1043 Pnv8Psi *psi8 = &chip8->psi;
77864267
CLG		 1044 Error *local_err = NULL;
1045
709044fd
CLG		 1046 /* XSCOM bridge is first */
1047 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1048 if (local_err) {
1049 error_propagate(errp, local_err);
1050 return;
1051 }
1052 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1053
77864267
CLG		 1054 pcc->parent_realize(dev, &local_err);
1055 if (local_err) {
1056 error_propagate(errp, local_err);
1057 return;
1058 }
1059
1060 /* Processor Service Interface (PSI) Host Bridge */
1061 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1062 "bar", &error_fatal);
1063 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1064 if (local_err) {
1065 error_propagate(errp, local_err);
1066 return;
1067 }
ae856055
CLG		 1068 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1069 &PNV_PSI(psi8)->xscom_regs);
77864267
CLG		 1070
1071 /* Create LPC controller */
b63f3893
GK		 1072 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1073 &error_abort);
77864267
CLG		 1074 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1075 &error_fatal);
1076 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1077
64d011d5
CLG		 1078 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1079 (uint64_t) PNV_XSCOM_BASE(chip),
1080 PNV_XSCOM_LPC_BASE);
1081
59b7c1c2
B		 1082 /*
1083 * Interrupt Management Area. This is the memory region holding
1084 * all the Interrupt Control Presenter (ICP) registers
1085 */
77864267
CLG		 1086 pnv_chip_icp_realize(chip8, &local_err);
1087 if (local_err) {
1088 error_propagate(errp, local_err);
1089 return;
1090 }
1091
1092 /* Create the simplified OCC model */
ee3d2713
GK		 1093 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1094 &error_abort);
77864267
CLG		 1095 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1096 if (local_err) {
1097 error_propagate(errp, local_err);
1098 return;
1099 }
1100 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
f3db8266
B		 1101
1102 /* OCC SRAM model */
3a1b70b6 1103 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
f3db8266 1104 &chip8->occ.sram_regs);
3887d241
B		 1105
1106 /* HOMER */
f2582acf
GK		 1107 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1108 &error_abort);
3887d241
B		 1109 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1110 &local_err);
1111 if (local_err) {
1112 error_propagate(errp, local_err);
1113 return;
1114 }
8f092316
CLG		 1115 /* Homer Xscom region */
1116 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1117
1118 /* Homer mmio region */
3887d241
B		 1119 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1120 &chip8->homer.regs);
77864267
CLG		 1121}
1122
70c059e9
GK		 1123static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1124{
1125 addr &= (PNV_XSCOM_SIZE - 1);
1126 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1127}
1128
e997040e
CLG		 1129static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1130{
1131 DeviceClass *dc = DEVICE_CLASS(klass);
1132 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1133
e997040e
CLG		 1134 k->chip_type = PNV_CHIP_POWER8E;
1135 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
397a79e7 1136 k->cores_mask = POWER8E_CORE_MASK;
631adaff 1137 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1138 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1139 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1140 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1141 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1142 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1143 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1144 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1145 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1146 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1147 dc->desc = "PowerNV Chip POWER8E";
77864267
CLG		 1148
1149 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1150 &k->parent_realize);
e997040e
CLG		 1151}
1152
e997040e
CLG		 1153static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1154{
1155 DeviceClass *dc = DEVICE_CLASS(klass);
1156 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1157
e997040e
CLG		 1158 k->chip_type = PNV_CHIP_POWER8;
1159 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
397a79e7 1160 k->cores_mask = POWER8_CORE_MASK;
631adaff 1161 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1162 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1163 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1164 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1165 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1166 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1167 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1168 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1169 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1170 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1171 dc->desc = "PowerNV Chip POWER8";
77864267
CLG		 1172
1173 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1174 &k->parent_realize);
e997040e
CLG		 1175}
1176
e997040e
CLG		 1177static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1178{
1179 DeviceClass *dc = DEVICE_CLASS(klass);
1180 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1181
e997040e
CLG		 1182 k->chip_type = PNV_CHIP_POWER8NVL;
1183 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
397a79e7 1184 k->cores_mask = POWER8_CORE_MASK;
631adaff 1185 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1186 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1187 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1188 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1189 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1190 k->isa_create = pnv_chip_power8nvl_isa_create;
eb859a27 1191 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1192 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1193 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1194 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1195 dc->desc = "PowerNV Chip POWER8NVL";
77864267
CLG		 1196
1197 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1198 &k->parent_realize);
1199}
1200
1201static void pnv_chip_power9_instance_init(Object *obj)
1202{
2dfa91a2
CLG		 1203 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1204
1205 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1206 TYPE_PNV_XIVE, &error_abort, NULL);
c38536bc
CLG		 1207
1208 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1209 TYPE_PNV9_PSI, &error_abort, NULL);
15376c66
CLG		 1210
1211 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1212 TYPE_PNV9_LPC, &error_abort, NULL);
6598a70d
CLG		 1213
1214 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1215 TYPE_PNV9_OCC, &error_abort, NULL);
3887d241
B		 1216
1217 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1218 TYPE_PNV9_HOMER, &error_abort, NULL);
77864267
CLG		 1219}
1220
5dad902c
CLG		 1221static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1222{
1223 PnvChip *chip = PNV_CHIP(chip9);
5dad902c
CLG		 1224 int i;
1225
1226 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1227 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1228
1229 for (i = 0; i < chip9->nr_quads; i++) {
1230 char eq_name[32];
1231 PnvQuad *eq = &chip9->quads[i];
4fa28f23 1232 PnvCore *pnv_core = chip->cores[i * 4];
5dad902c
CLG		 1233 int core_id = CPU_CORE(pnv_core)->core_id;
1234
5dad902c 1235 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
bc4c406c
PMD		 1236 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1237 TYPE_PNV_QUAD, &error_fatal, NULL);
5dad902c 1238
5dad902c
CLG		 1239 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1240 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
5dad902c
CLG		 1241
1242 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1243 &eq->xscom_regs);
1244 }
1245}
1246
77864267
CLG		 1247static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1248{
1249 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2dfa91a2
CLG		 1250 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1251 PnvChip *chip = PNV_CHIP(dev);
c38536bc 1252 Pnv9Psi *psi9 = &chip9->psi;
77864267
CLG		 1253 Error *local_err = NULL;
1254
709044fd
CLG		 1255 /* XSCOM bridge is first */
1256 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1257 if (local_err) {
1258 error_propagate(errp, local_err);
1259 return;
1260 }
1261 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1262
77864267
CLG		 1263 pcc->parent_realize(dev, &local_err);
1264 if (local_err) {
1265 error_propagate(errp, local_err);
1266 return;
1267 }
2dfa91a2 1268
5dad902c
CLG		 1269 pnv_chip_quad_realize(chip9, &local_err);
1270 if (local_err) {
1271 error_propagate(errp, local_err);
1272 return;
1273 }
1274
2dfa91a2
CLG		 1275 /* XIVE interrupt controller (POWER9) */
1276 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1277 "ic-bar", &error_fatal);
1278 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1279 "vc-bar", &error_fatal);
1280 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1281 "pc-bar", &error_fatal);
1282 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1283 "tm-bar", &error_fatal);
7ae54cc3
GK		 1284 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1285 &error_abort);
2dfa91a2
CLG		 1286 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1287 &local_err);
1288 if (local_err) {
1289 error_propagate(errp, local_err);
1290 return;
1291 }
1292 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1293 &chip9->xive.xscom_regs);
c38536bc
CLG		 1294
1295 /* Processor Service Interface (PSI) Host Bridge */
1296 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1297 "bar", &error_fatal);
1298 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1299 if (local_err) {
1300 error_propagate(errp, local_err);
1301 return;
1302 }
1303 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1304 &PNV_PSI(psi9)->xscom_regs);
15376c66
CLG		 1305
1306 /* LPC */
b63f3893
GK		 1307 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1308 &error_abort);
15376c66
CLG		 1309 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1310 if (local_err) {
1311 error_propagate(errp, local_err);
1312 return;
1313 }
1314 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1315 &chip9->lpc.xscom_regs);
1316
1317 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1318 (uint64_t) PNV9_LPCM_BASE(chip));
6598a70d
CLG		 1319
1320 /* Create the simplified OCC model */
ee3d2713
GK		 1321 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1322 &error_abort);
6598a70d
CLG		 1323 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1324 if (local_err) {
1325 error_propagate(errp, local_err);
1326 return;
1327 }
1328 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
f3db8266
B		 1329
1330 /* OCC SRAM model */
3a1b70b6 1331 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
f3db8266 1332 &chip9->occ.sram_regs);
3887d241
B		 1333
1334 /* HOMER */
f2582acf
GK		 1335 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1336 &error_abort);
3887d241
B		 1337 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1338 &local_err);
1339 if (local_err) {
1340 error_propagate(errp, local_err);
1341 return;
1342 }
8f092316
CLG		 1343 /* Homer Xscom region */
1344 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1345
1346 /* Homer mmio region */
3887d241
B		 1347 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1348 &chip9->homer.regs);
e997040e
CLG		 1349}
1350
70c059e9
GK		 1351static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1352{
1353 addr &= (PNV9_XSCOM_SIZE - 1);
1354 return addr >> 3;
1355}
1356
e997040e
CLG		 1357static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1358{
1359 DeviceClass *dc = DEVICE_CLASS(klass);
1360 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1361
e997040e 1362 k->chip_type = PNV_CHIP_POWER9;
83028a2b 1363 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
397a79e7 1364 k->cores_mask = POWER9_CORE_MASK;
631adaff 1365 k->core_pir = pnv_chip_core_pir_p9;
d35aefa9 1366 k->intc_create = pnv_chip_power9_intc_create;
d49e8a9b 1367 k->intc_reset = pnv_chip_power9_intc_reset;
0990ce6a 1368 k->intc_destroy = pnv_chip_power9_intc_destroy;
85913070 1369 k->intc_print_info = pnv_chip_power9_intc_print_info;
04026890 1370 k->isa_create = pnv_chip_power9_isa_create;
eb859a27 1371 k->dt_populate = pnv_chip_power9_dt_populate;
d8e4aad5 1372 k->pic_print_info = pnv_chip_power9_pic_print_info;
c4b2c40c 1373 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
70c059e9 1374 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
e997040e 1375 dc->desc = "PowerNV Chip POWER9";
77864267
CLG		 1376
1377 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1378 &k->parent_realize);
e997040e
CLG		 1379}
1380
2b548a42
CLG		 1381static void pnv_chip_power10_instance_init(Object *obj)
1382{
8b50ce85
CLG		 1383 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1384
1385 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1386 TYPE_PNV10_PSI, &error_abort, NULL);
2661f6ab
CLG		 1387 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1388 TYPE_PNV10_LPC, &error_abort, NULL);
2b548a42
CLG		 1389}
1390
1391static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1392{
1393 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1394 PnvChip *chip = PNV_CHIP(dev);
8b50ce85 1395 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2b548a42
CLG		 1396 Error *local_err = NULL;
1397
1398 /* XSCOM bridge is first */
1399 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1400 if (local_err) {
1401 error_propagate(errp, local_err);
1402 return;
1403 }
1404 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1405
1406 pcc->parent_realize(dev, &local_err);
1407 if (local_err) {
1408 error_propagate(errp, local_err);
1409 return;
1410 }
8b50ce85
CLG		 1411
1412 /* Processor Service Interface (PSI) Host Bridge */
1413 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1414 "bar", &error_fatal);
1415 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1416 &local_err);
1417 if (local_err) {
1418 error_propagate(errp, local_err);
1419 return;
1420 }
1421 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1422 &PNV_PSI(&chip10->psi)->xscom_regs);
2661f6ab
CLG		 1423
1424 /* LPC */
1425 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1426 &error_abort);
1427 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1428 &local_err);
1429 if (local_err) {
1430 error_propagate(errp, local_err);
1431 return;
1432 }
1433 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1434 &chip10->lpc.xscom_regs);
1435
1436 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1437 (uint64_t) PNV10_LPCM_BASE(chip));
2b548a42
CLG		 1438}
1439
70c059e9
GK		 1440static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1441{
1442 addr &= (PNV10_XSCOM_SIZE - 1);
1443 return addr >> 3;
1444}
1445
2b548a42
CLG		 1446static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1447{
1448 DeviceClass *dc = DEVICE_CLASS(klass);
1449 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1450
1451 k->chip_type = PNV_CHIP_POWER10;
1452 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1453 k->cores_mask = POWER10_CORE_MASK;
1454 k->core_pir = pnv_chip_core_pir_p10;
1455 k->intc_create = pnv_chip_power10_intc_create;
1456 k->intc_reset = pnv_chip_power10_intc_reset;
1457 k->intc_destroy = pnv_chip_power10_intc_destroy;
85913070 1458 k->intc_print_info = pnv_chip_power10_intc_print_info;
2b548a42
CLG		 1459 k->isa_create = pnv_chip_power10_isa_create;
1460 k->dt_populate = pnv_chip_power10_dt_populate;
1461 k->pic_print_info = pnv_chip_power10_pic_print_info;
c4b2c40c 1462 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
70c059e9 1463 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2b548a42
CLG		 1464 dc->desc = "PowerNV Chip POWER10";
1465
1466 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1467 &k->parent_realize);
1468}
1469
397a79e7
CLG		 1470static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1471{
1472 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1473 int cores_max;
1474
1475 /*
1476 * No custom mask for this chip, let's use the default one from *
1477 * the chip class
1478 */
1479 if (!chip->cores_mask) {
1480 chip->cores_mask = pcc->cores_mask;
1481 }
1482
1483 /* filter alien core ids ! some are reserved */
1484 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1485 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1486 chip->cores_mask);
1487 return;
1488 }
1489 chip->cores_mask &= pcc->cores_mask;
1490
1491 /* now that we have a sane layout, let check the number of cores */
27d9ffd4 1492 cores_max = ctpop64(chip->cores_mask);
397a79e7
CLG		 1493 if (chip->nr_cores > cores_max) {
1494 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1495 cores_max);
1496 return;
1497 }
1498}
1499
51c04728 1500static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
e997040e 1501{
fe6b6346 1502 MachineState *ms = MACHINE(qdev_get_machine());
397a79e7 1503 Error *error = NULL;
d2fd9612 1504 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
40abf43f 1505 const char *typename = pnv_chip_core_typename(chip);
d2fd9612
CLG		 1506 int i, core_hwid;
1507
1508 if (!object_class_by_name(typename)) {
1509 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1510 return;
1511 }
397a79e7 1512
d2fd9612 1513 /* Cores */
397a79e7
CLG		 1514 pnv_chip_core_sanitize(chip, &error);
1515 if (error) {
1516 error_propagate(errp, error);
1517 return;
1518 }
d2fd9612 1519
4fa28f23 1520 chip->cores = g_new0(PnvCore *, chip->nr_cores);
d2fd9612
CLG		 1521
1522 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1523 && (i < chip->nr_cores); core_hwid++) {
1524 char core_name[32];
4fa28f23 1525 PnvCore *pnv_core;
c035851a 1526 uint64_t xscom_core_base;
d2fd9612
CLG		 1527
1528 if (!(chip->cores_mask & (1ull << core_hwid))) {
1529 continue;
1530 }
1531
4fa28f23
GK		 1532 pnv_core = PNV_CORE(object_new(typename));
1533
d2fd9612 1534 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
4fa28f23
GK		 1535 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1536 &error_abort);
1537 chip->cores[i] = pnv_core;
fe6b6346 1538 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
d2fd9612
CLG		 1539 &error_fatal);
1540 object_property_set_int(OBJECT(pnv_core), core_hwid,
1541 CPU_CORE_PROP_CORE_ID, &error_fatal);
1542 object_property_set_int(OBJECT(pnv_core),
1543 pcc->core_pir(chip, core_hwid),
1544 "pir", &error_fatal);
158e17a6
GK		 1545 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1546 &error_abort);
d2fd9612
CLG		 1547 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1548 &error_fatal);
24ece072
CLG		 1549
1550 /* Each core has an XSCOM MMIO region */
c4b2c40c 1551 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
c035851a
CLG		 1552
1553 pnv_xscom_add_subregion(chip, xscom_core_base,
4fa28f23 1554 &pnv_core->xscom_regs);
d2fd9612
CLG		 1555 i++;
1556 }
51c04728
CLG		 1557}
1558
1559static void pnv_chip_realize(DeviceState *dev, Error **errp)
1560{
1561 PnvChip *chip = PNV_CHIP(dev);
1562 Error *error = NULL;
1563
51c04728
CLG		 1564 /* Cores */
1565 pnv_chip_core_realize(chip, &error);
1566 if (error) {
1567 error_propagate(errp, error);
1568 return;
1569 }
e997040e
CLG		 1570}
1571
1572static Property pnv_chip_properties[] = {
1573 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1574 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1575 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
397a79e7
CLG		 1576 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1577 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
e997040e
CLG		 1578 DEFINE_PROP_END_OF_LIST(),
1579};
1580
1581static void pnv_chip_class_init(ObjectClass *klass, void *data)
1582{
1583 DeviceClass *dc = DEVICE_CLASS(klass);
1584
9d169fb3 1585 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
e997040e
CLG		 1586 dc->realize = pnv_chip_realize;
1587 dc->props = pnv_chip_properties;
1588 dc->desc = "PowerNV Chip";
1589}
1590
119eaa9d
CLG		 1591PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1592{
1593 int i, j;
1594
1595 for (i = 0; i < chip->nr_cores; i++) {
1596 PnvCore *pc = chip->cores[i];
1597 CPUCore *cc = CPU_CORE(pc);
1598
1599 for (j = 0; j < cc->nr_threads; j++) {
1600 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1601 return pc->threads[j];
1602 }
1603 }
1604 }
1605 return NULL;
1606}
1607
54f59d78
CLG		 1608static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1609{
b168a138 1610 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1611 int i;
1612
1613 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1614 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1615
1616 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1617 return &chip8->psi.ics;
54f59d78
CLG		 1618 }
1619 }
1620 return NULL;
1621}
1622
1623static void pnv_ics_resend(XICSFabric *xi)
1624{
b168a138 1625 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1626 int i;
1627
1628 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1629 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1630 ics_resend(&chip8->psi.ics);
54f59d78
CLG		 1631 }
1632}
1633
36fc6f08
CLG		 1634static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1635{
1636 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1637
956b8f46 1638 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
36fc6f08
CLG		 1639}
1640
47fea43a
CLG		 1641static void pnv_pic_print_info(InterruptStatsProvider *obj,
1642 Monitor *mon)
1643{
b168a138 1644 PnvMachineState *pnv = PNV_MACHINE(obj);
54f59d78 1645 int i;
47fea43a
CLG		 1646 CPUState *cs;
1647
1648 CPU_FOREACH(cs) {
1649 PowerPCCPU *cpu = POWERPC_CPU(cs);
1650
85913070
GK		 1651 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1652 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1653 mon);
47fea43a 1654 }
54f59d78
CLG		 1655
1656 for (i = 0; i < pnv->num_chips; i++) {
d8e4aad5 1657 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
54f59d78 1658 }
47fea43a
CLG		 1659}
1660
c722579e
CLG		 1661static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1662 uint8_t nvt_blk, uint32_t nvt_idx,
1663 bool cam_ignore, uint8_t priority,
1664 uint32_t logic_serv,
1665 XiveTCTXMatch *match)
1666{
1667 PnvMachineState *pnv = PNV_MACHINE(xfb);
1668 int total_count = 0;
1669 int i;
1670
1671 for (i = 0; i < pnv->num_chips; i++) {
1672 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1673 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1674 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1675 int count;
1676
1677 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1678 priority, logic_serv, match);
1679
1680 if (count < 0) {
1681 return count;
1682 }
1683
1684 total_count += count;
1685 }
1686
1687 return total_count;
1688}
1689
5373c61d
CLG		 1690PnvChip *pnv_get_chip(uint32_t chip_id)
1691{
1692 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1693 int i;
1694
1695 for (i = 0; i < pnv->num_chips; i++) {
1696 PnvChip *chip = pnv->chips[i];
1697 if (chip->chip_id == chip_id) {
1698 return chip;
1699 }
1700 }
1701 return NULL;
1702}
1703
e997040e
CLG		 1704static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1705 void *opaque, Error **errp)
1706{
b168a138 1707 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
e997040e
CLG		 1708}
1709
1710static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1711 void *opaque, Error **errp)
1712{
b168a138 1713 PnvMachineState *pnv = PNV_MACHINE(obj);
e997040e
CLG		 1714 uint32_t num_chips;
1715 Error *local_err = NULL;
1716
1717 visit_type_uint32(v, name, &num_chips, &local_err);
1718 if (local_err) {
1719 error_propagate(errp, local_err);
1720 return;
1721 }
1722
1723 /*
1724 * TODO: should we decide on how many chips we can create based
1725 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1726 */
1727 if (!is_power_of_2(num_chips) || num_chips > 4) {
1728 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1729 return;
1730 }
1731
1732 pnv->num_chips = num_chips;
1733}
1734
77864267 1735static void pnv_machine_instance_init(Object *obj)
e997040e 1736{
b168a138 1737 PnvMachineState *pnv = PNV_MACHINE(obj);
e997040e
CLG		 1738 pnv->num_chips = 1;
1739}
1740
b168a138 1741static void pnv_machine_class_props_init(ObjectClass *oc)
e997040e 1742{
1e507bb0 1743 object_class_property_add(oc, "num-chips", "uint32",
e997040e
CLG		 1744 pnv_get_num_chips, pnv_set_num_chips,
1745 NULL, NULL, NULL);
1746 object_class_property_set_description(oc, "num-chips",
1747 "Specifies the number of processor chips",
1748 NULL);
9e933f4a
BH		 1749}
1750
f30c843c 1751static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
9e933f4a
BH		 1752{
1753 MachineClass *mc = MACHINE_CLASS(oc);
36fc6f08 1754 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
d76f2da7
GK		 1755 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1756 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
f30c843c
CLG		 1757
1758 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1759 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1760
1761 xic->icp_get = pnv_icp_get;
1762 xic->ics_get = pnv_ics_get;
1763 xic->ics_resend = pnv_ics_resend;
d76f2da7
GK		 1764
1765 pmc->compat = compat;
1766 pmc->compat_size = sizeof(compat);
f30c843c
CLG		 1767}
1768
1769static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1770{
1771 MachineClass *mc = MACHINE_CLASS(oc);
c722579e 1772 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
d76f2da7
GK		 1773 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1774 static const char compat[] = "qemu,powernv9\0ibm,powernv";
f30c843c
CLG		 1775
1776 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1777 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
c722579e 1778 xfc->match_nvt = pnv_match_nvt;
f30c843c
CLG		 1779
1780 mc->alias = "powernv";
d76f2da7
GK		 1781
1782 pmc->compat = compat;
1783 pmc->compat_size = sizeof(compat);
7a90c6a1 1784 pmc->dt_power_mgt = pnv_dt_power_mgt;
f30c843c
CLG		 1785}
1786
2b548a42
CLG		 1787static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1788{
1789 MachineClass *mc = MACHINE_CLASS(oc);
d76f2da7
GK		 1790 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1791 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2b548a42
CLG		 1792
1793 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1794 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
d76f2da7
GK		 1795
1796 pmc->compat = compat;
1797 pmc->compat_size = sizeof(compat);
7a90c6a1 1798 pmc->dt_power_mgt = pnv_dt_power_mgt;
2b548a42
CLG		 1799}
1800
f30c843c
CLG		 1801static void pnv_machine_class_init(ObjectClass *oc, void *data)
1802{
1803 MachineClass *mc = MACHINE_CLASS(oc);
47fea43a 1804 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
9e933f4a
BH		 1805
1806 mc->desc = "IBM PowerNV (Non-Virtualized)";
b168a138
CLG		 1807 mc->init = pnv_init;
1808 mc->reset = pnv_reset;
9e933f4a 1809 mc->max_cpus = MAX_CPUS;
59b7c1c2
B		 1810 /* Pnv provides a AHCI device for storage */
1811 mc->block_default_type = IF_IDE;
9e933f4a
BH		 1812 mc->no_parallel = 1;
1813 mc->default_boot_order = NULL;
f1d18b0a
JS		 1814 /*
1815 * RAM defaults to less than 2048 for 32-bit hosts, and large
1816 * enough to fit the maximum initrd size at it's load address
1817 */
1818 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
47fea43a 1819 ispc->print_info = pnv_pic_print_info;
e997040e 1820
b168a138 1821 pnv_machine_class_props_init(oc);
9e933f4a
BH		 1822}
1823
77864267
CLG		 1824#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1825 { \
1826 .name = type, \
1827 .class_init = class_initfn, \
1828 .parent = TYPE_PNV8_CHIP, \
1829 }
1830
1831#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1832 { \
1833 .name = type, \
1834 .class_init = class_initfn, \
1835 .parent = TYPE_PNV9_CHIP, \
beba5c0f
IM		 1836 }
1837
2b548a42
CLG		 1838#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1839 { \
1840 .name = type, \
1841 .class_init = class_initfn, \
1842 .parent = TYPE_PNV10_CHIP, \
1843 }
1844
beba5c0f 1845static const TypeInfo types[] = {
2b548a42
CLG		 1846 {
1847 .name = MACHINE_TYPE_NAME("powernv10"),
1848 .parent = TYPE_PNV_MACHINE,
1849 .class_init = pnv_machine_power10_class_init,
1850 },
1aba8716
CLG		 1851 {
1852 .name = MACHINE_TYPE_NAME("powernv9"),
1853 .parent = TYPE_PNV_MACHINE,
1854 .class_init = pnv_machine_power9_class_init,
c722579e
CLG		 1855 .interfaces = (InterfaceInfo[]) {
1856 { TYPE_XIVE_FABRIC },
1857 { },
1858 },
1aba8716
CLG		 1859 },
1860 {
1861 .name = MACHINE_TYPE_NAME("powernv8"),
1862 .parent = TYPE_PNV_MACHINE,
1863 .class_init = pnv_machine_power8_class_init,
1864 .interfaces = (InterfaceInfo[]) {
1865 { TYPE_XICS_FABRIC },
1866 { },
1867 },
1868 },
beba5c0f 1869 {
b168a138 1870 .name = TYPE_PNV_MACHINE,
beba5c0f 1871 .parent = TYPE_MACHINE,
f30c843c 1872 .abstract = true,
beba5c0f 1873 .instance_size = sizeof(PnvMachineState),
77864267 1874 .instance_init = pnv_machine_instance_init,
b168a138 1875 .class_init = pnv_machine_class_init,
d76f2da7 1876 .class_size = sizeof(PnvMachineClass),
beba5c0f 1877 .interfaces = (InterfaceInfo[]) {
beba5c0f
IM		 1878 { TYPE_INTERRUPT_STATS_PROVIDER },
1879 { },
1880 },
36fc6f08 1881 },
beba5c0f
IM		 1882 {
1883 .name = TYPE_PNV_CHIP,
1884 .parent = TYPE_SYS_BUS_DEVICE,
1885 .class_init = pnv_chip_class_init,
beba5c0f
IM		 1886 .instance_size = sizeof(PnvChip),
1887 .class_size = sizeof(PnvChipClass),
1888 .abstract = true,
1889 },
77864267 1890
2b548a42
CLG		 1891 /*
1892 * P10 chip and variants
1893 */
1894 {
1895 .name = TYPE_PNV10_CHIP,
1896 .parent = TYPE_PNV_CHIP,
1897 .instance_init = pnv_chip_power10_instance_init,
1898 .instance_size = sizeof(Pnv10Chip),
1899 },
1900 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
1901
77864267
CLG		 1902 /*
1903 * P9 chip and variants
1904 */
1905 {
1906 .name = TYPE_PNV9_CHIP,
1907 .parent = TYPE_PNV_CHIP,
1908 .instance_init = pnv_chip_power9_instance_init,
1909 .instance_size = sizeof(Pnv9Chip),
1910 },
1911 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1912
1913 /*
1914 * P8 chip and variants
1915 */
1916 {
1917 .name = TYPE_PNV8_CHIP,
1918 .parent = TYPE_PNV_CHIP,
1919 .instance_init = pnv_chip_power8_instance_init,
1920 .instance_size = sizeof(Pnv8Chip),
1921 },
1922 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1923 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1924 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1925 pnv_chip_power8nvl_class_init),
9e933f4a
BH		 1926};
1927
beba5c0f 1928DEFINE_TYPES(types)
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