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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV machine model | |
3 | * | |
4 | * Copyright (c) 2016, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
a8d25326 | 21 | #include "qemu-common.h" |
fc6b3cf9 | 22 | #include "qemu/units.h" |
9e933f4a BH |
23 | #include "qapi/error.h" |
24 | #include "sysemu/sysemu.h" | |
25 | #include "sysemu/numa.h" | |
71e8a915 | 26 | #include "sysemu/reset.h" |
54d31236 | 27 | #include "sysemu/runstate.h" |
d2528bdc | 28 | #include "sysemu/cpus.h" |
8d409261 | 29 | #include "sysemu/device_tree.h" |
fcf5ef2a | 30 | #include "target/ppc/cpu.h" |
9e933f4a BH |
31 | #include "qemu/log.h" |
32 | #include "hw/ppc/fdt.h" | |
33 | #include "hw/ppc/ppc.h" | |
34 | #include "hw/ppc/pnv.h" | |
d2fd9612 | 35 | #include "hw/ppc/pnv_core.h" |
9e933f4a BH |
36 | #include "hw/loader.h" |
37 | #include "exec/address-spaces.h" | |
e997040e | 38 | #include "qapi/visitor.h" |
47fea43a CLG |
39 | #include "monitor/monitor.h" |
40 | #include "hw/intc/intc.h" | |
aeaef83d | 41 | #include "hw/ipmi/ipmi.h" |
58969eee | 42 | #include "target/ppc/mmu-hash64.h" |
9e933f4a | 43 | |
36fc6f08 | 44 | #include "hw/ppc/xics.h" |
a27bd6c7 | 45 | #include "hw/qdev-properties.h" |
967b7523 CLG |
46 | #include "hw/ppc/pnv_xscom.h" |
47 | ||
3495b6b6 | 48 | #include "hw/isa/isa.h" |
12e9493d | 49 | #include "hw/boards.h" |
3495b6b6 CLG |
50 | #include "hw/char/serial.h" |
51 | #include "hw/timer/mc146818rtc.h" | |
52 | ||
9e933f4a BH |
53 | #include <libfdt.h> |
54 | ||
b268a616 | 55 | #define FDT_MAX_SIZE (1 * MiB) |
9e933f4a BH |
56 | |
57 | #define FW_FILE_NAME "skiboot.lid" | |
58 | #define FW_LOAD_ADDR 0x0 | |
b268a616 | 59 | #define FW_MAX_SIZE (4 * MiB) |
9e933f4a BH |
60 | |
61 | #define KERNEL_LOAD_ADDR 0x20000000 | |
b45b56ba | 62 | #define KERNEL_MAX_SIZE (256 * MiB) |
fef592f9 | 63 | #define INITRD_LOAD_ADDR 0x60000000 |
584ea7e7 | 64 | #define INITRD_MAX_SIZE (256 * MiB) |
9e933f4a | 65 | |
40abf43f IM |
66 | static const char *pnv_chip_core_typename(const PnvChip *o) |
67 | { | |
68 | const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); | |
69 | int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); | |
70 | char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); | |
71 | const char *core_type = object_class_get_name(object_class_by_name(s)); | |
72 | g_free(s); | |
73 | return core_type; | |
74 | } | |
75 | ||
9e933f4a BH |
76 | /* |
77 | * On Power Systems E880 (POWER8), the max cpus (threads) should be : | |
78 | * 4 * 4 sockets * 12 cores * 8 threads = 1536 | |
79 | * Let's make it 2^11 | |
80 | */ | |
81 | #define MAX_CPUS 2048 | |
82 | ||
83 | /* | |
84 | * Memory nodes are created by hostboot, one for each range of memory | |
85 | * that has a different "affinity". In practice, it means one range | |
86 | * per chip. | |
87 | */ | |
b168a138 | 88 | static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) |
9e933f4a BH |
89 | { |
90 | char *mem_name; | |
91 | uint64_t mem_reg_property[2]; | |
92 | int off; | |
93 | ||
94 | mem_reg_property[0] = cpu_to_be64(start); | |
95 | mem_reg_property[1] = cpu_to_be64(size); | |
96 | ||
97 | mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); | |
98 | off = fdt_add_subnode(fdt, 0, mem_name); | |
99 | g_free(mem_name); | |
100 | ||
101 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
102 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
103 | sizeof(mem_reg_property)))); | |
104 | _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); | |
105 | } | |
106 | ||
d2fd9612 CLG |
107 | static int get_cpus_node(void *fdt) |
108 | { | |
109 | int cpus_offset = fdt_path_offset(fdt, "/cpus"); | |
110 | ||
111 | if (cpus_offset < 0) { | |
a4f3885c | 112 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
d2fd9612 CLG |
113 | if (cpus_offset) { |
114 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
115 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
116 | } | |
117 | } | |
118 | _FDT(cpus_offset); | |
119 | return cpus_offset; | |
120 | } | |
121 | ||
122 | /* | |
123 | * The PowerNV cores (and threads) need to use real HW ids and not an | |
124 | * incremental index like it has been done on other platforms. This HW | |
125 | * id is stored in the CPU PIR, it is used to create cpu nodes in the | |
126 | * device tree, used in XSCOM to address cores and in interrupt | |
127 | * servers. | |
128 | */ | |
b168a138 | 129 | static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) |
d2fd9612 | 130 | { |
08304a86 DG |
131 | PowerPCCPU *cpu = pc->threads[0]; |
132 | CPUState *cs = CPU(cpu); | |
d2fd9612 | 133 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
8bd9530e | 134 | int smt_threads = CPU_CORE(pc)->nr_threads; |
d2fd9612 CLG |
135 | CPUPPCState *env = &cpu->env; |
136 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
137 | uint32_t servers_prop[smt_threads]; | |
138 | int i; | |
139 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
140 | 0xffffffff, 0xffffffff}; | |
141 | uint32_t tbfreq = PNV_TIMEBASE_FREQ; | |
142 | uint32_t cpufreq = 1000000000; | |
143 | uint32_t page_sizes_prop[64]; | |
144 | size_t page_sizes_prop_size; | |
145 | const uint8_t pa_features[] = { 24, 0, | |
146 | 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, | |
147 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
148 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
149 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
150 | int offset; | |
151 | char *nodename; | |
152 | int cpus_offset = get_cpus_node(fdt); | |
153 | ||
154 | nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); | |
155 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
156 | _FDT(offset); | |
157 | g_free(nodename); | |
158 | ||
159 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); | |
160 | ||
161 | _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); | |
162 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); | |
163 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
164 | ||
165 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
166 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
167 | env->dcache_line_size))); | |
168 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
169 | env->dcache_line_size))); | |
170 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
171 | env->icache_line_size))); | |
172 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
173 | env->icache_line_size))); | |
174 | ||
175 | if (pcc->l1_dcache_size) { | |
176 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
177 | pcc->l1_dcache_size))); | |
178 | } else { | |
3dc6f869 | 179 | warn_report("Unknown L1 dcache size for cpu"); |
d2fd9612 CLG |
180 | } |
181 | if (pcc->l1_icache_size) { | |
182 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
183 | pcc->l1_icache_size))); | |
184 | } else { | |
3dc6f869 | 185 | warn_report("Unknown L1 icache size for cpu"); |
d2fd9612 CLG |
186 | } |
187 | ||
188 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
189 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
67d7d66f | 190 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); |
d2fd9612 CLG |
191 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); |
192 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
193 | ||
194 | if (env->spr_cb[SPR_PURR].oea_read) { | |
195 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
196 | } | |
197 | ||
58969eee | 198 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
d2fd9612 CLG |
199 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", |
200 | segs, sizeof(segs)))); | |
201 | } | |
202 | ||
203 | /* Advertise VMX/VSX (vector extensions) if available | |
204 | * 0 / no property == no vector extensions | |
205 | * 1 == VMX / Altivec available | |
206 | * 2 == VSX available */ | |
207 | if (env->insns_flags & PPC_ALTIVEC) { | |
208 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
209 | ||
210 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
211 | } | |
212 | ||
213 | /* Advertise DFP (Decimal Floating Point) if available | |
214 | * 0 / no property == no DFP | |
215 | * 1 == DFP available */ | |
216 | if (env->insns_flags2 & PPC2_DFP) { | |
217 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
218 | } | |
219 | ||
644a2c99 DG |
220 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
221 | sizeof(page_sizes_prop)); | |
d2fd9612 CLG |
222 | if (page_sizes_prop_size) { |
223 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
224 | page_sizes_prop, page_sizes_prop_size))); | |
225 | } | |
226 | ||
227 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", | |
228 | pa_features, sizeof(pa_features)))); | |
229 | ||
d2fd9612 CLG |
230 | /* Build interrupt servers properties */ |
231 | for (i = 0; i < smt_threads; i++) { | |
232 | servers_prop[i] = cpu_to_be32(pc->pir + i); | |
233 | } | |
234 | _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
235 | servers_prop, sizeof(servers_prop)))); | |
236 | } | |
237 | ||
b168a138 CLG |
238 | static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, |
239 | uint32_t nr_threads) | |
bf5615e7 CLG |
240 | { |
241 | uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); | |
242 | char *name; | |
243 | const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; | |
244 | uint32_t irange[2], i, rsize; | |
245 | uint64_t *reg; | |
246 | int offset; | |
247 | ||
248 | irange[0] = cpu_to_be32(pir); | |
249 | irange[1] = cpu_to_be32(nr_threads); | |
250 | ||
251 | rsize = sizeof(uint64_t) * 2 * nr_threads; | |
252 | reg = g_malloc(rsize); | |
253 | for (i = 0; i < nr_threads; i++) { | |
254 | reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); | |
255 | reg[i * 2 + 1] = cpu_to_be64(0x1000); | |
256 | } | |
257 | ||
258 | name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); | |
259 | offset = fdt_add_subnode(fdt, 0, name); | |
260 | _FDT(offset); | |
261 | g_free(name); | |
262 | ||
263 | _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); | |
264 | _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); | |
265 | _FDT((fdt_setprop_string(fdt, offset, "device_type", | |
266 | "PowerPC-External-Interrupt-Presentation"))); | |
267 | _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); | |
268 | _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", | |
269 | irange, sizeof(irange)))); | |
270 | _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); | |
271 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); | |
272 | g_free(reg); | |
273 | } | |
274 | ||
eb859a27 | 275 | static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) |
e997040e | 276 | { |
40abf43f | 277 | const char *typename = pnv_chip_core_typename(chip); |
d2fd9612 CLG |
278 | size_t typesize = object_type_get_instance_size(typename); |
279 | int i; | |
280 | ||
b168a138 | 281 | pnv_dt_xscom(chip, fdt, 0); |
967b7523 | 282 | |
d2fd9612 CLG |
283 | for (i = 0; i < chip->nr_cores; i++) { |
284 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
285 | ||
b168a138 | 286 | pnv_dt_core(chip, pnv_core, fdt); |
bf5615e7 CLG |
287 | |
288 | /* Interrupt Control Presenters (ICP). One per core. */ | |
b168a138 | 289 | pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); |
d2fd9612 CLG |
290 | } |
291 | ||
e997040e | 292 | if (chip->ram_size) { |
b168a138 | 293 | pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); |
e997040e CLG |
294 | } |
295 | } | |
296 | ||
eb859a27 CLG |
297 | static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) |
298 | { | |
299 | const char *typename = pnv_chip_core_typename(chip); | |
300 | size_t typesize = object_type_get_instance_size(typename); | |
301 | int i; | |
302 | ||
303 | pnv_dt_xscom(chip, fdt, 0); | |
304 | ||
305 | for (i = 0; i < chip->nr_cores; i++) { | |
306 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
307 | ||
308 | pnv_dt_core(chip, pnv_core, fdt); | |
309 | } | |
310 | ||
311 | if (chip->ram_size) { | |
312 | pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); | |
313 | } | |
15376c66 CLG |
314 | |
315 | pnv_dt_lpc(chip, fdt, 0); | |
eb859a27 CLG |
316 | } |
317 | ||
b168a138 | 318 | static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) |
c5ffdcae CLG |
319 | { |
320 | uint32_t io_base = d->ioport_id; | |
321 | uint32_t io_regs[] = { | |
322 | cpu_to_be32(1), | |
323 | cpu_to_be32(io_base), | |
324 | cpu_to_be32(2) | |
325 | }; | |
326 | char *name; | |
327 | int node; | |
328 | ||
329 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
330 | node = fdt_add_subnode(fdt, lpc_off, name); | |
331 | _FDT(node); | |
332 | g_free(name); | |
333 | ||
334 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); | |
335 | _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); | |
336 | } | |
337 | ||
b168a138 | 338 | static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) |
cb228f5a CLG |
339 | { |
340 | const char compatible[] = "ns16550\0pnpPNP,501"; | |
341 | uint32_t io_base = d->ioport_id; | |
342 | uint32_t io_regs[] = { | |
343 | cpu_to_be32(1), | |
344 | cpu_to_be32(io_base), | |
345 | cpu_to_be32(8) | |
346 | }; | |
347 | char *name; | |
348 | int node; | |
349 | ||
350 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
351 | node = fdt_add_subnode(fdt, lpc_off, name); | |
352 | _FDT(node); | |
353 | g_free(name); | |
354 | ||
355 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); | |
356 | _FDT((fdt_setprop(fdt, node, "compatible", compatible, | |
357 | sizeof(compatible)))); | |
358 | ||
359 | _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); | |
360 | _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); | |
361 | _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); | |
362 | _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", | |
363 | fdt_get_phandle(fdt, lpc_off)))); | |
364 | ||
365 | /* This is needed by Linux */ | |
366 | _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); | |
367 | } | |
368 | ||
b168a138 | 369 | static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) |
04f6c8b2 CLG |
370 | { |
371 | const char compatible[] = "bt\0ipmi-bt"; | |
372 | uint32_t io_base; | |
373 | uint32_t io_regs[] = { | |
374 | cpu_to_be32(1), | |
375 | 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ | |
376 | cpu_to_be32(3) | |
377 | }; | |
378 | uint32_t irq; | |
379 | char *name; | |
380 | int node; | |
381 | ||
382 | io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); | |
383 | io_regs[1] = cpu_to_be32(io_base); | |
384 | ||
385 | irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); | |
386 | ||
387 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
388 | node = fdt_add_subnode(fdt, lpc_off, name); | |
389 | _FDT(node); | |
390 | g_free(name); | |
391 | ||
7032d92a CLG |
392 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); |
393 | _FDT((fdt_setprop(fdt, node, "compatible", compatible, | |
394 | sizeof(compatible)))); | |
04f6c8b2 CLG |
395 | |
396 | /* Mark it as reserved to avoid Linux trying to claim it */ | |
397 | _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); | |
398 | _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); | |
399 | _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", | |
400 | fdt_get_phandle(fdt, lpc_off)))); | |
401 | } | |
402 | ||
e7a3fee3 CLG |
403 | typedef struct ForeachPopulateArgs { |
404 | void *fdt; | |
405 | int offset; | |
406 | } ForeachPopulateArgs; | |
407 | ||
b168a138 | 408 | static int pnv_dt_isa_device(DeviceState *dev, void *opaque) |
e7a3fee3 | 409 | { |
c5ffdcae CLG |
410 | ForeachPopulateArgs *args = opaque; |
411 | ISADevice *d = ISA_DEVICE(dev); | |
412 | ||
413 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { | |
b168a138 | 414 | pnv_dt_rtc(d, args->fdt, args->offset); |
cb228f5a | 415 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { |
b168a138 | 416 | pnv_dt_serial(d, args->fdt, args->offset); |
04f6c8b2 | 417 | } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { |
b168a138 | 418 | pnv_dt_ipmi_bt(d, args->fdt, args->offset); |
c5ffdcae CLG |
419 | } else { |
420 | error_report("unknown isa device %s@i%x", qdev_fw_name(dev), | |
421 | d->ioport_id); | |
422 | } | |
423 | ||
e7a3fee3 CLG |
424 | return 0; |
425 | } | |
426 | ||
bb7ab95c CLG |
427 | /* The default LPC bus of a multichip system is on chip 0. It's |
428 | * recognized by the firmware (skiboot) using a "primary" property. | |
429 | */ | |
430 | static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) | |
431 | { | |
64d011d5 | 432 | int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); |
e7a3fee3 CLG |
433 | ForeachPopulateArgs args = { |
434 | .fdt = fdt, | |
bb7ab95c | 435 | .offset = isa_offset, |
e7a3fee3 | 436 | }; |
f47a08d1 | 437 | uint32_t phandle; |
e7a3fee3 | 438 | |
bb7ab95c CLG |
439 | _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); |
440 | ||
f47a08d1 CLG |
441 | phandle = qemu_fdt_alloc_phandle(fdt); |
442 | assert(phandle > 0); | |
443 | _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); | |
444 | ||
e7a3fee3 CLG |
445 | /* ISA devices are not necessarily parented to the ISA bus so we |
446 | * can not use object_child_foreach() */ | |
bb7ab95c CLG |
447 | qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, |
448 | &args); | |
e7a3fee3 CLG |
449 | } |
450 | ||
e5694793 CLG |
451 | static void pnv_dt_power_mgt(void *fdt) |
452 | { | |
453 | int off; | |
454 | ||
455 | off = fdt_add_subnode(fdt, 0, "ibm,opal"); | |
456 | off = fdt_add_subnode(fdt, off, "power-mgt"); | |
457 | ||
458 | _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); | |
459 | } | |
460 | ||
b168a138 | 461 | static void *pnv_dt_create(MachineState *machine) |
9e933f4a | 462 | { |
83b90bf0 CLG |
463 | const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; |
464 | const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; | |
b168a138 | 465 | PnvMachineState *pnv = PNV_MACHINE(machine); |
9e933f4a BH |
466 | void *fdt; |
467 | char *buf; | |
468 | int off; | |
e997040e | 469 | int i; |
9e933f4a BH |
470 | |
471 | fdt = g_malloc0(FDT_MAX_SIZE); | |
472 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
473 | ||
474 | /* Root node */ | |
475 | _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); | |
476 | _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); | |
477 | _FDT((fdt_setprop_string(fdt, 0, "model", | |
478 | "IBM PowerNV (emulated by qemu)"))); | |
83b90bf0 CLG |
479 | if (pnv_is_power9(pnv)) { |
480 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, | |
481 | sizeof(plat_compat9)))); | |
482 | } else { | |
483 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, | |
484 | sizeof(plat_compat8)))); | |
485 | } | |
486 | ||
9e933f4a BH |
487 | |
488 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
489 | _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); | |
490 | if (qemu_uuid_set) { | |
491 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
492 | } | |
493 | g_free(buf); | |
494 | ||
495 | off = fdt_add_subnode(fdt, 0, "chosen"); | |
496 | if (machine->kernel_cmdline) { | |
497 | _FDT((fdt_setprop_string(fdt, off, "bootargs", | |
498 | machine->kernel_cmdline))); | |
499 | } | |
500 | ||
501 | if (pnv->initrd_size) { | |
502 | uint32_t start_prop = cpu_to_be32(pnv->initrd_base); | |
503 | uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); | |
504 | ||
505 | _FDT((fdt_setprop(fdt, off, "linux,initrd-start", | |
506 | &start_prop, sizeof(start_prop)))); | |
507 | _FDT((fdt_setprop(fdt, off, "linux,initrd-end", | |
508 | &end_prop, sizeof(end_prop)))); | |
509 | } | |
510 | ||
e997040e CLG |
511 | /* Populate device tree for each chip */ |
512 | for (i = 0; i < pnv->num_chips; i++) { | |
eb859a27 | 513 | PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); |
e997040e | 514 | } |
e7a3fee3 CLG |
515 | |
516 | /* Populate ISA devices on chip 0 */ | |
bb7ab95c | 517 | pnv_dt_isa(pnv, fdt); |
aeaef83d CLG |
518 | |
519 | if (pnv->bmc) { | |
b168a138 | 520 | pnv_dt_bmc_sensors(pnv->bmc, fdt); |
aeaef83d CLG |
521 | } |
522 | ||
e5694793 CLG |
523 | /* Create an extra node for power management on Power9 */ |
524 | if (pnv_is_power9(pnv)) { | |
525 | pnv_dt_power_mgt(fdt); | |
526 | } | |
527 | ||
9e933f4a BH |
528 | return fdt; |
529 | } | |
530 | ||
bce0b691 CLG |
531 | static void pnv_powerdown_notify(Notifier *n, void *opaque) |
532 | { | |
b168a138 | 533 | PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); |
bce0b691 CLG |
534 | |
535 | if (pnv->bmc) { | |
536 | pnv_bmc_powerdown(pnv->bmc); | |
537 | } | |
538 | } | |
539 | ||
a0628599 | 540 | static void pnv_reset(MachineState *machine) |
9e933f4a | 541 | { |
b168a138 | 542 | PnvMachineState *pnv = PNV_MACHINE(machine); |
9e933f4a | 543 | void *fdt; |
aeaef83d | 544 | Object *obj; |
9e933f4a BH |
545 | |
546 | qemu_devices_reset(); | |
547 | ||
aeaef83d CLG |
548 | /* OpenPOWER systems have a BMC, which can be defined on the |
549 | * command line with: | |
550 | * | |
551 | * -device ipmi-bmc-sim,id=bmc0 | |
552 | * | |
553 | * This is the internal simulator but it could also be an external | |
554 | * BMC. | |
555 | */ | |
a1a636b8 | 556 | obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); |
aeaef83d CLG |
557 | if (obj) { |
558 | pnv->bmc = IPMI_BMC(obj); | |
559 | } | |
560 | ||
b168a138 | 561 | fdt = pnv_dt_create(machine); |
9e933f4a BH |
562 | |
563 | /* Pack resulting tree */ | |
564 | _FDT((fdt_pack(fdt))); | |
565 | ||
8d409261 | 566 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); |
9e933f4a BH |
567 | cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); |
568 | } | |
569 | ||
04026890 | 570 | static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) |
3495b6b6 | 571 | { |
77864267 CLG |
572 | Pnv8Chip *chip8 = PNV8_CHIP(chip); |
573 | return pnv_lpc_isa_create(&chip8->lpc, true, errp); | |
04026890 | 574 | } |
3495b6b6 | 575 | |
04026890 CLG |
576 | static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) |
577 | { | |
77864267 CLG |
578 | Pnv8Chip *chip8 = PNV8_CHIP(chip); |
579 | return pnv_lpc_isa_create(&chip8->lpc, false, errp); | |
04026890 | 580 | } |
3495b6b6 | 581 | |
04026890 CLG |
582 | static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) |
583 | { | |
15376c66 CLG |
584 | Pnv9Chip *chip9 = PNV9_CHIP(chip); |
585 | return pnv_lpc_isa_create(&chip9->lpc, false, errp); | |
04026890 | 586 | } |
3495b6b6 | 587 | |
04026890 CLG |
588 | static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) |
589 | { | |
590 | return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); | |
3495b6b6 CLG |
591 | } |
592 | ||
d8e4aad5 CLG |
593 | static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) |
594 | { | |
595 | Pnv8Chip *chip8 = PNV8_CHIP(chip); | |
596 | ||
597 | ics_pic_print_info(&chip8->psi.ics, mon); | |
598 | } | |
599 | ||
600 | static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) | |
601 | { | |
602 | Pnv9Chip *chip9 = PNV9_CHIP(chip); | |
603 | ||
604 | pnv_xive_pic_print_info(&chip9->xive, mon); | |
c38536bc | 605 | pnv_psi_pic_print_info(&chip9->psi, mon); |
d8e4aad5 CLG |
606 | } |
607 | ||
f30c843c CLG |
608 | static bool pnv_match_cpu(const char *default_type, const char *cpu_type) |
609 | { | |
610 | PowerPCCPUClass *ppc_default = | |
611 | POWERPC_CPU_CLASS(object_class_by_name(default_type)); | |
612 | PowerPCCPUClass *ppc = | |
613 | POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); | |
614 | ||
615 | return ppc_default->pvr_match(ppc_default, ppc->pvr); | |
616 | } | |
617 | ||
b168a138 | 618 | static void pnv_init(MachineState *machine) |
9e933f4a | 619 | { |
b168a138 | 620 | PnvMachineState *pnv = PNV_MACHINE(machine); |
f30c843c | 621 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
9e933f4a BH |
622 | MemoryRegion *ram; |
623 | char *fw_filename; | |
624 | long fw_size; | |
e997040e CLG |
625 | int i; |
626 | char *chip_typename; | |
9e933f4a BH |
627 | |
628 | /* allocate RAM */ | |
d23b6caa | 629 | if (machine->ram_size < (1 * GiB)) { |
3dc6f869 | 630 | warn_report("skiboot may not work with < 1GB of RAM"); |
9e933f4a BH |
631 | } |
632 | ||
633 | ram = g_new(MemoryRegion, 1); | |
b168a138 | 634 | memory_region_allocate_system_memory(ram, NULL, "pnv.ram", |
9e933f4a BH |
635 | machine->ram_size); |
636 | memory_region_add_subregion(get_system_memory(), 0, ram); | |
637 | ||
638 | /* load skiboot firmware */ | |
639 | if (bios_name == NULL) { | |
640 | bios_name = FW_FILE_NAME; | |
641 | } | |
642 | ||
643 | fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
15fcedb2 CLG |
644 | if (!fw_filename) { |
645 | error_report("Could not find OPAL firmware '%s'", bios_name); | |
646 | exit(1); | |
647 | } | |
9e933f4a BH |
648 | |
649 | fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); | |
650 | if (fw_size < 0) { | |
15fcedb2 | 651 | error_report("Could not load OPAL firmware '%s'", fw_filename); |
9e933f4a BH |
652 | exit(1); |
653 | } | |
654 | g_free(fw_filename); | |
655 | ||
656 | /* load kernel */ | |
657 | if (machine->kernel_filename) { | |
658 | long kernel_size; | |
659 | ||
660 | kernel_size = load_image_targphys(machine->kernel_filename, | |
b45b56ba | 661 | KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); |
9e933f4a | 662 | if (kernel_size < 0) { |
802fc7ab | 663 | error_report("Could not load kernel '%s'", |
7c6e8797 | 664 | machine->kernel_filename); |
9e933f4a BH |
665 | exit(1); |
666 | } | |
667 | } | |
668 | ||
669 | /* load initrd */ | |
670 | if (machine->initrd_filename) { | |
671 | pnv->initrd_base = INITRD_LOAD_ADDR; | |
672 | pnv->initrd_size = load_image_targphys(machine->initrd_filename, | |
584ea7e7 | 673 | pnv->initrd_base, INITRD_MAX_SIZE); |
9e933f4a | 674 | if (pnv->initrd_size < 0) { |
802fc7ab | 675 | error_report("Could not load initial ram disk '%s'", |
9e933f4a BH |
676 | machine->initrd_filename); |
677 | exit(1); | |
678 | } | |
679 | } | |
e997040e | 680 | |
f30c843c CLG |
681 | /* |
682 | * Check compatibility of the specified CPU with the machine | |
683 | * default. | |
684 | */ | |
685 | if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { | |
686 | error_report("invalid CPU model '%s' for %s machine", | |
687 | machine->cpu_type, mc->name); | |
688 | exit(1); | |
689 | } | |
690 | ||
e997040e | 691 | /* Create the processor chips */ |
4a12c699 | 692 | i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); |
7fd544d8 | 693 | chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), |
4a12c699 | 694 | i, machine->cpu_type); |
e997040e | 695 | if (!object_class_by_name(chip_typename)) { |
f30c843c CLG |
696 | error_report("invalid chip model '%.*s' for %s machine", |
697 | i, machine->cpu_type, mc->name); | |
e997040e CLG |
698 | exit(1); |
699 | } | |
700 | ||
701 | pnv->chips = g_new0(PnvChip *, pnv->num_chips); | |
702 | for (i = 0; i < pnv->num_chips; i++) { | |
703 | char chip_name[32]; | |
704 | Object *chip = object_new(chip_typename); | |
705 | ||
706 | pnv->chips[i] = PNV_CHIP(chip); | |
707 | ||
708 | /* TODO: put all the memory in one node on chip 0 until we find a | |
709 | * way to specify different ranges for each chip | |
710 | */ | |
711 | if (i == 0) { | |
712 | object_property_set_int(chip, machine->ram_size, "ram-size", | |
713 | &error_fatal); | |
714 | } | |
715 | ||
716 | snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); | |
717 | object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); | |
718 | object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", | |
719 | &error_fatal); | |
fe6b6346 LX |
720 | object_property_set_int(chip, machine->smp.cores, |
721 | "nr-cores", &error_fatal); | |
e997040e CLG |
722 | object_property_set_bool(chip, true, "realized", &error_fatal); |
723 | } | |
724 | g_free(chip_typename); | |
3495b6b6 CLG |
725 | |
726 | /* Instantiate ISA bus on chip 0 */ | |
04026890 | 727 | pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); |
3495b6b6 CLG |
728 | |
729 | /* Create serial port */ | |
def337ff | 730 | serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
3495b6b6 CLG |
731 | |
732 | /* Create an RTC ISA device too */ | |
6c646a11 | 733 | mc146818_rtc_init(pnv->isa_bus, 2000, NULL); |
bce0b691 CLG |
734 | |
735 | /* OpenPOWER systems use a IPMI SEL Event message to notify the | |
736 | * host to powerdown */ | |
737 | pnv->powerdown_notifier.notify = pnv_powerdown_notify; | |
738 | qemu_register_powerdown_notifier(&pnv->powerdown_notifier); | |
e997040e CLG |
739 | } |
740 | ||
631adaff CLG |
741 | /* |
742 | * 0:21 Reserved - Read as zeros | |
743 | * 22:24 Chip ID | |
744 | * 25:28 Core number | |
745 | * 29:31 Thread ID | |
746 | */ | |
747 | static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) | |
748 | { | |
749 | return (chip->chip_id << 7) | (core_id << 3); | |
750 | } | |
751 | ||
8fa1f4ef CLG |
752 | static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, |
753 | Error **errp) | |
d35aefa9 | 754 | { |
8fa1f4ef CLG |
755 | Error *local_err = NULL; |
756 | Object *obj; | |
8907fc25 | 757 | PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); |
8fa1f4ef CLG |
758 | |
759 | obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), | |
760 | &local_err); | |
761 | if (local_err) { | |
762 | error_propagate(errp, local_err); | |
763 | return; | |
764 | } | |
765 | ||
956b8f46 | 766 | pnv_cpu->intc = obj; |
d35aefa9 CLG |
767 | } |
768 | ||
631adaff CLG |
769 | /* |
770 | * 0:48 Reserved - Read as zeroes | |
771 | * 49:52 Node ID | |
772 | * 53:55 Chip ID | |
773 | * 56 Reserved - Read as zero | |
774 | * 57:61 Core number | |
775 | * 62:63 Thread ID | |
776 | * | |
777 | * We only care about the lower bits. uint32_t is fine for the moment. | |
778 | */ | |
779 | static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) | |
780 | { | |
781 | return (chip->chip_id << 8) | (core_id << 2); | |
782 | } | |
783 | ||
8fa1f4ef CLG |
784 | static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, |
785 | Error **errp) | |
d35aefa9 | 786 | { |
2dfa91a2 CLG |
787 | Pnv9Chip *chip9 = PNV9_CHIP(chip); |
788 | Error *local_err = NULL; | |
789 | Object *obj; | |
790 | PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); | |
791 | ||
792 | /* | |
793 | * The core creates its interrupt presenter but the XIVE interrupt | |
794 | * controller object is initialized afterwards. Hopefully, it's | |
795 | * only used at runtime. | |
796 | */ | |
26aa5b1e | 797 | obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); |
2dfa91a2 CLG |
798 | if (local_err) { |
799 | error_propagate(errp, local_err); | |
800 | return; | |
801 | } | |
802 | ||
803 | pnv_cpu->intc = obj; | |
d35aefa9 CLG |
804 | } |
805 | ||
397a79e7 CLG |
806 | /* Allowed core identifiers on a POWER8 Processor Chip : |
807 | * | |
808 | * <EX0 reserved> | |
809 | * EX1 - Venice only | |
810 | * EX2 - Venice only | |
811 | * EX3 - Venice only | |
812 | * EX4 | |
813 | * EX5 | |
814 | * EX6 | |
815 | * <EX7,8 reserved> <reserved> | |
816 | * EX9 - Venice only | |
817 | * EX10 - Venice only | |
818 | * EX11 - Venice only | |
819 | * EX12 | |
820 | * EX13 | |
821 | * EX14 | |
822 | * <EX15 reserved> | |
823 | */ | |
824 | #define POWER8E_CORE_MASK (0x7070ull) | |
825 | #define POWER8_CORE_MASK (0x7e7eull) | |
826 | ||
827 | /* | |
09279d7e | 828 | * POWER9 has 24 cores, ids starting at 0x0 |
397a79e7 | 829 | */ |
09279d7e | 830 | #define POWER9_CORE_MASK (0xffffffffffffffull) |
397a79e7 | 831 | |
77864267 CLG |
832 | static void pnv_chip_power8_instance_init(Object *obj) |
833 | { | |
834 | Pnv8Chip *chip8 = PNV8_CHIP(obj); | |
835 | ||
f6d4dca8 | 836 | object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), |
ae856055 | 837 | TYPE_PNV8_PSI, &error_abort, NULL); |
77864267 CLG |
838 | object_property_add_const_link(OBJECT(&chip8->psi), "xics", |
839 | OBJECT(qdev_get_machine()), &error_abort); | |
840 | ||
f6d4dca8 | 841 | object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), |
82514be2 | 842 | TYPE_PNV8_LPC, &error_abort, NULL); |
77864267 CLG |
843 | object_property_add_const_link(OBJECT(&chip8->lpc), "psi", |
844 | OBJECT(&chip8->psi), &error_abort); | |
845 | ||
f6d4dca8 | 846 | object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), |
3233838c | 847 | TYPE_PNV8_OCC, &error_abort, NULL); |
77864267 CLG |
848 | object_property_add_const_link(OBJECT(&chip8->occ), "psi", |
849 | OBJECT(&chip8->psi), &error_abort); | |
850 | } | |
851 | ||
852 | static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) | |
853 | { | |
854 | PnvChip *chip = PNV_CHIP(chip8); | |
855 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
856 | const char *typename = pnv_chip_core_typename(chip); | |
857 | size_t typesize = object_type_get_instance_size(typename); | |
858 | int i, j; | |
859 | char *name; | |
860 | XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); | |
861 | ||
862 | name = g_strdup_printf("icp-%x", chip->chip_id); | |
863 | memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); | |
864 | sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); | |
865 | g_free(name); | |
866 | ||
867 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); | |
868 | ||
869 | /* Map the ICP registers for each thread */ | |
870 | for (i = 0; i < chip->nr_cores; i++) { | |
871 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
872 | int core_hwid = CPU_CORE(pnv_core)->core_id; | |
873 | ||
874 | for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { | |
875 | uint32_t pir = pcc->core_pir(chip, core_hwid) + j; | |
876 | PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); | |
877 | ||
878 | memory_region_add_subregion(&chip8->icp_mmio, pir << 12, | |
879 | &icp->mmio); | |
880 | } | |
881 | } | |
882 | } | |
883 | ||
884 | static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) | |
885 | { | |
886 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); | |
887 | PnvChip *chip = PNV_CHIP(dev); | |
888 | Pnv8Chip *chip8 = PNV8_CHIP(dev); | |
ae856055 | 889 | Pnv8Psi *psi8 = &chip8->psi; |
77864267 CLG |
890 | Error *local_err = NULL; |
891 | ||
709044fd CLG |
892 | /* XSCOM bridge is first */ |
893 | pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); | |
894 | if (local_err) { | |
895 | error_propagate(errp, local_err); | |
896 | return; | |
897 | } | |
898 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); | |
899 | ||
77864267 CLG |
900 | pcc->parent_realize(dev, &local_err); |
901 | if (local_err) { | |
902 | error_propagate(errp, local_err); | |
903 | return; | |
904 | } | |
905 | ||
906 | /* Processor Service Interface (PSI) Host Bridge */ | |
907 | object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), | |
908 | "bar", &error_fatal); | |
909 | object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); | |
910 | if (local_err) { | |
911 | error_propagate(errp, local_err); | |
912 | return; | |
913 | } | |
ae856055 CLG |
914 | pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, |
915 | &PNV_PSI(psi8)->xscom_regs); | |
77864267 CLG |
916 | |
917 | /* Create LPC controller */ | |
918 | object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", | |
919 | &error_fatal); | |
920 | pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); | |
921 | ||
64d011d5 CLG |
922 | chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", |
923 | (uint64_t) PNV_XSCOM_BASE(chip), | |
924 | PNV_XSCOM_LPC_BASE); | |
925 | ||
77864267 CLG |
926 | /* Interrupt Management Area. This is the memory region holding |
927 | * all the Interrupt Control Presenter (ICP) registers */ | |
928 | pnv_chip_icp_realize(chip8, &local_err); | |
929 | if (local_err) { | |
930 | error_propagate(errp, local_err); | |
931 | return; | |
932 | } | |
933 | ||
934 | /* Create the simplified OCC model */ | |
935 | object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); | |
936 | if (local_err) { | |
937 | error_propagate(errp, local_err); | |
938 | return; | |
939 | } | |
940 | pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); | |
941 | } | |
942 | ||
e997040e CLG |
943 | static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) |
944 | { | |
945 | DeviceClass *dc = DEVICE_CLASS(klass); | |
946 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
947 | ||
e997040e CLG |
948 | k->chip_type = PNV_CHIP_POWER8E; |
949 | k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ | |
397a79e7 | 950 | k->cores_mask = POWER8E_CORE_MASK; |
631adaff | 951 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 952 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 953 | k->isa_create = pnv_chip_power8_isa_create; |
eb859a27 | 954 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 955 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
e997040e | 956 | dc->desc = "PowerNV Chip POWER8E"; |
77864267 CLG |
957 | |
958 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
959 | &k->parent_realize); | |
e997040e CLG |
960 | } |
961 | ||
e997040e CLG |
962 | static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) |
963 | { | |
964 | DeviceClass *dc = DEVICE_CLASS(klass); | |
965 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
966 | ||
e997040e CLG |
967 | k->chip_type = PNV_CHIP_POWER8; |
968 | k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ | |
397a79e7 | 969 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 970 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 971 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 972 | k->isa_create = pnv_chip_power8_isa_create; |
eb859a27 | 973 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 974 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
e997040e | 975 | dc->desc = "PowerNV Chip POWER8"; |
77864267 CLG |
976 | |
977 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
978 | &k->parent_realize); | |
e997040e CLG |
979 | } |
980 | ||
e997040e CLG |
981 | static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) |
982 | { | |
983 | DeviceClass *dc = DEVICE_CLASS(klass); | |
984 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
985 | ||
e997040e CLG |
986 | k->chip_type = PNV_CHIP_POWER8NVL; |
987 | k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ | |
397a79e7 | 988 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 989 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 990 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 991 | k->isa_create = pnv_chip_power8nvl_isa_create; |
eb859a27 | 992 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 993 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
e997040e | 994 | dc->desc = "PowerNV Chip POWER8NVL"; |
77864267 CLG |
995 | |
996 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
997 | &k->parent_realize); | |
998 | } | |
999 | ||
1000 | static void pnv_chip_power9_instance_init(Object *obj) | |
1001 | { | |
2dfa91a2 CLG |
1002 | Pnv9Chip *chip9 = PNV9_CHIP(obj); |
1003 | ||
1004 | object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), | |
1005 | TYPE_PNV_XIVE, &error_abort, NULL); | |
1006 | object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, | |
1007 | &error_abort); | |
c38536bc CLG |
1008 | |
1009 | object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), | |
1010 | TYPE_PNV9_PSI, &error_abort, NULL); | |
1011 | object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, | |
1012 | &error_abort); | |
15376c66 CLG |
1013 | |
1014 | object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), | |
1015 | TYPE_PNV9_LPC, &error_abort, NULL); | |
1016 | object_property_add_const_link(OBJECT(&chip9->lpc), "psi", | |
1017 | OBJECT(&chip9->psi), &error_abort); | |
6598a70d CLG |
1018 | |
1019 | object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), | |
1020 | TYPE_PNV9_OCC, &error_abort, NULL); | |
1021 | object_property_add_const_link(OBJECT(&chip9->occ), "psi", | |
1022 | OBJECT(&chip9->psi), &error_abort); | |
77864267 CLG |
1023 | } |
1024 | ||
5dad902c CLG |
1025 | static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) |
1026 | { | |
1027 | PnvChip *chip = PNV_CHIP(chip9); | |
1028 | const char *typename = pnv_chip_core_typename(chip); | |
1029 | size_t typesize = object_type_get_instance_size(typename); | |
1030 | int i; | |
1031 | ||
1032 | chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); | |
1033 | chip9->quads = g_new0(PnvQuad, chip9->nr_quads); | |
1034 | ||
1035 | for (i = 0; i < chip9->nr_quads; i++) { | |
1036 | char eq_name[32]; | |
1037 | PnvQuad *eq = &chip9->quads[i]; | |
1038 | PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); | |
1039 | int core_id = CPU_CORE(pnv_core)->core_id; | |
1040 | ||
5dad902c | 1041 | snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); |
bc4c406c PMD |
1042 | object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), |
1043 | TYPE_PNV_QUAD, &error_fatal, NULL); | |
5dad902c | 1044 | |
5dad902c CLG |
1045 | object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); |
1046 | object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); | |
5dad902c CLG |
1047 | |
1048 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), | |
1049 | &eq->xscom_regs); | |
1050 | } | |
1051 | } | |
1052 | ||
77864267 CLG |
1053 | static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) |
1054 | { | |
1055 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); | |
2dfa91a2 CLG |
1056 | Pnv9Chip *chip9 = PNV9_CHIP(dev); |
1057 | PnvChip *chip = PNV_CHIP(dev); | |
c38536bc | 1058 | Pnv9Psi *psi9 = &chip9->psi; |
77864267 CLG |
1059 | Error *local_err = NULL; |
1060 | ||
709044fd CLG |
1061 | /* XSCOM bridge is first */ |
1062 | pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); | |
1063 | if (local_err) { | |
1064 | error_propagate(errp, local_err); | |
1065 | return; | |
1066 | } | |
1067 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); | |
1068 | ||
77864267 CLG |
1069 | pcc->parent_realize(dev, &local_err); |
1070 | if (local_err) { | |
1071 | error_propagate(errp, local_err); | |
1072 | return; | |
1073 | } | |
2dfa91a2 | 1074 | |
5dad902c CLG |
1075 | pnv_chip_quad_realize(chip9, &local_err); |
1076 | if (local_err) { | |
1077 | error_propagate(errp, local_err); | |
1078 | return; | |
1079 | } | |
1080 | ||
2dfa91a2 CLG |
1081 | /* XIVE interrupt controller (POWER9) */ |
1082 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), | |
1083 | "ic-bar", &error_fatal); | |
1084 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), | |
1085 | "vc-bar", &error_fatal); | |
1086 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), | |
1087 | "pc-bar", &error_fatal); | |
1088 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), | |
1089 | "tm-bar", &error_fatal); | |
1090 | object_property_set_bool(OBJECT(&chip9->xive), true, "realized", | |
1091 | &local_err); | |
1092 | if (local_err) { | |
1093 | error_propagate(errp, local_err); | |
1094 | return; | |
1095 | } | |
1096 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, | |
1097 | &chip9->xive.xscom_regs); | |
c38536bc CLG |
1098 | |
1099 | /* Processor Service Interface (PSI) Host Bridge */ | |
1100 | object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), | |
1101 | "bar", &error_fatal); | |
1102 | object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); | |
1103 | if (local_err) { | |
1104 | error_propagate(errp, local_err); | |
1105 | return; | |
1106 | } | |
1107 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, | |
1108 | &PNV_PSI(psi9)->xscom_regs); | |
15376c66 CLG |
1109 | |
1110 | /* LPC */ | |
1111 | object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); | |
1112 | if (local_err) { | |
1113 | error_propagate(errp, local_err); | |
1114 | return; | |
1115 | } | |
1116 | memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), | |
1117 | &chip9->lpc.xscom_regs); | |
1118 | ||
1119 | chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", | |
1120 | (uint64_t) PNV9_LPCM_BASE(chip)); | |
6598a70d CLG |
1121 | |
1122 | /* Create the simplified OCC model */ | |
1123 | object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); | |
1124 | if (local_err) { | |
1125 | error_propagate(errp, local_err); | |
1126 | return; | |
1127 | } | |
1128 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); | |
e997040e CLG |
1129 | } |
1130 | ||
e997040e CLG |
1131 | static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) |
1132 | { | |
1133 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1134 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
1135 | ||
e997040e | 1136 | k->chip_type = PNV_CHIP_POWER9; |
83028a2b | 1137 | k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ |
397a79e7 | 1138 | k->cores_mask = POWER9_CORE_MASK; |
631adaff | 1139 | k->core_pir = pnv_chip_core_pir_p9; |
d35aefa9 | 1140 | k->intc_create = pnv_chip_power9_intc_create; |
04026890 | 1141 | k->isa_create = pnv_chip_power9_isa_create; |
eb859a27 | 1142 | k->dt_populate = pnv_chip_power9_dt_populate; |
d8e4aad5 | 1143 | k->pic_print_info = pnv_chip_power9_pic_print_info; |
e997040e | 1144 | dc->desc = "PowerNV Chip POWER9"; |
77864267 CLG |
1145 | |
1146 | device_class_set_parent_realize(dc, pnv_chip_power9_realize, | |
1147 | &k->parent_realize); | |
e997040e CLG |
1148 | } |
1149 | ||
397a79e7 CLG |
1150 | static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) |
1151 | { | |
1152 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
1153 | int cores_max; | |
1154 | ||
1155 | /* | |
1156 | * No custom mask for this chip, let's use the default one from * | |
1157 | * the chip class | |
1158 | */ | |
1159 | if (!chip->cores_mask) { | |
1160 | chip->cores_mask = pcc->cores_mask; | |
1161 | } | |
1162 | ||
1163 | /* filter alien core ids ! some are reserved */ | |
1164 | if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { | |
1165 | error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", | |
1166 | chip->cores_mask); | |
1167 | return; | |
1168 | } | |
1169 | chip->cores_mask &= pcc->cores_mask; | |
1170 | ||
1171 | /* now that we have a sane layout, let check the number of cores */ | |
27d9ffd4 | 1172 | cores_max = ctpop64(chip->cores_mask); |
397a79e7 CLG |
1173 | if (chip->nr_cores > cores_max) { |
1174 | error_setg(errp, "warning: too many cores for chip ! Limit is %d", | |
1175 | cores_max); | |
1176 | return; | |
1177 | } | |
1178 | } | |
1179 | ||
51c04728 | 1180 | static void pnv_chip_core_realize(PnvChip *chip, Error **errp) |
e997040e | 1181 | { |
fe6b6346 | 1182 | MachineState *ms = MACHINE(qdev_get_machine()); |
397a79e7 | 1183 | Error *error = NULL; |
d2fd9612 | 1184 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
40abf43f | 1185 | const char *typename = pnv_chip_core_typename(chip); |
d2fd9612 CLG |
1186 | size_t typesize = object_type_get_instance_size(typename); |
1187 | int i, core_hwid; | |
1188 | ||
1189 | if (!object_class_by_name(typename)) { | |
1190 | error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); | |
1191 | return; | |
1192 | } | |
397a79e7 | 1193 | |
d2fd9612 | 1194 | /* Cores */ |
397a79e7 CLG |
1195 | pnv_chip_core_sanitize(chip, &error); |
1196 | if (error) { | |
1197 | error_propagate(errp, error); | |
1198 | return; | |
1199 | } | |
d2fd9612 CLG |
1200 | |
1201 | chip->cores = g_malloc0(typesize * chip->nr_cores); | |
1202 | ||
1203 | for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) | |
1204 | && (i < chip->nr_cores); core_hwid++) { | |
1205 | char core_name[32]; | |
1206 | void *pnv_core = chip->cores + i * typesize; | |
c035851a | 1207 | uint64_t xscom_core_base; |
d2fd9612 CLG |
1208 | |
1209 | if (!(chip->cores_mask & (1ull << core_hwid))) { | |
1210 | continue; | |
1211 | } | |
1212 | ||
d2fd9612 | 1213 | snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); |
bc4c406c PMD |
1214 | object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, |
1215 | typename, &error_fatal, NULL); | |
fe6b6346 | 1216 | object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", |
d2fd9612 CLG |
1217 | &error_fatal); |
1218 | object_property_set_int(OBJECT(pnv_core), core_hwid, | |
1219 | CPU_CORE_PROP_CORE_ID, &error_fatal); | |
1220 | object_property_set_int(OBJECT(pnv_core), | |
1221 | pcc->core_pir(chip, core_hwid), | |
1222 | "pir", &error_fatal); | |
d35aefa9 CLG |
1223 | object_property_add_const_link(OBJECT(pnv_core), "chip", |
1224 | OBJECT(chip), &error_fatal); | |
d2fd9612 CLG |
1225 | object_property_set_bool(OBJECT(pnv_core), true, "realized", |
1226 | &error_fatal); | |
24ece072 CLG |
1227 | |
1228 | /* Each core has an XSCOM MMIO region */ | |
c035851a CLG |
1229 | if (!pnv_chip_is_power9(chip)) { |
1230 | xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); | |
1231 | } else { | |
5dad902c | 1232 | xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); |
c035851a CLG |
1233 | } |
1234 | ||
1235 | pnv_xscom_add_subregion(chip, xscom_core_base, | |
24ece072 | 1236 | &PNV_CORE(pnv_core)->xscom_regs); |
d2fd9612 CLG |
1237 | i++; |
1238 | } | |
51c04728 CLG |
1239 | } |
1240 | ||
1241 | static void pnv_chip_realize(DeviceState *dev, Error **errp) | |
1242 | { | |
1243 | PnvChip *chip = PNV_CHIP(dev); | |
1244 | Error *error = NULL; | |
1245 | ||
51c04728 CLG |
1246 | /* Cores */ |
1247 | pnv_chip_core_realize(chip, &error); | |
1248 | if (error) { | |
1249 | error_propagate(errp, error); | |
1250 | return; | |
1251 | } | |
e997040e CLG |
1252 | } |
1253 | ||
1254 | static Property pnv_chip_properties[] = { | |
1255 | DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), | |
1256 | DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), | |
1257 | DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), | |
397a79e7 CLG |
1258 | DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), |
1259 | DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), | |
e997040e CLG |
1260 | DEFINE_PROP_END_OF_LIST(), |
1261 | }; | |
1262 | ||
1263 | static void pnv_chip_class_init(ObjectClass *klass, void *data) | |
1264 | { | |
1265 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1266 | ||
9d169fb3 | 1267 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
e997040e CLG |
1268 | dc->realize = pnv_chip_realize; |
1269 | dc->props = pnv_chip_properties; | |
1270 | dc->desc = "PowerNV Chip"; | |
1271 | } | |
1272 | ||
54f59d78 CLG |
1273 | static ICSState *pnv_ics_get(XICSFabric *xi, int irq) |
1274 | { | |
b168a138 | 1275 | PnvMachineState *pnv = PNV_MACHINE(xi); |
54f59d78 CLG |
1276 | int i; |
1277 | ||
1278 | for (i = 0; i < pnv->num_chips; i++) { | |
77864267 CLG |
1279 | Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); |
1280 | ||
1281 | if (ics_valid_irq(&chip8->psi.ics, irq)) { | |
1282 | return &chip8->psi.ics; | |
54f59d78 CLG |
1283 | } |
1284 | } | |
1285 | return NULL; | |
1286 | } | |
1287 | ||
1288 | static void pnv_ics_resend(XICSFabric *xi) | |
1289 | { | |
b168a138 | 1290 | PnvMachineState *pnv = PNV_MACHINE(xi); |
54f59d78 CLG |
1291 | int i; |
1292 | ||
1293 | for (i = 0; i < pnv->num_chips; i++) { | |
77864267 CLG |
1294 | Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); |
1295 | ics_resend(&chip8->psi.ics); | |
54f59d78 CLG |
1296 | } |
1297 | } | |
1298 | ||
36fc6f08 CLG |
1299 | static ICPState *pnv_icp_get(XICSFabric *xi, int pir) |
1300 | { | |
1301 | PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); | |
1302 | ||
956b8f46 | 1303 | return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; |
36fc6f08 CLG |
1304 | } |
1305 | ||
47fea43a CLG |
1306 | static void pnv_pic_print_info(InterruptStatsProvider *obj, |
1307 | Monitor *mon) | |
1308 | { | |
b168a138 | 1309 | PnvMachineState *pnv = PNV_MACHINE(obj); |
54f59d78 | 1310 | int i; |
47fea43a CLG |
1311 | CPUState *cs; |
1312 | ||
1313 | CPU_FOREACH(cs) { | |
1314 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1315 | ||
d8e4aad5 CLG |
1316 | if (pnv_chip_is_power9(pnv->chips[0])) { |
1317 | xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); | |
1318 | } else { | |
1319 | icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); | |
1320 | } | |
47fea43a | 1321 | } |
54f59d78 CLG |
1322 | |
1323 | for (i = 0; i < pnv->num_chips; i++) { | |
d8e4aad5 | 1324 | PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); |
54f59d78 | 1325 | } |
47fea43a CLG |
1326 | } |
1327 | ||
e997040e CLG |
1328 | static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, |
1329 | void *opaque, Error **errp) | |
1330 | { | |
b168a138 | 1331 | visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); |
e997040e CLG |
1332 | } |
1333 | ||
1334 | static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, | |
1335 | void *opaque, Error **errp) | |
1336 | { | |
b168a138 | 1337 | PnvMachineState *pnv = PNV_MACHINE(obj); |
e997040e CLG |
1338 | uint32_t num_chips; |
1339 | Error *local_err = NULL; | |
1340 | ||
1341 | visit_type_uint32(v, name, &num_chips, &local_err); | |
1342 | if (local_err) { | |
1343 | error_propagate(errp, local_err); | |
1344 | return; | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * TODO: should we decide on how many chips we can create based | |
1349 | * on #cores and Venice vs. Murano vs. Naples chip type etc..., | |
1350 | */ | |
1351 | if (!is_power_of_2(num_chips) || num_chips > 4) { | |
1352 | error_setg(errp, "invalid number of chips: '%d'", num_chips); | |
1353 | return; | |
1354 | } | |
1355 | ||
1356 | pnv->num_chips = num_chips; | |
1357 | } | |
1358 | ||
77864267 | 1359 | static void pnv_machine_instance_init(Object *obj) |
e997040e | 1360 | { |
b168a138 | 1361 | PnvMachineState *pnv = PNV_MACHINE(obj); |
e997040e CLG |
1362 | pnv->num_chips = 1; |
1363 | } | |
1364 | ||
b168a138 | 1365 | static void pnv_machine_class_props_init(ObjectClass *oc) |
e997040e | 1366 | { |
1e507bb0 | 1367 | object_class_property_add(oc, "num-chips", "uint32", |
e997040e CLG |
1368 | pnv_get_num_chips, pnv_set_num_chips, |
1369 | NULL, NULL, NULL); | |
1370 | object_class_property_set_description(oc, "num-chips", | |
1371 | "Specifies the number of processor chips", | |
1372 | NULL); | |
9e933f4a BH |
1373 | } |
1374 | ||
f30c843c | 1375 | static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) |
9e933f4a BH |
1376 | { |
1377 | MachineClass *mc = MACHINE_CLASS(oc); | |
36fc6f08 | 1378 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
f30c843c CLG |
1379 | |
1380 | mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; | |
1381 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); | |
1382 | ||
1383 | xic->icp_get = pnv_icp_get; | |
1384 | xic->ics_get = pnv_ics_get; | |
1385 | xic->ics_resend = pnv_ics_resend; | |
1386 | } | |
1387 | ||
1388 | static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) | |
1389 | { | |
1390 | MachineClass *mc = MACHINE_CLASS(oc); | |
1391 | ||
1392 | mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; | |
1393 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); | |
1394 | ||
1395 | mc->alias = "powernv"; | |
1396 | } | |
1397 | ||
1398 | static void pnv_machine_class_init(ObjectClass *oc, void *data) | |
1399 | { | |
1400 | MachineClass *mc = MACHINE_CLASS(oc); | |
47fea43a | 1401 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
9e933f4a BH |
1402 | |
1403 | mc->desc = "IBM PowerNV (Non-Virtualized)"; | |
b168a138 CLG |
1404 | mc->init = pnv_init; |
1405 | mc->reset = pnv_reset; | |
9e933f4a BH |
1406 | mc->max_cpus = MAX_CPUS; |
1407 | mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for | |
1408 | * storage */ | |
1409 | mc->no_parallel = 1; | |
1410 | mc->default_boot_order = NULL; | |
f1d18b0a JS |
1411 | /* |
1412 | * RAM defaults to less than 2048 for 32-bit hosts, and large | |
1413 | * enough to fit the maximum initrd size at it's load address | |
1414 | */ | |
1415 | mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; | |
47fea43a | 1416 | ispc->print_info = pnv_pic_print_info; |
e997040e | 1417 | |
b168a138 | 1418 | pnv_machine_class_props_init(oc); |
9e933f4a BH |
1419 | } |
1420 | ||
77864267 CLG |
1421 | #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ |
1422 | { \ | |
1423 | .name = type, \ | |
1424 | .class_init = class_initfn, \ | |
1425 | .parent = TYPE_PNV8_CHIP, \ | |
1426 | } | |
1427 | ||
1428 | #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ | |
1429 | { \ | |
1430 | .name = type, \ | |
1431 | .class_init = class_initfn, \ | |
1432 | .parent = TYPE_PNV9_CHIP, \ | |
beba5c0f IM |
1433 | } |
1434 | ||
f30c843c CLG |
1435 | #define DEFINE_PNV_MACHINE_TYPE(cpu, class_initfn) \ |
1436 | { \ | |
1437 | .name = MACHINE_TYPE_NAME(cpu), \ | |
1438 | .parent = TYPE_PNV_MACHINE, \ | |
1439 | .instance_size = sizeof(PnvMachineState), \ | |
1440 | .instance_init = pnv_machine_instance_init, \ | |
1441 | .class_init = class_initfn, \ | |
1442 | .interfaces = (InterfaceInfo[]) { \ | |
1443 | { TYPE_XICS_FABRIC }, \ | |
1444 | { TYPE_INTERRUPT_STATS_PROVIDER }, \ | |
1445 | { }, \ | |
1446 | }, \ | |
1447 | } | |
1448 | ||
beba5c0f | 1449 | static const TypeInfo types[] = { |
f30c843c CLG |
1450 | DEFINE_PNV_MACHINE_TYPE("powernv8", pnv_machine_power8_class_init), |
1451 | DEFINE_PNV_MACHINE_TYPE("powernv9", pnv_machine_power9_class_init), | |
beba5c0f | 1452 | { |
b168a138 | 1453 | .name = TYPE_PNV_MACHINE, |
beba5c0f | 1454 | .parent = TYPE_MACHINE, |
f30c843c | 1455 | .abstract = true, |
beba5c0f | 1456 | .instance_size = sizeof(PnvMachineState), |
77864267 | 1457 | .instance_init = pnv_machine_instance_init, |
b168a138 | 1458 | .class_init = pnv_machine_class_init, |
beba5c0f IM |
1459 | .interfaces = (InterfaceInfo[]) { |
1460 | { TYPE_XICS_FABRIC }, | |
1461 | { TYPE_INTERRUPT_STATS_PROVIDER }, | |
1462 | { }, | |
1463 | }, | |
36fc6f08 | 1464 | }, |
beba5c0f IM |
1465 | { |
1466 | .name = TYPE_PNV_CHIP, | |
1467 | .parent = TYPE_SYS_BUS_DEVICE, | |
1468 | .class_init = pnv_chip_class_init, | |
beba5c0f IM |
1469 | .instance_size = sizeof(PnvChip), |
1470 | .class_size = sizeof(PnvChipClass), | |
1471 | .abstract = true, | |
1472 | }, | |
77864267 CLG |
1473 | |
1474 | /* | |
1475 | * P9 chip and variants | |
1476 | */ | |
1477 | { | |
1478 | .name = TYPE_PNV9_CHIP, | |
1479 | .parent = TYPE_PNV_CHIP, | |
1480 | .instance_init = pnv_chip_power9_instance_init, | |
1481 | .instance_size = sizeof(Pnv9Chip), | |
1482 | }, | |
1483 | DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), | |
1484 | ||
1485 | /* | |
1486 | * P8 chip and variants | |
1487 | */ | |
1488 | { | |
1489 | .name = TYPE_PNV8_CHIP, | |
1490 | .parent = TYPE_PNV_CHIP, | |
1491 | .instance_init = pnv_chip_power8_instance_init, | |
1492 | .instance_size = sizeof(Pnv8Chip), | |
1493 | }, | |
1494 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), | |
1495 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), | |
1496 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, | |
1497 | pnv_chip_power8nvl_class_init), | |
9e933f4a BH |
1498 | }; |
1499 | ||
beba5c0f | 1500 | DEFINE_TYPES(types) |