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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV machine model | |
3 | * | |
4 | * Copyright (c) 2016, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qapi/error.h" | |
22 | #include "sysemu/sysemu.h" | |
23 | #include "sysemu/numa.h" | |
d2528bdc | 24 | #include "sysemu/cpus.h" |
9e933f4a | 25 | #include "hw/hw.h" |
fcf5ef2a | 26 | #include "target/ppc/cpu.h" |
9e933f4a BH |
27 | #include "qemu/log.h" |
28 | #include "hw/ppc/fdt.h" | |
29 | #include "hw/ppc/ppc.h" | |
30 | #include "hw/ppc/pnv.h" | |
d2fd9612 | 31 | #include "hw/ppc/pnv_core.h" |
9e933f4a BH |
32 | #include "hw/loader.h" |
33 | #include "exec/address-spaces.h" | |
34 | #include "qemu/cutils.h" | |
e997040e | 35 | #include "qapi/visitor.h" |
47fea43a CLG |
36 | #include "monitor/monitor.h" |
37 | #include "hw/intc/intc.h" | |
9e933f4a | 38 | |
36fc6f08 | 39 | #include "hw/ppc/xics.h" |
967b7523 CLG |
40 | #include "hw/ppc/pnv_xscom.h" |
41 | ||
3495b6b6 CLG |
42 | #include "hw/isa/isa.h" |
43 | #include "hw/char/serial.h" | |
44 | #include "hw/timer/mc146818rtc.h" | |
45 | ||
9e933f4a BH |
46 | #include <libfdt.h> |
47 | ||
48 | #define FDT_MAX_SIZE 0x00100000 | |
49 | ||
50 | #define FW_FILE_NAME "skiboot.lid" | |
51 | #define FW_LOAD_ADDR 0x0 | |
52 | #define FW_MAX_SIZE 0x00400000 | |
53 | ||
54 | #define KERNEL_LOAD_ADDR 0x20000000 | |
55 | #define INITRD_LOAD_ADDR 0x40000000 | |
56 | ||
57 | /* | |
58 | * On Power Systems E880 (POWER8), the max cpus (threads) should be : | |
59 | * 4 * 4 sockets * 12 cores * 8 threads = 1536 | |
60 | * Let's make it 2^11 | |
61 | */ | |
62 | #define MAX_CPUS 2048 | |
63 | ||
64 | /* | |
65 | * Memory nodes are created by hostboot, one for each range of memory | |
66 | * that has a different "affinity". In practice, it means one range | |
67 | * per chip. | |
68 | */ | |
69 | static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, | |
70 | hwaddr size) | |
71 | { | |
72 | char *mem_name; | |
73 | uint64_t mem_reg_property[2]; | |
74 | int off; | |
75 | ||
76 | mem_reg_property[0] = cpu_to_be64(start); | |
77 | mem_reg_property[1] = cpu_to_be64(size); | |
78 | ||
79 | mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); | |
80 | off = fdt_add_subnode(fdt, 0, mem_name); | |
81 | g_free(mem_name); | |
82 | ||
83 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
84 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
85 | sizeof(mem_reg_property)))); | |
86 | _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); | |
87 | } | |
88 | ||
d2fd9612 CLG |
89 | static int get_cpus_node(void *fdt) |
90 | { | |
91 | int cpus_offset = fdt_path_offset(fdt, "/cpus"); | |
92 | ||
93 | if (cpus_offset < 0) { | |
94 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
95 | "cpus"); | |
96 | if (cpus_offset) { | |
97 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
98 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
99 | } | |
100 | } | |
101 | _FDT(cpus_offset); | |
102 | return cpus_offset; | |
103 | } | |
104 | ||
105 | /* | |
106 | * The PowerNV cores (and threads) need to use real HW ids and not an | |
107 | * incremental index like it has been done on other platforms. This HW | |
108 | * id is stored in the CPU PIR, it is used to create cpu nodes in the | |
109 | * device tree, used in XSCOM to address cores and in interrupt | |
110 | * servers. | |
111 | */ | |
112 | static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) | |
113 | { | |
114 | CPUState *cs = CPU(DEVICE(pc->threads)); | |
115 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
116 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
8bd9530e | 117 | int smt_threads = CPU_CORE(pc)->nr_threads; |
d2fd9612 CLG |
118 | CPUPPCState *env = &cpu->env; |
119 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
120 | uint32_t servers_prop[smt_threads]; | |
121 | int i; | |
122 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
123 | 0xffffffff, 0xffffffff}; | |
124 | uint32_t tbfreq = PNV_TIMEBASE_FREQ; | |
125 | uint32_t cpufreq = 1000000000; | |
126 | uint32_t page_sizes_prop[64]; | |
127 | size_t page_sizes_prop_size; | |
128 | const uint8_t pa_features[] = { 24, 0, | |
129 | 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, | |
130 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
131 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
132 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
133 | int offset; | |
134 | char *nodename; | |
135 | int cpus_offset = get_cpus_node(fdt); | |
136 | ||
137 | nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); | |
138 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
139 | _FDT(offset); | |
140 | g_free(nodename); | |
141 | ||
142 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); | |
143 | ||
144 | _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); | |
145 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); | |
146 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
147 | ||
148 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
149 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
150 | env->dcache_line_size))); | |
151 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
152 | env->dcache_line_size))); | |
153 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
154 | env->icache_line_size))); | |
155 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
156 | env->icache_line_size))); | |
157 | ||
158 | if (pcc->l1_dcache_size) { | |
159 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
160 | pcc->l1_dcache_size))); | |
161 | } else { | |
162 | error_report("Warning: Unknown L1 dcache size for cpu"); | |
163 | } | |
164 | if (pcc->l1_icache_size) { | |
165 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
166 | pcc->l1_icache_size))); | |
167 | } else { | |
168 | error_report("Warning: Unknown L1 icache size for cpu"); | |
169 | } | |
170 | ||
171 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
172 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
173 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); | |
174 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
175 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
176 | ||
177 | if (env->spr_cb[SPR_PURR].oea_read) { | |
178 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
179 | } | |
180 | ||
181 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
182 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
183 | segs, sizeof(segs)))); | |
184 | } | |
185 | ||
186 | /* Advertise VMX/VSX (vector extensions) if available | |
187 | * 0 / no property == no vector extensions | |
188 | * 1 == VMX / Altivec available | |
189 | * 2 == VSX available */ | |
190 | if (env->insns_flags & PPC_ALTIVEC) { | |
191 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
192 | ||
193 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
194 | } | |
195 | ||
196 | /* Advertise DFP (Decimal Floating Point) if available | |
197 | * 0 / no property == no DFP | |
198 | * 1 == DFP available */ | |
199 | if (env->insns_flags2 & PPC2_DFP) { | |
200 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
201 | } | |
202 | ||
203 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, | |
204 | sizeof(page_sizes_prop)); | |
205 | if (page_sizes_prop_size) { | |
206 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
207 | page_sizes_prop, page_sizes_prop_size))); | |
208 | } | |
209 | ||
210 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", | |
211 | pa_features, sizeof(pa_features)))); | |
212 | ||
d2fd9612 CLG |
213 | /* Build interrupt servers properties */ |
214 | for (i = 0; i < smt_threads; i++) { | |
215 | servers_prop[i] = cpu_to_be32(pc->pir + i); | |
216 | } | |
217 | _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
218 | servers_prop, sizeof(servers_prop)))); | |
219 | } | |
220 | ||
bf5615e7 CLG |
221 | static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir, |
222 | uint32_t nr_threads) | |
223 | { | |
224 | uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); | |
225 | char *name; | |
226 | const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; | |
227 | uint32_t irange[2], i, rsize; | |
228 | uint64_t *reg; | |
229 | int offset; | |
230 | ||
231 | irange[0] = cpu_to_be32(pir); | |
232 | irange[1] = cpu_to_be32(nr_threads); | |
233 | ||
234 | rsize = sizeof(uint64_t) * 2 * nr_threads; | |
235 | reg = g_malloc(rsize); | |
236 | for (i = 0; i < nr_threads; i++) { | |
237 | reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); | |
238 | reg[i * 2 + 1] = cpu_to_be64(0x1000); | |
239 | } | |
240 | ||
241 | name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); | |
242 | offset = fdt_add_subnode(fdt, 0, name); | |
243 | _FDT(offset); | |
244 | g_free(name); | |
245 | ||
246 | _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); | |
247 | _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); | |
248 | _FDT((fdt_setprop_string(fdt, offset, "device_type", | |
249 | "PowerPC-External-Interrupt-Presentation"))); | |
250 | _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); | |
251 | _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", | |
252 | irange, sizeof(irange)))); | |
253 | _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); | |
254 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); | |
255 | g_free(reg); | |
256 | } | |
257 | ||
5a7e14a2 CLG |
258 | static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) |
259 | { | |
260 | char *name; | |
261 | int offset; | |
262 | ||
263 | name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", | |
264 | (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); | |
265 | offset = fdt_path_offset(fdt, name); | |
266 | g_free(name); | |
267 | return offset; | |
268 | } | |
269 | ||
e997040e CLG |
270 | static void powernv_populate_chip(PnvChip *chip, void *fdt) |
271 | { | |
d2fd9612 CLG |
272 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
273 | char *typename = pnv_core_typename(pcc->cpu_model); | |
274 | size_t typesize = object_type_get_instance_size(typename); | |
275 | int i; | |
276 | ||
967b7523 CLG |
277 | pnv_xscom_populate(chip, fdt, 0); |
278 | ||
5a7e14a2 CLG |
279 | /* The default LPC bus of a multichip system is on chip 0. It's |
280 | * recognized by the firmware (skiboot) using a "primary" | |
281 | * property. | |
282 | */ | |
283 | if (chip->chip_id == 0x0) { | |
284 | int lpc_offset = pnv_chip_lpc_offset(chip, fdt); | |
285 | ||
286 | _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); | |
287 | } | |
288 | ||
d2fd9612 CLG |
289 | for (i = 0; i < chip->nr_cores; i++) { |
290 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
291 | ||
292 | powernv_create_core_node(chip, pnv_core, fdt); | |
bf5615e7 CLG |
293 | |
294 | /* Interrupt Control Presenters (ICP). One per core. */ | |
295 | powernv_populate_icp(chip, fdt, pnv_core->pir, | |
296 | CPU_CORE(pnv_core)->nr_threads); | |
d2fd9612 CLG |
297 | } |
298 | ||
e997040e CLG |
299 | if (chip->ram_size) { |
300 | powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, | |
301 | chip->ram_size); | |
302 | } | |
d2fd9612 | 303 | g_free(typename); |
e997040e CLG |
304 | } |
305 | ||
c5ffdcae CLG |
306 | static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) |
307 | { | |
308 | uint32_t io_base = d->ioport_id; | |
309 | uint32_t io_regs[] = { | |
310 | cpu_to_be32(1), | |
311 | cpu_to_be32(io_base), | |
312 | cpu_to_be32(2) | |
313 | }; | |
314 | char *name; | |
315 | int node; | |
316 | ||
317 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
318 | node = fdt_add_subnode(fdt, lpc_off, name); | |
319 | _FDT(node); | |
320 | g_free(name); | |
321 | ||
322 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); | |
323 | _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); | |
324 | } | |
325 | ||
e7a3fee3 CLG |
326 | typedef struct ForeachPopulateArgs { |
327 | void *fdt; | |
328 | int offset; | |
329 | } ForeachPopulateArgs; | |
330 | ||
331 | static int powernv_populate_isa_device(DeviceState *dev, void *opaque) | |
332 | { | |
c5ffdcae CLG |
333 | ForeachPopulateArgs *args = opaque; |
334 | ISADevice *d = ISA_DEVICE(dev); | |
335 | ||
336 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { | |
337 | powernv_populate_rtc(d, args->fdt, args->offset); | |
338 | } else { | |
339 | error_report("unknown isa device %s@i%x", qdev_fw_name(dev), | |
340 | d->ioport_id); | |
341 | } | |
342 | ||
e7a3fee3 CLG |
343 | return 0; |
344 | } | |
345 | ||
346 | static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) | |
347 | { | |
348 | ForeachPopulateArgs args = { | |
349 | .fdt = fdt, | |
350 | .offset = lpc_offset, | |
351 | }; | |
352 | ||
353 | /* ISA devices are not necessarily parented to the ISA bus so we | |
354 | * can not use object_child_foreach() */ | |
355 | qbus_walk_children(BUS(bus), powernv_populate_isa_device, | |
356 | NULL, NULL, NULL, &args); | |
357 | } | |
358 | ||
9e933f4a BH |
359 | static void *powernv_create_fdt(MachineState *machine) |
360 | { | |
361 | const char plat_compat[] = "qemu,powernv\0ibm,powernv"; | |
362 | PnvMachineState *pnv = POWERNV_MACHINE(machine); | |
363 | void *fdt; | |
364 | char *buf; | |
365 | int off; | |
e997040e | 366 | int i; |
e7a3fee3 | 367 | int lpc_offset; |
9e933f4a BH |
368 | |
369 | fdt = g_malloc0(FDT_MAX_SIZE); | |
370 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
371 | ||
372 | /* Root node */ | |
373 | _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); | |
374 | _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); | |
375 | _FDT((fdt_setprop_string(fdt, 0, "model", | |
376 | "IBM PowerNV (emulated by qemu)"))); | |
377 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, | |
378 | sizeof(plat_compat)))); | |
379 | ||
380 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
381 | _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); | |
382 | if (qemu_uuid_set) { | |
383 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
384 | } | |
385 | g_free(buf); | |
386 | ||
387 | off = fdt_add_subnode(fdt, 0, "chosen"); | |
388 | if (machine->kernel_cmdline) { | |
389 | _FDT((fdt_setprop_string(fdt, off, "bootargs", | |
390 | machine->kernel_cmdline))); | |
391 | } | |
392 | ||
393 | if (pnv->initrd_size) { | |
394 | uint32_t start_prop = cpu_to_be32(pnv->initrd_base); | |
395 | uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); | |
396 | ||
397 | _FDT((fdt_setprop(fdt, off, "linux,initrd-start", | |
398 | &start_prop, sizeof(start_prop)))); | |
399 | _FDT((fdt_setprop(fdt, off, "linux,initrd-end", | |
400 | &end_prop, sizeof(end_prop)))); | |
401 | } | |
402 | ||
e997040e CLG |
403 | /* Populate device tree for each chip */ |
404 | for (i = 0; i < pnv->num_chips; i++) { | |
405 | powernv_populate_chip(pnv->chips[i], fdt); | |
406 | } | |
e7a3fee3 CLG |
407 | |
408 | /* Populate ISA devices on chip 0 */ | |
409 | lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt); | |
410 | powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); | |
9e933f4a BH |
411 | return fdt; |
412 | } | |
413 | ||
414 | static void ppc_powernv_reset(void) | |
415 | { | |
416 | MachineState *machine = MACHINE(qdev_get_machine()); | |
417 | void *fdt; | |
418 | ||
419 | qemu_devices_reset(); | |
420 | ||
421 | fdt = powernv_create_fdt(machine); | |
422 | ||
423 | /* Pack resulting tree */ | |
424 | _FDT((fdt_pack(fdt))); | |
425 | ||
426 | cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); | |
427 | } | |
428 | ||
3495b6b6 CLG |
429 | static ISABus *pnv_isa_create(PnvChip *chip) |
430 | { | |
431 | PnvLpcController *lpc = &chip->lpc; | |
432 | ISABus *isa_bus; | |
433 | qemu_irq *irqs; | |
434 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
435 | ||
436 | /* let isa_bus_new() create its own bridge on SysBus otherwise | |
437 | * devices speficied on the command line won't find the bus and | |
438 | * will fail to create. | |
439 | */ | |
440 | isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, | |
441 | &error_fatal); | |
442 | ||
4d1df88b | 443 | irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); |
3495b6b6 CLG |
444 | |
445 | isa_bus_irqs(isa_bus, irqs); | |
446 | return isa_bus; | |
447 | } | |
448 | ||
9e933f4a BH |
449 | static void ppc_powernv_init(MachineState *machine) |
450 | { | |
451 | PnvMachineState *pnv = POWERNV_MACHINE(machine); | |
452 | MemoryRegion *ram; | |
453 | char *fw_filename; | |
454 | long fw_size; | |
e997040e CLG |
455 | int i; |
456 | char *chip_typename; | |
9e933f4a BH |
457 | |
458 | /* allocate RAM */ | |
459 | if (machine->ram_size < (1 * G_BYTE)) { | |
460 | error_report("Warning: skiboot may not work with < 1GB of RAM"); | |
461 | } | |
462 | ||
463 | ram = g_new(MemoryRegion, 1); | |
464 | memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", | |
465 | machine->ram_size); | |
466 | memory_region_add_subregion(get_system_memory(), 0, ram); | |
467 | ||
468 | /* load skiboot firmware */ | |
469 | if (bios_name == NULL) { | |
470 | bios_name = FW_FILE_NAME; | |
471 | } | |
472 | ||
473 | fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
474 | ||
475 | fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); | |
476 | if (fw_size < 0) { | |
802fc7ab | 477 | error_report("Could not load OPAL '%s'", fw_filename); |
9e933f4a BH |
478 | exit(1); |
479 | } | |
480 | g_free(fw_filename); | |
481 | ||
482 | /* load kernel */ | |
483 | if (machine->kernel_filename) { | |
484 | long kernel_size; | |
485 | ||
486 | kernel_size = load_image_targphys(machine->kernel_filename, | |
487 | KERNEL_LOAD_ADDR, 0x2000000); | |
488 | if (kernel_size < 0) { | |
802fc7ab | 489 | error_report("Could not load kernel '%s'", |
7c6e8797 | 490 | machine->kernel_filename); |
9e933f4a BH |
491 | exit(1); |
492 | } | |
493 | } | |
494 | ||
495 | /* load initrd */ | |
496 | if (machine->initrd_filename) { | |
497 | pnv->initrd_base = INITRD_LOAD_ADDR; | |
498 | pnv->initrd_size = load_image_targphys(machine->initrd_filename, | |
499 | pnv->initrd_base, 0x10000000); /* 128MB max */ | |
500 | if (pnv->initrd_size < 0) { | |
802fc7ab | 501 | error_report("Could not load initial ram disk '%s'", |
9e933f4a BH |
502 | machine->initrd_filename); |
503 | exit(1); | |
504 | } | |
505 | } | |
e997040e CLG |
506 | |
507 | /* We need some cpu model to instantiate the PnvChip class */ | |
508 | if (machine->cpu_model == NULL) { | |
509 | machine->cpu_model = "POWER8"; | |
510 | } | |
511 | ||
512 | /* Create the processor chips */ | |
513 | chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model); | |
514 | if (!object_class_by_name(chip_typename)) { | |
515 | error_report("qemu: invalid CPU model '%s' for %s machine", | |
516 | machine->cpu_model, MACHINE_GET_CLASS(machine)->name); | |
517 | exit(1); | |
518 | } | |
519 | ||
520 | pnv->chips = g_new0(PnvChip *, pnv->num_chips); | |
521 | for (i = 0; i < pnv->num_chips; i++) { | |
522 | char chip_name[32]; | |
523 | Object *chip = object_new(chip_typename); | |
524 | ||
525 | pnv->chips[i] = PNV_CHIP(chip); | |
526 | ||
527 | /* TODO: put all the memory in one node on chip 0 until we find a | |
528 | * way to specify different ranges for each chip | |
529 | */ | |
530 | if (i == 0) { | |
531 | object_property_set_int(chip, machine->ram_size, "ram-size", | |
532 | &error_fatal); | |
533 | } | |
534 | ||
535 | snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); | |
536 | object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); | |
537 | object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", | |
538 | &error_fatal); | |
397a79e7 | 539 | object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); |
e997040e CLG |
540 | object_property_set_bool(chip, true, "realized", &error_fatal); |
541 | } | |
542 | g_free(chip_typename); | |
3495b6b6 CLG |
543 | |
544 | /* Instantiate ISA bus on chip 0 */ | |
545 | pnv->isa_bus = pnv_isa_create(pnv->chips[0]); | |
546 | ||
547 | /* Create serial port */ | |
548 | serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); | |
549 | ||
550 | /* Create an RTC ISA device too */ | |
551 | rtc_init(pnv->isa_bus, 2000, NULL); | |
e997040e CLG |
552 | } |
553 | ||
631adaff CLG |
554 | /* |
555 | * 0:21 Reserved - Read as zeros | |
556 | * 22:24 Chip ID | |
557 | * 25:28 Core number | |
558 | * 29:31 Thread ID | |
559 | */ | |
560 | static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) | |
561 | { | |
562 | return (chip->chip_id << 7) | (core_id << 3); | |
563 | } | |
564 | ||
565 | /* | |
566 | * 0:48 Reserved - Read as zeroes | |
567 | * 49:52 Node ID | |
568 | * 53:55 Chip ID | |
569 | * 56 Reserved - Read as zero | |
570 | * 57:61 Core number | |
571 | * 62:63 Thread ID | |
572 | * | |
573 | * We only care about the lower bits. uint32_t is fine for the moment. | |
574 | */ | |
575 | static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) | |
576 | { | |
577 | return (chip->chip_id << 8) | (core_id << 2); | |
578 | } | |
579 | ||
397a79e7 CLG |
580 | /* Allowed core identifiers on a POWER8 Processor Chip : |
581 | * | |
582 | * <EX0 reserved> | |
583 | * EX1 - Venice only | |
584 | * EX2 - Venice only | |
585 | * EX3 - Venice only | |
586 | * EX4 | |
587 | * EX5 | |
588 | * EX6 | |
589 | * <EX7,8 reserved> <reserved> | |
590 | * EX9 - Venice only | |
591 | * EX10 - Venice only | |
592 | * EX11 - Venice only | |
593 | * EX12 | |
594 | * EX13 | |
595 | * EX14 | |
596 | * <EX15 reserved> | |
597 | */ | |
598 | #define POWER8E_CORE_MASK (0x7070ull) | |
599 | #define POWER8_CORE_MASK (0x7e7eull) | |
600 | ||
601 | /* | |
602 | * POWER9 has 24 cores, ids starting at 0x20 | |
603 | */ | |
604 | #define POWER9_CORE_MASK (0xffffff00000000ull) | |
605 | ||
e997040e CLG |
606 | static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) |
607 | { | |
608 | DeviceClass *dc = DEVICE_CLASS(klass); | |
609 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
610 | ||
611 | k->cpu_model = "POWER8E"; | |
612 | k->chip_type = PNV_CHIP_POWER8E; | |
613 | k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ | |
397a79e7 | 614 | k->cores_mask = POWER8E_CORE_MASK; |
631adaff | 615 | k->core_pir = pnv_chip_core_pir_p8; |
967b7523 | 616 | k->xscom_base = 0x003fc0000000000ull; |
ad521238 | 617 | k->xscom_core_base = 0x10000000ull; |
e997040e CLG |
618 | dc->desc = "PowerNV Chip POWER8E"; |
619 | } | |
620 | ||
621 | static const TypeInfo pnv_chip_power8e_info = { | |
622 | .name = TYPE_PNV_CHIP_POWER8E, | |
623 | .parent = TYPE_PNV_CHIP, | |
624 | .instance_size = sizeof(PnvChip), | |
625 | .class_init = pnv_chip_power8e_class_init, | |
626 | }; | |
627 | ||
628 | static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) | |
629 | { | |
630 | DeviceClass *dc = DEVICE_CLASS(klass); | |
631 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
632 | ||
633 | k->cpu_model = "POWER8"; | |
634 | k->chip_type = PNV_CHIP_POWER8; | |
635 | k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ | |
397a79e7 | 636 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 637 | k->core_pir = pnv_chip_core_pir_p8; |
967b7523 | 638 | k->xscom_base = 0x003fc0000000000ull; |
ad521238 | 639 | k->xscom_core_base = 0x10000000ull; |
e997040e CLG |
640 | dc->desc = "PowerNV Chip POWER8"; |
641 | } | |
642 | ||
643 | static const TypeInfo pnv_chip_power8_info = { | |
644 | .name = TYPE_PNV_CHIP_POWER8, | |
645 | .parent = TYPE_PNV_CHIP, | |
646 | .instance_size = sizeof(PnvChip), | |
647 | .class_init = pnv_chip_power8_class_init, | |
648 | }; | |
649 | ||
650 | static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) | |
651 | { | |
652 | DeviceClass *dc = DEVICE_CLASS(klass); | |
653 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
654 | ||
655 | k->cpu_model = "POWER8NVL"; | |
656 | k->chip_type = PNV_CHIP_POWER8NVL; | |
657 | k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ | |
397a79e7 | 658 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 659 | k->core_pir = pnv_chip_core_pir_p8; |
967b7523 | 660 | k->xscom_base = 0x003fc0000000000ull; |
ad521238 | 661 | k->xscom_core_base = 0x10000000ull; |
e997040e CLG |
662 | dc->desc = "PowerNV Chip POWER8NVL"; |
663 | } | |
664 | ||
665 | static const TypeInfo pnv_chip_power8nvl_info = { | |
666 | .name = TYPE_PNV_CHIP_POWER8NVL, | |
667 | .parent = TYPE_PNV_CHIP, | |
668 | .instance_size = sizeof(PnvChip), | |
669 | .class_init = pnv_chip_power8nvl_class_init, | |
670 | }; | |
671 | ||
672 | static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) | |
673 | { | |
674 | DeviceClass *dc = DEVICE_CLASS(klass); | |
675 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
676 | ||
677 | k->cpu_model = "POWER9"; | |
678 | k->chip_type = PNV_CHIP_POWER9; | |
679 | k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ | |
397a79e7 | 680 | k->cores_mask = POWER9_CORE_MASK; |
631adaff | 681 | k->core_pir = pnv_chip_core_pir_p9; |
967b7523 | 682 | k->xscom_base = 0x00603fc00000000ull; |
ad521238 | 683 | k->xscom_core_base = 0x0ull; |
e997040e CLG |
684 | dc->desc = "PowerNV Chip POWER9"; |
685 | } | |
686 | ||
687 | static const TypeInfo pnv_chip_power9_info = { | |
688 | .name = TYPE_PNV_CHIP_POWER9, | |
689 | .parent = TYPE_PNV_CHIP, | |
690 | .instance_size = sizeof(PnvChip), | |
691 | .class_init = pnv_chip_power9_class_init, | |
692 | }; | |
693 | ||
397a79e7 CLG |
694 | static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) |
695 | { | |
696 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
697 | int cores_max; | |
698 | ||
699 | /* | |
700 | * No custom mask for this chip, let's use the default one from * | |
701 | * the chip class | |
702 | */ | |
703 | if (!chip->cores_mask) { | |
704 | chip->cores_mask = pcc->cores_mask; | |
705 | } | |
706 | ||
707 | /* filter alien core ids ! some are reserved */ | |
708 | if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { | |
709 | error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", | |
710 | chip->cores_mask); | |
711 | return; | |
712 | } | |
713 | chip->cores_mask &= pcc->cores_mask; | |
714 | ||
715 | /* now that we have a sane layout, let check the number of cores */ | |
27d9ffd4 | 716 | cores_max = ctpop64(chip->cores_mask); |
397a79e7 CLG |
717 | if (chip->nr_cores > cores_max) { |
718 | error_setg(errp, "warning: too many cores for chip ! Limit is %d", | |
719 | cores_max); | |
720 | return; | |
721 | } | |
722 | } | |
723 | ||
967b7523 CLG |
724 | static void pnv_chip_init(Object *obj) |
725 | { | |
726 | PnvChip *chip = PNV_CHIP(obj); | |
727 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
728 | ||
729 | chip->xscom_base = pcc->xscom_base; | |
a3980bf5 BH |
730 | |
731 | object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); | |
732 | object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); | |
54f59d78 CLG |
733 | |
734 | object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); | |
735 | object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); | |
736 | object_property_add_const_link(OBJECT(&chip->psi), "xics", | |
737 | OBJECT(qdev_get_machine()), &error_abort); | |
0722d05a BH |
738 | |
739 | object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); | |
740 | object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); | |
741 | object_property_add_const_link(OBJECT(&chip->occ), "psi", | |
742 | OBJECT(&chip->psi), &error_abort); | |
4d1df88b BH |
743 | |
744 | /* The LPC controller needs PSI to generate interrupts */ | |
745 | object_property_add_const_link(OBJECT(&chip->lpc), "psi", | |
746 | OBJECT(&chip->psi), &error_abort); | |
967b7523 CLG |
747 | } |
748 | ||
bf5615e7 CLG |
749 | static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) |
750 | { | |
751 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
752 | char *typename = pnv_core_typename(pcc->cpu_model); | |
753 | size_t typesize = object_type_get_instance_size(typename); | |
754 | int i, j; | |
755 | char *name; | |
756 | XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); | |
757 | ||
758 | name = g_strdup_printf("icp-%x", chip->chip_id); | |
759 | memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); | |
760 | sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); | |
761 | g_free(name); | |
762 | ||
763 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); | |
764 | ||
765 | /* Map the ICP registers for each thread */ | |
766 | for (i = 0; i < chip->nr_cores; i++) { | |
767 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
768 | int core_hwid = CPU_CORE(pnv_core)->core_id; | |
769 | ||
770 | for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { | |
771 | uint32_t pir = pcc->core_pir(chip, core_hwid) + j; | |
772 | PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); | |
773 | ||
774 | memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio); | |
775 | } | |
776 | } | |
777 | ||
778 | g_free(typename); | |
779 | } | |
780 | ||
e997040e CLG |
781 | static void pnv_chip_realize(DeviceState *dev, Error **errp) |
782 | { | |
397a79e7 CLG |
783 | PnvChip *chip = PNV_CHIP(dev); |
784 | Error *error = NULL; | |
d2fd9612 CLG |
785 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
786 | char *typename = pnv_core_typename(pcc->cpu_model); | |
787 | size_t typesize = object_type_get_instance_size(typename); | |
788 | int i, core_hwid; | |
789 | ||
790 | if (!object_class_by_name(typename)) { | |
791 | error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); | |
792 | return; | |
793 | } | |
397a79e7 | 794 | |
967b7523 CLG |
795 | /* XSCOM bridge */ |
796 | pnv_xscom_realize(chip, &error); | |
797 | if (error) { | |
798 | error_propagate(errp, error); | |
799 | return; | |
800 | } | |
801 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); | |
802 | ||
d2fd9612 | 803 | /* Cores */ |
397a79e7 CLG |
804 | pnv_chip_core_sanitize(chip, &error); |
805 | if (error) { | |
806 | error_propagate(errp, error); | |
807 | return; | |
808 | } | |
d2fd9612 CLG |
809 | |
810 | chip->cores = g_malloc0(typesize * chip->nr_cores); | |
811 | ||
812 | for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) | |
813 | && (i < chip->nr_cores); core_hwid++) { | |
814 | char core_name[32]; | |
815 | void *pnv_core = chip->cores + i * typesize; | |
816 | ||
817 | if (!(chip->cores_mask & (1ull << core_hwid))) { | |
818 | continue; | |
819 | } | |
820 | ||
821 | object_initialize(pnv_core, typesize, typename); | |
822 | snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); | |
823 | object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), | |
824 | &error_fatal); | |
825 | object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", | |
826 | &error_fatal); | |
827 | object_property_set_int(OBJECT(pnv_core), core_hwid, | |
828 | CPU_CORE_PROP_CORE_ID, &error_fatal); | |
829 | object_property_set_int(OBJECT(pnv_core), | |
830 | pcc->core_pir(chip, core_hwid), | |
831 | "pir", &error_fatal); | |
960fbd29 CLG |
832 | object_property_add_const_link(OBJECT(pnv_core), "xics", |
833 | qdev_get_machine(), &error_fatal); | |
d2fd9612 CLG |
834 | object_property_set_bool(OBJECT(pnv_core), true, "realized", |
835 | &error_fatal); | |
836 | object_unref(OBJECT(pnv_core)); | |
24ece072 CLG |
837 | |
838 | /* Each core has an XSCOM MMIO region */ | |
ad521238 CLG |
839 | pnv_xscom_add_subregion(chip, |
840 | PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base, | |
841 | core_hwid), | |
24ece072 | 842 | &PNV_CORE(pnv_core)->xscom_regs); |
d2fd9612 CLG |
843 | i++; |
844 | } | |
845 | g_free(typename); | |
a3980bf5 BH |
846 | |
847 | /* Create LPC controller */ | |
848 | object_property_set_bool(OBJECT(&chip->lpc), true, "realized", | |
849 | &error_fatal); | |
850 | pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); | |
bf5615e7 CLG |
851 | |
852 | /* Interrupt Management Area. This is the memory region holding | |
853 | * all the Interrupt Control Presenter (ICP) registers */ | |
854 | pnv_chip_icp_realize(chip, &error); | |
855 | if (error) { | |
856 | error_propagate(errp, error); | |
857 | return; | |
858 | } | |
54f59d78 CLG |
859 | |
860 | /* Processor Service Interface (PSI) Host Bridge */ | |
861 | object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), | |
862 | "bar", &error_fatal); | |
863 | object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); | |
864 | if (error) { | |
865 | error_propagate(errp, error); | |
866 | return; | |
867 | } | |
868 | pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs); | |
0722d05a BH |
869 | |
870 | /* Create the simplified OCC model */ | |
871 | object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); | |
872 | if (error) { | |
873 | error_propagate(errp, error); | |
874 | return; | |
875 | } | |
876 | pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs); | |
e997040e CLG |
877 | } |
878 | ||
879 | static Property pnv_chip_properties[] = { | |
880 | DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), | |
881 | DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), | |
882 | DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), | |
397a79e7 CLG |
883 | DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), |
884 | DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), | |
e997040e CLG |
885 | DEFINE_PROP_END_OF_LIST(), |
886 | }; | |
887 | ||
888 | static void pnv_chip_class_init(ObjectClass *klass, void *data) | |
889 | { | |
890 | DeviceClass *dc = DEVICE_CLASS(klass); | |
891 | ||
9d169fb3 | 892 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
e997040e CLG |
893 | dc->realize = pnv_chip_realize; |
894 | dc->props = pnv_chip_properties; | |
895 | dc->desc = "PowerNV Chip"; | |
896 | } | |
897 | ||
898 | static const TypeInfo pnv_chip_info = { | |
899 | .name = TYPE_PNV_CHIP, | |
900 | .parent = TYPE_SYS_BUS_DEVICE, | |
901 | .class_init = pnv_chip_class_init, | |
967b7523 | 902 | .instance_init = pnv_chip_init, |
e997040e CLG |
903 | .class_size = sizeof(PnvChipClass), |
904 | .abstract = true, | |
905 | }; | |
906 | ||
54f59d78 CLG |
907 | static ICSState *pnv_ics_get(XICSFabric *xi, int irq) |
908 | { | |
909 | PnvMachineState *pnv = POWERNV_MACHINE(xi); | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < pnv->num_chips; i++) { | |
913 | if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { | |
914 | return &pnv->chips[i]->psi.ics; | |
915 | } | |
916 | } | |
917 | return NULL; | |
918 | } | |
919 | ||
920 | static void pnv_ics_resend(XICSFabric *xi) | |
921 | { | |
922 | PnvMachineState *pnv = POWERNV_MACHINE(xi); | |
923 | int i; | |
924 | ||
925 | for (i = 0; i < pnv->num_chips; i++) { | |
926 | ics_resend(&pnv->chips[i]->psi.ics); | |
927 | } | |
928 | } | |
929 | ||
36fc6f08 CLG |
930 | static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) |
931 | { | |
932 | CPUState *cs; | |
933 | ||
934 | CPU_FOREACH(cs) { | |
935 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
936 | CPUPPCState *env = &cpu->env; | |
937 | ||
938 | if (env->spr_cb[SPR_PIR].default_value == pir) { | |
939 | return cpu; | |
940 | } | |
941 | } | |
942 | ||
943 | return NULL; | |
944 | } | |
945 | ||
946 | static ICPState *pnv_icp_get(XICSFabric *xi, int pir) | |
947 | { | |
948 | PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); | |
949 | ||
950 | return cpu ? ICP(cpu->intc) : NULL; | |
951 | } | |
952 | ||
47fea43a CLG |
953 | static void pnv_pic_print_info(InterruptStatsProvider *obj, |
954 | Monitor *mon) | |
955 | { | |
54f59d78 CLG |
956 | PnvMachineState *pnv = POWERNV_MACHINE(obj); |
957 | int i; | |
47fea43a CLG |
958 | CPUState *cs; |
959 | ||
960 | CPU_FOREACH(cs) { | |
961 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
962 | ||
963 | icp_pic_print_info(ICP(cpu->intc), mon); | |
964 | } | |
54f59d78 CLG |
965 | |
966 | for (i = 0; i < pnv->num_chips; i++) { | |
967 | ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); | |
968 | } | |
47fea43a CLG |
969 | } |
970 | ||
e997040e CLG |
971 | static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, |
972 | void *opaque, Error **errp) | |
973 | { | |
974 | visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); | |
975 | } | |
976 | ||
977 | static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, | |
978 | void *opaque, Error **errp) | |
979 | { | |
980 | PnvMachineState *pnv = POWERNV_MACHINE(obj); | |
981 | uint32_t num_chips; | |
982 | Error *local_err = NULL; | |
983 | ||
984 | visit_type_uint32(v, name, &num_chips, &local_err); | |
985 | if (local_err) { | |
986 | error_propagate(errp, local_err); | |
987 | return; | |
988 | } | |
989 | ||
990 | /* | |
991 | * TODO: should we decide on how many chips we can create based | |
992 | * on #cores and Venice vs. Murano vs. Naples chip type etc..., | |
993 | */ | |
994 | if (!is_power_of_2(num_chips) || num_chips > 4) { | |
995 | error_setg(errp, "invalid number of chips: '%d'", num_chips); | |
996 | return; | |
997 | } | |
998 | ||
999 | pnv->num_chips = num_chips; | |
1000 | } | |
1001 | ||
1002 | static void powernv_machine_initfn(Object *obj) | |
1003 | { | |
1004 | PnvMachineState *pnv = POWERNV_MACHINE(obj); | |
1005 | pnv->num_chips = 1; | |
1006 | } | |
1007 | ||
1008 | static void powernv_machine_class_props_init(ObjectClass *oc) | |
1009 | { | |
1010 | object_class_property_add(oc, "num-chips", "uint32_t", | |
1011 | pnv_get_num_chips, pnv_set_num_chips, | |
1012 | NULL, NULL, NULL); | |
1013 | object_class_property_set_description(oc, "num-chips", | |
1014 | "Specifies the number of processor chips", | |
1015 | NULL); | |
9e933f4a BH |
1016 | } |
1017 | ||
1018 | static void powernv_machine_class_init(ObjectClass *oc, void *data) | |
1019 | { | |
1020 | MachineClass *mc = MACHINE_CLASS(oc); | |
36fc6f08 | 1021 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
47fea43a | 1022 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
9e933f4a BH |
1023 | |
1024 | mc->desc = "IBM PowerNV (Non-Virtualized)"; | |
1025 | mc->init = ppc_powernv_init; | |
1026 | mc->reset = ppc_powernv_reset; | |
1027 | mc->max_cpus = MAX_CPUS; | |
1028 | mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for | |
1029 | * storage */ | |
1030 | mc->no_parallel = 1; | |
1031 | mc->default_boot_order = NULL; | |
1032 | mc->default_ram_size = 1 * G_BYTE; | |
36fc6f08 | 1033 | xic->icp_get = pnv_icp_get; |
54f59d78 CLG |
1034 | xic->ics_get = pnv_ics_get; |
1035 | xic->ics_resend = pnv_ics_resend; | |
47fea43a | 1036 | ispc->print_info = pnv_pic_print_info; |
e997040e CLG |
1037 | |
1038 | powernv_machine_class_props_init(oc); | |
9e933f4a BH |
1039 | } |
1040 | ||
1041 | static const TypeInfo powernv_machine_info = { | |
1042 | .name = TYPE_POWERNV_MACHINE, | |
1043 | .parent = TYPE_MACHINE, | |
1044 | .instance_size = sizeof(PnvMachineState), | |
e997040e | 1045 | .instance_init = powernv_machine_initfn, |
9e933f4a | 1046 | .class_init = powernv_machine_class_init, |
36fc6f08 CLG |
1047 | .interfaces = (InterfaceInfo[]) { |
1048 | { TYPE_XICS_FABRIC }, | |
47fea43a | 1049 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
36fc6f08 CLG |
1050 | { }, |
1051 | }, | |
9e933f4a BH |
1052 | }; |
1053 | ||
1054 | static void powernv_machine_register_types(void) | |
1055 | { | |
1056 | type_register_static(&powernv_machine_info); | |
e997040e CLG |
1057 | type_register_static(&pnv_chip_info); |
1058 | type_register_static(&pnv_chip_power8e_info); | |
1059 | type_register_static(&pnv_chip_power8_info); | |
1060 | type_register_static(&pnv_chip_power8nvl_info); | |
1061 | type_register_static(&pnv_chip_power9_info); | |
9e933f4a BH |
1062 | } |
1063 | ||
1064 | type_init(powernv_machine_register_types) |