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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV machine model | |
3 | * | |
4 | * Copyright (c) 2016, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qapi/error.h" | |
22 | #include "sysemu/sysemu.h" | |
23 | #include "sysemu/numa.h" | |
24 | #include "hw/hw.h" | |
25 | #include "target-ppc/cpu.h" | |
26 | #include "qemu/log.h" | |
27 | #include "hw/ppc/fdt.h" | |
28 | #include "hw/ppc/ppc.h" | |
29 | #include "hw/ppc/pnv.h" | |
d2fd9612 | 30 | #include "hw/ppc/pnv_core.h" |
9e933f4a BH |
31 | #include "hw/loader.h" |
32 | #include "exec/address-spaces.h" | |
33 | #include "qemu/cutils.h" | |
e997040e | 34 | #include "qapi/visitor.h" |
9e933f4a BH |
35 | |
36 | #include <libfdt.h> | |
37 | ||
38 | #define FDT_MAX_SIZE 0x00100000 | |
39 | ||
40 | #define FW_FILE_NAME "skiboot.lid" | |
41 | #define FW_LOAD_ADDR 0x0 | |
42 | #define FW_MAX_SIZE 0x00400000 | |
43 | ||
44 | #define KERNEL_LOAD_ADDR 0x20000000 | |
45 | #define INITRD_LOAD_ADDR 0x40000000 | |
46 | ||
47 | /* | |
48 | * On Power Systems E880 (POWER8), the max cpus (threads) should be : | |
49 | * 4 * 4 sockets * 12 cores * 8 threads = 1536 | |
50 | * Let's make it 2^11 | |
51 | */ | |
52 | #define MAX_CPUS 2048 | |
53 | ||
54 | /* | |
55 | * Memory nodes are created by hostboot, one for each range of memory | |
56 | * that has a different "affinity". In practice, it means one range | |
57 | * per chip. | |
58 | */ | |
59 | static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, | |
60 | hwaddr size) | |
61 | { | |
62 | char *mem_name; | |
63 | uint64_t mem_reg_property[2]; | |
64 | int off; | |
65 | ||
66 | mem_reg_property[0] = cpu_to_be64(start); | |
67 | mem_reg_property[1] = cpu_to_be64(size); | |
68 | ||
69 | mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); | |
70 | off = fdt_add_subnode(fdt, 0, mem_name); | |
71 | g_free(mem_name); | |
72 | ||
73 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
74 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
75 | sizeof(mem_reg_property)))); | |
76 | _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); | |
77 | } | |
78 | ||
d2fd9612 CLG |
79 | static int get_cpus_node(void *fdt) |
80 | { | |
81 | int cpus_offset = fdt_path_offset(fdt, "/cpus"); | |
82 | ||
83 | if (cpus_offset < 0) { | |
84 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
85 | "cpus"); | |
86 | if (cpus_offset) { | |
87 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
88 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
89 | } | |
90 | } | |
91 | _FDT(cpus_offset); | |
92 | return cpus_offset; | |
93 | } | |
94 | ||
95 | /* | |
96 | * The PowerNV cores (and threads) need to use real HW ids and not an | |
97 | * incremental index like it has been done on other platforms. This HW | |
98 | * id is stored in the CPU PIR, it is used to create cpu nodes in the | |
99 | * device tree, used in XSCOM to address cores and in interrupt | |
100 | * servers. | |
101 | */ | |
102 | static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) | |
103 | { | |
104 | CPUState *cs = CPU(DEVICE(pc->threads)); | |
105 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
106 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
107 | int smt_threads = ppc_get_compat_smt_threads(cpu); | |
108 | CPUPPCState *env = &cpu->env; | |
109 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
110 | uint32_t servers_prop[smt_threads]; | |
111 | int i; | |
112 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
113 | 0xffffffff, 0xffffffff}; | |
114 | uint32_t tbfreq = PNV_TIMEBASE_FREQ; | |
115 | uint32_t cpufreq = 1000000000; | |
116 | uint32_t page_sizes_prop[64]; | |
117 | size_t page_sizes_prop_size; | |
118 | const uint8_t pa_features[] = { 24, 0, | |
119 | 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, | |
120 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
121 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
122 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
123 | int offset; | |
124 | char *nodename; | |
125 | int cpus_offset = get_cpus_node(fdt); | |
126 | ||
127 | nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); | |
128 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
129 | _FDT(offset); | |
130 | g_free(nodename); | |
131 | ||
132 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); | |
133 | ||
134 | _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); | |
135 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); | |
136 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
137 | ||
138 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
139 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
140 | env->dcache_line_size))); | |
141 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
142 | env->dcache_line_size))); | |
143 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
144 | env->icache_line_size))); | |
145 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
146 | env->icache_line_size))); | |
147 | ||
148 | if (pcc->l1_dcache_size) { | |
149 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
150 | pcc->l1_dcache_size))); | |
151 | } else { | |
152 | error_report("Warning: Unknown L1 dcache size for cpu"); | |
153 | } | |
154 | if (pcc->l1_icache_size) { | |
155 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
156 | pcc->l1_icache_size))); | |
157 | } else { | |
158 | error_report("Warning: Unknown L1 icache size for cpu"); | |
159 | } | |
160 | ||
161 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
162 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
163 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); | |
164 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
165 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
166 | ||
167 | if (env->spr_cb[SPR_PURR].oea_read) { | |
168 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
169 | } | |
170 | ||
171 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
172 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
173 | segs, sizeof(segs)))); | |
174 | } | |
175 | ||
176 | /* Advertise VMX/VSX (vector extensions) if available | |
177 | * 0 / no property == no vector extensions | |
178 | * 1 == VMX / Altivec available | |
179 | * 2 == VSX available */ | |
180 | if (env->insns_flags & PPC_ALTIVEC) { | |
181 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
182 | ||
183 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
184 | } | |
185 | ||
186 | /* Advertise DFP (Decimal Floating Point) if available | |
187 | * 0 / no property == no DFP | |
188 | * 1 == DFP available */ | |
189 | if (env->insns_flags2 & PPC2_DFP) { | |
190 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
191 | } | |
192 | ||
193 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, | |
194 | sizeof(page_sizes_prop)); | |
195 | if (page_sizes_prop_size) { | |
196 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
197 | page_sizes_prop, page_sizes_prop_size))); | |
198 | } | |
199 | ||
200 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", | |
201 | pa_features, sizeof(pa_features)))); | |
202 | ||
203 | if (cpu->cpu_version) { | |
204 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version))); | |
205 | } | |
206 | ||
207 | /* Build interrupt servers properties */ | |
208 | for (i = 0; i < smt_threads; i++) { | |
209 | servers_prop[i] = cpu_to_be32(pc->pir + i); | |
210 | } | |
211 | _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
212 | servers_prop, sizeof(servers_prop)))); | |
213 | } | |
214 | ||
e997040e CLG |
215 | static void powernv_populate_chip(PnvChip *chip, void *fdt) |
216 | { | |
d2fd9612 CLG |
217 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
218 | char *typename = pnv_core_typename(pcc->cpu_model); | |
219 | size_t typesize = object_type_get_instance_size(typename); | |
220 | int i; | |
221 | ||
222 | for (i = 0; i < chip->nr_cores; i++) { | |
223 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
224 | ||
225 | powernv_create_core_node(chip, pnv_core, fdt); | |
226 | } | |
227 | ||
e997040e CLG |
228 | if (chip->ram_size) { |
229 | powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, | |
230 | chip->ram_size); | |
231 | } | |
d2fd9612 | 232 | g_free(typename); |
e997040e CLG |
233 | } |
234 | ||
9e933f4a BH |
235 | static void *powernv_create_fdt(MachineState *machine) |
236 | { | |
237 | const char plat_compat[] = "qemu,powernv\0ibm,powernv"; | |
238 | PnvMachineState *pnv = POWERNV_MACHINE(machine); | |
239 | void *fdt; | |
240 | char *buf; | |
241 | int off; | |
e997040e | 242 | int i; |
9e933f4a BH |
243 | |
244 | fdt = g_malloc0(FDT_MAX_SIZE); | |
245 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
246 | ||
247 | /* Root node */ | |
248 | _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); | |
249 | _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); | |
250 | _FDT((fdt_setprop_string(fdt, 0, "model", | |
251 | "IBM PowerNV (emulated by qemu)"))); | |
252 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, | |
253 | sizeof(plat_compat)))); | |
254 | ||
255 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
256 | _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); | |
257 | if (qemu_uuid_set) { | |
258 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
259 | } | |
260 | g_free(buf); | |
261 | ||
262 | off = fdt_add_subnode(fdt, 0, "chosen"); | |
263 | if (machine->kernel_cmdline) { | |
264 | _FDT((fdt_setprop_string(fdt, off, "bootargs", | |
265 | machine->kernel_cmdline))); | |
266 | } | |
267 | ||
268 | if (pnv->initrd_size) { | |
269 | uint32_t start_prop = cpu_to_be32(pnv->initrd_base); | |
270 | uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); | |
271 | ||
272 | _FDT((fdt_setprop(fdt, off, "linux,initrd-start", | |
273 | &start_prop, sizeof(start_prop)))); | |
274 | _FDT((fdt_setprop(fdt, off, "linux,initrd-end", | |
275 | &end_prop, sizeof(end_prop)))); | |
276 | } | |
277 | ||
e997040e CLG |
278 | /* Populate device tree for each chip */ |
279 | for (i = 0; i < pnv->num_chips; i++) { | |
280 | powernv_populate_chip(pnv->chips[i], fdt); | |
281 | } | |
9e933f4a BH |
282 | return fdt; |
283 | } | |
284 | ||
285 | static void ppc_powernv_reset(void) | |
286 | { | |
287 | MachineState *machine = MACHINE(qdev_get_machine()); | |
288 | void *fdt; | |
289 | ||
290 | qemu_devices_reset(); | |
291 | ||
292 | fdt = powernv_create_fdt(machine); | |
293 | ||
294 | /* Pack resulting tree */ | |
295 | _FDT((fdt_pack(fdt))); | |
296 | ||
297 | cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); | |
298 | } | |
299 | ||
300 | static void ppc_powernv_init(MachineState *machine) | |
301 | { | |
302 | PnvMachineState *pnv = POWERNV_MACHINE(machine); | |
303 | MemoryRegion *ram; | |
304 | char *fw_filename; | |
305 | long fw_size; | |
e997040e CLG |
306 | int i; |
307 | char *chip_typename; | |
9e933f4a BH |
308 | |
309 | /* allocate RAM */ | |
310 | if (machine->ram_size < (1 * G_BYTE)) { | |
311 | error_report("Warning: skiboot may not work with < 1GB of RAM"); | |
312 | } | |
313 | ||
314 | ram = g_new(MemoryRegion, 1); | |
315 | memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", | |
316 | machine->ram_size); | |
317 | memory_region_add_subregion(get_system_memory(), 0, ram); | |
318 | ||
319 | /* load skiboot firmware */ | |
320 | if (bios_name == NULL) { | |
321 | bios_name = FW_FILE_NAME; | |
322 | } | |
323 | ||
324 | fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
325 | ||
326 | fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); | |
327 | if (fw_size < 0) { | |
328 | hw_error("qemu: could not load OPAL '%s'\n", fw_filename); | |
329 | exit(1); | |
330 | } | |
331 | g_free(fw_filename); | |
332 | ||
333 | /* load kernel */ | |
334 | if (machine->kernel_filename) { | |
335 | long kernel_size; | |
336 | ||
337 | kernel_size = load_image_targphys(machine->kernel_filename, | |
338 | KERNEL_LOAD_ADDR, 0x2000000); | |
339 | if (kernel_size < 0) { | |
340 | hw_error("qemu: could not load kernel'%s'\n", | |
341 | machine->kernel_filename); | |
342 | exit(1); | |
343 | } | |
344 | } | |
345 | ||
346 | /* load initrd */ | |
347 | if (machine->initrd_filename) { | |
348 | pnv->initrd_base = INITRD_LOAD_ADDR; | |
349 | pnv->initrd_size = load_image_targphys(machine->initrd_filename, | |
350 | pnv->initrd_base, 0x10000000); /* 128MB max */ | |
351 | if (pnv->initrd_size < 0) { | |
352 | error_report("qemu: could not load initial ram disk '%s'", | |
353 | machine->initrd_filename); | |
354 | exit(1); | |
355 | } | |
356 | } | |
e997040e CLG |
357 | |
358 | /* We need some cpu model to instantiate the PnvChip class */ | |
359 | if (machine->cpu_model == NULL) { | |
360 | machine->cpu_model = "POWER8"; | |
361 | } | |
362 | ||
363 | /* Create the processor chips */ | |
364 | chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model); | |
365 | if (!object_class_by_name(chip_typename)) { | |
366 | error_report("qemu: invalid CPU model '%s' for %s machine", | |
367 | machine->cpu_model, MACHINE_GET_CLASS(machine)->name); | |
368 | exit(1); | |
369 | } | |
370 | ||
371 | pnv->chips = g_new0(PnvChip *, pnv->num_chips); | |
372 | for (i = 0; i < pnv->num_chips; i++) { | |
373 | char chip_name[32]; | |
374 | Object *chip = object_new(chip_typename); | |
375 | ||
376 | pnv->chips[i] = PNV_CHIP(chip); | |
377 | ||
378 | /* TODO: put all the memory in one node on chip 0 until we find a | |
379 | * way to specify different ranges for each chip | |
380 | */ | |
381 | if (i == 0) { | |
382 | object_property_set_int(chip, machine->ram_size, "ram-size", | |
383 | &error_fatal); | |
384 | } | |
385 | ||
386 | snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); | |
387 | object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); | |
388 | object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", | |
389 | &error_fatal); | |
397a79e7 | 390 | object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); |
e997040e CLG |
391 | object_property_set_bool(chip, true, "realized", &error_fatal); |
392 | } | |
393 | g_free(chip_typename); | |
394 | } | |
395 | ||
631adaff CLG |
396 | /* |
397 | * 0:21 Reserved - Read as zeros | |
398 | * 22:24 Chip ID | |
399 | * 25:28 Core number | |
400 | * 29:31 Thread ID | |
401 | */ | |
402 | static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) | |
403 | { | |
404 | return (chip->chip_id << 7) | (core_id << 3); | |
405 | } | |
406 | ||
407 | /* | |
408 | * 0:48 Reserved - Read as zeroes | |
409 | * 49:52 Node ID | |
410 | * 53:55 Chip ID | |
411 | * 56 Reserved - Read as zero | |
412 | * 57:61 Core number | |
413 | * 62:63 Thread ID | |
414 | * | |
415 | * We only care about the lower bits. uint32_t is fine for the moment. | |
416 | */ | |
417 | static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) | |
418 | { | |
419 | return (chip->chip_id << 8) | (core_id << 2); | |
420 | } | |
421 | ||
397a79e7 CLG |
422 | /* Allowed core identifiers on a POWER8 Processor Chip : |
423 | * | |
424 | * <EX0 reserved> | |
425 | * EX1 - Venice only | |
426 | * EX2 - Venice only | |
427 | * EX3 - Venice only | |
428 | * EX4 | |
429 | * EX5 | |
430 | * EX6 | |
431 | * <EX7,8 reserved> <reserved> | |
432 | * EX9 - Venice only | |
433 | * EX10 - Venice only | |
434 | * EX11 - Venice only | |
435 | * EX12 | |
436 | * EX13 | |
437 | * EX14 | |
438 | * <EX15 reserved> | |
439 | */ | |
440 | #define POWER8E_CORE_MASK (0x7070ull) | |
441 | #define POWER8_CORE_MASK (0x7e7eull) | |
442 | ||
443 | /* | |
444 | * POWER9 has 24 cores, ids starting at 0x20 | |
445 | */ | |
446 | #define POWER9_CORE_MASK (0xffffff00000000ull) | |
447 | ||
e997040e CLG |
448 | static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) |
449 | { | |
450 | DeviceClass *dc = DEVICE_CLASS(klass); | |
451 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
452 | ||
453 | k->cpu_model = "POWER8E"; | |
454 | k->chip_type = PNV_CHIP_POWER8E; | |
455 | k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ | |
397a79e7 | 456 | k->cores_mask = POWER8E_CORE_MASK; |
631adaff | 457 | k->core_pir = pnv_chip_core_pir_p8; |
e997040e CLG |
458 | dc->desc = "PowerNV Chip POWER8E"; |
459 | } | |
460 | ||
461 | static const TypeInfo pnv_chip_power8e_info = { | |
462 | .name = TYPE_PNV_CHIP_POWER8E, | |
463 | .parent = TYPE_PNV_CHIP, | |
464 | .instance_size = sizeof(PnvChip), | |
465 | .class_init = pnv_chip_power8e_class_init, | |
466 | }; | |
467 | ||
468 | static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) | |
469 | { | |
470 | DeviceClass *dc = DEVICE_CLASS(klass); | |
471 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
472 | ||
473 | k->cpu_model = "POWER8"; | |
474 | k->chip_type = PNV_CHIP_POWER8; | |
475 | k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ | |
397a79e7 | 476 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 477 | k->core_pir = pnv_chip_core_pir_p8; |
e997040e CLG |
478 | dc->desc = "PowerNV Chip POWER8"; |
479 | } | |
480 | ||
481 | static const TypeInfo pnv_chip_power8_info = { | |
482 | .name = TYPE_PNV_CHIP_POWER8, | |
483 | .parent = TYPE_PNV_CHIP, | |
484 | .instance_size = sizeof(PnvChip), | |
485 | .class_init = pnv_chip_power8_class_init, | |
486 | }; | |
487 | ||
488 | static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) | |
489 | { | |
490 | DeviceClass *dc = DEVICE_CLASS(klass); | |
491 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
492 | ||
493 | k->cpu_model = "POWER8NVL"; | |
494 | k->chip_type = PNV_CHIP_POWER8NVL; | |
495 | k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ | |
397a79e7 | 496 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 497 | k->core_pir = pnv_chip_core_pir_p8; |
e997040e CLG |
498 | dc->desc = "PowerNV Chip POWER8NVL"; |
499 | } | |
500 | ||
501 | static const TypeInfo pnv_chip_power8nvl_info = { | |
502 | .name = TYPE_PNV_CHIP_POWER8NVL, | |
503 | .parent = TYPE_PNV_CHIP, | |
504 | .instance_size = sizeof(PnvChip), | |
505 | .class_init = pnv_chip_power8nvl_class_init, | |
506 | }; | |
507 | ||
508 | static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) | |
509 | { | |
510 | DeviceClass *dc = DEVICE_CLASS(klass); | |
511 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
512 | ||
513 | k->cpu_model = "POWER9"; | |
514 | k->chip_type = PNV_CHIP_POWER9; | |
515 | k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ | |
397a79e7 | 516 | k->cores_mask = POWER9_CORE_MASK; |
631adaff | 517 | k->core_pir = pnv_chip_core_pir_p9; |
e997040e CLG |
518 | dc->desc = "PowerNV Chip POWER9"; |
519 | } | |
520 | ||
521 | static const TypeInfo pnv_chip_power9_info = { | |
522 | .name = TYPE_PNV_CHIP_POWER9, | |
523 | .parent = TYPE_PNV_CHIP, | |
524 | .instance_size = sizeof(PnvChip), | |
525 | .class_init = pnv_chip_power9_class_init, | |
526 | }; | |
527 | ||
397a79e7 CLG |
528 | static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) |
529 | { | |
530 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
531 | int cores_max; | |
532 | ||
533 | /* | |
534 | * No custom mask for this chip, let's use the default one from * | |
535 | * the chip class | |
536 | */ | |
537 | if (!chip->cores_mask) { | |
538 | chip->cores_mask = pcc->cores_mask; | |
539 | } | |
540 | ||
541 | /* filter alien core ids ! some are reserved */ | |
542 | if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { | |
543 | error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", | |
544 | chip->cores_mask); | |
545 | return; | |
546 | } | |
547 | chip->cores_mask &= pcc->cores_mask; | |
548 | ||
549 | /* now that we have a sane layout, let check the number of cores */ | |
550 | cores_max = hweight_long(chip->cores_mask); | |
551 | if (chip->nr_cores > cores_max) { | |
552 | error_setg(errp, "warning: too many cores for chip ! Limit is %d", | |
553 | cores_max); | |
554 | return; | |
555 | } | |
556 | } | |
557 | ||
e997040e CLG |
558 | static void pnv_chip_realize(DeviceState *dev, Error **errp) |
559 | { | |
397a79e7 CLG |
560 | PnvChip *chip = PNV_CHIP(dev); |
561 | Error *error = NULL; | |
d2fd9612 CLG |
562 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
563 | char *typename = pnv_core_typename(pcc->cpu_model); | |
564 | size_t typesize = object_type_get_instance_size(typename); | |
565 | int i, core_hwid; | |
566 | ||
567 | if (!object_class_by_name(typename)) { | |
568 | error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); | |
569 | return; | |
570 | } | |
397a79e7 | 571 | |
d2fd9612 | 572 | /* Cores */ |
397a79e7 CLG |
573 | pnv_chip_core_sanitize(chip, &error); |
574 | if (error) { | |
575 | error_propagate(errp, error); | |
576 | return; | |
577 | } | |
d2fd9612 CLG |
578 | |
579 | chip->cores = g_malloc0(typesize * chip->nr_cores); | |
580 | ||
581 | for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) | |
582 | && (i < chip->nr_cores); core_hwid++) { | |
583 | char core_name[32]; | |
584 | void *pnv_core = chip->cores + i * typesize; | |
585 | ||
586 | if (!(chip->cores_mask & (1ull << core_hwid))) { | |
587 | continue; | |
588 | } | |
589 | ||
590 | object_initialize(pnv_core, typesize, typename); | |
591 | snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); | |
592 | object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), | |
593 | &error_fatal); | |
594 | object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", | |
595 | &error_fatal); | |
596 | object_property_set_int(OBJECT(pnv_core), core_hwid, | |
597 | CPU_CORE_PROP_CORE_ID, &error_fatal); | |
598 | object_property_set_int(OBJECT(pnv_core), | |
599 | pcc->core_pir(chip, core_hwid), | |
600 | "pir", &error_fatal); | |
601 | object_property_set_bool(OBJECT(pnv_core), true, "realized", | |
602 | &error_fatal); | |
603 | object_unref(OBJECT(pnv_core)); | |
604 | i++; | |
605 | } | |
606 | g_free(typename); | |
e997040e CLG |
607 | } |
608 | ||
609 | static Property pnv_chip_properties[] = { | |
610 | DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), | |
611 | DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), | |
612 | DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), | |
397a79e7 CLG |
613 | DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), |
614 | DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), | |
e997040e CLG |
615 | DEFINE_PROP_END_OF_LIST(), |
616 | }; | |
617 | ||
618 | static void pnv_chip_class_init(ObjectClass *klass, void *data) | |
619 | { | |
620 | DeviceClass *dc = DEVICE_CLASS(klass); | |
621 | ||
622 | dc->realize = pnv_chip_realize; | |
623 | dc->props = pnv_chip_properties; | |
624 | dc->desc = "PowerNV Chip"; | |
625 | } | |
626 | ||
627 | static const TypeInfo pnv_chip_info = { | |
628 | .name = TYPE_PNV_CHIP, | |
629 | .parent = TYPE_SYS_BUS_DEVICE, | |
630 | .class_init = pnv_chip_class_init, | |
631 | .class_size = sizeof(PnvChipClass), | |
632 | .abstract = true, | |
633 | }; | |
634 | ||
635 | static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, | |
636 | void *opaque, Error **errp) | |
637 | { | |
638 | visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); | |
639 | } | |
640 | ||
641 | static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, | |
642 | void *opaque, Error **errp) | |
643 | { | |
644 | PnvMachineState *pnv = POWERNV_MACHINE(obj); | |
645 | uint32_t num_chips; | |
646 | Error *local_err = NULL; | |
647 | ||
648 | visit_type_uint32(v, name, &num_chips, &local_err); | |
649 | if (local_err) { | |
650 | error_propagate(errp, local_err); | |
651 | return; | |
652 | } | |
653 | ||
654 | /* | |
655 | * TODO: should we decide on how many chips we can create based | |
656 | * on #cores and Venice vs. Murano vs. Naples chip type etc..., | |
657 | */ | |
658 | if (!is_power_of_2(num_chips) || num_chips > 4) { | |
659 | error_setg(errp, "invalid number of chips: '%d'", num_chips); | |
660 | return; | |
661 | } | |
662 | ||
663 | pnv->num_chips = num_chips; | |
664 | } | |
665 | ||
666 | static void powernv_machine_initfn(Object *obj) | |
667 | { | |
668 | PnvMachineState *pnv = POWERNV_MACHINE(obj); | |
669 | pnv->num_chips = 1; | |
670 | } | |
671 | ||
672 | static void powernv_machine_class_props_init(ObjectClass *oc) | |
673 | { | |
674 | object_class_property_add(oc, "num-chips", "uint32_t", | |
675 | pnv_get_num_chips, pnv_set_num_chips, | |
676 | NULL, NULL, NULL); | |
677 | object_class_property_set_description(oc, "num-chips", | |
678 | "Specifies the number of processor chips", | |
679 | NULL); | |
9e933f4a BH |
680 | } |
681 | ||
682 | static void powernv_machine_class_init(ObjectClass *oc, void *data) | |
683 | { | |
684 | MachineClass *mc = MACHINE_CLASS(oc); | |
685 | ||
686 | mc->desc = "IBM PowerNV (Non-Virtualized)"; | |
687 | mc->init = ppc_powernv_init; | |
688 | mc->reset = ppc_powernv_reset; | |
689 | mc->max_cpus = MAX_CPUS; | |
690 | mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for | |
691 | * storage */ | |
692 | mc->no_parallel = 1; | |
693 | mc->default_boot_order = NULL; | |
694 | mc->default_ram_size = 1 * G_BYTE; | |
e997040e CLG |
695 | |
696 | powernv_machine_class_props_init(oc); | |
9e933f4a BH |
697 | } |
698 | ||
699 | static const TypeInfo powernv_machine_info = { | |
700 | .name = TYPE_POWERNV_MACHINE, | |
701 | .parent = TYPE_MACHINE, | |
702 | .instance_size = sizeof(PnvMachineState), | |
e997040e | 703 | .instance_init = powernv_machine_initfn, |
9e933f4a BH |
704 | .class_init = powernv_machine_class_init, |
705 | }; | |
706 | ||
707 | static void powernv_machine_register_types(void) | |
708 | { | |
709 | type_register_static(&powernv_machine_info); | |
e997040e CLG |
710 | type_register_static(&pnv_chip_info); |
711 | type_register_static(&pnv_chip_power8e_info); | |
712 | type_register_static(&pnv_chip_power8_info); | |
713 | type_register_static(&pnv_chip_power8nvl_info); | |
714 | type_register_static(&pnv_chip_power9_info); | |
9e933f4a BH |
715 | } |
716 | ||
717 | type_init(powernv_machine_register_types) |