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ppc/pnv: Drop "num-chips" machine property
[mirror_qemu.git] / hw / ppc / pnv.c
CommitLineData
9e933f4a
BH		 1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
fc6b3cf9 22#include "qemu/units.h"
9e933f4a
BH		 23#include "qapi/error.h"
24#include "sysemu/sysemu.h"
25#include "sysemu/numa.h"
71e8a915 26#include "sysemu/reset.h"
54d31236 27#include "sysemu/runstate.h"
d2528bdc 28#include "sysemu/cpus.h"
8d409261 29#include "sysemu/device_tree.h"
fcf5ef2a 30#include "target/ppc/cpu.h"
9e933f4a
BH		 31#include "qemu/log.h"
32#include "hw/ppc/fdt.h"
33#include "hw/ppc/ppc.h"
34#include "hw/ppc/pnv.h"
d2fd9612 35#include "hw/ppc/pnv_core.h"
9e933f4a
BH		 36#include "hw/loader.h"
37#include "exec/address-spaces.h"
e997040e 38#include "qapi/visitor.h"
47fea43a
CLG		 39#include "monitor/monitor.h"
40#include "hw/intc/intc.h"
aeaef83d 41#include "hw/ipmi/ipmi.h"
58969eee 42#include "target/ppc/mmu-hash64.h"
9e933f4a 43
36fc6f08 44#include "hw/ppc/xics.h"
a27bd6c7 45#include "hw/qdev-properties.h"
967b7523 46#include "hw/ppc/pnv_xscom.h"
35dde576 47#include "hw/ppc/pnv_pnor.h"
967b7523 48
3495b6b6 49#include "hw/isa/isa.h"
12e9493d 50#include "hw/boards.h"
3495b6b6 51#include "hw/char/serial.h"
bcdb9064 52#include "hw/rtc/mc146818rtc.h"
3495b6b6 53
9e933f4a
BH		 54#include <libfdt.h>
55
b268a616 56#define FDT_MAX_SIZE (1 * MiB)
9e933f4a
BH		 57
58#define FW_FILE_NAME "skiboot.lid"
59#define FW_LOAD_ADDR 0x0
b268a616 60#define FW_MAX_SIZE (4 * MiB)
9e933f4a
BH		 61
62#define KERNEL_LOAD_ADDR 0x20000000
b45b56ba 63#define KERNEL_MAX_SIZE (256 * MiB)
fef592f9 64#define INITRD_LOAD_ADDR 0x60000000
584ea7e7 65#define INITRD_MAX_SIZE (256 * MiB)
9e933f4a 66
40abf43f
IM		 67static const char *pnv_chip_core_typename(const PnvChip *o)
68{
69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
72 const char *core_type = object_class_get_name(object_class_by_name(s));
73 g_free(s);
74 return core_type;
75}
76
9e933f4a
BH		 77/*
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
80 * Let's make it 2^11
81 */
82#define MAX_CPUS 2048
83
84/*
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
87 * per chip.
88 */
b168a138 89static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
9e933f4a
BH		 90{
91 char *mem_name;
92 uint64_t mem_reg_property[2];
93 int off;
94
95 mem_reg_property[0] = cpu_to_be64(start);
96 mem_reg_property[1] = cpu_to_be64(size);
97
98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
99 off = fdt_add_subnode(fdt, 0, mem_name);
100 g_free(mem_name);
101
102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
104 sizeof(mem_reg_property))));
105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
106}
107
d2fd9612
CLG		 108static int get_cpus_node(void *fdt)
109{
110 int cpus_offset = fdt_path_offset(fdt, "/cpus");
111
112 if (cpus_offset < 0) {
a4f3885c 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
d2fd9612
CLG		 114 if (cpus_offset) {
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
117 }
118 }
119 _FDT(cpus_offset);
120 return cpus_offset;
121}
122
123/*
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
128 * servers.
129 */
b168a138 130static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
d2fd9612 131{
08304a86
DG		 132 PowerPCCPU *cpu = pc->threads[0];
133 CPUState *cs = CPU(cpu);
d2fd9612 134 DeviceClass *dc = DEVICE_GET_CLASS(cs);
8bd9530e 135 int smt_threads = CPU_CORE(pc)->nr_threads;
d2fd9612
CLG		 136 CPUPPCState *env = &cpu->env;
137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
138 uint32_t servers_prop[smt_threads];
139 int i;
140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
143 uint32_t cpufreq = 1000000000;
144 uint32_t page_sizes_prop[64];
145 size_t page_sizes_prop_size;
146 const uint8_t pa_features[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
151 int offset;
152 char *nodename;
153 int cpus_offset = get_cpus_node(fdt);
154
155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
156 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
157 _FDT(offset);
158 g_free(nodename);
159
160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
161
162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
168 env->dcache_line_size)));
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
170 env->dcache_line_size)));
171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
172 env->icache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
174 env->icache_line_size)));
175
176 if (pcc->l1_dcache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
178 pcc->l1_dcache_size)));
179 } else {
3dc6f869 180 warn_report("Unknown L1 dcache size for cpu");
d2fd9612
CLG		 181 }
182 if (pcc->l1_icache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
184 pcc->l1_icache_size)));
185 } else {
3dc6f869 186 warn_report("Unknown L1 icache size for cpu");
d2fd9612
CLG		 187 }
188
189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
59b7c1c2
B		 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
192 cpu->hash64_opts->slb_size)));
d2fd9612
CLG		 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
195
196 if (env->spr_cb[SPR_PURR].oea_read) {
197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
198 }
199
58969eee 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
d2fd9612
CLG		 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
202 segs, sizeof(segs))));
203 }
204
59b7c1c2
B		 205 /*
206 * Advertise VMX/VSX (vector extensions) if available
d2fd9612
CLG		 207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
59b7c1c2
B		 209 * 2 == VSX available
210 */
d2fd9612
CLG		 211 if (env->insns_flags & PPC_ALTIVEC) {
212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
213
214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
215 }
216
59b7c1c2
B		 217 /*
218 * Advertise DFP (Decimal Floating Point) if available
d2fd9612 219 * 0 / no property == no DFP
59b7c1c2
B		 220 * 1 == DFP available
221 */
d2fd9612
CLG		 222 if (env->insns_flags2 & PPC2_DFP) {
223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
224 }
225
644a2c99
DG		 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
227 sizeof(page_sizes_prop));
d2fd9612
CLG		 228 if (page_sizes_prop_size) {
229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
230 page_sizes_prop, page_sizes_prop_size)));
231 }
232
233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
234 pa_features, sizeof(pa_features))));
235
d2fd9612
CLG		 236 /* Build interrupt servers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(pc->pir + i);
239 }
240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
241 servers_prop, sizeof(servers_prop))));
242}
243
b168a138
CLG		 244static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
245 uint32_t nr_threads)
bf5615e7
CLG		 246{
247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
248 char *name;
249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange[2], i, rsize;
251 uint64_t *reg;
252 int offset;
253
254 irange[0] = cpu_to_be32(pir);
255 irange[1] = cpu_to_be32(nr_threads);
256
257 rsize = sizeof(uint64_t) * 2 * nr_threads;
258 reg = g_malloc(rsize);
259 for (i = 0; i < nr_threads; i++) {
260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
261 reg[i * 2 + 1] = cpu_to_be64(0x1000);
262 }
263
264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
265 offset = fdt_add_subnode(fdt, 0, name);
266 _FDT(offset);
267 g_free(name);
268
269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
271 _FDT((fdt_setprop_string(fdt, offset, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
275 irange, sizeof(irange))));
276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
278 g_free(reg);
279}
280
eb859a27 281static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
e997040e 282{
c396c58a 283 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
d2fd9612
CLG		 284 int i;
285
3f5b45ca
GK		 286 pnv_dt_xscom(chip, fdt, 0,
287 cpu_to_be64(PNV_XSCOM_BASE(chip)),
c396c58a
GK		 288 cpu_to_be64(PNV_XSCOM_SIZE),
289 compat, sizeof(compat));
967b7523 290
d2fd9612 291 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 292 PnvCore *pnv_core = chip->cores[i];
d2fd9612 293
b168a138 294 pnv_dt_core(chip, pnv_core, fdt);
bf5615e7
CLG		 295
296 /* Interrupt Control Presenters (ICP). One per core. */
b168a138 297 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
d2fd9612
CLG		 298 }
299
e997040e 300 if (chip->ram_size) {
b168a138 301 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
e997040e
CLG		 302 }
303}
304
eb859a27
CLG		 305static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
306{
c396c58a 307 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
eb859a27
CLG		 308 int i;
309
3f5b45ca
GK		 310 pnv_dt_xscom(chip, fdt, 0,
311 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
c396c58a
GK		 312 cpu_to_be64(PNV9_XSCOM_SIZE),
313 compat, sizeof(compat));
eb859a27
CLG		 314
315 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 316 PnvCore *pnv_core = chip->cores[i];
eb859a27
CLG		 317
318 pnv_dt_core(chip, pnv_core, fdt);
319 }
320
321 if (chip->ram_size) {
322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
323 }
15376c66 324
2661f6ab 325 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
eb859a27
CLG		 326}
327
2b548a42
CLG		 328static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
329{
c396c58a 330 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
2b548a42
CLG		 331 int i;
332
3f5b45ca
GK		 333 pnv_dt_xscom(chip, fdt, 0,
334 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
c396c58a
GK		 335 cpu_to_be64(PNV10_XSCOM_SIZE),
336 compat, sizeof(compat));
2b548a42
CLG		 337
338 for (i = 0; i < chip->nr_cores; i++) {
339 PnvCore *pnv_core = chip->cores[i];
340
341 pnv_dt_core(chip, pnv_core, fdt);
342 }
343
344 if (chip->ram_size) {
345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
346 }
2661f6ab
CLG		 347
348 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
2b548a42
CLG		 349}
350
b168a138 351static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
c5ffdcae
CLG		 352{
353 uint32_t io_base = d->ioport_id;
354 uint32_t io_regs[] = {
355 cpu_to_be32(1),
356 cpu_to_be32(io_base),
357 cpu_to_be32(2)
358 };
359 char *name;
360 int node;
361
362 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
363 node = fdt_add_subnode(fdt, lpc_off, name);
364 _FDT(node);
365 g_free(name);
366
367 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
368 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
369}
370
b168a138 371static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cb228f5a
CLG		 372{
373 const char compatible[] = "ns16550\0pnpPNP,501";
374 uint32_t io_base = d->ioport_id;
375 uint32_t io_regs[] = {
376 cpu_to_be32(1),
377 cpu_to_be32(io_base),
378 cpu_to_be32(8)
379 };
380 char *name;
381 int node;
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
390 sizeof(compatible))));
391
392 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
393 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
396 fdt_get_phandle(fdt, lpc_off))));
397
398 /* This is needed by Linux */
399 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
400}
401
b168a138 402static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
04f6c8b2
CLG		 403{
404 const char compatible[] = "bt\0ipmi-bt";
405 uint32_t io_base;
406 uint32_t io_regs[] = {
407 cpu_to_be32(1),
408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
409 cpu_to_be32(3)
410 };
411 uint32_t irq;
412 char *name;
413 int node;
414
415 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
416 io_regs[1] = cpu_to_be32(io_base);
417
418 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
419
420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
421 node = fdt_add_subnode(fdt, lpc_off, name);
422 _FDT(node);
423 g_free(name);
424
7032d92a
CLG		 425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
426 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
427 sizeof(compatible))));
04f6c8b2
CLG		 428
429 /* Mark it as reserved to avoid Linux trying to claim it */
430 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
433 fdt_get_phandle(fdt, lpc_off))));
434}
435
e7a3fee3
CLG		 436typedef struct ForeachPopulateArgs {
437 void *fdt;
438 int offset;
439} ForeachPopulateArgs;
440
b168a138 441static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
e7a3fee3 442{
c5ffdcae
CLG		 443 ForeachPopulateArgs *args = opaque;
444 ISADevice *d = ISA_DEVICE(dev);
445
446 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
b168a138 447 pnv_dt_rtc(d, args->fdt, args->offset);
cb228f5a 448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
b168a138 449 pnv_dt_serial(d, args->fdt, args->offset);
04f6c8b2 450 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
b168a138 451 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
c5ffdcae
CLG		 452 } else {
453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
454 d->ioport_id);
455 }
456
e7a3fee3
CLG		 457 return 0;
458}
459
59b7c1c2
B		 460/*
461 * The default LPC bus of a multichip system is on chip 0. It's
bb7ab95c
CLG		 462 * recognized by the firmware (skiboot) using a "primary" property.
463 */
464static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
465{
64d011d5 466 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
e7a3fee3
CLG		 467 ForeachPopulateArgs args = {
468 .fdt = fdt,
bb7ab95c 469 .offset = isa_offset,
e7a3fee3 470 };
f47a08d1 471 uint32_t phandle;
e7a3fee3 472
bb7ab95c
CLG		 473 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
474
f47a08d1
CLG		 475 phandle = qemu_fdt_alloc_phandle(fdt);
476 assert(phandle > 0);
477 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
478
59b7c1c2
B		 479 /*
480 * ISA devices are not necessarily parented to the ISA bus so we
481 * can not use object_child_foreach()
482 */
bb7ab95c
CLG		 483 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
484 &args);
e7a3fee3
CLG		 485}
486
7a90c6a1 487static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
e5694793
CLG		 488{
489 int off;
490
491 off = fdt_add_subnode(fdt, 0, "ibm,opal");
492 off = fdt_add_subnode(fdt, off, "power-mgt");
493
494 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
495}
496
b168a138 497static void *pnv_dt_create(MachineState *machine)
9e933f4a 498{
d76f2da7 499 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
b168a138 500 PnvMachineState *pnv = PNV_MACHINE(machine);
9e933f4a
BH		 501 void *fdt;
502 char *buf;
503 int off;
e997040e 504 int i;
9e933f4a
BH		 505
506 fdt = g_malloc0(FDT_MAX_SIZE);
507 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
508
ccb099b3
CLG		 509 /* /qemu node */
510 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
511
9e933f4a
BH		 512 /* Root node */
513 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
514 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
515 _FDT((fdt_setprop_string(fdt, 0, "model",
516 "IBM PowerNV (emulated by qemu)")));
d76f2da7 517 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
9e933f4a
BH		 518
519 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
521 if (qemu_uuid_set) {
522 _FDT((fdt_property_string(fdt, "system-id", buf)));
523 }
524 g_free(buf);
525
526 off = fdt_add_subnode(fdt, 0, "chosen");
527 if (machine->kernel_cmdline) {
528 _FDT((fdt_setprop_string(fdt, off, "bootargs",
529 machine->kernel_cmdline)));
530 }
531
532 if (pnv->initrd_size) {
533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
535
536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
537 &start_prop, sizeof(start_prop))));
538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
539 &end_prop, sizeof(end_prop))));
540 }
541
e997040e
CLG		 542 /* Populate device tree for each chip */
543 for (i = 0; i < pnv->num_chips; i++) {
eb859a27 544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
e997040e 545 }
e7a3fee3
CLG		 546
547 /* Populate ISA devices on chip 0 */
bb7ab95c 548 pnv_dt_isa(pnv, fdt);
aeaef83d
CLG		 549
550 if (pnv->bmc) {
b168a138 551 pnv_dt_bmc_sensors(pnv->bmc, fdt);
aeaef83d
CLG		 552 }
553
7a90c6a1
GK		 554 /* Create an extra node for power management on machines that support it */
555 if (pmc->dt_power_mgt) {
556 pmc->dt_power_mgt(pnv, fdt);
e5694793
CLG		 557 }
558
9e933f4a
BH		 559 return fdt;
560}
561
bce0b691
CLG		 562static void pnv_powerdown_notify(Notifier *n, void *opaque)
563{
8f06e370 564 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
bce0b691
CLG		 565
566 if (pnv->bmc) {
567 pnv_bmc_powerdown(pnv->bmc);
568 }
569}
570
a0628599 571static void pnv_reset(MachineState *machine)
9e933f4a 572{
9e933f4a
BH		 573 void *fdt;
574
575 qemu_devices_reset();
576
b168a138 577 fdt = pnv_dt_create(machine);
9e933f4a
BH		 578
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt)));
581
8d409261 582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
9e933f4a
BH		 583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
584}
585
04026890 586static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
3495b6b6 587{
77864267
CLG		 588 Pnv8Chip *chip8 = PNV8_CHIP(chip);
589 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
04026890 590}
3495b6b6 591
04026890
CLG		 592static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
593{
77864267
CLG		 594 Pnv8Chip *chip8 = PNV8_CHIP(chip);
595 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
04026890 596}
3495b6b6 597
04026890
CLG		 598static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
599{
15376c66
CLG		 600 Pnv9Chip *chip9 = PNV9_CHIP(chip);
601 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
04026890 602}
3495b6b6 603
2b548a42
CLG		 604static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
605{
2661f6ab
CLG		 606 Pnv10Chip *chip10 = PNV10_CHIP(chip);
607 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
2b548a42
CLG		 608}
609
04026890
CLG		 610static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
611{
612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
3495b6b6
CLG		 613}
614
d8e4aad5
CLG		 615static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
616{
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618
619 ics_pic_print_info(&chip8->psi.ics, mon);
620}
621
622static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
623{
624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625
626 pnv_xive_pic_print_info(&chip9->xive, mon);
c38536bc 627 pnv_psi_pic_print_info(&chip9->psi, mon);
d8e4aad5
CLG		 628}
629
c4b2c40c
GK		 630static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
631 uint32_t core_id)
632{
633 return PNV_XSCOM_EX_BASE(core_id);
634}
635
636static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
637 uint32_t core_id)
638{
639 return PNV9_XSCOM_EC_BASE(core_id);
640}
641
642static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
643 uint32_t core_id)
644{
645 return PNV10_XSCOM_EC_BASE(core_id);
646}
647
f30c843c
CLG		 648static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
649{
650 PowerPCCPUClass *ppc_default =
651 POWERPC_CPU_CLASS(object_class_by_name(default_type));
652 PowerPCCPUClass *ppc =
653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
654
655 return ppc_default->pvr_match(ppc_default, ppc->pvr);
656}
657
e2392d43
CLG		 658static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
659{
660 Object *obj;
661
662 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
663 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
664 object_property_set_int(obj, irq, "irq", &error_fatal);
665 object_property_set_bool(obj, true, "realized", &error_fatal);
666}
667
2b548a42
CLG		 668static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
669{
8b50ce85
CLG		 670 Pnv10Chip *chip10 = PNV10_CHIP(chip);
671
672 pnv_psi_pic_print_info(&chip10->psi, mon);
2b548a42
CLG		 673}
674
b168a138 675static void pnv_init(MachineState *machine)
9e933f4a 676{
b168a138 677 PnvMachineState *pnv = PNV_MACHINE(machine);
f30c843c 678 MachineClass *mc = MACHINE_GET_CLASS(machine);
9e933f4a
BH		 679 MemoryRegion *ram;
680 char *fw_filename;
681 long fw_size;
e997040e
CLG		 682 int i;
683 char *chip_typename;
35dde576
CLG		 684 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
685 DeviceState *dev;
9e933f4a
BH		 686
687 /* allocate RAM */
d23b6caa 688 if (machine->ram_size < (1 * GiB)) {
3dc6f869 689 warn_report("skiboot may not work with < 1GB of RAM");
9e933f4a
BH		 690 }
691
692 ram = g_new(MemoryRegion, 1);
b168a138 693 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
9e933f4a
BH		 694 machine->ram_size);
695 memory_region_add_subregion(get_system_memory(), 0, ram);
696
35dde576
CLG		 697 /*
698 * Create our simple PNOR device
699 */
700 dev = qdev_create(NULL, TYPE_PNV_PNOR);
701 if (pnor) {
702 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
703 &error_abort);
704 }
705 qdev_init_nofail(dev);
706 pnv->pnor = PNV_PNOR(dev);
707
9e933f4a
BH		 708 /* load skiboot firmware */
709 if (bios_name == NULL) {
710 bios_name = FW_FILE_NAME;
711 }
712
713 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
15fcedb2
CLG		 714 if (!fw_filename) {
715 error_report("Could not find OPAL firmware '%s'", bios_name);
716 exit(1);
717 }
9e933f4a
BH		 718
719 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
720 if (fw_size < 0) {
15fcedb2 721 error_report("Could not load OPAL firmware '%s'", fw_filename);
9e933f4a
BH		 722 exit(1);
723 }
724 g_free(fw_filename);
725
726 /* load kernel */
727 if (machine->kernel_filename) {
728 long kernel_size;
729
730 kernel_size = load_image_targphys(machine->kernel_filename,
b45b56ba 731 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
9e933f4a 732 if (kernel_size < 0) {
802fc7ab 733 error_report("Could not load kernel '%s'",
7c6e8797 734 machine->kernel_filename);
9e933f4a
BH		 735 exit(1);
736 }
737 }
738
739 /* load initrd */
740 if (machine->initrd_filename) {
741 pnv->initrd_base = INITRD_LOAD_ADDR;
742 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
584ea7e7 743 pnv->initrd_base, INITRD_MAX_SIZE);
9e933f4a 744 if (pnv->initrd_size < 0) {
802fc7ab 745 error_report("Could not load initial ram disk '%s'",
9e933f4a
BH		 746 machine->initrd_filename);
747 exit(1);
748 }
749 }
e997040e 750
f30c843c
CLG		 751 /*
752 * Check compatibility of the specified CPU with the machine
753 * default.
754 */
755 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
756 error_report("invalid CPU model '%s' for %s machine",
757 machine->cpu_type, mc->name);
758 exit(1);
759 }
760
e997040e 761 /* Create the processor chips */
4a12c699 762 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
7fd544d8 763 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
4a12c699 764 i, machine->cpu_type);
e997040e 765 if (!object_class_by_name(chip_typename)) {
f30c843c
CLG		 766 error_report("invalid chip model '%.*s' for %s machine",
767 i, machine->cpu_type, mc->name);
e997040e
CLG		 768 exit(1);
769 }
770
e44acde2
GK		 771 pnv->num_chips =
772 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
773 /*
774 * TODO: should we decide on how many chips we can create based
775 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
776 */
777 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
778 error_report("invalid number of chips: '%d'", pnv->num_chips);
779 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
780 exit(1);
781 }
782
e997040e
CLG		 783 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
784 for (i = 0; i < pnv->num_chips; i++) {
785 char chip_name[32];
786 Object *chip = object_new(chip_typename);
787
788 pnv->chips[i] = PNV_CHIP(chip);
789
59b7c1c2
B		 790 /*
791 * TODO: put all the memory in one node on chip 0 until we find a
e997040e
CLG		 792 * way to specify different ranges for each chip
793 */
794 if (i == 0) {
795 object_property_set_int(chip, machine->ram_size, "ram-size",
796 &error_fatal);
797 }
798
799 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
800 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
801 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
802 &error_fatal);
fe6b6346
LX		 803 object_property_set_int(chip, machine->smp.cores,
804 "nr-cores", &error_fatal);
e997040e
CLG		 805 object_property_set_bool(chip, true, "realized", &error_fatal);
806 }
807 g_free(chip_typename);
3495b6b6 808
e2392d43
CLG		 809 /* Create the machine BMC simulator */
810 pnv->bmc = pnv_bmc_create();
811
3495b6b6 812 /* Instantiate ISA bus on chip 0 */
04026890 813 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
3495b6b6
CLG		 814
815 /* Create serial port */
def337ff 816 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
3495b6b6
CLG		 817
818 /* Create an RTC ISA device too */
6c646a11 819 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
bce0b691 820
e2392d43
CLG		 821 /* Create the IPMI BT device for communication with the BMC */
822 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
823
59b7c1c2
B		 824 /*
825 * OpenPOWER systems use a IPMI SEL Event message to notify the
826 * host to powerdown
827 */
bce0b691
CLG		 828 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
829 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
e997040e
CLG		 830}
831
631adaff
CLG		 832/*
833 * 0:21 Reserved - Read as zeros
834 * 22:24 Chip ID
835 * 25:28 Core number
836 * 29:31 Thread ID
837 */
838static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
839{
840 return (chip->chip_id << 7) | (core_id << 3);
841}
842
8fa1f4ef
CLG		 843static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
844 Error **errp)
d35aefa9 845{
8fa1f4ef
CLG		 846 Error *local_err = NULL;
847 Object *obj;
8907fc25 848 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8fa1f4ef
CLG		 849
850 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
851 &local_err);
852 if (local_err) {
853 error_propagate(errp, local_err);
854 return;
855 }
856
956b8f46 857 pnv_cpu->intc = obj;
d35aefa9
CLG		 858}
859
0990ce6a 860
d49e8a9b
CLG		 861static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
862{
863 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
864
865 icp_reset(ICP(pnv_cpu->intc));
866}
867
0990ce6a
GK		 868static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
869{
870 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
871
872 icp_destroy(ICP(pnv_cpu->intc));
873 pnv_cpu->intc = NULL;
874}
875
85913070
GK		 876static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
877 Monitor *mon)
878{
879 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
880}
881
631adaff
CLG		 882/*
883 * 0:48 Reserved - Read as zeroes
884 * 49:52 Node ID
885 * 53:55 Chip ID
886 * 56 Reserved - Read as zero
887 * 57:61 Core number
888 * 62:63 Thread ID
889 *
890 * We only care about the lower bits. uint32_t is fine for the moment.
891 */
892static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
893{
894 return (chip->chip_id << 8) | (core_id << 2);
895}
896
2b548a42
CLG		 897static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
898{
899 return (chip->chip_id << 8) | (core_id << 2);
900}
901
8fa1f4ef
CLG		 902static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
903 Error **errp)
d35aefa9 904{
2dfa91a2
CLG		 905 Pnv9Chip *chip9 = PNV9_CHIP(chip);
906 Error *local_err = NULL;
907 Object *obj;
908 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
909
910 /*
911 * The core creates its interrupt presenter but the XIVE interrupt
912 * controller object is initialized afterwards. Hopefully, it's
913 * only used at runtime.
914 */
26aa5b1e 915 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
2dfa91a2
CLG		 916 if (local_err) {
917 error_propagate(errp, local_err);
918 return;
919 }
920
921 pnv_cpu->intc = obj;
d35aefa9
CLG		 922}
923
d49e8a9b
CLG		 924static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
925{
926 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
927
928 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
929}
930
0990ce6a
GK		 931static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
932{
933 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
934
935 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
936 pnv_cpu->intc = NULL;
937}
938
85913070
GK		 939static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
940 Monitor *mon)
941{
942 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
943}
944
2b548a42
CLG		 945static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
946 Error **errp)
947{
948 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
949
950 /* Will be defined when the interrupt controller is */
951 pnv_cpu->intc = NULL;
952}
953
954static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
955{
956 ;
957}
958
959static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
960{
961 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
962
963 pnv_cpu->intc = NULL;
964}
965
85913070
GK		 966static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
967 Monitor *mon)
968{
969}
970
59b7c1c2
B		 971/*
972 * Allowed core identifiers on a POWER8 Processor Chip :
397a79e7
CLG		 973 *
974 * <EX0 reserved>
975 * EX1 - Venice only
976 * EX2 - Venice only
977 * EX3 - Venice only
978 * EX4
979 * EX5
980 * EX6
981 * <EX7,8 reserved> <reserved>
982 * EX9 - Venice only
983 * EX10 - Venice only
984 * EX11 - Venice only
985 * EX12
986 * EX13
987 * EX14
988 * <EX15 reserved>
989 */
990#define POWER8E_CORE_MASK (0x7070ull)
991#define POWER8_CORE_MASK (0x7e7eull)
992
993/*
09279d7e 994 * POWER9 has 24 cores, ids starting at 0x0
397a79e7 995 */
09279d7e 996#define POWER9_CORE_MASK (0xffffffffffffffull)
397a79e7 997
2b548a42
CLG		 998
999#define POWER10_CORE_MASK (0xffffffffffffffull)
1000
77864267
CLG		 1001static void pnv_chip_power8_instance_init(Object *obj)
1002{
1003 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1004
f6d4dca8 1005 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
ae856055 1006 TYPE_PNV8_PSI, &error_abort, NULL);
77864267
CLG		 1007 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
1008 OBJECT(qdev_get_machine()), &error_abort);
1009
f6d4dca8 1010 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
82514be2 1011 TYPE_PNV8_LPC, &error_abort, NULL);
77864267 1012
f6d4dca8 1013 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
3233838c 1014 TYPE_PNV8_OCC, &error_abort, NULL);
3887d241
B		 1015
1016 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
1017 TYPE_PNV8_HOMER, &error_abort, NULL);
77864267
CLG		 1018}
1019
1020static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1021 {
1022 PnvChip *chip = PNV_CHIP(chip8);
1023 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
77864267
CLG		 1024 int i, j;
1025 char *name;
1026 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
1027
1028 name = g_strdup_printf("icp-%x", chip->chip_id);
1029 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1030 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1031 g_free(name);
1032
1033 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1034
1035 /* Map the ICP registers for each thread */
1036 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 1037 PnvCore *pnv_core = chip->cores[i];
77864267
CLG		 1038 int core_hwid = CPU_CORE(pnv_core)->core_id;
1039
1040 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1041 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1042 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
1043
1044 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1045 &icp->mmio);
1046 }
1047 }
1048}
1049
1050static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1051{
1052 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1053 PnvChip *chip = PNV_CHIP(dev);
1054 Pnv8Chip *chip8 = PNV8_CHIP(dev);
ae856055 1055 Pnv8Psi *psi8 = &chip8->psi;
77864267
CLG		 1056 Error *local_err = NULL;
1057
709044fd
CLG		 1058 /* XSCOM bridge is first */
1059 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1060 if (local_err) {
1061 error_propagate(errp, local_err);
1062 return;
1063 }
1064 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1065
77864267
CLG		 1066 pcc->parent_realize(dev, &local_err);
1067 if (local_err) {
1068 error_propagate(errp, local_err);
1069 return;
1070 }
1071
1072 /* Processor Service Interface (PSI) Host Bridge */
1073 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1074 "bar", &error_fatal);
1075 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1076 if (local_err) {
1077 error_propagate(errp, local_err);
1078 return;
1079 }
ae856055
CLG		 1080 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1081 &PNV_PSI(psi8)->xscom_regs);
77864267
CLG		 1082
1083 /* Create LPC controller */
b63f3893
GK		 1084 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1085 &error_abort);
77864267
CLG		 1086 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1087 &error_fatal);
1088 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1089
64d011d5
CLG		 1090 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1091 (uint64_t) PNV_XSCOM_BASE(chip),
1092 PNV_XSCOM_LPC_BASE);
1093
59b7c1c2
B		 1094 /*
1095 * Interrupt Management Area. This is the memory region holding
1096 * all the Interrupt Control Presenter (ICP) registers
1097 */
77864267
CLG		 1098 pnv_chip_icp_realize(chip8, &local_err);
1099 if (local_err) {
1100 error_propagate(errp, local_err);
1101 return;
1102 }
1103
1104 /* Create the simplified OCC model */
ee3d2713
GK		 1105 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1106 &error_abort);
77864267
CLG		 1107 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1108 if (local_err) {
1109 error_propagate(errp, local_err);
1110 return;
1111 }
1112 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
f3db8266
B		 1113
1114 /* OCC SRAM model */
3a1b70b6 1115 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
f3db8266 1116 &chip8->occ.sram_regs);
3887d241
B		 1117
1118 /* HOMER */
f2582acf
GK		 1119 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1120 &error_abort);
3887d241
B		 1121 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1122 &local_err);
1123 if (local_err) {
1124 error_propagate(errp, local_err);
1125 return;
1126 }
8f092316
CLG		 1127 /* Homer Xscom region */
1128 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1129
1130 /* Homer mmio region */
3887d241
B		 1131 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1132 &chip8->homer.regs);
77864267
CLG		 1133}
1134
70c059e9
GK		 1135static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1136{
1137 addr &= (PNV_XSCOM_SIZE - 1);
1138 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1139}
1140
e997040e
CLG		 1141static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1142{
1143 DeviceClass *dc = DEVICE_CLASS(klass);
1144 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1145
e997040e 1146 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
397a79e7 1147 k->cores_mask = POWER8E_CORE_MASK;
631adaff 1148 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1149 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1150 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1151 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1152 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1153 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1154 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1155 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1156 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1157 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1158 dc->desc = "PowerNV Chip POWER8E";
77864267
CLG		 1159
1160 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1161 &k->parent_realize);
e997040e
CLG		 1162}
1163
e997040e
CLG		 1164static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1165{
1166 DeviceClass *dc = DEVICE_CLASS(klass);
1167 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1168
e997040e 1169 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
397a79e7 1170 k->cores_mask = POWER8_CORE_MASK;
631adaff 1171 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1172 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1173 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1174 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1175 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1176 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1177 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1178 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1179 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1180 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1181 dc->desc = "PowerNV Chip POWER8";
77864267
CLG		 1182
1183 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1184 &k->parent_realize);
e997040e
CLG		 1185}
1186
e997040e
CLG		 1187static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1188{
1189 DeviceClass *dc = DEVICE_CLASS(klass);
1190 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1191
e997040e 1192 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
397a79e7 1193 k->cores_mask = POWER8_CORE_MASK;
631adaff 1194 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1195 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1196 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1197 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1198 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1199 k->isa_create = pnv_chip_power8nvl_isa_create;
eb859a27 1200 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1201 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1202 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1203 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1204 dc->desc = "PowerNV Chip POWER8NVL";
77864267
CLG		 1205
1206 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1207 &k->parent_realize);
1208}
1209
1210static void pnv_chip_power9_instance_init(Object *obj)
1211{
2dfa91a2
CLG		 1212 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1213
1214 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1215 TYPE_PNV_XIVE, &error_abort, NULL);
c38536bc
CLG		 1216
1217 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1218 TYPE_PNV9_PSI, &error_abort, NULL);
15376c66
CLG		 1219
1220 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1221 TYPE_PNV9_LPC, &error_abort, NULL);
6598a70d
CLG		 1222
1223 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1224 TYPE_PNV9_OCC, &error_abort, NULL);
3887d241
B		 1225
1226 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1227 TYPE_PNV9_HOMER, &error_abort, NULL);
77864267
CLG		 1228}
1229
5dad902c
CLG		 1230static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1231{
1232 PnvChip *chip = PNV_CHIP(chip9);
5dad902c
CLG		 1233 int i;
1234
1235 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1236 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1237
1238 for (i = 0; i < chip9->nr_quads; i++) {
1239 char eq_name[32];
1240 PnvQuad *eq = &chip9->quads[i];
4fa28f23 1241 PnvCore *pnv_core = chip->cores[i * 4];
5dad902c
CLG		 1242 int core_id = CPU_CORE(pnv_core)->core_id;
1243
5dad902c 1244 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
bc4c406c
PMD		 1245 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1246 TYPE_PNV_QUAD, &error_fatal, NULL);
5dad902c 1247
5dad902c
CLG		 1248 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1249 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
5dad902c
CLG		 1250
1251 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1252 &eq->xscom_regs);
1253 }
1254}
1255
77864267
CLG		 1256static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1257{
1258 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2dfa91a2
CLG		 1259 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1260 PnvChip *chip = PNV_CHIP(dev);
c38536bc 1261 Pnv9Psi *psi9 = &chip9->psi;
77864267
CLG		 1262 Error *local_err = NULL;
1263
709044fd
CLG		 1264 /* XSCOM bridge is first */
1265 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1266 if (local_err) {
1267 error_propagate(errp, local_err);
1268 return;
1269 }
1270 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1271
77864267
CLG		 1272 pcc->parent_realize(dev, &local_err);
1273 if (local_err) {
1274 error_propagate(errp, local_err);
1275 return;
1276 }
2dfa91a2 1277
5dad902c
CLG		 1278 pnv_chip_quad_realize(chip9, &local_err);
1279 if (local_err) {
1280 error_propagate(errp, local_err);
1281 return;
1282 }
1283
2dfa91a2
CLG		 1284 /* XIVE interrupt controller (POWER9) */
1285 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1286 "ic-bar", &error_fatal);
1287 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1288 "vc-bar", &error_fatal);
1289 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1290 "pc-bar", &error_fatal);
1291 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1292 "tm-bar", &error_fatal);
7ae54cc3
GK		 1293 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1294 &error_abort);
2dfa91a2
CLG		 1295 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1296 &local_err);
1297 if (local_err) {
1298 error_propagate(errp, local_err);
1299 return;
1300 }
1301 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1302 &chip9->xive.xscom_regs);
c38536bc
CLG		 1303
1304 /* Processor Service Interface (PSI) Host Bridge */
1305 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1306 "bar", &error_fatal);
1307 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1308 if (local_err) {
1309 error_propagate(errp, local_err);
1310 return;
1311 }
1312 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1313 &PNV_PSI(psi9)->xscom_regs);
15376c66
CLG		 1314
1315 /* LPC */
b63f3893
GK		 1316 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1317 &error_abort);
15376c66
CLG		 1318 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1319 if (local_err) {
1320 error_propagate(errp, local_err);
1321 return;
1322 }
1323 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1324 &chip9->lpc.xscom_regs);
1325
1326 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1327 (uint64_t) PNV9_LPCM_BASE(chip));
6598a70d
CLG		 1328
1329 /* Create the simplified OCC model */
ee3d2713
GK		 1330 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1331 &error_abort);
6598a70d
CLG		 1332 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1333 if (local_err) {
1334 error_propagate(errp, local_err);
1335 return;
1336 }
1337 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
f3db8266
B		 1338
1339 /* OCC SRAM model */
3a1b70b6 1340 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
f3db8266 1341 &chip9->occ.sram_regs);
3887d241
B		 1342
1343 /* HOMER */
f2582acf
GK		 1344 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1345 &error_abort);
3887d241
B		 1346 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1347 &local_err);
1348 if (local_err) {
1349 error_propagate(errp, local_err);
1350 return;
1351 }
8f092316
CLG		 1352 /* Homer Xscom region */
1353 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1354
1355 /* Homer mmio region */
3887d241
B		 1356 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1357 &chip9->homer.regs);
e997040e
CLG		 1358}
1359
70c059e9
GK		 1360static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1361{
1362 addr &= (PNV9_XSCOM_SIZE - 1);
1363 return addr >> 3;
1364}
1365
e997040e
CLG		 1366static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1367{
1368 DeviceClass *dc = DEVICE_CLASS(klass);
1369 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1370
83028a2b 1371 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
397a79e7 1372 k->cores_mask = POWER9_CORE_MASK;
631adaff 1373 k->core_pir = pnv_chip_core_pir_p9;
d35aefa9 1374 k->intc_create = pnv_chip_power9_intc_create;
d49e8a9b 1375 k->intc_reset = pnv_chip_power9_intc_reset;
0990ce6a 1376 k->intc_destroy = pnv_chip_power9_intc_destroy;
85913070 1377 k->intc_print_info = pnv_chip_power9_intc_print_info;
04026890 1378 k->isa_create = pnv_chip_power9_isa_create;
eb859a27 1379 k->dt_populate = pnv_chip_power9_dt_populate;
d8e4aad5 1380 k->pic_print_info = pnv_chip_power9_pic_print_info;
c4b2c40c 1381 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
70c059e9 1382 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
e997040e 1383 dc->desc = "PowerNV Chip POWER9";
77864267
CLG		 1384
1385 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1386 &k->parent_realize);
e997040e
CLG		 1387}
1388
2b548a42
CLG		 1389static void pnv_chip_power10_instance_init(Object *obj)
1390{
8b50ce85
CLG		 1391 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1392
1393 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1394 TYPE_PNV10_PSI, &error_abort, NULL);
2661f6ab
CLG		 1395 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1396 TYPE_PNV10_LPC, &error_abort, NULL);
2b548a42
CLG		 1397}
1398
1399static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1400{
1401 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1402 PnvChip *chip = PNV_CHIP(dev);
8b50ce85 1403 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2b548a42
CLG		 1404 Error *local_err = NULL;
1405
1406 /* XSCOM bridge is first */
1407 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1408 if (local_err) {
1409 error_propagate(errp, local_err);
1410 return;
1411 }
1412 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1413
1414 pcc->parent_realize(dev, &local_err);
1415 if (local_err) {
1416 error_propagate(errp, local_err);
1417 return;
1418 }
8b50ce85
CLG		 1419
1420 /* Processor Service Interface (PSI) Host Bridge */
1421 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1422 "bar", &error_fatal);
1423 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1424 &local_err);
1425 if (local_err) {
1426 error_propagate(errp, local_err);
1427 return;
1428 }
1429 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1430 &PNV_PSI(&chip10->psi)->xscom_regs);
2661f6ab
CLG		 1431
1432 /* LPC */
1433 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1434 &error_abort);
1435 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1436 &local_err);
1437 if (local_err) {
1438 error_propagate(errp, local_err);
1439 return;
1440 }
1441 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1442 &chip10->lpc.xscom_regs);
1443
1444 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1445 (uint64_t) PNV10_LPCM_BASE(chip));
2b548a42
CLG		 1446}
1447
70c059e9
GK		 1448static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1449{
1450 addr &= (PNV10_XSCOM_SIZE - 1);
1451 return addr >> 3;
1452}
1453
2b548a42
CLG		 1454static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1455{
1456 DeviceClass *dc = DEVICE_CLASS(klass);
1457 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1458
2b548a42
CLG		 1459 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1460 k->cores_mask = POWER10_CORE_MASK;
1461 k->core_pir = pnv_chip_core_pir_p10;
1462 k->intc_create = pnv_chip_power10_intc_create;
1463 k->intc_reset = pnv_chip_power10_intc_reset;
1464 k->intc_destroy = pnv_chip_power10_intc_destroy;
85913070 1465 k->intc_print_info = pnv_chip_power10_intc_print_info;
2b548a42
CLG		 1466 k->isa_create = pnv_chip_power10_isa_create;
1467 k->dt_populate = pnv_chip_power10_dt_populate;
1468 k->pic_print_info = pnv_chip_power10_pic_print_info;
c4b2c40c 1469 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
70c059e9 1470 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2b548a42
CLG		 1471 dc->desc = "PowerNV Chip POWER10";
1472
1473 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1474 &k->parent_realize);
1475}
1476
397a79e7
CLG		 1477static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1478{
1479 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1480 int cores_max;
1481
1482 /*
1483 * No custom mask for this chip, let's use the default one from *
1484 * the chip class
1485 */
1486 if (!chip->cores_mask) {
1487 chip->cores_mask = pcc->cores_mask;
1488 }
1489
1490 /* filter alien core ids ! some are reserved */
1491 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1492 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1493 chip->cores_mask);
1494 return;
1495 }
1496 chip->cores_mask &= pcc->cores_mask;
1497
1498 /* now that we have a sane layout, let check the number of cores */
27d9ffd4 1499 cores_max = ctpop64(chip->cores_mask);
397a79e7
CLG		 1500 if (chip->nr_cores > cores_max) {
1501 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1502 cores_max);
1503 return;
1504 }
1505}
1506
51c04728 1507static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
e997040e 1508{
fe6b6346 1509 MachineState *ms = MACHINE(qdev_get_machine());
397a79e7 1510 Error *error = NULL;
d2fd9612 1511 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
40abf43f 1512 const char *typename = pnv_chip_core_typename(chip);
d2fd9612
CLG		 1513 int i, core_hwid;
1514
1515 if (!object_class_by_name(typename)) {
1516 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1517 return;
1518 }
397a79e7 1519
d2fd9612 1520 /* Cores */
397a79e7
CLG		 1521 pnv_chip_core_sanitize(chip, &error);
1522 if (error) {
1523 error_propagate(errp, error);
1524 return;
1525 }
d2fd9612 1526
4fa28f23 1527 chip->cores = g_new0(PnvCore *, chip->nr_cores);
d2fd9612
CLG		 1528
1529 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1530 && (i < chip->nr_cores); core_hwid++) {
1531 char core_name[32];
4fa28f23 1532 PnvCore *pnv_core;
c035851a 1533 uint64_t xscom_core_base;
d2fd9612
CLG		 1534
1535 if (!(chip->cores_mask & (1ull << core_hwid))) {
1536 continue;
1537 }
1538
4fa28f23
GK		 1539 pnv_core = PNV_CORE(object_new(typename));
1540
d2fd9612 1541 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
4fa28f23
GK		 1542 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1543 &error_abort);
1544 chip->cores[i] = pnv_core;
fe6b6346 1545 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
d2fd9612
CLG		 1546 &error_fatal);
1547 object_property_set_int(OBJECT(pnv_core), core_hwid,
1548 CPU_CORE_PROP_CORE_ID, &error_fatal);
1549 object_property_set_int(OBJECT(pnv_core),
1550 pcc->core_pir(chip, core_hwid),
1551 "pir", &error_fatal);
158e17a6
GK		 1552 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1553 &error_abort);
d2fd9612
CLG		 1554 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1555 &error_fatal);
24ece072
CLG		 1556
1557 /* Each core has an XSCOM MMIO region */
c4b2c40c 1558 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
c035851a
CLG		 1559
1560 pnv_xscom_add_subregion(chip, xscom_core_base,
4fa28f23 1561 &pnv_core->xscom_regs);
d2fd9612
CLG		 1562 i++;
1563 }
51c04728
CLG		 1564}
1565
1566static void pnv_chip_realize(DeviceState *dev, Error **errp)
1567{
1568 PnvChip *chip = PNV_CHIP(dev);
1569 Error *error = NULL;
1570
51c04728
CLG		 1571 /* Cores */
1572 pnv_chip_core_realize(chip, &error);
1573 if (error) {
1574 error_propagate(errp, error);
1575 return;
1576 }
e997040e
CLG		 1577}
1578
1579static Property pnv_chip_properties[] = {
1580 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1581 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1582 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
397a79e7
CLG		 1583 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1584 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
e997040e
CLG		 1585 DEFINE_PROP_END_OF_LIST(),
1586};
1587
1588static void pnv_chip_class_init(ObjectClass *klass, void *data)
1589{
1590 DeviceClass *dc = DEVICE_CLASS(klass);
1591
9d169fb3 1592 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
e997040e
CLG		 1593 dc->realize = pnv_chip_realize;
1594 dc->props = pnv_chip_properties;
1595 dc->desc = "PowerNV Chip";
1596}
1597
119eaa9d
CLG		 1598PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1599{
1600 int i, j;
1601
1602 for (i = 0; i < chip->nr_cores; i++) {
1603 PnvCore *pc = chip->cores[i];
1604 CPUCore *cc = CPU_CORE(pc);
1605
1606 for (j = 0; j < cc->nr_threads; j++) {
1607 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1608 return pc->threads[j];
1609 }
1610 }
1611 }
1612 return NULL;
1613}
1614
54f59d78
CLG		 1615static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1616{
b168a138 1617 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1618 int i;
1619
1620 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1621 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1622
1623 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1624 return &chip8->psi.ics;
54f59d78
CLG		 1625 }
1626 }
1627 return NULL;
1628}
1629
1630static void pnv_ics_resend(XICSFabric *xi)
1631{
b168a138 1632 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1633 int i;
1634
1635 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1636 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1637 ics_resend(&chip8->psi.ics);
54f59d78
CLG		 1638 }
1639}
1640
36fc6f08
CLG		 1641static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1642{
1643 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1644
956b8f46 1645 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
36fc6f08
CLG		 1646}
1647
47fea43a
CLG		 1648static void pnv_pic_print_info(InterruptStatsProvider *obj,
1649 Monitor *mon)
1650{
b168a138 1651 PnvMachineState *pnv = PNV_MACHINE(obj);
54f59d78 1652 int i;
47fea43a
CLG		 1653 CPUState *cs;
1654
1655 CPU_FOREACH(cs) {
1656 PowerPCCPU *cpu = POWERPC_CPU(cs);
1657
85913070
GK		 1658 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1659 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1660 mon);
47fea43a 1661 }
54f59d78
CLG		 1662
1663 for (i = 0; i < pnv->num_chips; i++) {
d8e4aad5 1664 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
54f59d78 1665 }
47fea43a
CLG		 1666}
1667
c722579e
CLG		 1668static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1669 uint8_t nvt_blk, uint32_t nvt_idx,
1670 bool cam_ignore, uint8_t priority,
1671 uint32_t logic_serv,
1672 XiveTCTXMatch *match)
1673{
1674 PnvMachineState *pnv = PNV_MACHINE(xfb);
1675 int total_count = 0;
1676 int i;
1677
1678 for (i = 0; i < pnv->num_chips; i++) {
1679 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1680 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1681 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1682 int count;
1683
1684 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1685 priority, logic_serv, match);
1686
1687 if (count < 0) {
1688 return count;
1689 }
1690
1691 total_count += count;
1692 }
1693
1694 return total_count;
1695}
1696
5373c61d
CLG		 1697PnvChip *pnv_get_chip(uint32_t chip_id)
1698{
1699 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1700 int i;
1701
1702 for (i = 0; i < pnv->num_chips; i++) {
1703 PnvChip *chip = pnv->chips[i];
1704 if (chip->chip_id == chip_id) {
1705 return chip;
1706 }
1707 }
1708 return NULL;
1709}
1710
f30c843c 1711static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
9e933f4a
BH		 1712{
1713 MachineClass *mc = MACHINE_CLASS(oc);
36fc6f08 1714 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
d76f2da7
GK		 1715 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1716 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
f30c843c
CLG		 1717
1718 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1719 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1720
1721 xic->icp_get = pnv_icp_get;
1722 xic->ics_get = pnv_ics_get;
1723 xic->ics_resend = pnv_ics_resend;
d76f2da7
GK		 1724
1725 pmc->compat = compat;
1726 pmc->compat_size = sizeof(compat);
f30c843c
CLG		 1727}
1728
1729static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1730{
1731 MachineClass *mc = MACHINE_CLASS(oc);
c722579e 1732 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
d76f2da7
GK		 1733 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1734 static const char compat[] = "qemu,powernv9\0ibm,powernv";
f30c843c
CLG		 1735
1736 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1737 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
c722579e 1738 xfc->match_nvt = pnv_match_nvt;
f30c843c
CLG		 1739
1740 mc->alias = "powernv";
d76f2da7
GK		 1741
1742 pmc->compat = compat;
1743 pmc->compat_size = sizeof(compat);
7a90c6a1 1744 pmc->dt_power_mgt = pnv_dt_power_mgt;
f30c843c
CLG		 1745}
1746
2b548a42
CLG		 1747static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1748{
1749 MachineClass *mc = MACHINE_CLASS(oc);
d76f2da7
GK		 1750 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1751 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2b548a42
CLG		 1752
1753 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1754 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
d76f2da7
GK		 1755
1756 pmc->compat = compat;
1757 pmc->compat_size = sizeof(compat);
7a90c6a1 1758 pmc->dt_power_mgt = pnv_dt_power_mgt;
2b548a42
CLG		 1759}
1760
f30c843c
CLG		 1761static void pnv_machine_class_init(ObjectClass *oc, void *data)
1762{
1763 MachineClass *mc = MACHINE_CLASS(oc);
47fea43a 1764 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
9e933f4a
BH		 1765
1766 mc->desc = "IBM PowerNV (Non-Virtualized)";
b168a138
CLG		 1767 mc->init = pnv_init;
1768 mc->reset = pnv_reset;
9e933f4a 1769 mc->max_cpus = MAX_CPUS;
59b7c1c2
B		 1770 /* Pnv provides a AHCI device for storage */
1771 mc->block_default_type = IF_IDE;
9e933f4a
BH		 1772 mc->no_parallel = 1;
1773 mc->default_boot_order = NULL;
f1d18b0a
JS		 1774 /*
1775 * RAM defaults to less than 2048 for 32-bit hosts, and large
1776 * enough to fit the maximum initrd size at it's load address
1777 */
1778 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
47fea43a 1779 ispc->print_info = pnv_pic_print_info;
9e933f4a
BH		 1780}
1781
77864267
CLG		 1782#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1783 { \
1784 .name = type, \
1785 .class_init = class_initfn, \
1786 .parent = TYPE_PNV8_CHIP, \
1787 }
1788
1789#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1790 { \
1791 .name = type, \
1792 .class_init = class_initfn, \
1793 .parent = TYPE_PNV9_CHIP, \
beba5c0f
IM		 1794 }
1795
2b548a42
CLG		 1796#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1797 { \
1798 .name = type, \
1799 .class_init = class_initfn, \
1800 .parent = TYPE_PNV10_CHIP, \
1801 }
1802
beba5c0f 1803static const TypeInfo types[] = {
2b548a42
CLG		 1804 {
1805 .name = MACHINE_TYPE_NAME("powernv10"),
1806 .parent = TYPE_PNV_MACHINE,
1807 .class_init = pnv_machine_power10_class_init,
1808 },
1aba8716
CLG		 1809 {
1810 .name = MACHINE_TYPE_NAME("powernv9"),
1811 .parent = TYPE_PNV_MACHINE,
1812 .class_init = pnv_machine_power9_class_init,
c722579e
CLG		 1813 .interfaces = (InterfaceInfo[]) {
1814 { TYPE_XIVE_FABRIC },
1815 { },
1816 },
1aba8716
CLG		 1817 },
1818 {
1819 .name = MACHINE_TYPE_NAME("powernv8"),
1820 .parent = TYPE_PNV_MACHINE,
1821 .class_init = pnv_machine_power8_class_init,
1822 .interfaces = (InterfaceInfo[]) {
1823 { TYPE_XICS_FABRIC },
1824 { },
1825 },
1826 },
beba5c0f 1827 {
b168a138 1828 .name = TYPE_PNV_MACHINE,
beba5c0f 1829 .parent = TYPE_MACHINE,
f30c843c 1830 .abstract = true,
beba5c0f 1831 .instance_size = sizeof(PnvMachineState),
b168a138 1832 .class_init = pnv_machine_class_init,
d76f2da7 1833 .class_size = sizeof(PnvMachineClass),
beba5c0f 1834 .interfaces = (InterfaceInfo[]) {
beba5c0f
IM		 1835 { TYPE_INTERRUPT_STATS_PROVIDER },
1836 { },
1837 },
36fc6f08 1838 },
beba5c0f
IM		 1839 {
1840 .name = TYPE_PNV_CHIP,
1841 .parent = TYPE_SYS_BUS_DEVICE,
1842 .class_init = pnv_chip_class_init,
beba5c0f
IM		 1843 .instance_size = sizeof(PnvChip),
1844 .class_size = sizeof(PnvChipClass),
1845 .abstract = true,
1846 },
77864267 1847
2b548a42
CLG		 1848 /*
1849 * P10 chip and variants
1850 */
1851 {
1852 .name = TYPE_PNV10_CHIP,
1853 .parent = TYPE_PNV_CHIP,
1854 .instance_init = pnv_chip_power10_instance_init,
1855 .instance_size = sizeof(Pnv10Chip),
1856 },
1857 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
1858
77864267
CLG		 1859 /*
1860 * P9 chip and variants
1861 */
1862 {
1863 .name = TYPE_PNV9_CHIP,
1864 .parent = TYPE_PNV_CHIP,
1865 .instance_init = pnv_chip_power9_instance_init,
1866 .instance_size = sizeof(Pnv9Chip),
1867 },
1868 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1869
1870 /*
1871 * P8 chip and variants
1872 */
1873 {
1874 .name = TYPE_PNV8_CHIP,
1875 .parent = TYPE_PNV_CHIP,
1876 .instance_init = pnv_chip_power8_instance_init,
1877 .instance_size = sizeof(Pnv8Chip),
1878 },
1879 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1880 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1881 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1882 pnv_chip_power8nvl_class_init),
9e933f4a
BH		 1883};
1884
beba5c0f 1885DEFINE_TYPES(types)
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