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9e933f4a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV machine model | |
3 | * | |
4 | * Copyright (c) 2016, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
fc6b3cf9 | 21 | #include "qemu/units.h" |
9e933f4a BH |
22 | #include "qapi/error.h" |
23 | #include "sysemu/sysemu.h" | |
24 | #include "sysemu/numa.h" | |
d2528bdc | 25 | #include "sysemu/cpus.h" |
9e933f4a | 26 | #include "hw/hw.h" |
fcf5ef2a | 27 | #include "target/ppc/cpu.h" |
9e933f4a BH |
28 | #include "qemu/log.h" |
29 | #include "hw/ppc/fdt.h" | |
30 | #include "hw/ppc/ppc.h" | |
31 | #include "hw/ppc/pnv.h" | |
d2fd9612 | 32 | #include "hw/ppc/pnv_core.h" |
9e933f4a BH |
33 | #include "hw/loader.h" |
34 | #include "exec/address-spaces.h" | |
e997040e | 35 | #include "qapi/visitor.h" |
47fea43a CLG |
36 | #include "monitor/monitor.h" |
37 | #include "hw/intc/intc.h" | |
aeaef83d | 38 | #include "hw/ipmi/ipmi.h" |
58969eee | 39 | #include "target/ppc/mmu-hash64.h" |
9e933f4a | 40 | |
36fc6f08 | 41 | #include "hw/ppc/xics.h" |
967b7523 CLG |
42 | #include "hw/ppc/pnv_xscom.h" |
43 | ||
3495b6b6 CLG |
44 | #include "hw/isa/isa.h" |
45 | #include "hw/char/serial.h" | |
46 | #include "hw/timer/mc146818rtc.h" | |
47 | ||
9e933f4a BH |
48 | #include <libfdt.h> |
49 | ||
b268a616 | 50 | #define FDT_MAX_SIZE (1 * MiB) |
9e933f4a BH |
51 | |
52 | #define FW_FILE_NAME "skiboot.lid" | |
53 | #define FW_LOAD_ADDR 0x0 | |
b268a616 | 54 | #define FW_MAX_SIZE (4 * MiB) |
9e933f4a BH |
55 | |
56 | #define KERNEL_LOAD_ADDR 0x20000000 | |
b45b56ba | 57 | #define KERNEL_MAX_SIZE (256 * MiB) |
fef592f9 | 58 | #define INITRD_LOAD_ADDR 0x60000000 |
584ea7e7 | 59 | #define INITRD_MAX_SIZE (256 * MiB) |
9e933f4a | 60 | |
40abf43f IM |
61 | static const char *pnv_chip_core_typename(const PnvChip *o) |
62 | { | |
63 | const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); | |
64 | int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); | |
65 | char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); | |
66 | const char *core_type = object_class_get_name(object_class_by_name(s)); | |
67 | g_free(s); | |
68 | return core_type; | |
69 | } | |
70 | ||
9e933f4a BH |
71 | /* |
72 | * On Power Systems E880 (POWER8), the max cpus (threads) should be : | |
73 | * 4 * 4 sockets * 12 cores * 8 threads = 1536 | |
74 | * Let's make it 2^11 | |
75 | */ | |
76 | #define MAX_CPUS 2048 | |
77 | ||
78 | /* | |
79 | * Memory nodes are created by hostboot, one for each range of memory | |
80 | * that has a different "affinity". In practice, it means one range | |
81 | * per chip. | |
82 | */ | |
b168a138 | 83 | static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) |
9e933f4a BH |
84 | { |
85 | char *mem_name; | |
86 | uint64_t mem_reg_property[2]; | |
87 | int off; | |
88 | ||
89 | mem_reg_property[0] = cpu_to_be64(start); | |
90 | mem_reg_property[1] = cpu_to_be64(size); | |
91 | ||
92 | mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); | |
93 | off = fdt_add_subnode(fdt, 0, mem_name); | |
94 | g_free(mem_name); | |
95 | ||
96 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
97 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
98 | sizeof(mem_reg_property)))); | |
99 | _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); | |
100 | } | |
101 | ||
d2fd9612 CLG |
102 | static int get_cpus_node(void *fdt) |
103 | { | |
104 | int cpus_offset = fdt_path_offset(fdt, "/cpus"); | |
105 | ||
106 | if (cpus_offset < 0) { | |
a4f3885c | 107 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
d2fd9612 CLG |
108 | if (cpus_offset) { |
109 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
110 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
111 | } | |
112 | } | |
113 | _FDT(cpus_offset); | |
114 | return cpus_offset; | |
115 | } | |
116 | ||
117 | /* | |
118 | * The PowerNV cores (and threads) need to use real HW ids and not an | |
119 | * incremental index like it has been done on other platforms. This HW | |
120 | * id is stored in the CPU PIR, it is used to create cpu nodes in the | |
121 | * device tree, used in XSCOM to address cores and in interrupt | |
122 | * servers. | |
123 | */ | |
b168a138 | 124 | static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) |
d2fd9612 | 125 | { |
08304a86 DG |
126 | PowerPCCPU *cpu = pc->threads[0]; |
127 | CPUState *cs = CPU(cpu); | |
d2fd9612 | 128 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
8bd9530e | 129 | int smt_threads = CPU_CORE(pc)->nr_threads; |
d2fd9612 CLG |
130 | CPUPPCState *env = &cpu->env; |
131 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
132 | uint32_t servers_prop[smt_threads]; | |
133 | int i; | |
134 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
135 | 0xffffffff, 0xffffffff}; | |
136 | uint32_t tbfreq = PNV_TIMEBASE_FREQ; | |
137 | uint32_t cpufreq = 1000000000; | |
138 | uint32_t page_sizes_prop[64]; | |
139 | size_t page_sizes_prop_size; | |
140 | const uint8_t pa_features[] = { 24, 0, | |
141 | 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, | |
142 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
143 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
144 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
145 | int offset; | |
146 | char *nodename; | |
147 | int cpus_offset = get_cpus_node(fdt); | |
148 | ||
149 | nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); | |
150 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
151 | _FDT(offset); | |
152 | g_free(nodename); | |
153 | ||
154 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); | |
155 | ||
156 | _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); | |
157 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); | |
158 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
159 | ||
160 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
161 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
162 | env->dcache_line_size))); | |
163 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
164 | env->dcache_line_size))); | |
165 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
166 | env->icache_line_size))); | |
167 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
168 | env->icache_line_size))); | |
169 | ||
170 | if (pcc->l1_dcache_size) { | |
171 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
172 | pcc->l1_dcache_size))); | |
173 | } else { | |
3dc6f869 | 174 | warn_report("Unknown L1 dcache size for cpu"); |
d2fd9612 CLG |
175 | } |
176 | if (pcc->l1_icache_size) { | |
177 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
178 | pcc->l1_icache_size))); | |
179 | } else { | |
3dc6f869 | 180 | warn_report("Unknown L1 icache size for cpu"); |
d2fd9612 CLG |
181 | } |
182 | ||
183 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
184 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
67d7d66f | 185 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); |
d2fd9612 CLG |
186 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); |
187 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
188 | ||
189 | if (env->spr_cb[SPR_PURR].oea_read) { | |
190 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
191 | } | |
192 | ||
58969eee | 193 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
d2fd9612 CLG |
194 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", |
195 | segs, sizeof(segs)))); | |
196 | } | |
197 | ||
198 | /* Advertise VMX/VSX (vector extensions) if available | |
199 | * 0 / no property == no vector extensions | |
200 | * 1 == VMX / Altivec available | |
201 | * 2 == VSX available */ | |
202 | if (env->insns_flags & PPC_ALTIVEC) { | |
203 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
204 | ||
205 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
206 | } | |
207 | ||
208 | /* Advertise DFP (Decimal Floating Point) if available | |
209 | * 0 / no property == no DFP | |
210 | * 1 == DFP available */ | |
211 | if (env->insns_flags2 & PPC2_DFP) { | |
212 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
213 | } | |
214 | ||
644a2c99 DG |
215 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
216 | sizeof(page_sizes_prop)); | |
d2fd9612 CLG |
217 | if (page_sizes_prop_size) { |
218 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
219 | page_sizes_prop, page_sizes_prop_size))); | |
220 | } | |
221 | ||
222 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", | |
223 | pa_features, sizeof(pa_features)))); | |
224 | ||
d2fd9612 CLG |
225 | /* Build interrupt servers properties */ |
226 | for (i = 0; i < smt_threads; i++) { | |
227 | servers_prop[i] = cpu_to_be32(pc->pir + i); | |
228 | } | |
229 | _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
230 | servers_prop, sizeof(servers_prop)))); | |
231 | } | |
232 | ||
b168a138 CLG |
233 | static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, |
234 | uint32_t nr_threads) | |
bf5615e7 CLG |
235 | { |
236 | uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); | |
237 | char *name; | |
238 | const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; | |
239 | uint32_t irange[2], i, rsize; | |
240 | uint64_t *reg; | |
241 | int offset; | |
242 | ||
243 | irange[0] = cpu_to_be32(pir); | |
244 | irange[1] = cpu_to_be32(nr_threads); | |
245 | ||
246 | rsize = sizeof(uint64_t) * 2 * nr_threads; | |
247 | reg = g_malloc(rsize); | |
248 | for (i = 0; i < nr_threads; i++) { | |
249 | reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); | |
250 | reg[i * 2 + 1] = cpu_to_be64(0x1000); | |
251 | } | |
252 | ||
253 | name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); | |
254 | offset = fdt_add_subnode(fdt, 0, name); | |
255 | _FDT(offset); | |
256 | g_free(name); | |
257 | ||
258 | _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); | |
259 | _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); | |
260 | _FDT((fdt_setprop_string(fdt, offset, "device_type", | |
261 | "PowerPC-External-Interrupt-Presentation"))); | |
262 | _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); | |
263 | _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", | |
264 | irange, sizeof(irange)))); | |
265 | _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); | |
266 | _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); | |
267 | g_free(reg); | |
268 | } | |
269 | ||
eb859a27 | 270 | static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) |
e997040e | 271 | { |
40abf43f | 272 | const char *typename = pnv_chip_core_typename(chip); |
d2fd9612 CLG |
273 | size_t typesize = object_type_get_instance_size(typename); |
274 | int i; | |
275 | ||
b168a138 | 276 | pnv_dt_xscom(chip, fdt, 0); |
967b7523 | 277 | |
d2fd9612 CLG |
278 | for (i = 0; i < chip->nr_cores; i++) { |
279 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
280 | ||
b168a138 | 281 | pnv_dt_core(chip, pnv_core, fdt); |
bf5615e7 CLG |
282 | |
283 | /* Interrupt Control Presenters (ICP). One per core. */ | |
b168a138 | 284 | pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); |
d2fd9612 CLG |
285 | } |
286 | ||
e997040e | 287 | if (chip->ram_size) { |
b168a138 | 288 | pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); |
e997040e CLG |
289 | } |
290 | } | |
291 | ||
eb859a27 CLG |
292 | static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) |
293 | { | |
294 | const char *typename = pnv_chip_core_typename(chip); | |
295 | size_t typesize = object_type_get_instance_size(typename); | |
296 | int i; | |
297 | ||
298 | pnv_dt_xscom(chip, fdt, 0); | |
299 | ||
300 | for (i = 0; i < chip->nr_cores; i++) { | |
301 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
302 | ||
303 | pnv_dt_core(chip, pnv_core, fdt); | |
304 | } | |
305 | ||
306 | if (chip->ram_size) { | |
307 | pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); | |
308 | } | |
15376c66 CLG |
309 | |
310 | pnv_dt_lpc(chip, fdt, 0); | |
eb859a27 CLG |
311 | } |
312 | ||
b168a138 | 313 | static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) |
c5ffdcae CLG |
314 | { |
315 | uint32_t io_base = d->ioport_id; | |
316 | uint32_t io_regs[] = { | |
317 | cpu_to_be32(1), | |
318 | cpu_to_be32(io_base), | |
319 | cpu_to_be32(2) | |
320 | }; | |
321 | char *name; | |
322 | int node; | |
323 | ||
324 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
325 | node = fdt_add_subnode(fdt, lpc_off, name); | |
326 | _FDT(node); | |
327 | g_free(name); | |
328 | ||
329 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); | |
330 | _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); | |
331 | } | |
332 | ||
b168a138 | 333 | static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) |
cb228f5a CLG |
334 | { |
335 | const char compatible[] = "ns16550\0pnpPNP,501"; | |
336 | uint32_t io_base = d->ioport_id; | |
337 | uint32_t io_regs[] = { | |
338 | cpu_to_be32(1), | |
339 | cpu_to_be32(io_base), | |
340 | cpu_to_be32(8) | |
341 | }; | |
342 | char *name; | |
343 | int node; | |
344 | ||
345 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
346 | node = fdt_add_subnode(fdt, lpc_off, name); | |
347 | _FDT(node); | |
348 | g_free(name); | |
349 | ||
350 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); | |
351 | _FDT((fdt_setprop(fdt, node, "compatible", compatible, | |
352 | sizeof(compatible)))); | |
353 | ||
354 | _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); | |
355 | _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); | |
356 | _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); | |
357 | _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", | |
358 | fdt_get_phandle(fdt, lpc_off)))); | |
359 | ||
360 | /* This is needed by Linux */ | |
361 | _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); | |
362 | } | |
363 | ||
b168a138 | 364 | static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) |
04f6c8b2 CLG |
365 | { |
366 | const char compatible[] = "bt\0ipmi-bt"; | |
367 | uint32_t io_base; | |
368 | uint32_t io_regs[] = { | |
369 | cpu_to_be32(1), | |
370 | 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ | |
371 | cpu_to_be32(3) | |
372 | }; | |
373 | uint32_t irq; | |
374 | char *name; | |
375 | int node; | |
376 | ||
377 | io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); | |
378 | io_regs[1] = cpu_to_be32(io_base); | |
379 | ||
380 | irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); | |
381 | ||
382 | name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); | |
383 | node = fdt_add_subnode(fdt, lpc_off, name); | |
384 | _FDT(node); | |
385 | g_free(name); | |
386 | ||
7032d92a CLG |
387 | _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); |
388 | _FDT((fdt_setprop(fdt, node, "compatible", compatible, | |
389 | sizeof(compatible)))); | |
04f6c8b2 CLG |
390 | |
391 | /* Mark it as reserved to avoid Linux trying to claim it */ | |
392 | _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); | |
393 | _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); | |
394 | _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", | |
395 | fdt_get_phandle(fdt, lpc_off)))); | |
396 | } | |
397 | ||
e7a3fee3 CLG |
398 | typedef struct ForeachPopulateArgs { |
399 | void *fdt; | |
400 | int offset; | |
401 | } ForeachPopulateArgs; | |
402 | ||
b168a138 | 403 | static int pnv_dt_isa_device(DeviceState *dev, void *opaque) |
e7a3fee3 | 404 | { |
c5ffdcae CLG |
405 | ForeachPopulateArgs *args = opaque; |
406 | ISADevice *d = ISA_DEVICE(dev); | |
407 | ||
408 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { | |
b168a138 | 409 | pnv_dt_rtc(d, args->fdt, args->offset); |
cb228f5a | 410 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { |
b168a138 | 411 | pnv_dt_serial(d, args->fdt, args->offset); |
04f6c8b2 | 412 | } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { |
b168a138 | 413 | pnv_dt_ipmi_bt(d, args->fdt, args->offset); |
c5ffdcae CLG |
414 | } else { |
415 | error_report("unknown isa device %s@i%x", qdev_fw_name(dev), | |
416 | d->ioport_id); | |
417 | } | |
418 | ||
e7a3fee3 CLG |
419 | return 0; |
420 | } | |
421 | ||
bb7ab95c CLG |
422 | /* The default LPC bus of a multichip system is on chip 0. It's |
423 | * recognized by the firmware (skiboot) using a "primary" property. | |
424 | */ | |
425 | static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) | |
426 | { | |
64d011d5 | 427 | int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); |
e7a3fee3 CLG |
428 | ForeachPopulateArgs args = { |
429 | .fdt = fdt, | |
bb7ab95c | 430 | .offset = isa_offset, |
e7a3fee3 CLG |
431 | }; |
432 | ||
bb7ab95c CLG |
433 | _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); |
434 | ||
e7a3fee3 CLG |
435 | /* ISA devices are not necessarily parented to the ISA bus so we |
436 | * can not use object_child_foreach() */ | |
bb7ab95c CLG |
437 | qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, |
438 | &args); | |
e7a3fee3 CLG |
439 | } |
440 | ||
e5694793 CLG |
441 | static void pnv_dt_power_mgt(void *fdt) |
442 | { | |
443 | int off; | |
444 | ||
445 | off = fdt_add_subnode(fdt, 0, "ibm,opal"); | |
446 | off = fdt_add_subnode(fdt, off, "power-mgt"); | |
447 | ||
448 | _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); | |
449 | } | |
450 | ||
b168a138 | 451 | static void *pnv_dt_create(MachineState *machine) |
9e933f4a | 452 | { |
83b90bf0 CLG |
453 | const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; |
454 | const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; | |
b168a138 | 455 | PnvMachineState *pnv = PNV_MACHINE(machine); |
9e933f4a BH |
456 | void *fdt; |
457 | char *buf; | |
458 | int off; | |
e997040e | 459 | int i; |
9e933f4a BH |
460 | |
461 | fdt = g_malloc0(FDT_MAX_SIZE); | |
462 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
463 | ||
464 | /* Root node */ | |
465 | _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); | |
466 | _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); | |
467 | _FDT((fdt_setprop_string(fdt, 0, "model", | |
468 | "IBM PowerNV (emulated by qemu)"))); | |
83b90bf0 CLG |
469 | if (pnv_is_power9(pnv)) { |
470 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, | |
471 | sizeof(plat_compat9)))); | |
472 | } else { | |
473 | _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, | |
474 | sizeof(plat_compat8)))); | |
475 | } | |
476 | ||
9e933f4a BH |
477 | |
478 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
479 | _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); | |
480 | if (qemu_uuid_set) { | |
481 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
482 | } | |
483 | g_free(buf); | |
484 | ||
485 | off = fdt_add_subnode(fdt, 0, "chosen"); | |
486 | if (machine->kernel_cmdline) { | |
487 | _FDT((fdt_setprop_string(fdt, off, "bootargs", | |
488 | machine->kernel_cmdline))); | |
489 | } | |
490 | ||
491 | if (pnv->initrd_size) { | |
492 | uint32_t start_prop = cpu_to_be32(pnv->initrd_base); | |
493 | uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); | |
494 | ||
495 | _FDT((fdt_setprop(fdt, off, "linux,initrd-start", | |
496 | &start_prop, sizeof(start_prop)))); | |
497 | _FDT((fdt_setprop(fdt, off, "linux,initrd-end", | |
498 | &end_prop, sizeof(end_prop)))); | |
499 | } | |
500 | ||
e997040e CLG |
501 | /* Populate device tree for each chip */ |
502 | for (i = 0; i < pnv->num_chips; i++) { | |
eb859a27 | 503 | PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); |
e997040e | 504 | } |
e7a3fee3 CLG |
505 | |
506 | /* Populate ISA devices on chip 0 */ | |
bb7ab95c | 507 | pnv_dt_isa(pnv, fdt); |
aeaef83d CLG |
508 | |
509 | if (pnv->bmc) { | |
b168a138 | 510 | pnv_dt_bmc_sensors(pnv->bmc, fdt); |
aeaef83d CLG |
511 | } |
512 | ||
e5694793 CLG |
513 | /* Create an extra node for power management on Power9 */ |
514 | if (pnv_is_power9(pnv)) { | |
515 | pnv_dt_power_mgt(fdt); | |
516 | } | |
517 | ||
9e933f4a BH |
518 | return fdt; |
519 | } | |
520 | ||
bce0b691 CLG |
521 | static void pnv_powerdown_notify(Notifier *n, void *opaque) |
522 | { | |
b168a138 | 523 | PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); |
bce0b691 CLG |
524 | |
525 | if (pnv->bmc) { | |
526 | pnv_bmc_powerdown(pnv->bmc); | |
527 | } | |
528 | } | |
529 | ||
b168a138 | 530 | static void pnv_reset(void) |
9e933f4a BH |
531 | { |
532 | MachineState *machine = MACHINE(qdev_get_machine()); | |
b168a138 | 533 | PnvMachineState *pnv = PNV_MACHINE(machine); |
9e933f4a | 534 | void *fdt; |
aeaef83d | 535 | Object *obj; |
9e933f4a BH |
536 | |
537 | qemu_devices_reset(); | |
538 | ||
aeaef83d CLG |
539 | /* OpenPOWER systems have a BMC, which can be defined on the |
540 | * command line with: | |
541 | * | |
542 | * -device ipmi-bmc-sim,id=bmc0 | |
543 | * | |
544 | * This is the internal simulator but it could also be an external | |
545 | * BMC. | |
546 | */ | |
a1a636b8 | 547 | obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); |
aeaef83d CLG |
548 | if (obj) { |
549 | pnv->bmc = IPMI_BMC(obj); | |
550 | } | |
551 | ||
b168a138 | 552 | fdt = pnv_dt_create(machine); |
9e933f4a BH |
553 | |
554 | /* Pack resulting tree */ | |
555 | _FDT((fdt_pack(fdt))); | |
556 | ||
557 | cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); | |
558 | } | |
559 | ||
04026890 | 560 | static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) |
3495b6b6 | 561 | { |
77864267 CLG |
562 | Pnv8Chip *chip8 = PNV8_CHIP(chip); |
563 | return pnv_lpc_isa_create(&chip8->lpc, true, errp); | |
04026890 | 564 | } |
3495b6b6 | 565 | |
04026890 CLG |
566 | static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) |
567 | { | |
77864267 CLG |
568 | Pnv8Chip *chip8 = PNV8_CHIP(chip); |
569 | return pnv_lpc_isa_create(&chip8->lpc, false, errp); | |
04026890 | 570 | } |
3495b6b6 | 571 | |
04026890 CLG |
572 | static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) |
573 | { | |
15376c66 CLG |
574 | Pnv9Chip *chip9 = PNV9_CHIP(chip); |
575 | return pnv_lpc_isa_create(&chip9->lpc, false, errp); | |
04026890 | 576 | } |
3495b6b6 | 577 | |
04026890 CLG |
578 | static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) |
579 | { | |
580 | return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); | |
3495b6b6 CLG |
581 | } |
582 | ||
d8e4aad5 CLG |
583 | static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) |
584 | { | |
585 | Pnv8Chip *chip8 = PNV8_CHIP(chip); | |
586 | ||
587 | ics_pic_print_info(&chip8->psi.ics, mon); | |
588 | } | |
589 | ||
590 | static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) | |
591 | { | |
592 | Pnv9Chip *chip9 = PNV9_CHIP(chip); | |
593 | ||
594 | pnv_xive_pic_print_info(&chip9->xive, mon); | |
c38536bc | 595 | pnv_psi_pic_print_info(&chip9->psi, mon); |
d8e4aad5 CLG |
596 | } |
597 | ||
b168a138 | 598 | static void pnv_init(MachineState *machine) |
9e933f4a | 599 | { |
b168a138 | 600 | PnvMachineState *pnv = PNV_MACHINE(machine); |
9e933f4a BH |
601 | MemoryRegion *ram; |
602 | char *fw_filename; | |
603 | long fw_size; | |
e997040e CLG |
604 | int i; |
605 | char *chip_typename; | |
9e933f4a BH |
606 | |
607 | /* allocate RAM */ | |
d23b6caa | 608 | if (machine->ram_size < (1 * GiB)) { |
3dc6f869 | 609 | warn_report("skiboot may not work with < 1GB of RAM"); |
9e933f4a BH |
610 | } |
611 | ||
612 | ram = g_new(MemoryRegion, 1); | |
b168a138 | 613 | memory_region_allocate_system_memory(ram, NULL, "pnv.ram", |
9e933f4a BH |
614 | machine->ram_size); |
615 | memory_region_add_subregion(get_system_memory(), 0, ram); | |
616 | ||
617 | /* load skiboot firmware */ | |
618 | if (bios_name == NULL) { | |
619 | bios_name = FW_FILE_NAME; | |
620 | } | |
621 | ||
622 | fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
15fcedb2 CLG |
623 | if (!fw_filename) { |
624 | error_report("Could not find OPAL firmware '%s'", bios_name); | |
625 | exit(1); | |
626 | } | |
9e933f4a BH |
627 | |
628 | fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); | |
629 | if (fw_size < 0) { | |
15fcedb2 | 630 | error_report("Could not load OPAL firmware '%s'", fw_filename); |
9e933f4a BH |
631 | exit(1); |
632 | } | |
633 | g_free(fw_filename); | |
634 | ||
635 | /* load kernel */ | |
636 | if (machine->kernel_filename) { | |
637 | long kernel_size; | |
638 | ||
639 | kernel_size = load_image_targphys(machine->kernel_filename, | |
b45b56ba | 640 | KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); |
9e933f4a | 641 | if (kernel_size < 0) { |
802fc7ab | 642 | error_report("Could not load kernel '%s'", |
7c6e8797 | 643 | machine->kernel_filename); |
9e933f4a BH |
644 | exit(1); |
645 | } | |
646 | } | |
647 | ||
648 | /* load initrd */ | |
649 | if (machine->initrd_filename) { | |
650 | pnv->initrd_base = INITRD_LOAD_ADDR; | |
651 | pnv->initrd_size = load_image_targphys(machine->initrd_filename, | |
584ea7e7 | 652 | pnv->initrd_base, INITRD_MAX_SIZE); |
9e933f4a | 653 | if (pnv->initrd_size < 0) { |
802fc7ab | 654 | error_report("Could not load initial ram disk '%s'", |
9e933f4a BH |
655 | machine->initrd_filename); |
656 | exit(1); | |
657 | } | |
658 | } | |
e997040e | 659 | |
e997040e | 660 | /* Create the processor chips */ |
4a12c699 | 661 | i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); |
7fd544d8 | 662 | chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), |
4a12c699 | 663 | i, machine->cpu_type); |
e997040e | 664 | if (!object_class_by_name(chip_typename)) { |
4a12c699 IM |
665 | error_report("invalid CPU model '%.*s' for %s machine", |
666 | i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); | |
e997040e CLG |
667 | exit(1); |
668 | } | |
669 | ||
670 | pnv->chips = g_new0(PnvChip *, pnv->num_chips); | |
671 | for (i = 0; i < pnv->num_chips; i++) { | |
672 | char chip_name[32]; | |
673 | Object *chip = object_new(chip_typename); | |
674 | ||
675 | pnv->chips[i] = PNV_CHIP(chip); | |
676 | ||
677 | /* TODO: put all the memory in one node on chip 0 until we find a | |
678 | * way to specify different ranges for each chip | |
679 | */ | |
680 | if (i == 0) { | |
681 | object_property_set_int(chip, machine->ram_size, "ram-size", | |
682 | &error_fatal); | |
683 | } | |
684 | ||
685 | snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); | |
686 | object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); | |
687 | object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", | |
688 | &error_fatal); | |
397a79e7 | 689 | object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); |
e997040e CLG |
690 | object_property_set_bool(chip, true, "realized", &error_fatal); |
691 | } | |
692 | g_free(chip_typename); | |
3495b6b6 CLG |
693 | |
694 | /* Instantiate ISA bus on chip 0 */ | |
04026890 | 695 | pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); |
3495b6b6 CLG |
696 | |
697 | /* Create serial port */ | |
def337ff | 698 | serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
3495b6b6 CLG |
699 | |
700 | /* Create an RTC ISA device too */ | |
6c646a11 | 701 | mc146818_rtc_init(pnv->isa_bus, 2000, NULL); |
bce0b691 CLG |
702 | |
703 | /* OpenPOWER systems use a IPMI SEL Event message to notify the | |
704 | * host to powerdown */ | |
705 | pnv->powerdown_notifier.notify = pnv_powerdown_notify; | |
706 | qemu_register_powerdown_notifier(&pnv->powerdown_notifier); | |
e997040e CLG |
707 | } |
708 | ||
631adaff CLG |
709 | /* |
710 | * 0:21 Reserved - Read as zeros | |
711 | * 22:24 Chip ID | |
712 | * 25:28 Core number | |
713 | * 29:31 Thread ID | |
714 | */ | |
715 | static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) | |
716 | { | |
717 | return (chip->chip_id << 7) | (core_id << 3); | |
718 | } | |
719 | ||
8fa1f4ef CLG |
720 | static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, |
721 | Error **errp) | |
d35aefa9 | 722 | { |
8fa1f4ef CLG |
723 | Error *local_err = NULL; |
724 | Object *obj; | |
8907fc25 | 725 | PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); |
8fa1f4ef CLG |
726 | |
727 | obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), | |
728 | &local_err); | |
729 | if (local_err) { | |
730 | error_propagate(errp, local_err); | |
731 | return; | |
732 | } | |
733 | ||
956b8f46 | 734 | pnv_cpu->intc = obj; |
d35aefa9 CLG |
735 | } |
736 | ||
631adaff CLG |
737 | /* |
738 | * 0:48 Reserved - Read as zeroes | |
739 | * 49:52 Node ID | |
740 | * 53:55 Chip ID | |
741 | * 56 Reserved - Read as zero | |
742 | * 57:61 Core number | |
743 | * 62:63 Thread ID | |
744 | * | |
745 | * We only care about the lower bits. uint32_t is fine for the moment. | |
746 | */ | |
747 | static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) | |
748 | { | |
749 | return (chip->chip_id << 8) | (core_id << 2); | |
750 | } | |
751 | ||
8fa1f4ef CLG |
752 | static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, |
753 | Error **errp) | |
d35aefa9 | 754 | { |
2dfa91a2 CLG |
755 | Pnv9Chip *chip9 = PNV9_CHIP(chip); |
756 | Error *local_err = NULL; | |
757 | Object *obj; | |
758 | PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); | |
759 | ||
760 | /* | |
761 | * The core creates its interrupt presenter but the XIVE interrupt | |
762 | * controller object is initialized afterwards. Hopefully, it's | |
763 | * only used at runtime. | |
764 | */ | |
26aa5b1e | 765 | obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); |
2dfa91a2 CLG |
766 | if (local_err) { |
767 | error_propagate(errp, local_err); | |
768 | return; | |
769 | } | |
770 | ||
771 | pnv_cpu->intc = obj; | |
d35aefa9 CLG |
772 | } |
773 | ||
397a79e7 CLG |
774 | /* Allowed core identifiers on a POWER8 Processor Chip : |
775 | * | |
776 | * <EX0 reserved> | |
777 | * EX1 - Venice only | |
778 | * EX2 - Venice only | |
779 | * EX3 - Venice only | |
780 | * EX4 | |
781 | * EX5 | |
782 | * EX6 | |
783 | * <EX7,8 reserved> <reserved> | |
784 | * EX9 - Venice only | |
785 | * EX10 - Venice only | |
786 | * EX11 - Venice only | |
787 | * EX12 | |
788 | * EX13 | |
789 | * EX14 | |
790 | * <EX15 reserved> | |
791 | */ | |
792 | #define POWER8E_CORE_MASK (0x7070ull) | |
793 | #define POWER8_CORE_MASK (0x7e7eull) | |
794 | ||
795 | /* | |
09279d7e | 796 | * POWER9 has 24 cores, ids starting at 0x0 |
397a79e7 | 797 | */ |
09279d7e | 798 | #define POWER9_CORE_MASK (0xffffffffffffffull) |
397a79e7 | 799 | |
77864267 CLG |
800 | static void pnv_chip_power8_instance_init(Object *obj) |
801 | { | |
802 | Pnv8Chip *chip8 = PNV8_CHIP(obj); | |
803 | ||
f6d4dca8 | 804 | object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), |
ae856055 | 805 | TYPE_PNV8_PSI, &error_abort, NULL); |
77864267 CLG |
806 | object_property_add_const_link(OBJECT(&chip8->psi), "xics", |
807 | OBJECT(qdev_get_machine()), &error_abort); | |
808 | ||
f6d4dca8 | 809 | object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), |
82514be2 | 810 | TYPE_PNV8_LPC, &error_abort, NULL); |
77864267 CLG |
811 | object_property_add_const_link(OBJECT(&chip8->lpc), "psi", |
812 | OBJECT(&chip8->psi), &error_abort); | |
813 | ||
f6d4dca8 | 814 | object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), |
3233838c | 815 | TYPE_PNV8_OCC, &error_abort, NULL); |
77864267 CLG |
816 | object_property_add_const_link(OBJECT(&chip8->occ), "psi", |
817 | OBJECT(&chip8->psi), &error_abort); | |
818 | } | |
819 | ||
820 | static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) | |
821 | { | |
822 | PnvChip *chip = PNV_CHIP(chip8); | |
823 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
824 | const char *typename = pnv_chip_core_typename(chip); | |
825 | size_t typesize = object_type_get_instance_size(typename); | |
826 | int i, j; | |
827 | char *name; | |
828 | XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); | |
829 | ||
830 | name = g_strdup_printf("icp-%x", chip->chip_id); | |
831 | memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); | |
832 | sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); | |
833 | g_free(name); | |
834 | ||
835 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); | |
836 | ||
837 | /* Map the ICP registers for each thread */ | |
838 | for (i = 0; i < chip->nr_cores; i++) { | |
839 | PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); | |
840 | int core_hwid = CPU_CORE(pnv_core)->core_id; | |
841 | ||
842 | for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { | |
843 | uint32_t pir = pcc->core_pir(chip, core_hwid) + j; | |
844 | PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); | |
845 | ||
846 | memory_region_add_subregion(&chip8->icp_mmio, pir << 12, | |
847 | &icp->mmio); | |
848 | } | |
849 | } | |
850 | } | |
851 | ||
852 | static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) | |
853 | { | |
854 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); | |
855 | PnvChip *chip = PNV_CHIP(dev); | |
856 | Pnv8Chip *chip8 = PNV8_CHIP(dev); | |
ae856055 | 857 | Pnv8Psi *psi8 = &chip8->psi; |
77864267 CLG |
858 | Error *local_err = NULL; |
859 | ||
860 | pcc->parent_realize(dev, &local_err); | |
861 | if (local_err) { | |
862 | error_propagate(errp, local_err); | |
863 | return; | |
864 | } | |
865 | ||
866 | /* Processor Service Interface (PSI) Host Bridge */ | |
867 | object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), | |
868 | "bar", &error_fatal); | |
869 | object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); | |
870 | if (local_err) { | |
871 | error_propagate(errp, local_err); | |
872 | return; | |
873 | } | |
ae856055 CLG |
874 | pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, |
875 | &PNV_PSI(psi8)->xscom_regs); | |
77864267 CLG |
876 | |
877 | /* Create LPC controller */ | |
878 | object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", | |
879 | &error_fatal); | |
880 | pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); | |
881 | ||
64d011d5 CLG |
882 | chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", |
883 | (uint64_t) PNV_XSCOM_BASE(chip), | |
884 | PNV_XSCOM_LPC_BASE); | |
885 | ||
77864267 CLG |
886 | /* Interrupt Management Area. This is the memory region holding |
887 | * all the Interrupt Control Presenter (ICP) registers */ | |
888 | pnv_chip_icp_realize(chip8, &local_err); | |
889 | if (local_err) { | |
890 | error_propagate(errp, local_err); | |
891 | return; | |
892 | } | |
893 | ||
894 | /* Create the simplified OCC model */ | |
895 | object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); | |
896 | if (local_err) { | |
897 | error_propagate(errp, local_err); | |
898 | return; | |
899 | } | |
900 | pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); | |
901 | } | |
902 | ||
e997040e CLG |
903 | static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) |
904 | { | |
905 | DeviceClass *dc = DEVICE_CLASS(klass); | |
906 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
907 | ||
e997040e CLG |
908 | k->chip_type = PNV_CHIP_POWER8E; |
909 | k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ | |
397a79e7 | 910 | k->cores_mask = POWER8E_CORE_MASK; |
631adaff | 911 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 912 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 913 | k->isa_create = pnv_chip_power8_isa_create; |
eb859a27 | 914 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 915 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
967b7523 | 916 | k->xscom_base = 0x003fc0000000000ull; |
e997040e | 917 | dc->desc = "PowerNV Chip POWER8E"; |
77864267 CLG |
918 | |
919 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
920 | &k->parent_realize); | |
e997040e CLG |
921 | } |
922 | ||
e997040e CLG |
923 | static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) |
924 | { | |
925 | DeviceClass *dc = DEVICE_CLASS(klass); | |
926 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
927 | ||
e997040e CLG |
928 | k->chip_type = PNV_CHIP_POWER8; |
929 | k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ | |
397a79e7 | 930 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 931 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 932 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 933 | k->isa_create = pnv_chip_power8_isa_create; |
eb859a27 | 934 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 935 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
967b7523 | 936 | k->xscom_base = 0x003fc0000000000ull; |
e997040e | 937 | dc->desc = "PowerNV Chip POWER8"; |
77864267 CLG |
938 | |
939 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
940 | &k->parent_realize); | |
e997040e CLG |
941 | } |
942 | ||
e997040e CLG |
943 | static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) |
944 | { | |
945 | DeviceClass *dc = DEVICE_CLASS(klass); | |
946 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
947 | ||
e997040e CLG |
948 | k->chip_type = PNV_CHIP_POWER8NVL; |
949 | k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ | |
397a79e7 | 950 | k->cores_mask = POWER8_CORE_MASK; |
631adaff | 951 | k->core_pir = pnv_chip_core_pir_p8; |
d35aefa9 | 952 | k->intc_create = pnv_chip_power8_intc_create; |
04026890 | 953 | k->isa_create = pnv_chip_power8nvl_isa_create; |
eb859a27 | 954 | k->dt_populate = pnv_chip_power8_dt_populate; |
d8e4aad5 | 955 | k->pic_print_info = pnv_chip_power8_pic_print_info; |
967b7523 | 956 | k->xscom_base = 0x003fc0000000000ull; |
e997040e | 957 | dc->desc = "PowerNV Chip POWER8NVL"; |
77864267 CLG |
958 | |
959 | device_class_set_parent_realize(dc, pnv_chip_power8_realize, | |
960 | &k->parent_realize); | |
961 | } | |
962 | ||
963 | static void pnv_chip_power9_instance_init(Object *obj) | |
964 | { | |
2dfa91a2 CLG |
965 | Pnv9Chip *chip9 = PNV9_CHIP(obj); |
966 | ||
967 | object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), | |
968 | TYPE_PNV_XIVE, &error_abort, NULL); | |
969 | object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, | |
970 | &error_abort); | |
c38536bc CLG |
971 | |
972 | object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), | |
973 | TYPE_PNV9_PSI, &error_abort, NULL); | |
974 | object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, | |
975 | &error_abort); | |
15376c66 CLG |
976 | |
977 | object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), | |
978 | TYPE_PNV9_LPC, &error_abort, NULL); | |
979 | object_property_add_const_link(OBJECT(&chip9->lpc), "psi", | |
980 | OBJECT(&chip9->psi), &error_abort); | |
6598a70d CLG |
981 | |
982 | object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), | |
983 | TYPE_PNV9_OCC, &error_abort, NULL); | |
984 | object_property_add_const_link(OBJECT(&chip9->occ), "psi", | |
985 | OBJECT(&chip9->psi), &error_abort); | |
77864267 CLG |
986 | } |
987 | ||
5dad902c CLG |
988 | static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) |
989 | { | |
990 | PnvChip *chip = PNV_CHIP(chip9); | |
991 | const char *typename = pnv_chip_core_typename(chip); | |
992 | size_t typesize = object_type_get_instance_size(typename); | |
993 | int i; | |
994 | ||
995 | chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); | |
996 | chip9->quads = g_new0(PnvQuad, chip9->nr_quads); | |
997 | ||
998 | for (i = 0; i < chip9->nr_quads; i++) { | |
999 | char eq_name[32]; | |
1000 | PnvQuad *eq = &chip9->quads[i]; | |
1001 | PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); | |
1002 | int core_id = CPU_CORE(pnv_core)->core_id; | |
1003 | ||
5dad902c | 1004 | snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); |
bc4c406c PMD |
1005 | object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), |
1006 | TYPE_PNV_QUAD, &error_fatal, NULL); | |
5dad902c | 1007 | |
5dad902c CLG |
1008 | object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); |
1009 | object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); | |
5dad902c CLG |
1010 | |
1011 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), | |
1012 | &eq->xscom_regs); | |
1013 | } | |
1014 | } | |
1015 | ||
77864267 CLG |
1016 | static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) |
1017 | { | |
1018 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); | |
2dfa91a2 CLG |
1019 | Pnv9Chip *chip9 = PNV9_CHIP(dev); |
1020 | PnvChip *chip = PNV_CHIP(dev); | |
c38536bc | 1021 | Pnv9Psi *psi9 = &chip9->psi; |
77864267 CLG |
1022 | Error *local_err = NULL; |
1023 | ||
1024 | pcc->parent_realize(dev, &local_err); | |
1025 | if (local_err) { | |
1026 | error_propagate(errp, local_err); | |
1027 | return; | |
1028 | } | |
2dfa91a2 | 1029 | |
5dad902c CLG |
1030 | pnv_chip_quad_realize(chip9, &local_err); |
1031 | if (local_err) { | |
1032 | error_propagate(errp, local_err); | |
1033 | return; | |
1034 | } | |
1035 | ||
2dfa91a2 CLG |
1036 | /* XIVE interrupt controller (POWER9) */ |
1037 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), | |
1038 | "ic-bar", &error_fatal); | |
1039 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), | |
1040 | "vc-bar", &error_fatal); | |
1041 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), | |
1042 | "pc-bar", &error_fatal); | |
1043 | object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), | |
1044 | "tm-bar", &error_fatal); | |
1045 | object_property_set_bool(OBJECT(&chip9->xive), true, "realized", | |
1046 | &local_err); | |
1047 | if (local_err) { | |
1048 | error_propagate(errp, local_err); | |
1049 | return; | |
1050 | } | |
1051 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, | |
1052 | &chip9->xive.xscom_regs); | |
c38536bc CLG |
1053 | |
1054 | /* Processor Service Interface (PSI) Host Bridge */ | |
1055 | object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), | |
1056 | "bar", &error_fatal); | |
1057 | object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); | |
1058 | if (local_err) { | |
1059 | error_propagate(errp, local_err); | |
1060 | return; | |
1061 | } | |
1062 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, | |
1063 | &PNV_PSI(psi9)->xscom_regs); | |
15376c66 CLG |
1064 | |
1065 | /* LPC */ | |
1066 | object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); | |
1067 | if (local_err) { | |
1068 | error_propagate(errp, local_err); | |
1069 | return; | |
1070 | } | |
1071 | memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), | |
1072 | &chip9->lpc.xscom_regs); | |
1073 | ||
1074 | chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", | |
1075 | (uint64_t) PNV9_LPCM_BASE(chip)); | |
6598a70d CLG |
1076 | |
1077 | /* Create the simplified OCC model */ | |
1078 | object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); | |
1079 | if (local_err) { | |
1080 | error_propagate(errp, local_err); | |
1081 | return; | |
1082 | } | |
1083 | pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); | |
e997040e CLG |
1084 | } |
1085 | ||
e997040e CLG |
1086 | static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) |
1087 | { | |
1088 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1089 | PnvChipClass *k = PNV_CHIP_CLASS(klass); | |
1090 | ||
e997040e | 1091 | k->chip_type = PNV_CHIP_POWER9; |
83028a2b | 1092 | k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ |
397a79e7 | 1093 | k->cores_mask = POWER9_CORE_MASK; |
631adaff | 1094 | k->core_pir = pnv_chip_core_pir_p9; |
d35aefa9 | 1095 | k->intc_create = pnv_chip_power9_intc_create; |
04026890 | 1096 | k->isa_create = pnv_chip_power9_isa_create; |
eb859a27 | 1097 | k->dt_populate = pnv_chip_power9_dt_populate; |
d8e4aad5 | 1098 | k->pic_print_info = pnv_chip_power9_pic_print_info; |
967b7523 | 1099 | k->xscom_base = 0x00603fc00000000ull; |
e997040e | 1100 | dc->desc = "PowerNV Chip POWER9"; |
77864267 CLG |
1101 | |
1102 | device_class_set_parent_realize(dc, pnv_chip_power9_realize, | |
1103 | &k->parent_realize); | |
e997040e CLG |
1104 | } |
1105 | ||
397a79e7 CLG |
1106 | static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) |
1107 | { | |
1108 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); | |
1109 | int cores_max; | |
1110 | ||
1111 | /* | |
1112 | * No custom mask for this chip, let's use the default one from * | |
1113 | * the chip class | |
1114 | */ | |
1115 | if (!chip->cores_mask) { | |
1116 | chip->cores_mask = pcc->cores_mask; | |
1117 | } | |
1118 | ||
1119 | /* filter alien core ids ! some are reserved */ | |
1120 | if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { | |
1121 | error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", | |
1122 | chip->cores_mask); | |
1123 | return; | |
1124 | } | |
1125 | chip->cores_mask &= pcc->cores_mask; | |
1126 | ||
1127 | /* now that we have a sane layout, let check the number of cores */ | |
27d9ffd4 | 1128 | cores_max = ctpop64(chip->cores_mask); |
397a79e7 CLG |
1129 | if (chip->nr_cores > cores_max) { |
1130 | error_setg(errp, "warning: too many cores for chip ! Limit is %d", | |
1131 | cores_max); | |
1132 | return; | |
1133 | } | |
1134 | } | |
1135 | ||
77864267 | 1136 | static void pnv_chip_instance_init(Object *obj) |
967b7523 | 1137 | { |
77864267 | 1138 | PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base; |
bf5615e7 CLG |
1139 | } |
1140 | ||
51c04728 | 1141 | static void pnv_chip_core_realize(PnvChip *chip, Error **errp) |
e997040e | 1142 | { |
397a79e7 | 1143 | Error *error = NULL; |
d2fd9612 | 1144 | PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); |
40abf43f | 1145 | const char *typename = pnv_chip_core_typename(chip); |
d2fd9612 CLG |
1146 | size_t typesize = object_type_get_instance_size(typename); |
1147 | int i, core_hwid; | |
1148 | ||
1149 | if (!object_class_by_name(typename)) { | |
1150 | error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); | |
1151 | return; | |
1152 | } | |
397a79e7 | 1153 | |
d2fd9612 | 1154 | /* Cores */ |
397a79e7 CLG |
1155 | pnv_chip_core_sanitize(chip, &error); |
1156 | if (error) { | |
1157 | error_propagate(errp, error); | |
1158 | return; | |
1159 | } | |
d2fd9612 CLG |
1160 | |
1161 | chip->cores = g_malloc0(typesize * chip->nr_cores); | |
1162 | ||
1163 | for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) | |
1164 | && (i < chip->nr_cores); core_hwid++) { | |
1165 | char core_name[32]; | |
1166 | void *pnv_core = chip->cores + i * typesize; | |
c035851a | 1167 | uint64_t xscom_core_base; |
d2fd9612 CLG |
1168 | |
1169 | if (!(chip->cores_mask & (1ull << core_hwid))) { | |
1170 | continue; | |
1171 | } | |
1172 | ||
d2fd9612 | 1173 | snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); |
bc4c406c PMD |
1174 | object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, |
1175 | typename, &error_fatal, NULL); | |
d2fd9612 CLG |
1176 | object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", |
1177 | &error_fatal); | |
1178 | object_property_set_int(OBJECT(pnv_core), core_hwid, | |
1179 | CPU_CORE_PROP_CORE_ID, &error_fatal); | |
1180 | object_property_set_int(OBJECT(pnv_core), | |
1181 | pcc->core_pir(chip, core_hwid), | |
1182 | "pir", &error_fatal); | |
d35aefa9 CLG |
1183 | object_property_add_const_link(OBJECT(pnv_core), "chip", |
1184 | OBJECT(chip), &error_fatal); | |
d2fd9612 CLG |
1185 | object_property_set_bool(OBJECT(pnv_core), true, "realized", |
1186 | &error_fatal); | |
24ece072 CLG |
1187 | |
1188 | /* Each core has an XSCOM MMIO region */ | |
c035851a CLG |
1189 | if (!pnv_chip_is_power9(chip)) { |
1190 | xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); | |
1191 | } else { | |
5dad902c | 1192 | xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); |
c035851a CLG |
1193 | } |
1194 | ||
1195 | pnv_xscom_add_subregion(chip, xscom_core_base, | |
24ece072 | 1196 | &PNV_CORE(pnv_core)->xscom_regs); |
d2fd9612 CLG |
1197 | i++; |
1198 | } | |
51c04728 CLG |
1199 | } |
1200 | ||
1201 | static void pnv_chip_realize(DeviceState *dev, Error **errp) | |
1202 | { | |
1203 | PnvChip *chip = PNV_CHIP(dev); | |
1204 | Error *error = NULL; | |
1205 | ||
1206 | /* XSCOM bridge */ | |
1207 | pnv_xscom_realize(chip, &error); | |
1208 | if (error) { | |
1209 | error_propagate(errp, error); | |
1210 | return; | |
1211 | } | |
1212 | sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); | |
1213 | ||
1214 | /* Cores */ | |
1215 | pnv_chip_core_realize(chip, &error); | |
1216 | if (error) { | |
1217 | error_propagate(errp, error); | |
1218 | return; | |
1219 | } | |
e997040e CLG |
1220 | } |
1221 | ||
1222 | static Property pnv_chip_properties[] = { | |
1223 | DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), | |
1224 | DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), | |
1225 | DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), | |
397a79e7 CLG |
1226 | DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), |
1227 | DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), | |
e997040e CLG |
1228 | DEFINE_PROP_END_OF_LIST(), |
1229 | }; | |
1230 | ||
1231 | static void pnv_chip_class_init(ObjectClass *klass, void *data) | |
1232 | { | |
1233 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1234 | ||
9d169fb3 | 1235 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
e997040e CLG |
1236 | dc->realize = pnv_chip_realize; |
1237 | dc->props = pnv_chip_properties; | |
1238 | dc->desc = "PowerNV Chip"; | |
1239 | } | |
1240 | ||
54f59d78 CLG |
1241 | static ICSState *pnv_ics_get(XICSFabric *xi, int irq) |
1242 | { | |
b168a138 | 1243 | PnvMachineState *pnv = PNV_MACHINE(xi); |
54f59d78 CLG |
1244 | int i; |
1245 | ||
1246 | for (i = 0; i < pnv->num_chips; i++) { | |
77864267 CLG |
1247 | Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); |
1248 | ||
1249 | if (ics_valid_irq(&chip8->psi.ics, irq)) { | |
1250 | return &chip8->psi.ics; | |
54f59d78 CLG |
1251 | } |
1252 | } | |
1253 | return NULL; | |
1254 | } | |
1255 | ||
1256 | static void pnv_ics_resend(XICSFabric *xi) | |
1257 | { | |
b168a138 | 1258 | PnvMachineState *pnv = PNV_MACHINE(xi); |
54f59d78 CLG |
1259 | int i; |
1260 | ||
1261 | for (i = 0; i < pnv->num_chips; i++) { | |
77864267 CLG |
1262 | Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); |
1263 | ics_resend(&chip8->psi.ics); | |
54f59d78 CLG |
1264 | } |
1265 | } | |
1266 | ||
36fc6f08 CLG |
1267 | static ICPState *pnv_icp_get(XICSFabric *xi, int pir) |
1268 | { | |
1269 | PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); | |
1270 | ||
956b8f46 | 1271 | return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; |
36fc6f08 CLG |
1272 | } |
1273 | ||
47fea43a CLG |
1274 | static void pnv_pic_print_info(InterruptStatsProvider *obj, |
1275 | Monitor *mon) | |
1276 | { | |
b168a138 | 1277 | PnvMachineState *pnv = PNV_MACHINE(obj); |
54f59d78 | 1278 | int i; |
47fea43a CLG |
1279 | CPUState *cs; |
1280 | ||
1281 | CPU_FOREACH(cs) { | |
1282 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1283 | ||
d8e4aad5 CLG |
1284 | if (pnv_chip_is_power9(pnv->chips[0])) { |
1285 | xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); | |
1286 | } else { | |
1287 | icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); | |
1288 | } | |
47fea43a | 1289 | } |
54f59d78 CLG |
1290 | |
1291 | for (i = 0; i < pnv->num_chips; i++) { | |
d8e4aad5 | 1292 | PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); |
54f59d78 | 1293 | } |
47fea43a CLG |
1294 | } |
1295 | ||
e997040e CLG |
1296 | static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, |
1297 | void *opaque, Error **errp) | |
1298 | { | |
b168a138 | 1299 | visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); |
e997040e CLG |
1300 | } |
1301 | ||
1302 | static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, | |
1303 | void *opaque, Error **errp) | |
1304 | { | |
b168a138 | 1305 | PnvMachineState *pnv = PNV_MACHINE(obj); |
e997040e CLG |
1306 | uint32_t num_chips; |
1307 | Error *local_err = NULL; | |
1308 | ||
1309 | visit_type_uint32(v, name, &num_chips, &local_err); | |
1310 | if (local_err) { | |
1311 | error_propagate(errp, local_err); | |
1312 | return; | |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * TODO: should we decide on how many chips we can create based | |
1317 | * on #cores and Venice vs. Murano vs. Naples chip type etc..., | |
1318 | */ | |
1319 | if (!is_power_of_2(num_chips) || num_chips > 4) { | |
1320 | error_setg(errp, "invalid number of chips: '%d'", num_chips); | |
1321 | return; | |
1322 | } | |
1323 | ||
1324 | pnv->num_chips = num_chips; | |
1325 | } | |
1326 | ||
77864267 | 1327 | static void pnv_machine_instance_init(Object *obj) |
e997040e | 1328 | { |
b168a138 | 1329 | PnvMachineState *pnv = PNV_MACHINE(obj); |
e997040e CLG |
1330 | pnv->num_chips = 1; |
1331 | } | |
1332 | ||
b168a138 | 1333 | static void pnv_machine_class_props_init(ObjectClass *oc) |
e997040e | 1334 | { |
1e507bb0 | 1335 | object_class_property_add(oc, "num-chips", "uint32", |
e997040e CLG |
1336 | pnv_get_num_chips, pnv_set_num_chips, |
1337 | NULL, NULL, NULL); | |
1338 | object_class_property_set_description(oc, "num-chips", | |
1339 | "Specifies the number of processor chips", | |
1340 | NULL); | |
9e933f4a BH |
1341 | } |
1342 | ||
b168a138 | 1343 | static void pnv_machine_class_init(ObjectClass *oc, void *data) |
9e933f4a BH |
1344 | { |
1345 | MachineClass *mc = MACHINE_CLASS(oc); | |
36fc6f08 | 1346 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
47fea43a | 1347 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
9e933f4a BH |
1348 | |
1349 | mc->desc = "IBM PowerNV (Non-Virtualized)"; | |
b168a138 CLG |
1350 | mc->init = pnv_init; |
1351 | mc->reset = pnv_reset; | |
9e933f4a | 1352 | mc->max_cpus = MAX_CPUS; |
4a12c699 | 1353 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
9e933f4a BH |
1354 | mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for |
1355 | * storage */ | |
1356 | mc->no_parallel = 1; | |
1357 | mc->default_boot_order = NULL; | |
d23b6caa | 1358 | mc->default_ram_size = 1 * GiB; |
36fc6f08 | 1359 | xic->icp_get = pnv_icp_get; |
54f59d78 CLG |
1360 | xic->ics_get = pnv_ics_get; |
1361 | xic->ics_resend = pnv_ics_resend; | |
47fea43a | 1362 | ispc->print_info = pnv_pic_print_info; |
e997040e | 1363 | |
b168a138 | 1364 | pnv_machine_class_props_init(oc); |
9e933f4a BH |
1365 | } |
1366 | ||
77864267 CLG |
1367 | #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ |
1368 | { \ | |
1369 | .name = type, \ | |
1370 | .class_init = class_initfn, \ | |
1371 | .parent = TYPE_PNV8_CHIP, \ | |
1372 | } | |
1373 | ||
1374 | #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ | |
1375 | { \ | |
1376 | .name = type, \ | |
1377 | .class_init = class_initfn, \ | |
1378 | .parent = TYPE_PNV9_CHIP, \ | |
beba5c0f IM |
1379 | } |
1380 | ||
1381 | static const TypeInfo types[] = { | |
1382 | { | |
b168a138 | 1383 | .name = TYPE_PNV_MACHINE, |
beba5c0f IM |
1384 | .parent = TYPE_MACHINE, |
1385 | .instance_size = sizeof(PnvMachineState), | |
77864267 | 1386 | .instance_init = pnv_machine_instance_init, |
b168a138 | 1387 | .class_init = pnv_machine_class_init, |
beba5c0f IM |
1388 | .interfaces = (InterfaceInfo[]) { |
1389 | { TYPE_XICS_FABRIC }, | |
1390 | { TYPE_INTERRUPT_STATS_PROVIDER }, | |
1391 | { }, | |
1392 | }, | |
36fc6f08 | 1393 | }, |
beba5c0f IM |
1394 | { |
1395 | .name = TYPE_PNV_CHIP, | |
1396 | .parent = TYPE_SYS_BUS_DEVICE, | |
1397 | .class_init = pnv_chip_class_init, | |
77864267 | 1398 | .instance_init = pnv_chip_instance_init, |
beba5c0f IM |
1399 | .instance_size = sizeof(PnvChip), |
1400 | .class_size = sizeof(PnvChipClass), | |
1401 | .abstract = true, | |
1402 | }, | |
77864267 CLG |
1403 | |
1404 | /* | |
1405 | * P9 chip and variants | |
1406 | */ | |
1407 | { | |
1408 | .name = TYPE_PNV9_CHIP, | |
1409 | .parent = TYPE_PNV_CHIP, | |
1410 | .instance_init = pnv_chip_power9_instance_init, | |
1411 | .instance_size = sizeof(Pnv9Chip), | |
1412 | }, | |
1413 | DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), | |
1414 | ||
1415 | /* | |
1416 | * P8 chip and variants | |
1417 | */ | |
1418 | { | |
1419 | .name = TYPE_PNV8_CHIP, | |
1420 | .parent = TYPE_PNV_CHIP, | |
1421 | .instance_init = pnv_chip_power8_instance_init, | |
1422 | .instance_size = sizeof(Pnv8Chip), | |
1423 | }, | |
1424 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), | |
1425 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), | |
1426 | DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, | |
1427 | pnv_chip_power8nvl_class_init), | |
9e933f4a BH |
1428 | }; |
1429 | ||
beba5c0f | 1430 | DEFINE_TYPES(types) |