[mirror_qemu.git] / hw / ppc / pnv_core.c

/*
 * QEMU PowerPC PowerNV CPU Core model
 *
 * Copyright (c) 2016, IBM Corporation.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public License
 * as published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/xics.h"

static const char *pnv_core_cpu_typename(PnvCore *pc)
{
    const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
    int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
    char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
    const char *cpu_type = object_class_get_name(object_class_by_name(s));
    g_free(s);
    return cpu_type;
}

static void pnv_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;

    cpu_reset(cs);

    /*
     * the skiboot firmware elects a primary thread to initialize the
     * system and it can be any.
     */
    env->gpr[3] = PNV_FDT_ADDR;
    env->nip = 0x10;
    env->msr |= MSR_HVB; /* Hypervisor mode */
}

/*
 * These values are read by the PowerNV HW monitors under Linux
 */
#define PNV_XSCOM_EX_DTS_RESULT0     0x50000
#define PNV_XSCOM_EX_DTS_RESULT1     0x50001

static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
                                           unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    /* The result should be 38 C */
    switch (offset) {
    case PNV_XSCOM_EX_DTS_RESULT0:
        val = 0x26f024f023f0000ull;
        break;
    case PNV_XSCOM_EX_DTS_RESULT1:
        val = 0x24f000000000000ull;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
                  addr);
    }

    return val;
}

static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                        unsigned int width)
{
    qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
                  addr);
}

static const MemoryRegionOps pnv_core_power8_xscom_ops = {
    .read = pnv_core_power8_xscom_read,
    .write = pnv_core_power8_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};


/*
 * POWER9 core controls
 */
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a

static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
                                           unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    /* The result should be 38 C */
    switch (offset) {
    case PNV_XSCOM_EX_DTS_RESULT0:
        val = 0x26f024f023f0000ull;
        break;
    case PNV_XSCOM_EX_DTS_RESULT1:
        val = 0x24f000000000000ull;
        break;
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
        val = 0x0;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
                  addr);
    }

    return val;
}

static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                        unsigned int width)
{
    uint32_t offset = addr >> 3;

    switch (offset) {
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
                      addr);
    }
}

static const MemoryRegionOps pnv_core_power9_xscom_ops = {
    .read = pnv_core_power9_xscom_read,
    .write = pnv_core_power9_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    int core_pir;
    int thread_index = 0; /* TODO: TCG supports only one thread */
    ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
    Error *local_err = NULL;
    PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);

    object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    pcc->intc_create(chip, cpu, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);

    /*
     * The PIR of a thread is the core PIR + the thread index. We will
     * need to find a way to get the thread index when TCG supports
     * more than 1. We could use the object name ?
     */
    pir->default_value = core_pir + thread_index;

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);

    qemu_register_reset(pnv_cpu_reset, cpu);
}

static void pnv_core_realize(DeviceState *dev, Error **errp)
{
    PnvCore *pc = PNV_CORE(OBJECT(dev));
    PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    const char *typename = pnv_core_cpu_typename(pc);
    Error *local_err = NULL;
    void *obj;
    int i, j;
    char name[32];
    Object *chip;

    chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
    if (!chip) {
        error_propagate_prepend(errp, local_err,
                                "required link 'chip' not found: ");
        return;
    }

    pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        PowerPCCPU *cpu;

        obj = object_new(typename);
        cpu = POWERPC_CPU(obj);

        pc->threads[i] = POWERPC_CPU(obj);

        snprintf(name, sizeof(name), "thread[%d]", i);
        object_property_add_child(OBJECT(pc), name, obj, &error_abort);
        object_property_add_alias(obj, "core-pir", OBJECT(pc),
                                  "pir", &error_abort);

        cpu->machine_data = g_new0(PnvCPUState, 1);

        object_unref(obj);
    }

    for (j = 0; j < cc->nr_threads; j++) {
        pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
        if (local_err) {
            goto err;
        }
    }

    snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
    pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
                          pc, name, PNV_XSCOM_EX_SIZE);
    return;

err:
    while (--i >= 0) {
        obj = OBJECT(pc->threads[i]);
        object_unparent(obj);
    }
    g_free(pc->threads);
    error_propagate(errp, local_err);
}

static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);

    qemu_unregister_reset(pnv_cpu_reset, cpu);
    object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
    cpu_remove_sync(CPU(cpu));
    cpu->machine_data = NULL;
    g_free(pnv_cpu);
    object_unparent(OBJECT(cpu));
}

static void pnv_core_unrealize(DeviceState *dev, Error **errp)
{
    PnvCore *pc = PNV_CORE(dev);
    CPUCore *cc = CPU_CORE(dev);
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        pnv_unrealize_vcpu(pc->threads[i]);
    }
    g_free(pc->threads);
}

static Property pnv_core_properties[] = {
    DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
{
    PnvCoreClass *pcc = PNV_CORE_CLASS(oc);

    pcc->xscom_ops = &pnv_core_power8_xscom_ops;
}

static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
{
    PnvCoreClass *pcc = PNV_CORE_CLASS(oc);

    pcc->xscom_ops = &pnv_core_power9_xscom_ops;
}

static void pnv_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = pnv_core_realize;
    dc->unrealize = pnv_core_unrealize;
    dc->props = pnv_core_properties;
}

#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
    {                                           \
        .parent = TYPE_PNV_CORE,                \
        .name = PNV_CORE_TYPE_NAME(cpu_model),  \
        .class_init = pnv_core_##family##_class_init, \
    }

static const TypeInfo pnv_core_infos[] = {
    {
        .name           = TYPE_PNV_CORE,
        .parent         = TYPE_CPU_CORE,
        .instance_size  = sizeof(PnvCore),
        .class_size     = sizeof(PnvCoreClass),
        .class_init = pnv_core_class_init,
        .abstract       = true,
    },
    DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
    DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
    DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
    DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
};

DEFINE_TYPES(pnv_core_infos)

/*
 * POWER9 Quads
 */

#define P9X_EX_NCU_SPEC_BAR                     0x11010

static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
                                    unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = -1;

    switch (offset) {
    case P9X_EX_NCU_SPEC_BAR:
    case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
        val = 0;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
                      offset);
    }

    return val;
}

static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                 unsigned int width)
{
    uint32_t offset = addr >> 3;

    switch (offset) {
    case P9X_EX_NCU_SPEC_BAR:
    case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
                  offset);
    }
}

static const MemoryRegionOps pnv_quad_xscom_ops = {
    .read = pnv_quad_xscom_read,
    .write = pnv_quad_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
    PnvQuad *eq = PNV_QUAD(dev);
    char name[32];

    snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
                          eq, name, PNV9_XSCOM_EQ_SIZE);
}

static Property pnv_quad_properties[] = {
    DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = pnv_quad_realize;
    dc->props = pnv_quad_properties;
}

static const TypeInfo pnv_quad_info = {
    .name          = TYPE_PNV_QUAD,
    .parent        = TYPE_DEVICE,
    .instance_size = sizeof(PnvQuad),
    .class_init    = pnv_quad_class_init,
};

static void pnv_core_register_types(void)
{
    type_register_static(&pnv_quad_info);
}

type_init(pnv_core_register_types)
Commit	Line	Data
d2fd9612 CLG	1	/*
	2	* QEMU PowerPC PowerNV CPU Core model
	3	*
	4	* Copyright (c) 2016, IBM Corporation.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public License
	8	* as published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
0b8fa32f	19
d2fd9612 CLG	20	#include "qemu/osdep.h"
	21	#include "sysemu/sysemu.h"
	22	#include "qapi/error.h"
24ece072	23	#include "qemu/log.h"
0b8fa32f	24	#include "qemu/module.h"
fcf5ef2a	25	#include "target/ppc/cpu.h"
d2fd9612 CLG	26	#include "hw/ppc/ppc.h"
	27	#include "hw/ppc/pnv.h"
	28	#include "hw/ppc/pnv_core.h"
ec575aa0	29	#include "hw/ppc/pnv_xscom.h"
960fbd29	30	#include "hw/ppc/xics.h"
d2fd9612	31
35bdb9de IM	32	static const char pnv_core_cpu_typename(PnvCore pc)
	33	{
	34	const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
	35	int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
	36	char s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.s"), len, core_type);
	37	const char *cpu_type = object_class_get_name(object_class_by_name(s));
	38	g_free(s);
	39	return cpu_type;
	40	}
	41
b168a138	42	static void pnv_cpu_reset(void *opaque)
d2fd9612 CLG	43	{
	44	PowerPCCPU *cpu = opaque;
	45	CPUState *cs = CPU(cpu);
	46	CPUPPCState *env = &cpu->env;
	47
	48	cpu_reset(cs);
	49
	50	/*
	51	* the skiboot firmware elects a primary thread to initialize the
	52	* system and it can be any.
	53	*/
	54	env->gpr[3] = PNV_FDT_ADDR;
	55	env->nip = 0x10;
	56	env->msr \|= MSR_HVB; /* Hypervisor mode */
	57	}
	58
24ece072 CLG	59	/*
	60	* These values are read by the PowerNV HW monitors under Linux
	61	*/
	62	#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
	63	#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
	64
90ef386c CLG	65	static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
90ef386c CLG	66	unsigned int width)
24ece072 CLG	67	{
	68	uint32_t offset = addr >> 3;
	69	uint64_t val = 0;
	70
	71	/* The result should be 38 C */
	72	switch (offset) {
	73	case PNV_XSCOM_EX_DTS_RESULT0:
	74	val = 0x26f024f023f0000ull;
	75	break;
	76	case PNV_XSCOM_EX_DTS_RESULT1:
	77	val = 0x24f000000000000ull;
	78	break;
	79	default:
c7e71a18	80	qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
24ece072 CLG	81	addr);
	82	}
	83
	84	return val;
	85	}
	86
90ef386c CLG	87	static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
90ef386c CLG	88	unsigned int width)
24ece072	89	{
c7e71a18	90	qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
24ece072 CLG	91	addr);
	92	}
	93
90ef386c CLG	94	static const MemoryRegionOps pnv_core_power8_xscom_ops = {
	95	.read = pnv_core_power8_xscom_read,
	96	.write = pnv_core_power8_xscom_write,
	97	.valid.min_access_size = 8,
	98	.valid.max_access_size = 8,
	99	.impl.min_access_size = 8,
	100	.impl.max_access_size = 8,
	101	.endianness = DEVICE_BIG_ENDIAN,
	102	};
	103
	104
	105	/*
	106	* POWER9 core controls
	107	*/
	108	#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
	109	#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
	110
	111	static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
	112	unsigned int width)
	113	{
	114	uint32_t offset = addr >> 3;
	115	uint64_t val = 0;
	116
	117	/* The result should be 38 C */
	118	switch (offset) {
	119	case PNV_XSCOM_EX_DTS_RESULT0:
	120	val = 0x26f024f023f0000ull;
	121	break;
	122	case PNV_XSCOM_EX_DTS_RESULT1:
	123	val = 0x24f000000000000ull;
	124	break;
	125	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
	126	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
	127	val = 0x0;
	128	break;
	129	default:
	130	qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
	131	addr);
	132	}
	133
	134	return val;
	135	}
	136
	137	static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
	138	unsigned int width)
	139	{
	140	uint32_t offset = addr >> 3;
	141
	142	switch (offset) {
	143	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
	144	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
	145	break;
	146	default:
	147	qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
	148	addr);
	149	}
	150	}
	151
	152	static const MemoryRegionOps pnv_core_power9_xscom_ops = {
	153	.read = pnv_core_power9_xscom_read,
	154	.write = pnv_core_power9_xscom_write,
24ece072 CLG	155	.valid.min_access_size = 8,
	156	.valid.max_access_size = 8,
	157	.impl.min_access_size = 8,
	158	.impl.max_access_size = 8,
	159	.endianness = DEVICE_BIG_ENDIAN,
	160	};
	161
d35aefa9	162	static void pnv_realize_vcpu(PowerPCCPU cpu, PnvChip chip, Error **errp)
d2fd9612	163	{
3a247521 DG	164	CPUPPCState *env = &cpu->env;
	165	int core_pir;
	166	int thread_index = 0; /* TODO: TCG supports only one thread */
	167	ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
d2fd9612	168	Error *local_err = NULL;
d35aefa9	169	PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
960fbd29	170
3a247521	171	object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
960fbd29 CLG	172	if (local_err) {
	173	error_propagate(errp, local_err);
	174	return;
	175	}
d2fd9612	176
8fa1f4ef	177	pcc->intc_create(chip, cpu, &local_err);
d2fd9612 CLG	178	if (local_err) {
	179	error_propagate(errp, local_err);
	180	return;
	181	}
	182
3a247521 DG	183	core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
	184
	185	/*
	186	* The PIR of a thread is the core PIR + the thread index. We will
	187	* need to find a way to get the thread index when TCG supports
	188	* more than 1. We could use the object name ?
	189	*/
	190	pir->default_value = core_pir + thread_index;
	191
	192	/* Set time-base frequency to 512 MHz */
	193	cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
	194
	195	qemu_register_reset(pnv_cpu_reset, cpu);
d2fd9612 CLG	196	}
	197
	198	static void pnv_core_realize(DeviceState dev, Error *errp)
	199	{
	200	PnvCore *pc = PNV_CORE(OBJECT(dev));
90ef386c	201	PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
d2fd9612	202	CPUCore *cc = CPU_CORE(OBJECT(dev));
35bdb9de	203	const char *typename = pnv_core_cpu_typename(pc);
d2fd9612 CLG	204	Error *local_err = NULL;
	205	void *obj;
	206	int i, j;
	207	char name[32];
d35aefa9	208	Object *chip;
960fbd29	209
d35aefa9 CLG	210	chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
d35aefa9 CLG	211	if (!chip) {
4b576648 MA	212	error_propagate_prepend(errp, local_err,
4b576648 MA	213	"required link 'chip' not found: ");
56f68439	214	return;
960fbd29	215	}
d2fd9612	216
08304a86	217	pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
d2fd9612	218	for (i = 0; i < cc->nr_threads; i++) {
8907fc25 CLG	219	PowerPCCPU *cpu;
8907fc25 CLG	220
08304a86	221	obj = object_new(typename);
8907fc25	222	cpu = POWERPC_CPU(obj);
d2fd9612	223
08304a86	224	pc->threads[i] = POWERPC_CPU(obj);
d2fd9612 CLG	225
d2fd9612 CLG	226	snprintf(name, sizeof(name), "thread[%d]", i);
937c2146	227	object_property_add_child(OBJECT(pc), name, obj, &error_abort);
d2fd9612	228	object_property_add_alias(obj, "core-pir", OBJECT(pc),
937c2146	229	"pir", &error_abort);
8907fc25 CLG	230
	231	cpu->machine_data = g_new0(PnvCPUState, 1);
	232
d2fd9612 CLG	233	object_unref(obj);
	234	}
	235
	236	for (j = 0; j < cc->nr_threads; j++) {
d35aefa9	237	pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
d2fd9612 CLG	238	if (local_err) {
	239	goto err;
	240	}
	241	}
24ece072 CLG	242
24ece072 CLG	243	snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
90ef386c	244	pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
c035851a	245	pc, name, PNV_XSCOM_EX_SIZE);
d2fd9612 CLG	246	return;
	247
	248	err:
	249	while (--i >= 0) {
08304a86	250	obj = OBJECT(pc->threads[i]);
d2fd9612 CLG	251	object_unparent(obj);
	252	}
	253	g_free(pc->threads);
	254	error_propagate(errp, local_err);
	255	}
	256
5e22e292 DG	257	static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
5e22e292 DG	258	{
8907fc25 CLG	259	PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8907fc25 CLG	260
5e22e292	261	qemu_unregister_reset(pnv_cpu_reset, cpu);
956b8f46	262	object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
5e22e292	263	cpu_remove_sync(CPU(cpu));
8907fc25 CLG	264	cpu->machine_data = NULL;
8907fc25 CLG	265	g_free(pnv_cpu);
5e22e292 DG	266	object_unparent(OBJECT(cpu));
	267	}
	268
	269	static void pnv_core_unrealize(DeviceState dev, Error *errp)
	270	{
	271	PnvCore *pc = PNV_CORE(dev);
	272	CPUCore *cc = CPU_CORE(dev);
	273	int i;
	274
	275	for (i = 0; i < cc->nr_threads; i++) {
	276	pnv_unrealize_vcpu(pc->threads[i]);
	277	}
	278	g_free(pc->threads);
	279	}
	280
d2fd9612 CLG	281	static Property pnv_core_properties[] = {
	282	DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
	283	DEFINE_PROP_END_OF_LIST(),
	284	};
	285
90ef386c CLG	286	static void pnv_core_power8_class_init(ObjectClass oc, void data)
	287	{
	288	PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
	289
	290	pcc->xscom_ops = &pnv_core_power8_xscom_ops;
	291	}
	292
	293	static void pnv_core_power9_class_init(ObjectClass oc, void data)
	294	{
	295	PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
	296
	297	pcc->xscom_ops = &pnv_core_power9_xscom_ops;
	298	}
	299
d2fd9612 CLG	300	static void pnv_core_class_init(ObjectClass oc, void data)
	301	{
	302	DeviceClass *dc = DEVICE_CLASS(oc);
d2fd9612 CLG	303
d2fd9612 CLG	304	dc->realize = pnv_core_realize;
5e22e292	305	dc->unrealize = pnv_core_unrealize;
d2fd9612	306	dc->props = pnv_core_properties;
d2fd9612 CLG	307	}
d2fd9612 CLG	308
90ef386c	309	#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
7383af1e IM	310	{ \
	311	.parent = TYPE_PNV_CORE, \
	312	.name = PNV_CORE_TYPE_NAME(cpu_model), \
90ef386c	313	.class_init = pnv_core_##family##_class_init, \
d2fd9612	314	}
d2fd9612	315
7383af1e IM	316	static const TypeInfo pnv_core_infos[] = {
	317	{
	318	.name = TYPE_PNV_CORE,
	319	.parent = TYPE_CPU_CORE,
	320	.instance_size = sizeof(PnvCore),
	321	.class_size = sizeof(PnvCoreClass),
	322	.class_init = pnv_core_class_init,
	323	.abstract = true,
	324	},
90ef386c CLG	325	DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
	326	DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
	327	DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
	328	DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
7383af1e	329	};
d2fd9612	330
7383af1e	331	DEFINE_TYPES(pnv_core_infos)
5dad902c CLG	332
	333	/*
	334	* POWER9 Quads
	335	*/
	336
	337	#define P9X_EX_NCU_SPEC_BAR 0x11010
	338
	339	static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
	340	unsigned int width)
	341	{
	342	uint32_t offset = addr >> 3;
	343	uint64_t val = -1;
	344
	345	switch (offset) {
	346	case P9X_EX_NCU_SPEC_BAR:
	347	case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
	348	val = 0;
	349	break;
	350	default:
	351	qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
	352	offset);
	353	}
	354
	355	return val;
	356	}
	357
	358	static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
	359	unsigned int width)
	360	{
	361	uint32_t offset = addr >> 3;
	362
	363	switch (offset) {
	364	case P9X_EX_NCU_SPEC_BAR:
	365	case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
	366	break;
	367	default:
	368	qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
	369	offset);
	370	}
	371	}
	372
	373	static const MemoryRegionOps pnv_quad_xscom_ops = {
	374	.read = pnv_quad_xscom_read,
	375	.write = pnv_quad_xscom_write,
	376	.valid.min_access_size = 8,
	377	.valid.max_access_size = 8,
	378	.impl.min_access_size = 8,
	379	.impl.max_access_size = 8,
	380	.endianness = DEVICE_BIG_ENDIAN,
	381	};
	382
	383	static void pnv_quad_realize(DeviceState dev, Error *errp)
	384	{
	385	PnvQuad *eq = PNV_QUAD(dev);
	386	char name[32];
	387
	388	snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
	389	pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
	390	eq, name, PNV9_XSCOM_EQ_SIZE);
	391	}
	392
	393	static Property pnv_quad_properties[] = {
	394	DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
	395	DEFINE_PROP_END_OF_LIST(),
396	};
397
398	static void pnv_quad_class_init(ObjectClass oc, void data)
399	{
400	DeviceClass *dc = DEVICE_CLASS(oc);
401
402	dc->realize = pnv_quad_realize;
403	dc->props = pnv_quad_properties;
404	}
405
406	static const TypeInfo pnv_quad_info = {
407	.name = TYPE_PNV_QUAD,
408	.parent = TYPE_DEVICE,
409	.instance_size = sizeof(PnvQuad),
410	.class_init = pnv_quad_class_init,
411	};
412
413	static void pnv_core_register_types(void)
414	{
415	type_register_static(&pnv_quad_info);
416	}
417
418	type_init(pnv_core_register_types)