[mirror_qemu.git] / hw / ppc / pnv_occ.c

/*
 * QEMU PowerPC PowerNV Emulation of a few OCC related registers
 *
 * Copyright (c) 2015-2017, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "sysemu/sysemu.h"
#include "target/ppc/cpu.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"

#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/pnv_occ.h"

#define OCB_OCI_OCCMISC         0x4020
#define OCB_OCI_OCCMISC_AND     0x4021
#define OCB_OCI_OCCMISC_OR      0x4022

static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
{
    bool irq_state;
    PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);

    val &= 0xffff000000000000ull;

    occ->occmisc = val;
    irq_state = !!(val >> 63);
    pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
}

static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
                                          unsigned size)
{
    PnvOCC *occ = PNV_OCC(opaque);
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    switch (offset) {
    case OCB_OCI_OCCMISC:
        val = occ->occmisc;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
                      HWADDR_PRIx "\n", addr >> 3);
    }
    return val;
}

static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
                                       uint64_t val, unsigned size)
{
    PnvOCC *occ = PNV_OCC(opaque);
    uint32_t offset = addr >> 3;

    switch (offset) {
    case OCB_OCI_OCCMISC_AND:
        pnv_occ_set_misc(occ, occ->occmisc & val);
        break;
    case OCB_OCI_OCCMISC_OR:
        pnv_occ_set_misc(occ, occ->occmisc | val);
        break;
    case OCB_OCI_OCCMISC:
        pnv_occ_set_misc(occ, val);
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
                      HWADDR_PRIx "\n", addr >> 3);
    }
}

static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
    .read = pnv_occ_power8_xscom_read,
    .write = pnv_occ_power8_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
{
    PnvOCCClass *poc = PNV_OCC_CLASS(klass);

    poc->xscom_size = PNV_XSCOM_OCC_SIZE;
    poc->xscom_ops = &pnv_occ_power8_xscom_ops;
    poc->psi_irq = PSIHB_IRQ_OCC;
}

static const TypeInfo pnv_occ_power8_type_info = {
    .name          = TYPE_PNV8_OCC,
    .parent        = TYPE_PNV_OCC,
    .instance_size = sizeof(PnvOCC),
    .class_init    = pnv_occ_power8_class_init,
};

#define P9_OCB_OCI_OCCMISC              0x6080
#define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
#define P9_OCB_OCI_OCCMISC_OR           0x6082


static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
                                          unsigned size)
{
    PnvOCC *occ = PNV_OCC(opaque);
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    switch (offset) {
    case P9_OCB_OCI_OCCMISC:
        val = occ->occmisc;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
                      HWADDR_PRIx "\n", addr >> 3);
    }
    return val;
}

static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
                                       uint64_t val, unsigned size)
{
    PnvOCC *occ = PNV_OCC(opaque);
    uint32_t offset = addr >> 3;

    switch (offset) {
    case P9_OCB_OCI_OCCMISC_CLEAR:
        pnv_occ_set_misc(occ, 0);
        break;
    case P9_OCB_OCI_OCCMISC_OR:
        pnv_occ_set_misc(occ, occ->occmisc | val);
        break;
    case P9_OCB_OCI_OCCMISC:
        pnv_occ_set_misc(occ, val);
       break;
    default:
        qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
                      HWADDR_PRIx "\n", addr >> 3);
    }
}

static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
    .read = pnv_occ_power9_xscom_read,
    .write = pnv_occ_power9_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
{
    PnvOCCClass *poc = PNV_OCC_CLASS(klass);

    poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
    poc->xscom_ops = &pnv_occ_power9_xscom_ops;
    poc->psi_irq = PSIHB9_IRQ_OCC;
}

static const TypeInfo pnv_occ_power9_type_info = {
    .name          = TYPE_PNV9_OCC,
    .parent        = TYPE_PNV_OCC,
    .instance_size = sizeof(PnvOCC),
    .class_init    = pnv_occ_power9_class_init,
};

static void pnv_occ_realize(DeviceState *dev, Error **errp)
{
    PnvOCC *occ = PNV_OCC(dev);
    PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
    Object *obj;
    Error *local_err = NULL;

    occ->occmisc = 0;

    obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
    if (!obj) {
        error_propagate(errp, local_err);
        error_prepend(errp, "required link 'psi' not found: ");
        return;
    }
    occ->psi = PNV_PSI(obj);

    /* XScom region for OCC registers */
    pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
                          occ, "xscom-occ", poc->xscom_size);
}

static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pnv_occ_realize;
    dc->desc = "PowerNV OCC Controller";
}

static const TypeInfo pnv_occ_type_info = {
    .name          = TYPE_PNV_OCC,
    .parent        = TYPE_DEVICE,
    .instance_size = sizeof(PnvOCC),
    .class_init    = pnv_occ_class_init,
    .class_size    = sizeof(PnvOCCClass),
    .abstract      = true,
};

static void pnv_occ_register_types(void)
{
    type_register_static(&pnv_occ_type_info);
    type_register_static(&pnv_occ_power8_type_info);
    type_register_static(&pnv_occ_power9_type_info);
}

type_init(pnv_occ_register_types);
Commit	Line	Data
0722d05a BH	1	/*
	2	* QEMU PowerPC PowerNV Emulation of a few OCC related registers
	3	*
	4	* Copyright (c) 2015-2017, IBM Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License, version 2, as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include "qemu/osdep.h"
	20	#include "hw/hw.h"
	21	#include "sysemu/sysemu.h"
	22	#include "target/ppc/cpu.h"
	23	#include "qapi/error.h"
	24	#include "qemu/log.h"
0b8fa32f	25	#include "qemu/module.h"
0722d05a BH	26
	27	#include "hw/ppc/pnv.h"
	28	#include "hw/ppc/pnv_xscom.h"
	29	#include "hw/ppc/pnv_occ.h"
	30
	31	#define OCB_OCI_OCCMISC 0x4020
	32	#define OCB_OCI_OCCMISC_AND 0x4021
	33	#define OCB_OCI_OCCMISC_OR 0x4022
	34
	35	static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
	36	{
	37	bool irq_state;
3233838c	38	PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
0722d05a BH	39
	40	val &= 0xffff000000000000ull;
	41
	42	occ->occmisc = val;
	43	irq_state = !!(val >> 63);
3233838c	44	pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
0722d05a BH	45	}
0722d05a BH	46
3233838c CLG	47	static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
3233838c CLG	48	unsigned size)
0722d05a BH	49	{
	50	PnvOCC *occ = PNV_OCC(opaque);
	51	uint32_t offset = addr >> 3;
	52	uint64_t val = 0;
	53
	54	switch (offset) {
	55	case OCB_OCI_OCCMISC:
	56	val = occ->occmisc;
	57	break;
	58	default:
	59	qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
3233838c	60	HWADDR_PRIx "\n", addr >> 3);
0722d05a BH	61	}
	62	return val;
	63	}
	64
3233838c CLG	65	static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
3233838c CLG	66	uint64_t val, unsigned size)
0722d05a BH	67	{
	68	PnvOCC *occ = PNV_OCC(opaque);
	69	uint32_t offset = addr >> 3;
	70
	71	switch (offset) {
	72	case OCB_OCI_OCCMISC_AND:
	73	pnv_occ_set_misc(occ, occ->occmisc & val);
	74	break;
	75	case OCB_OCI_OCCMISC_OR:
	76	pnv_occ_set_misc(occ, occ->occmisc \| val);
	77	break;
	78	case OCB_OCI_OCCMISC:
	79	pnv_occ_set_misc(occ, val);
	80	break;
	81	default:
	82	qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
3233838c	83	HWADDR_PRIx "\n", addr >> 3);
0722d05a BH	84	}
	85	}
	86
3233838c CLG	87	static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
	88	.read = pnv_occ_power8_xscom_read,
	89	.write = pnv_occ_power8_xscom_write,
0722d05a BH	90	.valid.min_access_size = 8,
	91	.valid.max_access_size = 8,
	92	.impl.min_access_size = 8,
	93	.impl.max_access_size = 8,
	94	.endianness = DEVICE_BIG_ENDIAN,
	95	};
	96
3233838c CLG	97	static void pnv_occ_power8_class_init(ObjectClass klass, void data)
	98	{
	99	PnvOCCClass *poc = PNV_OCC_CLASS(klass);
	100
	101	poc->xscom_size = PNV_XSCOM_OCC_SIZE;
	102	poc->xscom_ops = &pnv_occ_power8_xscom_ops;
	103	poc->psi_irq = PSIHB_IRQ_OCC;
	104	}
	105
	106	static const TypeInfo pnv_occ_power8_type_info = {
	107	.name = TYPE_PNV8_OCC,
	108	.parent = TYPE_PNV_OCC,
	109	.instance_size = sizeof(PnvOCC),
	110	.class_init = pnv_occ_power8_class_init,
	111	};
0722d05a	112
6598a70d CLG	113	#define P9_OCB_OCI_OCCMISC 0x6080
	114	#define P9_OCB_OCI_OCCMISC_CLEAR 0x6081
	115	#define P9_OCB_OCI_OCCMISC_OR 0x6082
	116
	117
	118	static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
	119	unsigned size)
	120	{
	121	PnvOCC *occ = PNV_OCC(opaque);
	122	uint32_t offset = addr >> 3;
	123	uint64_t val = 0;
	124
	125	switch (offset) {
	126	case P9_OCB_OCI_OCCMISC:
	127	val = occ->occmisc;
	128	break;
	129	default:
	130	qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
	131	HWADDR_PRIx "\n", addr >> 3);
	132	}
	133	return val;
	134	}
	135
	136	static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
	137	uint64_t val, unsigned size)
	138	{
	139	PnvOCC *occ = PNV_OCC(opaque);
	140	uint32_t offset = addr >> 3;
	141
	142	switch (offset) {
	143	case P9_OCB_OCI_OCCMISC_CLEAR:
	144	pnv_occ_set_misc(occ, 0);
	145	break;
	146	case P9_OCB_OCI_OCCMISC_OR:
	147	pnv_occ_set_misc(occ, occ->occmisc \| val);
	148	break;
	149	case P9_OCB_OCI_OCCMISC:
	150	pnv_occ_set_misc(occ, val);
	151	break;
	152	default:
	153	qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
	154	HWADDR_PRIx "\n", addr >> 3);
	155	}
	156	}
	157
	158	static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
	159	.read = pnv_occ_power9_xscom_read,
	160	.write = pnv_occ_power9_xscom_write,
	161	.valid.min_access_size = 8,
	162	.valid.max_access_size = 8,
	163	.impl.min_access_size = 8,
	164	.impl.max_access_size = 8,
	165	.endianness = DEVICE_BIG_ENDIAN,
	166	};
	167
	168	static void pnv_occ_power9_class_init(ObjectClass klass, void data)
	169	{
	170	PnvOCCClass *poc = PNV_OCC_CLASS(klass);
	171
	172	poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
	173	poc->xscom_ops = &pnv_occ_power9_xscom_ops;
	174	poc->psi_irq = PSIHB9_IRQ_OCC;
	175	}
	176
177	static const TypeInfo pnv_occ_power9_type_info = {
178	.name = TYPE_PNV9_OCC,
179	.parent = TYPE_PNV_OCC,
180	.instance_size = sizeof(PnvOCC),
181	.class_init = pnv_occ_power9_class_init,
182	};
183
0722d05a BH	184	static void pnv_occ_realize(DeviceState dev, Error *errp)
	185	{
	186	PnvOCC *occ = PNV_OCC(dev);
3233838c	187	PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
0722d05a	188	Object *obj;
3233838c	189	Error *local_err = NULL;
0722d05a BH	190
	191	occ->occmisc = 0;
	192
3233838c	193	obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
0722d05a	194	if (!obj) {
3233838c CLG	195	error_propagate(errp, local_err);
3233838c CLG	196	error_prepend(errp, "required link 'psi' not found: ");
0722d05a BH	197	return;
	198	}
	199	occ->psi = PNV_PSI(obj);
	200
	201	/* XScom region for OCC registers */
3233838c CLG	202	pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
3233838c CLG	203	occ, "xscom-occ", poc->xscom_size);
0722d05a BH	204	}
	205
	206	static void pnv_occ_class_init(ObjectClass klass, void data)
	207	{
	208	DeviceClass *dc = DEVICE_CLASS(klass);
	209
	210	dc->realize = pnv_occ_realize;
3233838c	211	dc->desc = "PowerNV OCC Controller";
0722d05a BH	212	}
	213
	214	static const TypeInfo pnv_occ_type_info = {
	215	.name = TYPE_PNV_OCC,
	216	.parent = TYPE_DEVICE,
	217	.instance_size = sizeof(PnvOCC),
	218	.class_init = pnv_occ_class_init,
3233838c CLG	219	.class_size = sizeof(PnvOCCClass),
3233838c CLG	220	.abstract = true,
0722d05a BH	221	};
	222
	223	static void pnv_occ_register_types(void)
	224	{
	225	type_register_static(&pnv_occ_type_info);
3233838c	226	type_register_static(&pnv_occ_power8_type_info);
6598a70d	227	type_register_static(&pnv_occ_power9_type_info);
0722d05a BH	228	}
0722d05a BH	229
3233838c	230	type_init(pnv_occ_register_types);