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0722d05a BH |
1 | /* |
2 | * QEMU PowerPC PowerNV Emulation of a few OCC related registers | |
3 | * | |
4 | * Copyright (c) 2015-2017, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License, version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "hw/hw.h" | |
21 | #include "sysemu/sysemu.h" | |
22 | #include "target/ppc/cpu.h" | |
23 | #include "qapi/error.h" | |
24 | #include "qemu/log.h" | |
25 | ||
26 | #include "hw/ppc/pnv.h" | |
27 | #include "hw/ppc/pnv_xscom.h" | |
28 | #include "hw/ppc/pnv_occ.h" | |
29 | ||
30 | #define OCB_OCI_OCCMISC 0x4020 | |
31 | #define OCB_OCI_OCCMISC_AND 0x4021 | |
32 | #define OCB_OCI_OCCMISC_OR 0x4022 | |
33 | ||
34 | static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) | |
35 | { | |
36 | bool irq_state; | |
3233838c | 37 | PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); |
0722d05a BH |
38 | |
39 | val &= 0xffff000000000000ull; | |
40 | ||
41 | occ->occmisc = val; | |
42 | irq_state = !!(val >> 63); | |
3233838c | 43 | pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state); |
0722d05a BH |
44 | } |
45 | ||
3233838c CLG |
46 | static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, |
47 | unsigned size) | |
0722d05a BH |
48 | { |
49 | PnvOCC *occ = PNV_OCC(opaque); | |
50 | uint32_t offset = addr >> 3; | |
51 | uint64_t val = 0; | |
52 | ||
53 | switch (offset) { | |
54 | case OCB_OCI_OCCMISC: | |
55 | val = occ->occmisc; | |
56 | break; | |
57 | default: | |
58 | qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" | |
3233838c | 59 | HWADDR_PRIx "\n", addr >> 3); |
0722d05a BH |
60 | } |
61 | return val; | |
62 | } | |
63 | ||
3233838c CLG |
64 | static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, |
65 | uint64_t val, unsigned size) | |
0722d05a BH |
66 | { |
67 | PnvOCC *occ = PNV_OCC(opaque); | |
68 | uint32_t offset = addr >> 3; | |
69 | ||
70 | switch (offset) { | |
71 | case OCB_OCI_OCCMISC_AND: | |
72 | pnv_occ_set_misc(occ, occ->occmisc & val); | |
73 | break; | |
74 | case OCB_OCI_OCCMISC_OR: | |
75 | pnv_occ_set_misc(occ, occ->occmisc | val); | |
76 | break; | |
77 | case OCB_OCI_OCCMISC: | |
78 | pnv_occ_set_misc(occ, val); | |
79 | break; | |
80 | default: | |
81 | qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" | |
3233838c | 82 | HWADDR_PRIx "\n", addr >> 3); |
0722d05a BH |
83 | } |
84 | } | |
85 | ||
3233838c CLG |
86 | static const MemoryRegionOps pnv_occ_power8_xscom_ops = { |
87 | .read = pnv_occ_power8_xscom_read, | |
88 | .write = pnv_occ_power8_xscom_write, | |
0722d05a BH |
89 | .valid.min_access_size = 8, |
90 | .valid.max_access_size = 8, | |
91 | .impl.min_access_size = 8, | |
92 | .impl.max_access_size = 8, | |
93 | .endianness = DEVICE_BIG_ENDIAN, | |
94 | }; | |
95 | ||
3233838c CLG |
96 | static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) |
97 | { | |
98 | PnvOCCClass *poc = PNV_OCC_CLASS(klass); | |
99 | ||
100 | poc->xscom_size = PNV_XSCOM_OCC_SIZE; | |
101 | poc->xscom_ops = &pnv_occ_power8_xscom_ops; | |
102 | poc->psi_irq = PSIHB_IRQ_OCC; | |
103 | } | |
104 | ||
105 | static const TypeInfo pnv_occ_power8_type_info = { | |
106 | .name = TYPE_PNV8_OCC, | |
107 | .parent = TYPE_PNV_OCC, | |
108 | .instance_size = sizeof(PnvOCC), | |
109 | .class_init = pnv_occ_power8_class_init, | |
110 | }; | |
0722d05a BH |
111 | |
112 | static void pnv_occ_realize(DeviceState *dev, Error **errp) | |
113 | { | |
114 | PnvOCC *occ = PNV_OCC(dev); | |
3233838c | 115 | PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); |
0722d05a | 116 | Object *obj; |
3233838c | 117 | Error *local_err = NULL; |
0722d05a BH |
118 | |
119 | occ->occmisc = 0; | |
120 | ||
3233838c | 121 | obj = object_property_get_link(OBJECT(dev), "psi", &local_err); |
0722d05a | 122 | if (!obj) { |
3233838c CLG |
123 | error_propagate(errp, local_err); |
124 | error_prepend(errp, "required link 'psi' not found: "); | |
0722d05a BH |
125 | return; |
126 | } | |
127 | occ->psi = PNV_PSI(obj); | |
128 | ||
129 | /* XScom region for OCC registers */ | |
3233838c CLG |
130 | pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, |
131 | occ, "xscom-occ", poc->xscom_size); | |
0722d05a BH |
132 | } |
133 | ||
134 | static void pnv_occ_class_init(ObjectClass *klass, void *data) | |
135 | { | |
136 | DeviceClass *dc = DEVICE_CLASS(klass); | |
137 | ||
138 | dc->realize = pnv_occ_realize; | |
3233838c | 139 | dc->desc = "PowerNV OCC Controller"; |
0722d05a BH |
140 | } |
141 | ||
142 | static const TypeInfo pnv_occ_type_info = { | |
143 | .name = TYPE_PNV_OCC, | |
144 | .parent = TYPE_DEVICE, | |
145 | .instance_size = sizeof(PnvOCC), | |
146 | .class_init = pnv_occ_class_init, | |
3233838c CLG |
147 | .class_size = sizeof(PnvOCCClass), |
148 | .abstract = true, | |
0722d05a BH |
149 | }; |
150 | ||
151 | static void pnv_occ_register_types(void) | |
152 | { | |
153 | type_register_static(&pnv_occ_type_info); | |
3233838c | 154 | type_register_static(&pnv_occ_power8_type_info); |
0722d05a BH |
155 | } |
156 | ||
3233838c | 157 | type_init(pnv_occ_register_types); |