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54f59d78 CLG |
1 | /* |
2 | * QEMU PowerPC PowerNV Processor Service Interface (PSI) model | |
3 | * | |
4 | * Copyright (c) 2015-2017, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
64552b6b | 21 | #include "hw/irq.h" |
54f59d78 CLG |
22 | #include "target/ppc/cpu.h" |
23 | #include "qemu/log.h" | |
0b8fa32f | 24 | #include "qemu/module.h" |
71e8a915 | 25 | #include "sysemu/reset.h" |
54f59d78 | 26 | #include "qapi/error.h" |
c38536bc | 27 | #include "monitor/monitor.h" |
54f59d78 CLG |
28 | |
29 | #include "exec/address-spaces.h" | |
30 | ||
31 | #include "hw/ppc/fdt.h" | |
32 | #include "hw/ppc/pnv.h" | |
33 | #include "hw/ppc/pnv_xscom.h" | |
a27bd6c7 | 34 | #include "hw/qdev-properties.h" |
54f59d78 CLG |
35 | #include "hw/ppc/pnv_psi.h" |
36 | ||
37 | #include <libfdt.h> | |
38 | ||
39 | #define PSIHB_XSCOM_FIR_RW 0x00 | |
40 | #define PSIHB_XSCOM_FIR_AND 0x01 | |
41 | #define PSIHB_XSCOM_FIR_OR 0x02 | |
42 | #define PSIHB_XSCOM_FIRMASK_RW 0x03 | |
43 | #define PSIHB_XSCOM_FIRMASK_AND 0x04 | |
44 | #define PSIHB_XSCOM_FIRMASK_OR 0x05 | |
45 | #define PSIHB_XSCOM_FIRACT0 0x06 | |
46 | #define PSIHB_XSCOM_FIRACT1 0x07 | |
47 | ||
48 | /* Host Bridge Base Address Register */ | |
49 | #define PSIHB_XSCOM_BAR 0x0a | |
50 | #define PSIHB_BAR_EN 0x0000000000000001ull | |
51 | ||
52 | /* FSP Base Address Register */ | |
53 | #define PSIHB_XSCOM_FSPBAR 0x0b | |
54 | ||
55 | /* PSI Host Bridge Control/Status Register */ | |
56 | #define PSIHB_XSCOM_CR 0x0e | |
57 | #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull | |
58 | #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull | |
59 | #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull | |
60 | #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull | |
61 | #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull | |
62 | #define PSIHB_CR_FSP_RESET 0x0200000000000000ull | |
63 | #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull | |
64 | #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull | |
65 | #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull | |
66 | #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull | |
67 | #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull | |
68 | /* and more ... */ | |
69 | ||
70 | /* PSIHB Status / Error Mask Register */ | |
71 | #define PSIHB_XSCOM_SEMR 0x0f | |
72 | ||
73 | /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ | |
74 | #define PSIHB_XSCOM_XIVR_FSP 0x10 | |
75 | #define PSIHB_XIVR_SERVER_SH 40 | |
76 | #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) | |
77 | #define PSIHB_XIVR_PRIO_SH 32 | |
78 | #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) | |
79 | #define PSIHB_XIVR_SRC_SH 29 | |
80 | #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) | |
81 | #define PSIHB_XIVR_PENDING 0x01000000ull | |
82 | ||
83 | /* PSI Host Bridge Set Control/ Status Register */ | |
84 | #define PSIHB_XSCOM_SCR 0x12 | |
85 | ||
86 | /* PSI Host Bridge Clear Control/ Status Register */ | |
87 | #define PSIHB_XSCOM_CCR 0x13 | |
88 | ||
89 | /* DMA Upper Address Register */ | |
90 | #define PSIHB_XSCOM_DMA_UPADD 0x14 | |
91 | ||
92 | /* Interrupt Status */ | |
93 | #define PSIHB_XSCOM_IRQ_STAT 0x15 | |
94 | #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull | |
95 | #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull | |
96 | #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull | |
97 | #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull | |
98 | #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull | |
99 | ||
100 | /* remaining XIVR */ | |
101 | #define PSIHB_XSCOM_XIVR_OCC 0x16 | |
102 | #define PSIHB_XSCOM_XIVR_FSI 0x17 | |
103 | #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 | |
104 | #define PSIHB_XSCOM_XIVR_LOCERR 0x19 | |
105 | #define PSIHB_XSCOM_XIVR_EXT 0x1a | |
106 | ||
107 | /* Interrupt Requester Source Compare Register */ | |
108 | #define PSIHB_XSCOM_IRSN 0x1b | |
109 | #define PSIHB_IRSN_COMP_SH 45 | |
110 | #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) | |
111 | #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull | |
112 | #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull | |
113 | #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull | |
114 | #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull | |
115 | #define PSIHB_IRSN_COMPMASK_SH 13 | |
116 | #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) | |
117 | ||
118 | #define PSIHB_BAR_MASK 0x0003fffffff00000ull | |
119 | #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull | |
120 | ||
c38536bc CLG |
121 | #define PSIHB9_BAR_MASK 0x00fffffffff00000ull |
122 | #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull | |
123 | ||
029699aa CLG |
124 | #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) |
125 | ||
54f59d78 CLG |
126 | static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) |
127 | { | |
ae856055 | 128 | PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); |
54f59d78 CLG |
129 | MemoryRegion *sysmem = get_system_memory(); |
130 | uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; | |
131 | ||
ae856055 | 132 | psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); |
54f59d78 CLG |
133 | |
134 | /* Update MR, always remove it first */ | |
135 | if (old & PSIHB_BAR_EN) { | |
136 | memory_region_del_subregion(sysmem, &psi->regs_mr); | |
137 | } | |
138 | ||
139 | /* Then add it back if needed */ | |
140 | if (bar & PSIHB_BAR_EN) { | |
ae856055 | 141 | uint64_t addr = bar & ppc->bar_mask; |
54f59d78 CLG |
142 | memory_region_add_subregion(sysmem, addr, &psi->regs_mr); |
143 | } | |
144 | } | |
145 | ||
146 | static void pnv_psi_update_fsp_mr(PnvPsi *psi) | |
147 | { | |
148 | /* TODO: Update FSP MR if/when we support FSP BAR */ | |
149 | } | |
150 | ||
151 | static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) | |
152 | { | |
153 | uint64_t old = psi->regs[PSIHB_XSCOM_CR]; | |
154 | ||
155 | psi->regs[PSIHB_XSCOM_CR] = cr; | |
156 | ||
157 | /* Check some bit changes */ | |
158 | if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { | |
159 | pnv_psi_update_fsp_mr(psi); | |
160 | } | |
161 | } | |
162 | ||
163 | static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) | |
164 | { | |
ae856055 | 165 | ICSState *ics = &PNV8_PSI(psi)->ics; |
54f59d78 CLG |
166 | |
167 | /* In this model we ignore the up/down enable bits for now | |
168 | * as SW doesn't use them (other than setting them at boot). | |
169 | * We ignore IRQ_MUX, its meaning isn't clear and we don't use | |
170 | * it and finally we ignore reset (XXX fix that ?) | |
171 | */ | |
172 | psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | | |
173 | PSIHB_IRSN_IRQ_MUX | | |
174 | PSIHB_IRSN_IRQ_RESET | | |
175 | PSIHB_IRSN_DOWNSTREAM_EN | | |
176 | PSIHB_IRSN_UPSTREAM_EN); | |
177 | ||
178 | /* We ignore the compare mask as well, our ICS emulation is too | |
179 | * simplistic to make any use if it, and we extract the offset | |
180 | * from the compare value | |
181 | */ | |
182 | ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; | |
183 | } | |
184 | ||
185 | /* | |
186 | * FSP and PSI interrupts are muxed under the same number. | |
187 | */ | |
188 | static const uint32_t xivr_regs[] = { | |
189 | [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP, | |
190 | [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, | |
191 | [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, | |
192 | [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, | |
193 | [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, | |
194 | [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, | |
195 | [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, | |
196 | }; | |
197 | ||
198 | static const uint32_t stat_regs[] = { | |
199 | [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR, | |
200 | [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, | |
201 | [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, | |
202 | [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, | |
203 | [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, | |
204 | [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, | |
205 | [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, | |
206 | }; | |
207 | ||
208 | static const uint64_t stat_bits[] = { | |
209 | [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ, | |
210 | [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, | |
211 | [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, | |
212 | [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, | |
213 | [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, | |
214 | [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, | |
215 | [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, | |
216 | }; | |
217 | ||
ae856055 CLG |
218 | void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state) |
219 | { | |
220 | PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state); | |
221 | } | |
222 | ||
223 | static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state) | |
54f59d78 | 224 | { |
54f59d78 CLG |
225 | uint32_t xivr_reg; |
226 | uint32_t stat_reg; | |
227 | uint32_t src; | |
228 | bool masked; | |
229 | ||
230 | if (irq > PSIHB_IRQ_EXTERNAL) { | |
231 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); | |
232 | return; | |
233 | } | |
234 | ||
235 | xivr_reg = xivr_regs[irq]; | |
236 | stat_reg = stat_regs[irq]; | |
237 | ||
238 | src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; | |
239 | if (state) { | |
240 | psi->regs[stat_reg] |= stat_bits[irq]; | |
241 | /* TODO: optimization, check mask here. That means | |
242 | * re-evaluating when unmasking | |
243 | */ | |
f8df9003 | 244 | qemu_irq_raise(psi->qirqs[src]); |
54f59d78 CLG |
245 | } else { |
246 | psi->regs[stat_reg] &= ~stat_bits[irq]; | |
247 | ||
248 | /* FSP and PSI are muxed so don't lower if either is still set */ | |
249 | if (stat_reg != PSIHB_XSCOM_CR || | |
250 | !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { | |
f8df9003 | 251 | qemu_irq_lower(psi->qirqs[src]); |
54f59d78 CLG |
252 | } else { |
253 | state = true; | |
254 | } | |
255 | } | |
256 | ||
257 | /* Note about the emulation of the pending bit: This isn't | |
258 | * entirely correct. The pending bit should be cleared when the | |
259 | * EOI has been received. However, we don't have callbacks on EOI | |
260 | * (especially not under KVM) so no way to emulate that properly, | |
261 | * so instead we just set that bit as the logical "output" of the | |
262 | * XIVR (ie pending & !masked) | |
263 | * | |
264 | * CLG: We could define a new ICS object with a custom eoi() | |
265 | * handler to clear the pending bit. But I am not sure this would | |
266 | * be useful for the software anyhow. | |
267 | */ | |
268 | masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; | |
269 | if (state && !masked) { | |
270 | psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; | |
271 | } else { | |
272 | psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; | |
273 | } | |
274 | } | |
275 | ||
276 | static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) | |
277 | { | |
ae856055 | 278 | ICSState *ics = &PNV8_PSI(psi)->ics; |
54f59d78 CLG |
279 | uint16_t server; |
280 | uint8_t prio; | |
281 | uint8_t src; | |
282 | ||
283 | psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | | |
284 | (val & (PSIHB_XIVR_SERVER_MSK | | |
285 | PSIHB_XIVR_PRIO_MSK | | |
286 | PSIHB_XIVR_SRC_MSK)); | |
287 | val = psi->regs[reg]; | |
288 | server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; | |
289 | prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; | |
290 | src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; | |
291 | ||
292 | if (src >= PSI_NUM_INTERRUPTS) { | |
293 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); | |
294 | return; | |
295 | } | |
296 | ||
297 | /* Remove pending bit if the IRQ is masked */ | |
298 | if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { | |
299 | psi->regs[reg] &= ~PSIHB_XIVR_PENDING; | |
300 | } | |
301 | ||
302 | /* The low order 2 bits are the link pointer (Type II interrupts). | |
303 | * Shift back to get a valid IRQ server. | |
304 | */ | |
305 | server >>= 2; | |
306 | ||
307 | /* Now because of source remapping, weird things can happen | |
308 | * if you change the source number dynamically, our simple ICS | |
309 | * doesn't deal with remapping. So we just poke a different | |
310 | * ICS entry based on what source number was written. This will | |
311 | * do for now but a more accurate implementation would instead | |
312 | * use a fixed server/prio and a remapper of the generated irq. | |
313 | */ | |
28976c99 | 314 | ics_write_xive(ics, src, server, prio, prio); |
54f59d78 CLG |
315 | } |
316 | ||
317 | static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) | |
318 | { | |
319 | uint64_t val = 0xffffffffffffffffull; | |
320 | ||
321 | switch (offset) { | |
322 | case PSIHB_XSCOM_FIR_RW: | |
323 | case PSIHB_XSCOM_FIRACT0: | |
324 | case PSIHB_XSCOM_FIRACT1: | |
325 | case PSIHB_XSCOM_BAR: | |
326 | case PSIHB_XSCOM_FSPBAR: | |
327 | case PSIHB_XSCOM_CR: | |
328 | case PSIHB_XSCOM_XIVR_FSP: | |
329 | case PSIHB_XSCOM_XIVR_OCC: | |
330 | case PSIHB_XSCOM_XIVR_FSI: | |
331 | case PSIHB_XSCOM_XIVR_LPCI2C: | |
332 | case PSIHB_XSCOM_XIVR_LOCERR: | |
333 | case PSIHB_XSCOM_XIVR_EXT: | |
334 | case PSIHB_XSCOM_IRQ_STAT: | |
335 | case PSIHB_XSCOM_SEMR: | |
336 | case PSIHB_XSCOM_DMA_UPADD: | |
337 | case PSIHB_XSCOM_IRSN: | |
338 | val = psi->regs[offset]; | |
339 | break; | |
340 | default: | |
cdbaf8cd | 341 | qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset); |
54f59d78 CLG |
342 | } |
343 | return val; | |
344 | } | |
345 | ||
346 | static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, | |
347 | bool mmio) | |
348 | { | |
349 | switch (offset) { | |
350 | case PSIHB_XSCOM_FIR_RW: | |
351 | case PSIHB_XSCOM_FIRACT0: | |
352 | case PSIHB_XSCOM_FIRACT1: | |
353 | case PSIHB_XSCOM_SEMR: | |
354 | case PSIHB_XSCOM_DMA_UPADD: | |
355 | psi->regs[offset] = val; | |
356 | break; | |
357 | case PSIHB_XSCOM_FIR_OR: | |
358 | psi->regs[PSIHB_XSCOM_FIR_RW] |= val; | |
359 | break; | |
360 | case PSIHB_XSCOM_FIR_AND: | |
361 | psi->regs[PSIHB_XSCOM_FIR_RW] &= val; | |
362 | break; | |
363 | case PSIHB_XSCOM_BAR: | |
364 | /* Only XSCOM can write this one */ | |
365 | if (!mmio) { | |
366 | pnv_psi_set_bar(psi, val); | |
367 | } else { | |
368 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); | |
369 | } | |
370 | break; | |
371 | case PSIHB_XSCOM_FSPBAR: | |
372 | psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; | |
373 | pnv_psi_update_fsp_mr(psi); | |
374 | break; | |
375 | case PSIHB_XSCOM_CR: | |
376 | pnv_psi_set_cr(psi, val); | |
377 | break; | |
378 | case PSIHB_XSCOM_SCR: | |
379 | pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); | |
380 | break; | |
381 | case PSIHB_XSCOM_CCR: | |
382 | pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); | |
383 | break; | |
384 | case PSIHB_XSCOM_XIVR_FSP: | |
385 | case PSIHB_XSCOM_XIVR_OCC: | |
386 | case PSIHB_XSCOM_XIVR_FSI: | |
387 | case PSIHB_XSCOM_XIVR_LPCI2C: | |
388 | case PSIHB_XSCOM_XIVR_LOCERR: | |
389 | case PSIHB_XSCOM_XIVR_EXT: | |
390 | pnv_psi_set_xivr(psi, offset, val); | |
391 | break; | |
392 | case PSIHB_XSCOM_IRQ_STAT: | |
393 | /* Read only */ | |
394 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); | |
395 | break; | |
396 | case PSIHB_XSCOM_IRSN: | |
397 | pnv_psi_set_irsn(psi, val); | |
398 | break; | |
399 | default: | |
cdbaf8cd | 400 | qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset); |
54f59d78 CLG |
401 | } |
402 | } | |
403 | ||
404 | /* | |
405 | * The values of the registers when accessed through the MMIO region | |
406 | * follow the relation : xscom = (mmio + 0x50) >> 3 | |
407 | */ | |
408 | static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) | |
409 | { | |
029699aa | 410 | return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); |
54f59d78 CLG |
411 | } |
412 | ||
413 | static void pnv_psi_mmio_write(void *opaque, hwaddr addr, | |
414 | uint64_t val, unsigned size) | |
415 | { | |
029699aa | 416 | pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); |
54f59d78 CLG |
417 | } |
418 | ||
419 | static const MemoryRegionOps psi_mmio_ops = { | |
420 | .read = pnv_psi_mmio_read, | |
421 | .write = pnv_psi_mmio_write, | |
422 | .endianness = DEVICE_BIG_ENDIAN, | |
423 | .valid = { | |
424 | .min_access_size = 8, | |
425 | .max_access_size = 8, | |
426 | }, | |
427 | .impl = { | |
428 | .min_access_size = 8, | |
429 | .max_access_size = 8, | |
430 | }, | |
431 | }; | |
432 | ||
433 | static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) | |
434 | { | |
435 | return pnv_psi_reg_read(opaque, addr >> 3, false); | |
436 | } | |
437 | ||
438 | static void pnv_psi_xscom_write(void *opaque, hwaddr addr, | |
439 | uint64_t val, unsigned size) | |
440 | { | |
441 | pnv_psi_reg_write(opaque, addr >> 3, val, false); | |
442 | } | |
443 | ||
444 | static const MemoryRegionOps pnv_psi_xscom_ops = { | |
445 | .read = pnv_psi_xscom_read, | |
446 | .write = pnv_psi_xscom_write, | |
447 | .endianness = DEVICE_BIG_ENDIAN, | |
448 | .valid = { | |
449 | .min_access_size = 8, | |
450 | .max_access_size = 8, | |
451 | }, | |
452 | .impl = { | |
453 | .min_access_size = 8, | |
454 | .max_access_size = 8, | |
455 | } | |
456 | }; | |
457 | ||
f7eb6a0a CLG |
458 | static void pnv_psi_reset(void *dev) |
459 | { | |
460 | PnvPsi *psi = PNV_PSI(dev); | |
461 | ||
462 | memset(psi->regs, 0x0, sizeof(psi->regs)); | |
463 | ||
464 | psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; | |
465 | } | |
466 | ||
ae856055 | 467 | static void pnv_psi_power8_instance_init(Object *obj) |
54f59d78 | 468 | { |
ae856055 | 469 | Pnv8Psi *psi8 = PNV8_PSI(obj); |
54f59d78 | 470 | |
ae856055 | 471 | object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics), |
642e9271 | 472 | TYPE_ICS, &error_abort, NULL); |
54f59d78 CLG |
473 | } |
474 | ||
475 | static const uint8_t irq_to_xivr[] = { | |
476 | PSIHB_XSCOM_XIVR_FSP, | |
477 | PSIHB_XSCOM_XIVR_OCC, | |
478 | PSIHB_XSCOM_XIVR_FSI, | |
479 | PSIHB_XSCOM_XIVR_LPCI2C, | |
480 | PSIHB_XSCOM_XIVR_LOCERR, | |
481 | PSIHB_XSCOM_XIVR_EXT, | |
482 | }; | |
483 | ||
ae856055 | 484 | static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) |
54f59d78 CLG |
485 | { |
486 | PnvPsi *psi = PNV_PSI(dev); | |
ae856055 | 487 | ICSState *ics = &PNV8_PSI(psi)->ics; |
54f59d78 CLG |
488 | Object *obj; |
489 | Error *err = NULL; | |
490 | unsigned int i; | |
491 | ||
492 | obj = object_property_get_link(OBJECT(dev), "xics", &err); | |
493 | if (!obj) { | |
494 | error_setg(errp, "%s: required link 'xics' not found: %s", | |
495 | __func__, error_get_pretty(err)); | |
496 | return; | |
497 | } | |
498 | ||
499 | /* Create PSI interrupt control source */ | |
ad265631 GK |
500 | object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj, |
501 | &error_abort); | |
54f59d78 CLG |
502 | object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); |
503 | if (err) { | |
504 | error_propagate(errp, err); | |
505 | return; | |
506 | } | |
507 | object_property_set_bool(OBJECT(ics), true, "realized", &err); | |
508 | if (err) { | |
509 | error_propagate(errp, err); | |
510 | return; | |
511 | } | |
512 | ||
513 | for (i = 0; i < ics->nr_irqs; i++) { | |
514 | ics_set_irq_type(ics, i, true); | |
515 | } | |
516 | ||
28976c99 | 517 | psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); |
f8df9003 | 518 | |
54f59d78 CLG |
519 | /* XSCOM region for PSI registers */ |
520 | pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, | |
521 | psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); | |
522 | ||
523 | /* Initialize MMIO region */ | |
524 | memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, | |
525 | "psihb", PNV_PSIHB_SIZE); | |
526 | ||
527 | /* Default BAR for MMIO region */ | |
528 | pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); | |
529 | ||
530 | /* Default sources in XIVR */ | |
531 | for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { | |
532 | uint8_t xivr = irq_to_xivr[i]; | |
533 | psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | | |
534 | ((uint64_t) i << PSIHB_XIVR_SRC_SH); | |
535 | } | |
f7eb6a0a CLG |
536 | |
537 | qemu_register_reset(pnv_psi_reset, dev); | |
54f59d78 CLG |
538 | } |
539 | ||
ae856055 | 540 | static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x"; |
c38536bc | 541 | static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x"; |
ae856055 | 542 | |
b168a138 | 543 | static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) |
54f59d78 | 544 | { |
ae856055 | 545 | PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); |
54f59d78 CLG |
546 | char *name; |
547 | int offset; | |
54f59d78 | 548 | uint32_t reg[] = { |
ae856055 CLG |
549 | cpu_to_be32(ppc->xscom_pcba), |
550 | cpu_to_be32(ppc->xscom_size) | |
54f59d78 CLG |
551 | }; |
552 | ||
ae856055 | 553 | name = g_strdup_printf("psihb@%x", ppc->xscom_pcba); |
54f59d78 CLG |
554 | offset = fdt_add_subnode(fdt, xscom_offset, name); |
555 | _FDT(offset); | |
556 | g_free(name); | |
557 | ||
ae856055 CLG |
558 | _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); |
559 | _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); | |
560 | _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); | |
c38536bc CLG |
561 | if (ppc->chip_type == PNV_CHIP_POWER9) { |
562 | _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, | |
563 | sizeof(compat_p9))); | |
564 | } else { | |
565 | _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, | |
566 | sizeof(compat_p8))); | |
567 | } | |
54f59d78 CLG |
568 | return 0; |
569 | } | |
570 | ||
571 | static Property pnv_psi_properties[] = { | |
572 | DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), | |
573 | DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), | |
574 | DEFINE_PROP_END_OF_LIST(), | |
575 | }; | |
576 | ||
ae856055 CLG |
577 | static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) |
578 | { | |
579 | DeviceClass *dc = DEVICE_CLASS(klass); | |
580 | PnvPsiClass *ppc = PNV_PSI_CLASS(klass); | |
581 | ||
582 | dc->desc = "PowerNV PSI Controller POWER8"; | |
583 | dc->realize = pnv_psi_power8_realize; | |
584 | ||
585 | ppc->chip_type = PNV_CHIP_POWER8; | |
586 | ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; | |
587 | ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; | |
588 | ppc->bar_mask = PSIHB_BAR_MASK; | |
589 | ppc->irq_set = pnv_psi_power8_irq_set; | |
590 | } | |
591 | ||
592 | static const TypeInfo pnv_psi_power8_info = { | |
593 | .name = TYPE_PNV8_PSI, | |
594 | .parent = TYPE_PNV_PSI, | |
595 | .instance_size = sizeof(Pnv8Psi), | |
596 | .instance_init = pnv_psi_power8_instance_init, | |
597 | .class_init = pnv_psi_power8_class_init, | |
598 | }; | |
599 | ||
c38536bc CLG |
600 | |
601 | /* Common registers */ | |
602 | ||
603 | #define PSIHB9_CR 0x20 | |
604 | #define PSIHB9_SEMR 0x28 | |
605 | ||
606 | /* P9 registers */ | |
607 | ||
608 | #define PSIHB9_INTERRUPT_CONTROL 0x58 | |
609 | #define PSIHB9_IRQ_METHOD PPC_BIT(0) | |
610 | #define PSIHB9_IRQ_RESET PPC_BIT(1) | |
611 | #define PSIHB9_ESB_CI_BASE 0x60 | |
612 | #define PSIHB9_ESB_CI_VALID 1 | |
613 | #define PSIHB9_ESB_NOTIF_ADDR 0x68 | |
614 | #define PSIHB9_ESB_NOTIF_VALID 1 | |
615 | #define PSIHB9_IVT_OFFSET 0x70 | |
616 | #define PSIHB9_IVT_OFF_SHIFT 32 | |
617 | ||
618 | #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ | |
619 | #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) | |
620 | #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) | |
621 | #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) | |
622 | #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) | |
623 | #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) | |
624 | #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) | |
625 | #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) | |
626 | #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) | |
627 | #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) | |
628 | #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) | |
629 | #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) | |
630 | #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) | |
631 | #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) | |
632 | #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) | |
633 | #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) | |
634 | #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) | |
635 | #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) | |
636 | #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) | |
637 | ||
638 | #define PSIHB9_IRQ_STAT 0x80 /* P bit */ | |
639 | #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) | |
640 | #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) | |
641 | #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) | |
642 | #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) | |
643 | #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) | |
644 | #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) | |
645 | #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) | |
646 | #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) | |
647 | #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) | |
648 | #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) | |
649 | #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) | |
650 | #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) | |
651 | #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) | |
652 | #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) | |
653 | ||
654 | static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno) | |
655 | { | |
656 | PnvPsi *psi = PNV_PSI(xf); | |
657 | uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; | |
658 | bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID; | |
659 | uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID; | |
660 | ||
661 | uint32_t offset = | |
662 | (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); | |
663 | uint64_t lisn = cpu_to_be64(offset + srcno); | |
664 | ||
665 | if (valid) { | |
666 | cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn)); | |
667 | } | |
668 | } | |
669 | ||
670 | static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) | |
671 | { | |
672 | PnvPsi *psi = PNV_PSI(opaque); | |
673 | uint32_t reg = PSIHB_REG(addr); | |
674 | uint64_t val = -1; | |
675 | ||
676 | switch (addr) { | |
677 | case PSIHB9_CR: | |
678 | case PSIHB9_SEMR: | |
679 | /* FSP stuff */ | |
680 | case PSIHB9_INTERRUPT_CONTROL: | |
681 | case PSIHB9_ESB_CI_BASE: | |
682 | case PSIHB9_ESB_NOTIF_ADDR: | |
683 | case PSIHB9_IVT_OFFSET: | |
684 | val = psi->regs[reg]; | |
685 | break; | |
686 | default: | |
687 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr); | |
688 | } | |
689 | ||
690 | return val; | |
691 | } | |
692 | ||
693 | static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, | |
694 | uint64_t val, unsigned size) | |
695 | { | |
696 | PnvPsi *psi = PNV_PSI(opaque); | |
697 | Pnv9Psi *psi9 = PNV9_PSI(psi); | |
698 | uint32_t reg = PSIHB_REG(addr); | |
699 | MemoryRegion *sysmem = get_system_memory(); | |
700 | ||
701 | switch (addr) { | |
702 | case PSIHB9_CR: | |
703 | case PSIHB9_SEMR: | |
704 | /* FSP stuff */ | |
705 | break; | |
706 | case PSIHB9_INTERRUPT_CONTROL: | |
707 | if (val & PSIHB9_IRQ_RESET) { | |
708 | device_reset(DEVICE(&psi9->source)); | |
709 | } | |
710 | psi->regs[reg] = val; | |
711 | break; | |
712 | ||
713 | case PSIHB9_ESB_CI_BASE: | |
714 | if (!(val & PSIHB9_ESB_CI_VALID)) { | |
715 | if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { | |
716 | memory_region_del_subregion(sysmem, &psi9->source.esb_mmio); | |
717 | } | |
718 | } else { | |
719 | if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { | |
720 | memory_region_add_subregion(sysmem, | |
721 | val & ~PSIHB9_ESB_CI_VALID, | |
722 | &psi9->source.esb_mmio); | |
723 | } | |
724 | } | |
725 | psi->regs[reg] = val; | |
726 | break; | |
727 | ||
728 | case PSIHB9_ESB_NOTIF_ADDR: | |
729 | psi->regs[reg] = val; | |
730 | break; | |
731 | case PSIHB9_IVT_OFFSET: | |
732 | psi->regs[reg] = val; | |
733 | break; | |
734 | default: | |
735 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr); | |
736 | } | |
737 | } | |
738 | ||
739 | static const MemoryRegionOps pnv_psi_p9_mmio_ops = { | |
740 | .read = pnv_psi_p9_mmio_read, | |
741 | .write = pnv_psi_p9_mmio_write, | |
742 | .endianness = DEVICE_BIG_ENDIAN, | |
743 | .valid = { | |
744 | .min_access_size = 8, | |
745 | .max_access_size = 8, | |
746 | }, | |
747 | .impl = { | |
748 | .min_access_size = 8, | |
749 | .max_access_size = 8, | |
750 | }, | |
751 | }; | |
752 | ||
753 | static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) | |
754 | { | |
755 | /* No read are expected */ | |
756 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr); | |
757 | return -1; | |
758 | } | |
759 | ||
760 | static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, | |
761 | uint64_t val, unsigned size) | |
762 | { | |
763 | PnvPsi *psi = PNV_PSI(opaque); | |
764 | ||
765 | /* XSCOM is only used to set the PSIHB MMIO region */ | |
766 | switch (addr >> 3) { | |
767 | case PSIHB_XSCOM_BAR: | |
768 | pnv_psi_set_bar(psi, val); | |
769 | break; | |
770 | default: | |
771 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n", | |
772 | addr); | |
773 | } | |
774 | } | |
775 | ||
776 | static const MemoryRegionOps pnv_psi_p9_xscom_ops = { | |
777 | .read = pnv_psi_p9_xscom_read, | |
778 | .write = pnv_psi_p9_xscom_write, | |
779 | .endianness = DEVICE_BIG_ENDIAN, | |
780 | .valid = { | |
781 | .min_access_size = 8, | |
782 | .max_access_size = 8, | |
783 | }, | |
784 | .impl = { | |
785 | .min_access_size = 8, | |
786 | .max_access_size = 8, | |
787 | } | |
788 | }; | |
789 | ||
790 | static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) | |
791 | { | |
f3e971ac | 792 | uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; |
c38536bc CLG |
793 | |
794 | if (irq > PSIHB9_NUM_IRQS) { | |
795 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); | |
796 | return; | |
797 | } | |
798 | ||
799 | if (irq_method & PSIHB9_IRQ_METHOD) { | |
800 | qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); | |
801 | return; | |
802 | } | |
803 | ||
804 | /* Update LSI levels */ | |
805 | if (state) { | |
806 | psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); | |
807 | } else { | |
808 | psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); | |
809 | } | |
810 | ||
811 | qemu_set_irq(psi->qirqs[irq], state); | |
812 | } | |
813 | ||
814 | static void pnv_psi_power9_reset(void *dev) | |
815 | { | |
816 | Pnv9Psi *psi = PNV9_PSI(dev); | |
817 | ||
818 | pnv_psi_reset(dev); | |
819 | ||
820 | if (memory_region_is_mapped(&psi->source.esb_mmio)) { | |
821 | memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); | |
822 | } | |
823 | } | |
824 | ||
825 | static void pnv_psi_power9_instance_init(Object *obj) | |
826 | { | |
827 | Pnv9Psi *psi = PNV9_PSI(obj); | |
828 | ||
829 | object_initialize_child(obj, "source", &psi->source, sizeof(psi->source), | |
830 | TYPE_XIVE_SOURCE, &error_abort, NULL); | |
831 | } | |
832 | ||
833 | static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) | |
834 | { | |
835 | PnvPsi *psi = PNV_PSI(dev); | |
836 | XiveSource *xsrc = &PNV9_PSI(psi)->source; | |
837 | Error *local_err = NULL; | |
838 | int i; | |
839 | ||
840 | /* This is the only device with 4k ESB pages */ | |
841 | object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift", | |
842 | &error_fatal); | |
843 | object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs", | |
844 | &error_fatal); | |
845 | object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi), | |
846 | &error_fatal); | |
847 | object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); | |
848 | if (local_err) { | |
849 | error_propagate(errp, local_err); | |
850 | return; | |
851 | } | |
852 | ||
853 | for (i = 0; i < xsrc->nr_irqs; i++) { | |
854 | xive_source_irq_set_lsi(xsrc, i); | |
855 | } | |
856 | ||
857 | psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); | |
858 | ||
859 | /* XSCOM region for PSI registers */ | |
860 | pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, | |
861 | psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); | |
862 | ||
863 | /* MMIO region for PSI registers */ | |
864 | memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, | |
865 | "psihb", PNV9_PSIHB_SIZE); | |
866 | ||
867 | pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); | |
868 | ||
869 | qemu_register_reset(pnv_psi_power9_reset, dev); | |
870 | } | |
871 | ||
872 | static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) | |
873 | { | |
874 | DeviceClass *dc = DEVICE_CLASS(klass); | |
875 | PnvPsiClass *ppc = PNV_PSI_CLASS(klass); | |
876 | XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); | |
877 | ||
878 | dc->desc = "PowerNV PSI Controller POWER9"; | |
879 | dc->realize = pnv_psi_power9_realize; | |
880 | ||
881 | ppc->chip_type = PNV_CHIP_POWER9; | |
882 | ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; | |
883 | ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; | |
884 | ppc->bar_mask = PSIHB9_BAR_MASK; | |
885 | ppc->irq_set = pnv_psi_power9_irq_set; | |
886 | ||
887 | xfc->notify = pnv_psi_notify; | |
888 | } | |
889 | ||
890 | static const TypeInfo pnv_psi_power9_info = { | |
891 | .name = TYPE_PNV9_PSI, | |
892 | .parent = TYPE_PNV_PSI, | |
893 | .instance_size = sizeof(Pnv9Psi), | |
894 | .instance_init = pnv_psi_power9_instance_init, | |
895 | .class_init = pnv_psi_power9_class_init, | |
896 | .interfaces = (InterfaceInfo[]) { | |
897 | { TYPE_XIVE_NOTIFIER }, | |
898 | { }, | |
899 | }, | |
900 | }; | |
901 | ||
54f59d78 CLG |
902 | static void pnv_psi_class_init(ObjectClass *klass, void *data) |
903 | { | |
904 | DeviceClass *dc = DEVICE_CLASS(klass); | |
905 | PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); | |
906 | ||
b168a138 | 907 | xdc->dt_xscom = pnv_psi_dt_xscom; |
54f59d78 | 908 | |
ae856055 | 909 | dc->desc = "PowerNV PSI Controller"; |
54f59d78 CLG |
910 | dc->props = pnv_psi_properties; |
911 | } | |
912 | ||
913 | static const TypeInfo pnv_psi_info = { | |
914 | .name = TYPE_PNV_PSI, | |
915 | .parent = TYPE_SYS_BUS_DEVICE, | |
916 | .instance_size = sizeof(PnvPsi), | |
54f59d78 | 917 | .class_init = pnv_psi_class_init, |
ae856055 CLG |
918 | .class_size = sizeof(PnvPsiClass), |
919 | .abstract = true, | |
54f59d78 CLG |
920 | .interfaces = (InterfaceInfo[]) { |
921 | { TYPE_PNV_XSCOM_INTERFACE }, | |
922 | { } | |
923 | } | |
924 | }; | |
925 | ||
926 | static void pnv_psi_register_types(void) | |
927 | { | |
928 | type_register_static(&pnv_psi_info); | |
ae856055 | 929 | type_register_static(&pnv_psi_power8_info); |
c38536bc | 930 | type_register_static(&pnv_psi_power9_info); |
54f59d78 CLG |
931 | } |
932 | ||
ae856055 | 933 | type_init(pnv_psi_register_types); |
c38536bc CLG |
934 | |
935 | void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon) | |
936 | { | |
937 | PnvPsi *psi = PNV_PSI(psi9); | |
938 | ||
939 | uint32_t offset = | |
940 | (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); | |
941 | ||
942 | monitor_printf(mon, "PSIHB Source %08x .. %08x\n", | |
943 | offset, offset + psi9->source.nr_irqs - 1); | |
944 | xive_source_pic_print_info(&psi9->source, offset, mon); | |
945 | } |