[mirror_qemu.git] / hw / ppc / pnv_xscom.c

/*
 * QEMU PowerPC PowerNV XSCOM bus
 *
 * Copyright (c) 2016, IBM Corporation.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/hw_accel.h"
#include "target/ppc/cpu.h"
#include "hw/sysbus.h"

#include "hw/ppc/fdt.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"

#include <libfdt.h>

/* PRD registers */
#define PRD_P8_IPOLL_REG_MASK           0x01020013
#define PRD_P8_IPOLL_REG_STATUS         0x01020014
#define PRD_P9_IPOLL_REG_MASK           0x000F0033
#define PRD_P9_IPOLL_REG_STATUS         0x000F0034

static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
{
    /*
     * TODO: When the read/write comes from the monitor, NULL is
     * passed for the cpu, and no CPU completion is generated.
     */
    if (cs) {
        PowerPCCPU *cpu = POWERPC_CPU(cs);
        CPUPPCState *env = &cpu->env;

        /*
         * TODO: Need a CPU helper to set HMER, also handle generation
         * of HMIs
         */
        cpu_synchronize_state(cs);
        env->spr[SPR_HMER] |= hmer_bits;
    }
}

static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
{
    addr &= (PNV_XSCOM_SIZE - 1);

    switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
    case PNV_CHIP_POWER8E:
    case PNV_CHIP_POWER8:
    case PNV_CHIP_POWER8NVL:
        return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
    case PNV_CHIP_POWER9:
    case PNV_CHIP_POWER10:
        return addr >> 3;
    default:
        g_assert_not_reached();
    }
}

static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
{
    switch (pcba) {
    case 0xf000f:
        return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
    case 0x18002:       /* ECID2 */
        return 0;

    case 0x1010c00:     /* PIBAM FIR */
    case 0x1010c03:     /* PIBAM FIR MASK */

        /* PRD registers */
    case PRD_P8_IPOLL_REG_MASK:
    case PRD_P8_IPOLL_REG_STATUS:
    case PRD_P9_IPOLL_REG_MASK:
    case PRD_P9_IPOLL_REG_STATUS:

        /* P9 xscom reset */
    case 0x0090018:     /* Receive status reg */
    case 0x0090012:     /* log register */
    case 0x0090013:     /* error register */

        /* P8 xscom reset */
    case 0x2020007:     /* ADU stuff, log register */
    case 0x2020009:     /* ADU stuff, error register */
    case 0x202000f:     /* ADU stuff, receive status register*/
        return 0;
    case 0x2013f01:     /* PBA stuff */
    case 0x2013f05:     /* PBA stuff */
        return 0;
    case 0x2013028:     /* CAPP stuff */
    case 0x201302a:     /* CAPP stuff */
    case 0x2013801:     /* CAPP stuff */
    case 0x2013802:     /* CAPP stuff */

        /* P9 CAPP regs */
    case 0x2010841:
    case 0x2010842:
    case 0x201082a:
    case 0x2010828:
    case 0x4010841:
    case 0x4010842:
    case 0x401082a:
    case 0x4010828:
        return 0;
    default:
        return -1;
    }
}

static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
{
    /* We ignore writes to these */
    switch (pcba) {
    case 0xf000f:       /* chip id is RO */
    case 0x1010c00:     /* PIBAM FIR */
    case 0x1010c01:     /* PIBAM FIR */
    case 0x1010c02:     /* PIBAM FIR */
    case 0x1010c03:     /* PIBAM FIR MASK */
    case 0x1010c04:     /* PIBAM FIR MASK */
    case 0x1010c05:     /* PIBAM FIR MASK */
        /* P9 xscom reset */
    case 0x0090018:     /* Receive status reg */
    case 0x0090012:     /* log register */
    case 0x0090013:     /* error register */

        /* P8 xscom reset */
    case 0x2020007:     /* ADU stuff, log register */
    case 0x2020009:     /* ADU stuff, error register */
    case 0x202000f:     /* ADU stuff, receive status register*/

    case 0x2013028:     /* CAPP stuff */
    case 0x201302a:     /* CAPP stuff */
    case 0x2013801:     /* CAPP stuff */
    case 0x2013802:     /* CAPP stuff */

        /* P9 CAPP regs */
    case 0x2010841:
    case 0x2010842:
    case 0x201082a:
    case 0x2010828:
    case 0x4010841:
    case 0x4010842:
    case 0x401082a:
    case 0x4010828:

        /* P8 PRD registers */
    case PRD_P8_IPOLL_REG_MASK:
    case PRD_P8_IPOLL_REG_STATUS:
    case PRD_P9_IPOLL_REG_MASK:
    case PRD_P9_IPOLL_REG_STATUS:
        return true;
    default:
        return false;
    }
}

static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
{
    PnvChip *chip = opaque;
    uint32_t pcba = pnv_xscom_pcba(chip, addr);
    uint64_t val = 0;
    MemTxResult result;

    /* Handle some SCOMs here before dispatch */
    val = xscom_read_default(chip, pcba);
    if (val != -1) {
        goto complete;
    }

    val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
                            MEMTXATTRS_UNSPECIFIED, &result);
    if (result != MEMTX_OK) {
        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
                      HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
        return 0;
    }

complete:
    xscom_complete(current_cpu, HMER_XSCOM_DONE);
    return val;
}

static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
                        unsigned width)
{
    PnvChip *chip = opaque;
    uint32_t pcba = pnv_xscom_pcba(chip, addr);
    MemTxResult result;

    /* Handle some SCOMs here before dispatch */
    if (xscom_write_default(chip, pcba, val)) {
        goto complete;
    }

    address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
                      MEMTXATTRS_UNSPECIFIED, &result);
    if (result != MEMTX_OK) {
        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
                      HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
                      addr, pcba, val);
        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
        return;
    }

complete:
    xscom_complete(current_cpu, HMER_XSCOM_DONE);
}

const MemoryRegionOps pnv_xscom_ops = {
    .read = xscom_read,
    .write = xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
    char *name;

    name = g_strdup_printf("xscom-%x", chip->chip_id);
    memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
                          chip, name, size);
    sysbus_init_mmio(sbd, &chip->xscom_mmio);

    memory_region_init(&chip->xscom, OBJECT(chip), name, size);
    address_space_init(&chip->xscom_as, &chip->xscom, name);
    g_free(name);
}

static const TypeInfo pnv_xscom_interface_info = {
    .name = TYPE_PNV_XSCOM_INTERFACE,
    .parent = TYPE_INTERFACE,
    .class_size = sizeof(PnvXScomInterfaceClass),
};

static void pnv_xscom_register_types(void)
{
    type_register_static(&pnv_xscom_interface_info);
}

type_init(pnv_xscom_register_types)

typedef struct ForeachPopulateArgs {
    void *fdt;
    int xscom_offset;
} ForeachPopulateArgs;

static int xscom_dt_child(Object *child, void *opaque)
{
    if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
        ForeachPopulateArgs *args = opaque;
        PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
        PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);

        /*
         * Only "realized" devices should be configured in the DT
         */
        if (xc->dt_xscom && DEVICE(child)->realized) {
            _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
        }
    }
    return 0;
}

int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
                 uint64_t xscom_base, uint64_t xscom_size,
                 const char *compat, int compat_size)
{
    uint64_t reg[] = { xscom_base, xscom_size };
    int xscom_offset;
    ForeachPopulateArgs args;
    char *name;

    name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
    xscom_offset = fdt_add_subnode(fdt, root_offset, name);
    _FDT(xscom_offset);
    g_free(name);
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
    _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
    _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
    _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));

    args.fdt = fdt;
    args.xscom_offset = xscom_offset;

    /*
     * Loop on the whole object hierarchy to catch all
     * PnvXScomInterface objects which can lie a bit deeper than the
     * first layer.
     */
    object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
    return 0;
}

void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
{
    memory_region_add_subregion(&chip->xscom, offset << 3, mr);
}

void pnv_xscom_region_init(MemoryRegion *mr,
                           struct Object *owner,
                           const MemoryRegionOps *ops,
                           void *opaque,
                           const char *name,
                           uint64_t size)
{
    memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
}
Commit	Line	Data
967b7523 CLG	1	/*
	2	* QEMU PowerPC PowerNV XSCOM bus
	3	*
	4	* Copyright (c) 2016, IBM Corporation.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
0b8fa32f	19
967b7523	20	#include "qemu/osdep.h"
967b7523	21	#include "qemu/log.h"
0b8fa32f	22	#include "qemu/module.h"
b3946626	23	#include "sysemu/hw_accel.h"
fcf5ef2a	24	#include "target/ppc/cpu.h"
967b7523 CLG	25	#include "hw/sysbus.h"
	26
	27	#include "hw/ppc/fdt.h"
967b7523	28	#include "hw/ppc/pnv.h"
ec575aa0	29	#include "hw/ppc/pnv_xscom.h"
967b7523 CLG	30
	31	#include <libfdt.h>
	32
ce4b1b56 CLG	33	/* PRD registers */
	34	#define PRD_P8_IPOLL_REG_MASK 0x01020013
	35	#define PRD_P8_IPOLL_REG_STATUS 0x01020014
	36	#define PRD_P9_IPOLL_REG_MASK 0x000F0033
	37	#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
	38
967b7523 CLG	39	static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
	40	{
	41	/*
	42	* TODO: When the read/write comes from the monitor, NULL is
	43	* passed for the cpu, and no CPU completion is generated.
	44	*/
	45	if (cs) {
	46	PowerPCCPU *cpu = POWERPC_CPU(cs);
	47	CPUPPCState *env = &cpu->env;
	48
	49	/*
	50	* TODO: Need a CPU helper to set HMER, also handle generation
	51	* of HMIs
	52	*/
	53	cpu_synchronize_state(cs);
	54	env->spr[SPR_HMER] \|= hmer_bits;
	55	}
	56	}
	57
	58	static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
	59	{
967b7523	60	addr &= (PNV_XSCOM_SIZE - 1);
b3b066e9	61
2b548a42 CLG	62	switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
	63	case PNV_CHIP_POWER8E:
	64	case PNV_CHIP_POWER8:
	65	case PNV_CHIP_POWER8NVL:
967b7523	66	return ((addr >> 4) & ~0xfull) \| ((addr >> 3) & 0xf);
2b548a42 CLG	67	case PNV_CHIP_POWER9:
	68	case PNV_CHIP_POWER10:
	69	return addr >> 3;
	70	default:
	71	g_assert_not_reached();
967b7523 CLG	72	}
	73	}
	74
	75	static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
	76	{
	77	switch (pcba) {
	78	case 0xf000f:
	79	return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
bc565116 CLG	80	case 0x18002: /* ECID2 */
	81	return 0;
	82
967b7523 CLG	83	case 0x1010c00: /* PIBAM FIR */
967b7523 CLG	84	case 0x1010c03: /* PIBAM FIR MASK */
bc565116	85
ce4b1b56 CLG	86	/* PRD registers */
	87	case PRD_P8_IPOLL_REG_MASK:
	88	case PRD_P8_IPOLL_REG_STATUS:
	89	case PRD_P9_IPOLL_REG_MASK:
	90	case PRD_P9_IPOLL_REG_STATUS:
	91
bc565116 CLG	92	/* P9 xscom reset */
	93	case 0x0090018: /* Receive status reg */
	94	case 0x0090012: /* log register */
	95	case 0x0090013: /* error register */
	96
	97	/* P8 xscom reset */
	98	case 0x2020007: /* ADU stuff, log register */
	99	case 0x2020009: /* ADU stuff, error register */
	100	case 0x202000f: /* ADU stuff, receive status register*/
967b7523	101	return 0;
967b7523	102	case 0x2013f01: /* PBA stuff */
967b7523	103	case 0x2013f05: /* PBA stuff */
967b7523 CLG	104	return 0;
	105	case 0x2013028: /* CAPP stuff */
	106	case 0x201302a: /* CAPP stuff */
	107	case 0x2013801: /* CAPP stuff */
	108	case 0x2013802: /* CAPP stuff */
45a73a19 CLG	109
	110	/* P9 CAPP regs */
	111	case 0x2010841:
	112	case 0x2010842:
	113	case 0x201082a:
	114	case 0x2010828:
	115	case 0x4010841:
	116	case 0x4010842:
	117	case 0x401082a:
	118	case 0x4010828:
967b7523 CLG	119	return 0;
	120	default:
	121	return -1;
	122	}
	123	}
	124
	125	static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
	126	{
	127	/* We ignore writes to these */
	128	switch (pcba) {
	129	case 0xf000f: /* chip id is RO */
	130	case 0x1010c00: /* PIBAM FIR */
	131	case 0x1010c01: /* PIBAM FIR */
	132	case 0x1010c02: /* PIBAM FIR */
	133	case 0x1010c03: /* PIBAM FIR MASK */
	134	case 0x1010c04: /* PIBAM FIR MASK */
	135	case 0x1010c05: /* PIBAM FIR MASK */
bc565116 CLG	136	/* P9 xscom reset */
	137	case 0x0090018: /* Receive status reg */
	138	case 0x0090012: /* log register */
	139	case 0x0090013: /* error register */
	140
	141	/* P8 xscom reset */
	142	case 0x2020007: /* ADU stuff, log register */
	143	case 0x2020009: /* ADU stuff, error register */
	144	case 0x202000f: /* ADU stuff, receive status register*/
	145
	146	case 0x2013028: /* CAPP stuff */
	147	case 0x201302a: /* CAPP stuff */
	148	case 0x2013801: /* CAPP stuff */
	149	case 0x2013802: /* CAPP stuff */
ce4b1b56	150
45a73a19 CLG	151	/* P9 CAPP regs */
	152	case 0x2010841:
	153	case 0x2010842:
	154	case 0x201082a:
	155	case 0x2010828:
	156	case 0x4010841:
	157	case 0x4010842:
	158	case 0x401082a:
	159	case 0x4010828:
	160
ce4b1b56 CLG	161	/* P8 PRD registers */
	162	case PRD_P8_IPOLL_REG_MASK:
	163	case PRD_P8_IPOLL_REG_STATUS:
	164	case PRD_P9_IPOLL_REG_MASK:
	165	case PRD_P9_IPOLL_REG_STATUS:
967b7523 CLG	166	return true;
	167	default:
	168	return false;
	169	}
	170	}
	171
	172	static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
	173	{
	174	PnvChip *chip = opaque;
	175	uint32_t pcba = pnv_xscom_pcba(chip, addr);
	176	uint64_t val = 0;
	177	MemTxResult result;
	178
	179	/* Handle some SCOMs here before dispatch */
	180	val = xscom_read_default(chip, pcba);
	181	if (val != -1) {
	182	goto complete;
	183	}
	184
f81e5512 CLG	185	val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
f81e5512 CLG	186	MEMTXATTRS_UNSPECIFIED, &result);
967b7523 CLG	187	if (result != MEMTX_OK) {
	188	qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
	189	HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
	190	xscom_complete(current_cpu, HMER_XSCOM_FAIL \| HMER_XSCOM_DONE);
	191	return 0;
	192	}
	193
	194	complete:
	195	xscom_complete(current_cpu, HMER_XSCOM_DONE);
	196	return val;
	197	}
	198
	199	static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
	200	unsigned width)
	201	{
	202	PnvChip *chip = opaque;
	203	uint32_t pcba = pnv_xscom_pcba(chip, addr);
	204	MemTxResult result;
	205
	206	/* Handle some SCOMs here before dispatch */
	207	if (xscom_write_default(chip, pcba, val)) {
	208	goto complete;
	209	}
	210
f81e5512 CLG	211	address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
f81e5512 CLG	212	MEMTXATTRS_UNSPECIFIED, &result);
967b7523 CLG	213	if (result != MEMTX_OK) {
	214	qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
	215	HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
	216	addr, pcba, val);
	217	xscom_complete(current_cpu, HMER_XSCOM_FAIL \| HMER_XSCOM_DONE);
	218	return;
	219	}
	220
	221	complete:
	222	xscom_complete(current_cpu, HMER_XSCOM_DONE);
	223	}
	224
	225	const MemoryRegionOps pnv_xscom_ops = {
	226	.read = xscom_read,
	227	.write = xscom_write,
	228	.valid.min_access_size = 8,
	229	.valid.max_access_size = 8,
	230	.impl.min_access_size = 8,
	231	.impl.max_access_size = 8,
	232	.endianness = DEVICE_BIG_ENDIAN,
	233	};
	234
709044fd	235	void pnv_xscom_realize(PnvChip chip, uint64_t size, Error *errp)
967b7523 CLG	236	{
	237	SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
	238	char *name;
	239
	240	name = g_strdup_printf("xscom-%x", chip->chip_id);
	241	memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
709044fd	242	chip, name, size);
967b7523 CLG	243	sysbus_init_mmio(sbd, &chip->xscom_mmio);
967b7523 CLG	244
709044fd	245	memory_region_init(&chip->xscom, OBJECT(chip), name, size);
967b7523 CLG	246	address_space_init(&chip->xscom_as, &chip->xscom, name);
	247	g_free(name);
	248	}
	249
	250	static const TypeInfo pnv_xscom_interface_info = {
	251	.name = TYPE_PNV_XSCOM_INTERFACE,
	252	.parent = TYPE_INTERFACE,
	253	.class_size = sizeof(PnvXScomInterfaceClass),
	254	};
	255
	256	static void pnv_xscom_register_types(void)
	257	{
	258	type_register_static(&pnv_xscom_interface_info);
	259	}
	260
	261	type_init(pnv_xscom_register_types)
	262
	263	typedef struct ForeachPopulateArgs {
	264	void *fdt;
	265	int xscom_offset;
	266	} ForeachPopulateArgs;
	267
b168a138	268	static int xscom_dt_child(Object child, void opaque)
967b7523 CLG	269	{
	270	if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
	271	ForeachPopulateArgs *args = opaque;
	272	PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
	273	PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
	274
9e028fff CLG	275	/*
	276	* Only "realized" devices should be configured in the DT
	277	*/
	278	if (xc->dt_xscom && DEVICE(child)->realized) {
b168a138	279	_FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
967b7523 CLG	280	}
	281	}
	282	return 0;
	283	}
	284
3f5b45ca	285	int pnv_dt_xscom(PnvChip chip, void fdt, int root_offset,
c396c58a GK	286	uint64_t xscom_base, uint64_t xscom_size,
c396c58a GK	287	const char *compat, int compat_size)
967b7523	288	{
3f5b45ca	289	uint64_t reg[] = { xscom_base, xscom_size };
967b7523 CLG	290	int xscom_offset;
	291	ForeachPopulateArgs args;
	292	char *name;
967b7523 CLG	293
	294	name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
	295	xscom_offset = fdt_add_subnode(fdt, root_offset, name);
	296	_FDT(xscom_offset);
	297	g_free(name);
	298	_FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
	299	_FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
	300	_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
	301	_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
c396c58a	302	_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
967b7523 CLG	303	_FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
	304
	305	args.fdt = fdt;
	306	args.xscom_offset = xscom_offset;
	307
109dce37 CLG	308	/*
	309	* Loop on the whole object hierarchy to catch all
	310	* PnvXScomInterface objects which can lie a bit deeper than the
	311	* first layer.
	312	*/
	313	object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
967b7523 CLG	314	return 0;
	315	}
	316
	317	void pnv_xscom_add_subregion(PnvChip chip, hwaddr offset, MemoryRegion mr)
	318	{
	319	memory_region_add_subregion(&chip->xscom, offset << 3, mr);
	320	}
	321
	322	void pnv_xscom_region_init(MemoryRegion *mr,
	323	struct Object *owner,
	324	const MemoryRegionOps *ops,
	325	void *opaque,
	326	const char *name,
	327	uint64_t size)
	328	{
	329	memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
	330	}