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967b7523 CLG |
1 | /* |
2 | * QEMU PowerPC PowerNV XSCOM bus | |
3 | * | |
4 | * Copyright (c) 2016, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0b8fa32f | 19 | |
967b7523 | 20 | #include "qemu/osdep.h" |
967b7523 | 21 | #include "qemu/log.h" |
0b8fa32f | 22 | #include "qemu/module.h" |
b3946626 | 23 | #include "sysemu/hw_accel.h" |
fcf5ef2a | 24 | #include "target/ppc/cpu.h" |
967b7523 CLG |
25 | #include "hw/sysbus.h" |
26 | ||
27 | #include "hw/ppc/fdt.h" | |
967b7523 | 28 | #include "hw/ppc/pnv.h" |
ec575aa0 | 29 | #include "hw/ppc/pnv_xscom.h" |
967b7523 CLG |
30 | |
31 | #include <libfdt.h> | |
32 | ||
ce4b1b56 CLG |
33 | /* PRD registers */ |
34 | #define PRD_P8_IPOLL_REG_MASK 0x01020013 | |
35 | #define PRD_P8_IPOLL_REG_STATUS 0x01020014 | |
36 | #define PRD_P9_IPOLL_REG_MASK 0x000F0033 | |
37 | #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 | |
38 | ||
967b7523 CLG |
39 | static void xscom_complete(CPUState *cs, uint64_t hmer_bits) |
40 | { | |
41 | /* | |
42 | * TODO: When the read/write comes from the monitor, NULL is | |
43 | * passed for the cpu, and no CPU completion is generated. | |
44 | */ | |
45 | if (cs) { | |
46 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
47 | CPUPPCState *env = &cpu->env; | |
48 | ||
49 | /* | |
50 | * TODO: Need a CPU helper to set HMER, also handle generation | |
51 | * of HMIs | |
52 | */ | |
53 | cpu_synchronize_state(cs); | |
54 | env->spr[SPR_HMER] |= hmer_bits; | |
55 | } | |
56 | } | |
57 | ||
58 | static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) | |
59 | { | |
967b7523 | 60 | addr &= (PNV_XSCOM_SIZE - 1); |
b3b066e9 | 61 | |
2b548a42 CLG |
62 | switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { |
63 | case PNV_CHIP_POWER8E: | |
64 | case PNV_CHIP_POWER8: | |
65 | case PNV_CHIP_POWER8NVL: | |
967b7523 | 66 | return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); |
2b548a42 CLG |
67 | case PNV_CHIP_POWER9: |
68 | case PNV_CHIP_POWER10: | |
69 | return addr >> 3; | |
70 | default: | |
71 | g_assert_not_reached(); | |
967b7523 CLG |
72 | } |
73 | } | |
74 | ||
75 | static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) | |
76 | { | |
77 | switch (pcba) { | |
78 | case 0xf000f: | |
79 | return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; | |
bc565116 CLG |
80 | case 0x18002: /* ECID2 */ |
81 | return 0; | |
82 | ||
967b7523 CLG |
83 | case 0x1010c00: /* PIBAM FIR */ |
84 | case 0x1010c03: /* PIBAM FIR MASK */ | |
bc565116 | 85 | |
ce4b1b56 CLG |
86 | /* PRD registers */ |
87 | case PRD_P8_IPOLL_REG_MASK: | |
88 | case PRD_P8_IPOLL_REG_STATUS: | |
89 | case PRD_P9_IPOLL_REG_MASK: | |
90 | case PRD_P9_IPOLL_REG_STATUS: | |
91 | ||
bc565116 CLG |
92 | /* P9 xscom reset */ |
93 | case 0x0090018: /* Receive status reg */ | |
94 | case 0x0090012: /* log register */ | |
95 | case 0x0090013: /* error register */ | |
96 | ||
97 | /* P8 xscom reset */ | |
98 | case 0x2020007: /* ADU stuff, log register */ | |
99 | case 0x2020009: /* ADU stuff, error register */ | |
100 | case 0x202000f: /* ADU stuff, receive status register*/ | |
967b7523 | 101 | return 0; |
967b7523 | 102 | case 0x2013f01: /* PBA stuff */ |
967b7523 | 103 | case 0x2013f05: /* PBA stuff */ |
967b7523 CLG |
104 | return 0; |
105 | case 0x2013028: /* CAPP stuff */ | |
106 | case 0x201302a: /* CAPP stuff */ | |
107 | case 0x2013801: /* CAPP stuff */ | |
108 | case 0x2013802: /* CAPP stuff */ | |
45a73a19 CLG |
109 | |
110 | /* P9 CAPP regs */ | |
111 | case 0x2010841: | |
112 | case 0x2010842: | |
113 | case 0x201082a: | |
114 | case 0x2010828: | |
115 | case 0x4010841: | |
116 | case 0x4010842: | |
117 | case 0x401082a: | |
118 | case 0x4010828: | |
967b7523 CLG |
119 | return 0; |
120 | default: | |
121 | return -1; | |
122 | } | |
123 | } | |
124 | ||
125 | static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val) | |
126 | { | |
127 | /* We ignore writes to these */ | |
128 | switch (pcba) { | |
129 | case 0xf000f: /* chip id is RO */ | |
130 | case 0x1010c00: /* PIBAM FIR */ | |
131 | case 0x1010c01: /* PIBAM FIR */ | |
132 | case 0x1010c02: /* PIBAM FIR */ | |
133 | case 0x1010c03: /* PIBAM FIR MASK */ | |
134 | case 0x1010c04: /* PIBAM FIR MASK */ | |
135 | case 0x1010c05: /* PIBAM FIR MASK */ | |
bc565116 CLG |
136 | /* P9 xscom reset */ |
137 | case 0x0090018: /* Receive status reg */ | |
138 | case 0x0090012: /* log register */ | |
139 | case 0x0090013: /* error register */ | |
140 | ||
141 | /* P8 xscom reset */ | |
142 | case 0x2020007: /* ADU stuff, log register */ | |
143 | case 0x2020009: /* ADU stuff, error register */ | |
144 | case 0x202000f: /* ADU stuff, receive status register*/ | |
145 | ||
146 | case 0x2013028: /* CAPP stuff */ | |
147 | case 0x201302a: /* CAPP stuff */ | |
148 | case 0x2013801: /* CAPP stuff */ | |
149 | case 0x2013802: /* CAPP stuff */ | |
ce4b1b56 | 150 | |
45a73a19 CLG |
151 | /* P9 CAPP regs */ |
152 | case 0x2010841: | |
153 | case 0x2010842: | |
154 | case 0x201082a: | |
155 | case 0x2010828: | |
156 | case 0x4010841: | |
157 | case 0x4010842: | |
158 | case 0x401082a: | |
159 | case 0x4010828: | |
160 | ||
ce4b1b56 CLG |
161 | /* P8 PRD registers */ |
162 | case PRD_P8_IPOLL_REG_MASK: | |
163 | case PRD_P8_IPOLL_REG_STATUS: | |
164 | case PRD_P9_IPOLL_REG_MASK: | |
165 | case PRD_P9_IPOLL_REG_STATUS: | |
967b7523 CLG |
166 | return true; |
167 | default: | |
168 | return false; | |
169 | } | |
170 | } | |
171 | ||
172 | static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) | |
173 | { | |
174 | PnvChip *chip = opaque; | |
175 | uint32_t pcba = pnv_xscom_pcba(chip, addr); | |
176 | uint64_t val = 0; | |
177 | MemTxResult result; | |
178 | ||
179 | /* Handle some SCOMs here before dispatch */ | |
180 | val = xscom_read_default(chip, pcba); | |
181 | if (val != -1) { | |
182 | goto complete; | |
183 | } | |
184 | ||
f81e5512 CLG |
185 | val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3, |
186 | MEMTXATTRS_UNSPECIFIED, &result); | |
967b7523 CLG |
187 | if (result != MEMTX_OK) { |
188 | qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" | |
189 | HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); | |
190 | xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | complete: | |
195 | xscom_complete(current_cpu, HMER_XSCOM_DONE); | |
196 | return val; | |
197 | } | |
198 | ||
199 | static void xscom_write(void *opaque, hwaddr addr, uint64_t val, | |
200 | unsigned width) | |
201 | { | |
202 | PnvChip *chip = opaque; | |
203 | uint32_t pcba = pnv_xscom_pcba(chip, addr); | |
204 | MemTxResult result; | |
205 | ||
206 | /* Handle some SCOMs here before dispatch */ | |
207 | if (xscom_write_default(chip, pcba, val)) { | |
208 | goto complete; | |
209 | } | |
210 | ||
f81e5512 CLG |
211 | address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val, |
212 | MEMTXATTRS_UNSPECIFIED, &result); | |
967b7523 CLG |
213 | if (result != MEMTX_OK) { |
214 | qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" | |
215 | HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", | |
216 | addr, pcba, val); | |
217 | xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); | |
218 | return; | |
219 | } | |
220 | ||
221 | complete: | |
222 | xscom_complete(current_cpu, HMER_XSCOM_DONE); | |
223 | } | |
224 | ||
225 | const MemoryRegionOps pnv_xscom_ops = { | |
226 | .read = xscom_read, | |
227 | .write = xscom_write, | |
228 | .valid.min_access_size = 8, | |
229 | .valid.max_access_size = 8, | |
230 | .impl.min_access_size = 8, | |
231 | .impl.max_access_size = 8, | |
232 | .endianness = DEVICE_BIG_ENDIAN, | |
233 | }; | |
234 | ||
709044fd | 235 | void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp) |
967b7523 CLG |
236 | { |
237 | SysBusDevice *sbd = SYS_BUS_DEVICE(chip); | |
238 | char *name; | |
239 | ||
240 | name = g_strdup_printf("xscom-%x", chip->chip_id); | |
241 | memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops, | |
709044fd | 242 | chip, name, size); |
967b7523 CLG |
243 | sysbus_init_mmio(sbd, &chip->xscom_mmio); |
244 | ||
709044fd | 245 | memory_region_init(&chip->xscom, OBJECT(chip), name, size); |
967b7523 CLG |
246 | address_space_init(&chip->xscom_as, &chip->xscom, name); |
247 | g_free(name); | |
248 | } | |
249 | ||
250 | static const TypeInfo pnv_xscom_interface_info = { | |
251 | .name = TYPE_PNV_XSCOM_INTERFACE, | |
252 | .parent = TYPE_INTERFACE, | |
253 | .class_size = sizeof(PnvXScomInterfaceClass), | |
254 | }; | |
255 | ||
256 | static void pnv_xscom_register_types(void) | |
257 | { | |
258 | type_register_static(&pnv_xscom_interface_info); | |
259 | } | |
260 | ||
261 | type_init(pnv_xscom_register_types) | |
262 | ||
263 | typedef struct ForeachPopulateArgs { | |
264 | void *fdt; | |
265 | int xscom_offset; | |
266 | } ForeachPopulateArgs; | |
267 | ||
b168a138 | 268 | static int xscom_dt_child(Object *child, void *opaque) |
967b7523 CLG |
269 | { |
270 | if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { | |
271 | ForeachPopulateArgs *args = opaque; | |
272 | PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); | |
273 | PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); | |
274 | ||
9e028fff CLG |
275 | /* |
276 | * Only "realized" devices should be configured in the DT | |
277 | */ | |
278 | if (xc->dt_xscom && DEVICE(child)->realized) { | |
b168a138 | 279 | _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); |
967b7523 CLG |
280 | } |
281 | } | |
282 | return 0; | |
283 | } | |
284 | ||
285 | static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; | |
286 | static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; | |
2b548a42 | 287 | static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; |
967b7523 | 288 | |
3f5b45ca GK |
289 | int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, |
290 | uint64_t xscom_base, uint64_t xscom_size) | |
967b7523 | 291 | { |
3f5b45ca | 292 | uint64_t reg[] = { xscom_base, xscom_size }; |
967b7523 CLG |
293 | int xscom_offset; |
294 | ForeachPopulateArgs args; | |
295 | char *name; | |
967b7523 CLG |
296 | |
297 | name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); | |
298 | xscom_offset = fdt_add_subnode(fdt, root_offset, name); | |
299 | _FDT(xscom_offset); | |
300 | g_free(name); | |
301 | _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id))); | |
302 | _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); | |
303 | _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); | |
304 | _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); | |
305 | ||
2b548a42 CLG |
306 | if (pnv_chip_is_power10(chip)) { |
307 | _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, | |
308 | sizeof(compat_p10)))); | |
309 | } else if (pnv_chip_is_power9(chip)) { | |
967b7523 CLG |
310 | _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, |
311 | sizeof(compat_p9)))); | |
312 | } else { | |
313 | _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, | |
314 | sizeof(compat_p8)))); | |
315 | } | |
316 | ||
317 | _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); | |
318 | ||
319 | args.fdt = fdt; | |
320 | args.xscom_offset = xscom_offset; | |
321 | ||
109dce37 CLG |
322 | /* |
323 | * Loop on the whole object hierarchy to catch all | |
324 | * PnvXScomInterface objects which can lie a bit deeper than the | |
325 | * first layer. | |
326 | */ | |
327 | object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args); | |
967b7523 CLG |
328 | return 0; |
329 | } | |
330 | ||
331 | void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr) | |
332 | { | |
333 | memory_region_add_subregion(&chip->xscom, offset << 3, mr); | |
334 | } | |
335 | ||
336 | void pnv_xscom_region_init(MemoryRegion *mr, | |
337 | struct Object *owner, | |
338 | const MemoryRegionOps *ops, | |
339 | void *opaque, | |
340 | const char *name, | |
341 | uint64_t size) | |
342 | { | |
343 | memory_region_init_io(mr, owner, ops, opaque, name, size << 3); | |
344 | } |