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a541f297 | 1 | /* |
e9df014c | 2 | * QEMU generic PowerPC hardware System Emulator |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
64552b6b | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
4771d756 | 26 | #include "cpu.h" |
64552b6b | 27 | #include "hw/irq.h" |
0d09e41a | 28 | #include "hw/ppc/ppc.h" |
2b927571 | 29 | #include "hw/ppc/ppc_e500.h" |
1de7afc9 | 30 | #include "qemu/timer.h" |
0ce470cd | 31 | #include "sysemu/cpus.h" |
1de7afc9 | 32 | #include "qemu/log.h" |
db725815 | 33 | #include "qemu/main-loop.h" |
98a8b524 | 34 | #include "qemu/error-report.h" |
9c17d615 | 35 | #include "sysemu/kvm.h" |
54d31236 | 36 | #include "sysemu/runstate.h" |
fc87e185 | 37 | #include "kvm_ppc.h" |
d6454270 | 38 | #include "migration/vmstate.h" |
98a8b524 | 39 | #include "trace.h" |
a541f297 | 40 | |
e9df014c | 41 | //#define PPC_DEBUG_IRQ |
4b6d0a4c | 42 | //#define PPC_DEBUG_TB |
e9df014c | 43 | |
d12d51d5 | 44 | #ifdef PPC_DEBUG_IRQ |
93fcfe39 | 45 | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
d12d51d5 AL |
46 | #else |
47 | # define LOG_IRQ(...) do { } while (0) | |
48 | #endif | |
49 | ||
50 | ||
51 | #ifdef PPC_DEBUG_TB | |
93fcfe39 | 52 | # define LOG_TB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
53 | #else |
54 | # define LOG_TB(...) do { } while (0) | |
55 | #endif | |
56 | ||
e2684c0b AF |
57 | static void cpu_ppc_tb_stop (CPUPPCState *env); |
58 | static void cpu_ppc_tb_start (CPUPPCState *env); | |
dbdd2506 | 59 | |
7058581a | 60 | void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) |
47103572 | 61 | { |
d8ed887b | 62 | CPUState *cs = CPU(cpu); |
7058581a | 63 | CPUPPCState *env = &cpu->env; |
8d04fb55 JK |
64 | unsigned int old_pending; |
65 | bool locked = false; | |
66 | ||
67 | /* We may already have the BQL if coming from the reset path */ | |
68 | if (!qemu_mutex_iothread_locked()) { | |
69 | locked = true; | |
70 | qemu_mutex_lock_iothread(); | |
71 | } | |
72 | ||
73 | old_pending = env->pending_interrupts; | |
fc87e185 | 74 | |
47103572 JM |
75 | if (level) { |
76 | env->pending_interrupts |= 1 << n_IRQ; | |
c3affe56 | 77 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
47103572 JM |
78 | } else { |
79 | env->pending_interrupts &= ~(1 << n_IRQ); | |
d8ed887b AF |
80 | if (env->pending_interrupts == 0) { |
81 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
82 | } | |
47103572 | 83 | } |
fc87e185 AG |
84 | |
85 | if (old_pending != env->pending_interrupts) { | |
7058581a | 86 | kvmppc_set_interrupt(cpu, n_IRQ, level); |
fc87e185 AG |
87 | } |
88 | ||
8d04fb55 | 89 | |
d12d51d5 | 90 | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 |
aae9366a | 91 | "req %08x\n", __func__, env, n_IRQ, level, |
259186a7 | 92 | env->pending_interrupts, CPU(cpu)->interrupt_request); |
8d04fb55 JK |
93 | |
94 | if (locked) { | |
95 | qemu_mutex_unlock_iothread(); | |
96 | } | |
47103572 JM |
97 | } |
98 | ||
e9df014c | 99 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
a0961245 | 100 | static void ppc6xx_set_irq(void *opaque, int pin, int level) |
d537cf6c | 101 | { |
a0961245 AF |
102 | PowerPCCPU *cpu = opaque; |
103 | CPUPPCState *env = &cpu->env; | |
e9df014c | 104 | int cur_level; |
d537cf6c | 105 | |
d12d51d5 | 106 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
a496775f | 107 | env, pin, level); |
e9df014c JM |
108 | cur_level = (env->irq_input_state >> pin) & 1; |
109 | /* Don't generate spurious events */ | |
24be5ae3 | 110 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
259186a7 AF |
111 | CPUState *cs = CPU(cpu); |
112 | ||
e9df014c | 113 | switch (pin) { |
dbdd2506 JM |
114 | case PPC6xx_INPUT_TBEN: |
115 | /* Level sensitive - active high */ | |
d12d51d5 | 116 | LOG_IRQ("%s: %s the time base\n", |
dbdd2506 | 117 | __func__, level ? "start" : "stop"); |
dbdd2506 JM |
118 | if (level) { |
119 | cpu_ppc_tb_start(env); | |
120 | } else { | |
121 | cpu_ppc_tb_stop(env); | |
122 | } | |
b2bd5b20 | 123 | break; |
24be5ae3 JM |
124 | case PPC6xx_INPUT_INT: |
125 | /* Level sensitive - active high */ | |
d12d51d5 | 126 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
a496775f | 127 | __func__, level); |
7058581a | 128 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
e9df014c | 129 | break; |
24be5ae3 | 130 | case PPC6xx_INPUT_SMI: |
e9df014c | 131 | /* Level sensitive - active high */ |
d12d51d5 | 132 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", |
a496775f | 133 | __func__, level); |
7058581a | 134 | ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); |
e9df014c | 135 | break; |
24be5ae3 | 136 | case PPC6xx_INPUT_MCP: |
e9df014c JM |
137 | /* Negative edge sensitive */ |
138 | /* XXX: TODO: actual reaction may depends on HID0 status | |
139 | * 603/604/740/750: check HID0[EMCP] | |
140 | */ | |
141 | if (cur_level == 1 && level == 0) { | |
d12d51d5 | 142 | LOG_IRQ("%s: raise machine check state\n", |
a496775f | 143 | __func__); |
7058581a | 144 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
e9df014c JM |
145 | } |
146 | break; | |
24be5ae3 | 147 | case PPC6xx_INPUT_CKSTP_IN: |
e9df014c JM |
148 | /* Level sensitive - active low */ |
149 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
e63ecc6f | 150 | /* XXX: Note that the only way to restart the CPU is to reset it */ |
e9df014c | 151 | if (level) { |
d12d51d5 | 152 | LOG_IRQ("%s: stop the CPU\n", __func__); |
259186a7 | 153 | cs->halted = 1; |
e9df014c JM |
154 | } |
155 | break; | |
24be5ae3 | 156 | case PPC6xx_INPUT_HRESET: |
e9df014c JM |
157 | /* Level sensitive - active low */ |
158 | if (level) { | |
d12d51d5 | 159 | LOG_IRQ("%s: reset the CPU\n", __func__); |
c3affe56 | 160 | cpu_interrupt(cs, CPU_INTERRUPT_RESET); |
e9df014c JM |
161 | } |
162 | break; | |
24be5ae3 | 163 | case PPC6xx_INPUT_SRESET: |
d12d51d5 | 164 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
a496775f | 165 | __func__, level); |
7058581a | 166 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
e9df014c JM |
167 | break; |
168 | default: | |
169 | /* Unknown pin - do nothing */ | |
d12d51d5 | 170 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
e9df014c JM |
171 | return; |
172 | } | |
173 | if (level) | |
174 | env->irq_input_state |= 1 << pin; | |
175 | else | |
176 | env->irq_input_state &= ~(1 << pin); | |
d537cf6c PB |
177 | } |
178 | } | |
179 | ||
aa5a9e24 | 180 | void ppc6xx_irq_init(PowerPCCPU *cpu) |
47103572 | 181 | { |
aa5a9e24 | 182 | CPUPPCState *env = &cpu->env; |
a0961245 AF |
183 | |
184 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, | |
7b62a955 | 185 | PPC6xx_INPUT_NB); |
47103572 JM |
186 | } |
187 | ||
00af685f | 188 | #if defined(TARGET_PPC64) |
d0dfae6e | 189 | /* PowerPC 970 internal IRQ controller */ |
a0961245 | 190 | static void ppc970_set_irq(void *opaque, int pin, int level) |
d0dfae6e | 191 | { |
a0961245 AF |
192 | PowerPCCPU *cpu = opaque; |
193 | CPUPPCState *env = &cpu->env; | |
d0dfae6e JM |
194 | int cur_level; |
195 | ||
d12d51d5 | 196 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
d0dfae6e | 197 | env, pin, level); |
d0dfae6e JM |
198 | cur_level = (env->irq_input_state >> pin) & 1; |
199 | /* Don't generate spurious events */ | |
200 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
259186a7 AF |
201 | CPUState *cs = CPU(cpu); |
202 | ||
d0dfae6e JM |
203 | switch (pin) { |
204 | case PPC970_INPUT_INT: | |
205 | /* Level sensitive - active high */ | |
d12d51d5 | 206 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
d0dfae6e | 207 | __func__, level); |
7058581a | 208 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
d0dfae6e JM |
209 | break; |
210 | case PPC970_INPUT_THINT: | |
211 | /* Level sensitive - active high */ | |
d12d51d5 | 212 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, |
d0dfae6e | 213 | level); |
7058581a | 214 | ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); |
d0dfae6e JM |
215 | break; |
216 | case PPC970_INPUT_MCP: | |
217 | /* Negative edge sensitive */ | |
218 | /* XXX: TODO: actual reaction may depends on HID0 status | |
219 | * 603/604/740/750: check HID0[EMCP] | |
220 | */ | |
221 | if (cur_level == 1 && level == 0) { | |
d12d51d5 | 222 | LOG_IRQ("%s: raise machine check state\n", |
d0dfae6e | 223 | __func__); |
7058581a | 224 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
d0dfae6e JM |
225 | } |
226 | break; | |
227 | case PPC970_INPUT_CKSTP: | |
228 | /* Level sensitive - active low */ | |
229 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ | |
230 | if (level) { | |
d12d51d5 | 231 | LOG_IRQ("%s: stop the CPU\n", __func__); |
259186a7 | 232 | cs->halted = 1; |
d0dfae6e | 233 | } else { |
d12d51d5 | 234 | LOG_IRQ("%s: restart the CPU\n", __func__); |
259186a7 AF |
235 | cs->halted = 0; |
236 | qemu_cpu_kick(cs); | |
d0dfae6e JM |
237 | } |
238 | break; | |
239 | case PPC970_INPUT_HRESET: | |
240 | /* Level sensitive - active low */ | |
241 | if (level) { | |
c3affe56 | 242 | cpu_interrupt(cs, CPU_INTERRUPT_RESET); |
d0dfae6e JM |
243 | } |
244 | break; | |
245 | case PPC970_INPUT_SRESET: | |
d12d51d5 | 246 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
d0dfae6e | 247 | __func__, level); |
7058581a | 248 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
d0dfae6e JM |
249 | break; |
250 | case PPC970_INPUT_TBEN: | |
d12d51d5 | 251 | LOG_IRQ("%s: set the TBEN state to %d\n", __func__, |
d0dfae6e | 252 | level); |
d0dfae6e JM |
253 | /* XXX: TODO */ |
254 | break; | |
255 | default: | |
256 | /* Unknown pin - do nothing */ | |
d12d51d5 | 257 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
d0dfae6e JM |
258 | return; |
259 | } | |
260 | if (level) | |
261 | env->irq_input_state |= 1 << pin; | |
262 | else | |
263 | env->irq_input_state &= ~(1 << pin); | |
264 | } | |
265 | } | |
266 | ||
aa5a9e24 | 267 | void ppc970_irq_init(PowerPCCPU *cpu) |
d0dfae6e | 268 | { |
aa5a9e24 | 269 | CPUPPCState *env = &cpu->env; |
a0961245 AF |
270 | |
271 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, | |
7b62a955 | 272 | PPC970_INPUT_NB); |
d0dfae6e | 273 | } |
9d52e907 DG |
274 | |
275 | /* POWER7 internal IRQ controller */ | |
a0961245 | 276 | static void power7_set_irq(void *opaque, int pin, int level) |
9d52e907 | 277 | { |
a0961245 | 278 | PowerPCCPU *cpu = opaque; |
9d52e907 DG |
279 | |
280 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, | |
c1ad0b89 | 281 | &cpu->env, pin, level); |
9d52e907 DG |
282 | |
283 | switch (pin) { | |
284 | case POWER7_INPUT_INT: | |
285 | /* Level sensitive - active high */ | |
286 | LOG_IRQ("%s: set the external IRQ state to %d\n", | |
287 | __func__, level); | |
7058581a | 288 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
9d52e907 DG |
289 | break; |
290 | default: | |
291 | /* Unknown pin - do nothing */ | |
292 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); | |
293 | return; | |
294 | } | |
9d52e907 DG |
295 | } |
296 | ||
aa5a9e24 | 297 | void ppcPOWER7_irq_init(PowerPCCPU *cpu) |
9d52e907 | 298 | { |
aa5a9e24 | 299 | CPUPPCState *env = &cpu->env; |
a0961245 AF |
300 | |
301 | env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, | |
9d52e907 DG |
302 | POWER7_INPUT_NB); |
303 | } | |
67afe775 BH |
304 | |
305 | /* POWER9 internal IRQ controller */ | |
306 | static void power9_set_irq(void *opaque, int pin, int level) | |
307 | { | |
308 | PowerPCCPU *cpu = opaque; | |
67afe775 BH |
309 | |
310 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, | |
c1ad0b89 | 311 | &cpu->env, pin, level); |
67afe775 BH |
312 | |
313 | switch (pin) { | |
314 | case POWER9_INPUT_INT: | |
315 | /* Level sensitive - active high */ | |
316 | LOG_IRQ("%s: set the external IRQ state to %d\n", | |
317 | __func__, level); | |
318 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); | |
319 | break; | |
320 | case POWER9_INPUT_HINT: | |
321 | /* Level sensitive - active high */ | |
322 | LOG_IRQ("%s: set the external IRQ state to %d\n", | |
323 | __func__, level); | |
324 | ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); | |
325 | break; | |
326 | default: | |
327 | /* Unknown pin - do nothing */ | |
328 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); | |
329 | return; | |
330 | } | |
67afe775 BH |
331 | } |
332 | ||
333 | void ppcPOWER9_irq_init(PowerPCCPU *cpu) | |
334 | { | |
335 | CPUPPCState *env = &cpu->env; | |
336 | ||
337 | env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, | |
338 | POWER9_INPUT_NB); | |
339 | } | |
00af685f | 340 | #endif /* defined(TARGET_PPC64) */ |
d0dfae6e | 341 | |
52144b69 TH |
342 | void ppc40x_core_reset(PowerPCCPU *cpu) |
343 | { | |
344 | CPUPPCState *env = &cpu->env; | |
345 | target_ulong dbsr; | |
346 | ||
347 | qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); | |
348 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); | |
349 | dbsr = env->spr[SPR_40x_DBSR]; | |
350 | dbsr &= ~0x00000300; | |
351 | dbsr |= 0x00000100; | |
352 | env->spr[SPR_40x_DBSR] = dbsr; | |
353 | } | |
354 | ||
355 | void ppc40x_chip_reset(PowerPCCPU *cpu) | |
356 | { | |
357 | CPUPPCState *env = &cpu->env; | |
358 | target_ulong dbsr; | |
359 | ||
360 | qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); | |
361 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); | |
362 | /* XXX: TODO reset all internal peripherals */ | |
363 | dbsr = env->spr[SPR_40x_DBSR]; | |
364 | dbsr &= ~0x00000300; | |
365 | dbsr |= 0x00000200; | |
366 | env->spr[SPR_40x_DBSR] = dbsr; | |
367 | } | |
368 | ||
369 | void ppc40x_system_reset(PowerPCCPU *cpu) | |
370 | { | |
371 | qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); | |
372 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
373 | } | |
374 | ||
375 | void store_40x_dbcr0(CPUPPCState *env, uint32_t val) | |
376 | { | |
db70b311 | 377 | PowerPCCPU *cpu = env_archcpu(env); |
52144b69 TH |
378 | |
379 | switch ((val >> 28) & 0x3) { | |
380 | case 0x0: | |
381 | /* No action */ | |
382 | break; | |
383 | case 0x1: | |
384 | /* Core reset */ | |
385 | ppc40x_core_reset(cpu); | |
386 | break; | |
387 | case 0x2: | |
388 | /* Chip reset */ | |
389 | ppc40x_chip_reset(cpu); | |
390 | break; | |
391 | case 0x3: | |
392 | /* System reset */ | |
393 | ppc40x_system_reset(cpu); | |
394 | break; | |
395 | } | |
396 | } | |
397 | ||
4e290a0b | 398 | /* PowerPC 40x internal IRQ controller */ |
a0961245 | 399 | static void ppc40x_set_irq(void *opaque, int pin, int level) |
24be5ae3 | 400 | { |
a0961245 AF |
401 | PowerPCCPU *cpu = opaque; |
402 | CPUPPCState *env = &cpu->env; | |
24be5ae3 JM |
403 | int cur_level; |
404 | ||
d12d51d5 | 405 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
8ecc7913 | 406 | env, pin, level); |
24be5ae3 JM |
407 | cur_level = (env->irq_input_state >> pin) & 1; |
408 | /* Don't generate spurious events */ | |
409 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
259186a7 AF |
410 | CPUState *cs = CPU(cpu); |
411 | ||
24be5ae3 | 412 | switch (pin) { |
4e290a0b | 413 | case PPC40x_INPUT_RESET_SYS: |
8ecc7913 | 414 | if (level) { |
d12d51d5 | 415 | LOG_IRQ("%s: reset the PowerPC system\n", |
8ecc7913 | 416 | __func__); |
f3273ba6 | 417 | ppc40x_system_reset(cpu); |
8ecc7913 JM |
418 | } |
419 | break; | |
4e290a0b | 420 | case PPC40x_INPUT_RESET_CHIP: |
8ecc7913 | 421 | if (level) { |
d12d51d5 | 422 | LOG_IRQ("%s: reset the PowerPC chip\n", __func__); |
f3273ba6 | 423 | ppc40x_chip_reset(cpu); |
8ecc7913 JM |
424 | } |
425 | break; | |
4e290a0b | 426 | case PPC40x_INPUT_RESET_CORE: |
24be5ae3 JM |
427 | /* XXX: TODO: update DBSR[MRR] */ |
428 | if (level) { | |
d12d51d5 | 429 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
f3273ba6 | 430 | ppc40x_core_reset(cpu); |
24be5ae3 JM |
431 | } |
432 | break; | |
4e290a0b | 433 | case PPC40x_INPUT_CINT: |
24be5ae3 | 434 | /* Level sensitive - active high */ |
d12d51d5 | 435 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
8ecc7913 | 436 | __func__, level); |
7058581a | 437 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
24be5ae3 | 438 | break; |
4e290a0b | 439 | case PPC40x_INPUT_INT: |
24be5ae3 | 440 | /* Level sensitive - active high */ |
d12d51d5 | 441 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
a496775f | 442 | __func__, level); |
7058581a | 443 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
24be5ae3 | 444 | break; |
4e290a0b | 445 | case PPC40x_INPUT_HALT: |
24be5ae3 JM |
446 | /* Level sensitive - active low */ |
447 | if (level) { | |
d12d51d5 | 448 | LOG_IRQ("%s: stop the CPU\n", __func__); |
259186a7 | 449 | cs->halted = 1; |
24be5ae3 | 450 | } else { |
d12d51d5 | 451 | LOG_IRQ("%s: restart the CPU\n", __func__); |
259186a7 AF |
452 | cs->halted = 0; |
453 | qemu_cpu_kick(cs); | |
24be5ae3 JM |
454 | } |
455 | break; | |
4e290a0b | 456 | case PPC40x_INPUT_DEBUG: |
24be5ae3 | 457 | /* Level sensitive - active high */ |
d12d51d5 | 458 | LOG_IRQ("%s: set the debug pin state to %d\n", |
a496775f | 459 | __func__, level); |
7058581a | 460 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
24be5ae3 JM |
461 | break; |
462 | default: | |
463 | /* Unknown pin - do nothing */ | |
d12d51d5 | 464 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
24be5ae3 JM |
465 | return; |
466 | } | |
467 | if (level) | |
468 | env->irq_input_state |= 1 << pin; | |
469 | else | |
470 | env->irq_input_state &= ~(1 << pin); | |
471 | } | |
472 | } | |
473 | ||
aa5a9e24 | 474 | void ppc40x_irq_init(PowerPCCPU *cpu) |
24be5ae3 | 475 | { |
aa5a9e24 | 476 | CPUPPCState *env = &cpu->env; |
a0961245 | 477 | |
4e290a0b | 478 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
a0961245 | 479 | cpu, PPC40x_INPUT_NB); |
24be5ae3 JM |
480 | } |
481 | ||
9fdc60bf | 482 | /* PowerPC E500 internal IRQ controller */ |
a0961245 | 483 | static void ppce500_set_irq(void *opaque, int pin, int level) |
9fdc60bf | 484 | { |
a0961245 AF |
485 | PowerPCCPU *cpu = opaque; |
486 | CPUPPCState *env = &cpu->env; | |
9fdc60bf AJ |
487 | int cur_level; |
488 | ||
489 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, | |
490 | env, pin, level); | |
491 | cur_level = (env->irq_input_state >> pin) & 1; | |
492 | /* Don't generate spurious events */ | |
493 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { | |
494 | switch (pin) { | |
495 | case PPCE500_INPUT_MCK: | |
496 | if (level) { | |
497 | LOG_IRQ("%s: reset the PowerPC system\n", | |
498 | __func__); | |
cf83f140 | 499 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
9fdc60bf AJ |
500 | } |
501 | break; | |
502 | case PPCE500_INPUT_RESET_CORE: | |
503 | if (level) { | |
504 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); | |
7058581a | 505 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); |
9fdc60bf AJ |
506 | } |
507 | break; | |
508 | case PPCE500_INPUT_CINT: | |
509 | /* Level sensitive - active high */ | |
510 | LOG_IRQ("%s: set the critical IRQ state to %d\n", | |
511 | __func__, level); | |
7058581a | 512 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
9fdc60bf AJ |
513 | break; |
514 | case PPCE500_INPUT_INT: | |
515 | /* Level sensitive - active high */ | |
516 | LOG_IRQ("%s: set the core IRQ state to %d\n", | |
517 | __func__, level); | |
7058581a | 518 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
9fdc60bf AJ |
519 | break; |
520 | case PPCE500_INPUT_DEBUG: | |
521 | /* Level sensitive - active high */ | |
522 | LOG_IRQ("%s: set the debug pin state to %d\n", | |
523 | __func__, level); | |
7058581a | 524 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
9fdc60bf AJ |
525 | break; |
526 | default: | |
527 | /* Unknown pin - do nothing */ | |
528 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); | |
529 | return; | |
530 | } | |
531 | if (level) | |
532 | env->irq_input_state |= 1 << pin; | |
533 | else | |
534 | env->irq_input_state &= ~(1 << pin); | |
535 | } | |
536 | } | |
537 | ||
aa5a9e24 | 538 | void ppce500_irq_init(PowerPCCPU *cpu) |
9fdc60bf | 539 | { |
aa5a9e24 | 540 | CPUPPCState *env = &cpu->env; |
a0961245 | 541 | |
9fdc60bf | 542 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, |
a0961245 | 543 | cpu, PPCE500_INPUT_NB); |
9fdc60bf | 544 | } |
e49798b1 AG |
545 | |
546 | /* Enable or Disable the E500 EPR capability */ | |
547 | void ppce500_set_mpic_proxy(bool enabled) | |
548 | { | |
182735ef | 549 | CPUState *cs; |
e49798b1 | 550 | |
bdc44640 | 551 | CPU_FOREACH(cs) { |
182735ef | 552 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
5b95b8b9 | 553 | |
182735ef | 554 | cpu->env.mpic_proxy = enabled; |
5b95b8b9 | 555 | if (kvm_enabled()) { |
182735ef | 556 | kvmppc_set_mpic_proxy(cpu, enabled); |
5b95b8b9 | 557 | } |
e49798b1 AG |
558 | } |
559 | } | |
560 | ||
9fddaa0c | 561 | /*****************************************************************************/ |
e9df014c | 562 | /* PowerPC time base and decrementer emulation */ |
9fddaa0c | 563 | |
ddd1055b | 564 | uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) |
9fddaa0c FB |
565 | { |
566 | /* TB time in tb periods */ | |
73bcb24d | 567 | return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; |
9fddaa0c FB |
568 | } |
569 | ||
e2684c0b | 570 | uint64_t cpu_ppc_load_tbl (CPUPPCState *env) |
9fddaa0c | 571 | { |
c227f099 | 572 | ppc_tb_t *tb_env = env->tb_env; |
9fddaa0c FB |
573 | uint64_t tb; |
574 | ||
90dc8812 SW |
575 | if (kvm_enabled()) { |
576 | return env->spr[SPR_TBL]; | |
577 | } | |
578 | ||
bc72ad67 | 579 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
d12d51d5 | 580 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
9fddaa0c | 581 | |
e3ea6529 | 582 | return tb; |
9fddaa0c FB |
583 | } |
584 | ||
e2684c0b | 585 | static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) |
9fddaa0c | 586 | { |
c227f099 | 587 | ppc_tb_t *tb_env = env->tb_env; |
9fddaa0c FB |
588 | uint64_t tb; |
589 | ||
bc72ad67 | 590 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
d12d51d5 | 591 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
76a66253 | 592 | |
9fddaa0c FB |
593 | return tb >> 32; |
594 | } | |
595 | ||
e2684c0b | 596 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env) |
8a84de23 | 597 | { |
90dc8812 SW |
598 | if (kvm_enabled()) { |
599 | return env->spr[SPR_TBU]; | |
600 | } | |
601 | ||
8a84de23 JM |
602 | return _cpu_ppc_load_tbu(env); |
603 | } | |
604 | ||
c227f099 | 605 | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
636aa200 | 606 | int64_t *tb_offsetp, uint64_t value) |
9fddaa0c | 607 | { |
73bcb24d RS |
608 | *tb_offsetp = value - |
609 | muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); | |
610 | ||
d12d51d5 | 611 | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
aae9366a | 612 | __func__, value, *tb_offsetp); |
9fddaa0c FB |
613 | } |
614 | ||
e2684c0b | 615 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) |
a062e36c | 616 | { |
c227f099 | 617 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c JM |
618 | uint64_t tb; |
619 | ||
bc72ad67 | 620 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
a062e36c | 621 | tb &= 0xFFFFFFFF00000000ULL; |
bc72ad67 | 622 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
dbdd2506 | 623 | &tb_env->tb_offset, tb | (uint64_t)value); |
a062e36c JM |
624 | } |
625 | ||
e2684c0b | 626 | static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) |
9fddaa0c | 627 | { |
c227f099 | 628 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c | 629 | uint64_t tb; |
9fddaa0c | 630 | |
bc72ad67 | 631 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
a062e36c | 632 | tb &= 0x00000000FFFFFFFFULL; |
bc72ad67 | 633 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
dbdd2506 | 634 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); |
9fddaa0c FB |
635 | } |
636 | ||
e2684c0b | 637 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) |
8a84de23 JM |
638 | { |
639 | _cpu_ppc_store_tbu(env, value); | |
640 | } | |
641 | ||
e2684c0b | 642 | uint64_t cpu_ppc_load_atbl (CPUPPCState *env) |
a062e36c | 643 | { |
c227f099 | 644 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c JM |
645 | uint64_t tb; |
646 | ||
bc72ad67 | 647 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
d12d51d5 | 648 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
a062e36c | 649 | |
b711de95 | 650 | return tb; |
a062e36c JM |
651 | } |
652 | ||
e2684c0b | 653 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env) |
a062e36c | 654 | { |
c227f099 | 655 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c JM |
656 | uint64_t tb; |
657 | ||
bc72ad67 | 658 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
d12d51d5 | 659 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
a062e36c JM |
660 | |
661 | return tb >> 32; | |
662 | } | |
663 | ||
e2684c0b | 664 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) |
a062e36c | 665 | { |
c227f099 | 666 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c JM |
667 | uint64_t tb; |
668 | ||
bc72ad67 | 669 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
a062e36c | 670 | tb &= 0xFFFFFFFF00000000ULL; |
bc72ad67 | 671 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
dbdd2506 | 672 | &tb_env->atb_offset, tb | (uint64_t)value); |
a062e36c JM |
673 | } |
674 | ||
e2684c0b | 675 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) |
9fddaa0c | 676 | { |
c227f099 | 677 | ppc_tb_t *tb_env = env->tb_env; |
a062e36c | 678 | uint64_t tb; |
9fddaa0c | 679 | |
bc72ad67 | 680 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
a062e36c | 681 | tb &= 0x00000000FFFFFFFFULL; |
bc72ad67 | 682 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
dbdd2506 JM |
683 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); |
684 | } | |
685 | ||
5d62725b SJS |
686 | uint64_t cpu_ppc_load_vtb(CPUPPCState *env) |
687 | { | |
688 | ppc_tb_t *tb_env = env->tb_env; | |
689 | ||
690 | return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
691 | tb_env->vtb_offset); | |
692 | } | |
693 | ||
694 | void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) | |
695 | { | |
696 | ppc_tb_t *tb_env = env->tb_env; | |
697 | ||
698 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
699 | &tb_env->vtb_offset, value); | |
700 | } | |
701 | ||
f0ec31b1 SJS |
702 | void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) |
703 | { | |
704 | ppc_tb_t *tb_env = env->tb_env; | |
705 | uint64_t tb; | |
706 | ||
707 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
708 | tb_env->tb_offset); | |
709 | tb &= 0xFFFFFFUL; | |
710 | tb |= (value & ~0xFFFFFFUL); | |
711 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
712 | &tb_env->tb_offset, tb); | |
713 | } | |
714 | ||
e2684c0b | 715 | static void cpu_ppc_tb_stop (CPUPPCState *env) |
dbdd2506 | 716 | { |
c227f099 | 717 | ppc_tb_t *tb_env = env->tb_env; |
dbdd2506 JM |
718 | uint64_t tb, atb, vmclk; |
719 | ||
720 | /* If the time base is already frozen, do nothing */ | |
721 | if (tb_env->tb_freq != 0) { | |
bc72ad67 | 722 | vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
dbdd2506 JM |
723 | /* Get the time base */ |
724 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); | |
725 | /* Get the alternate time base */ | |
726 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); | |
727 | /* Store the time base value (ie compute the current offset) */ | |
728 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
729 | /* Store the alternate time base value (compute the current offset) */ | |
730 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
731 | /* Set the time base frequency to zero */ | |
732 | tb_env->tb_freq = 0; | |
733 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ | |
734 | } | |
735 | } | |
736 | ||
e2684c0b | 737 | static void cpu_ppc_tb_start (CPUPPCState *env) |
dbdd2506 | 738 | { |
c227f099 | 739 | ppc_tb_t *tb_env = env->tb_env; |
dbdd2506 | 740 | uint64_t tb, atb, vmclk; |
aae9366a | 741 | |
dbdd2506 JM |
742 | /* If the time base is not frozen, do nothing */ |
743 | if (tb_env->tb_freq == 0) { | |
bc72ad67 | 744 | vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
dbdd2506 JM |
745 | /* Get the time base from tb_offset */ |
746 | tb = tb_env->tb_offset; | |
747 | /* Get the alternate time base from atb_offset */ | |
748 | atb = tb_env->atb_offset; | |
749 | /* Restore the tb frequency from the decrementer frequency */ | |
750 | tb_env->tb_freq = tb_env->decr_freq; | |
751 | /* Store the time base value */ | |
752 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); | |
753 | /* Store the alternate time base value */ | |
754 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); | |
755 | } | |
9fddaa0c FB |
756 | } |
757 | ||
e81a982a AG |
758 | bool ppc_decr_clear_on_delivery(CPUPPCState *env) |
759 | { | |
760 | ppc_tb_t *tb_env = env->tb_env; | |
761 | int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; | |
762 | return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); | |
763 | } | |
764 | ||
a8dafa52 | 765 | static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) |
9fddaa0c | 766 | { |
c227f099 | 767 | ppc_tb_t *tb_env = env->tb_env; |
a8dafa52 | 768 | int64_t decr, diff; |
9fddaa0c | 769 | |
bc72ad67 | 770 | diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
ddd1055b | 771 | if (diff >= 0) { |
73bcb24d | 772 | decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); |
ddd1055b FC |
773 | } else if (tb_env->flags & PPC_TIMER_BOOKE) { |
774 | decr = 0; | |
775 | } else { | |
73bcb24d | 776 | decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); |
ddd1055b | 777 | } |
a8dafa52 | 778 | LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); |
76a66253 | 779 | |
9fddaa0c FB |
780 | return decr; |
781 | } | |
782 | ||
a8dafa52 | 783 | target_ulong cpu_ppc_load_decr(CPUPPCState *env) |
58a7d328 | 784 | { |
c227f099 | 785 | ppc_tb_t *tb_env = env->tb_env; |
a8dafa52 | 786 | uint64_t decr; |
58a7d328 | 787 | |
90dc8812 SW |
788 | if (kvm_enabled()) { |
789 | return env->spr[SPR_DECR]; | |
790 | } | |
791 | ||
a8dafa52 SJS |
792 | decr = _cpu_ppc_load_decr(env, tb_env->decr_next); |
793 | ||
794 | /* | |
795 | * If large decrementer is enabled then the decrementer is signed extened | |
796 | * to 64 bits, otherwise it is a 32 bit value. | |
797 | */ | |
798 | if (env->spr[SPR_LPCR] & LPCR_LD) { | |
799 | return decr; | |
800 | } | |
801 | return (uint32_t) decr; | |
58a7d328 JM |
802 | } |
803 | ||
a8dafa52 | 804 | target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) |
58a7d328 | 805 | { |
db70b311 | 806 | PowerPCCPU *cpu = env_archcpu(env); |
a8dafa52 | 807 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
c227f099 | 808 | ppc_tb_t *tb_env = env->tb_env; |
a8dafa52 SJS |
809 | uint64_t hdecr; |
810 | ||
811 | hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); | |
58a7d328 | 812 | |
a8dafa52 SJS |
813 | /* |
814 | * If we have a large decrementer (POWER9 or later) then hdecr is sign | |
815 | * extended to 64 bits, otherwise it is 32 bits. | |
816 | */ | |
817 | if (pcc->lrg_decr_bits > 32) { | |
818 | return hdecr; | |
819 | } | |
820 | return (uint32_t) hdecr; | |
58a7d328 JM |
821 | } |
822 | ||
e2684c0b | 823 | uint64_t cpu_ppc_load_purr (CPUPPCState *env) |
58a7d328 | 824 | { |
c227f099 | 825 | ppc_tb_t *tb_env = env->tb_env; |
58a7d328 | 826 | |
5cc7e69f SJS |
827 | return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
828 | tb_env->purr_offset); | |
58a7d328 | 829 | } |
58a7d328 | 830 | |
9fddaa0c FB |
831 | /* When decrementer expires, |
832 | * all we need to do is generate or queue a CPU exception | |
833 | */ | |
7e0a9247 | 834 | static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) |
9fddaa0c FB |
835 | { |
836 | /* Raise it */ | |
d12d51d5 | 837 | LOG_TB("raise decrementer exception\n"); |
7058581a | 838 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); |
9fddaa0c FB |
839 | } |
840 | ||
e81a982a AG |
841 | static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) |
842 | { | |
843 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); | |
844 | } | |
845 | ||
7e0a9247 | 846 | static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) |
58a7d328 | 847 | { |
4b236b62 BH |
848 | CPUPPCState *env = &cpu->env; |
849 | ||
58a7d328 | 850 | /* Raise it */ |
4b236b62 BH |
851 | LOG_TB("raise hv decrementer exception\n"); |
852 | ||
853 | /* The architecture specifies that we don't deliver HDEC | |
854 | * interrupts in a PM state. Not only they don't cause a | |
855 | * wakeup but they also get effectively discarded. | |
856 | */ | |
1e7fd61d | 857 | if (!env->resume_as_sreset) { |
4b236b62 BH |
858 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); |
859 | } | |
58a7d328 JM |
860 | } |
861 | ||
e81a982a AG |
862 | static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) |
863 | { | |
864 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); | |
865 | } | |
866 | ||
7e0a9247 | 867 | static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, |
1246b259 | 868 | QEMUTimer *timer, |
e81a982a AG |
869 | void (*raise_excp)(void *), |
870 | void (*lower_excp)(PowerPCCPU *), | |
a8dafa52 SJS |
871 | target_ulong decr, target_ulong value, |
872 | int nr_bits) | |
9fddaa0c | 873 | { |
7e0a9247 | 874 | CPUPPCState *env = &cpu->env; |
c227f099 | 875 | ppc_tb_t *tb_env = env->tb_env; |
9fddaa0c | 876 | uint64_t now, next; |
a8dafa52 SJS |
877 | bool negative; |
878 | ||
879 | /* Truncate value to decr_width and sign extend for simplicity */ | |
880 | value &= ((1ULL << nr_bits) - 1); | |
881 | negative = !!(value & (1ULL << (nr_bits - 1))); | |
882 | if (negative) { | |
883 | value |= (0xFFFFFFFFULL << nr_bits); | |
884 | } | |
9fddaa0c | 885 | |
a8dafa52 | 886 | LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, |
aae9366a | 887 | decr, value); |
55f7d4b0 DG |
888 | |
889 | if (kvm_enabled()) { | |
890 | /* KVM handles decrementer exceptions, we don't need our own timer */ | |
891 | return; | |
892 | } | |
893 | ||
e81a982a AG |
894 | /* |
895 | * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC | |
896 | * interrupt. | |
897 | * | |
898 | * If we get a really small DEC value, we can assume that by the time we | |
899 | * handled it we should inject an interrupt already. | |
900 | * | |
901 | * On MSB level based DEC implementations the MSB always means the interrupt | |
902 | * is pending, so raise it on those. | |
903 | * | |
904 | * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers | |
905 | * an edge interrupt, so raise it here too. | |
906 | */ | |
907 | if ((value < 3) || | |
a8dafa52 SJS |
908 | ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || |
909 | ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative | |
910 | && !(decr & (1ULL << (nr_bits - 1))))) { | |
e81a982a AG |
911 | (*raise_excp)(cpu); |
912 | return; | |
ddd1055b | 913 | } |
e81a982a AG |
914 | |
915 | /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ | |
a8dafa52 | 916 | if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { |
e81a982a | 917 | (*lower_excp)(cpu); |
ddd1055b | 918 | } |
e81a982a AG |
919 | |
920 | /* Calculate the next timer event */ | |
921 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
73bcb24d | 922 | next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); |
58a7d328 | 923 | *nextp = next; |
e81a982a | 924 | |
9fddaa0c | 925 | /* Adjust timer */ |
bc72ad67 | 926 | timer_mod(timer, next); |
58a7d328 JM |
927 | } |
928 | ||
a8dafa52 SJS |
929 | static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, |
930 | target_ulong value, int nr_bits) | |
58a7d328 | 931 | { |
7e0a9247 | 932 | ppc_tb_t *tb_env = cpu->env.tb_env; |
58a7d328 | 933 | |
7e0a9247 | 934 | __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, |
e81a982a | 935 | tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, |
a8dafa52 | 936 | value, nr_bits); |
9fddaa0c FB |
937 | } |
938 | ||
a8dafa52 | 939 | void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) |
9fddaa0c | 940 | { |
db70b311 | 941 | PowerPCCPU *cpu = env_archcpu(env); |
a8dafa52 SJS |
942 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
943 | int nr_bits = 32; | |
944 | ||
945 | if (env->spr[SPR_LPCR] & LPCR_LD) { | |
946 | nr_bits = pcc->lrg_decr_bits; | |
947 | } | |
7e0a9247 | 948 | |
a8dafa52 | 949 | _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); |
9fddaa0c FB |
950 | } |
951 | ||
50c680f0 | 952 | static void cpu_ppc_decr_cb(void *opaque) |
9fddaa0c | 953 | { |
50c680f0 | 954 | PowerPCCPU *cpu = opaque; |
7e0a9247 | 955 | |
e81a982a | 956 | cpu_ppc_decr_excp(cpu); |
9fddaa0c FB |
957 | } |
958 | ||
a8dafa52 SJS |
959 | static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, |
960 | target_ulong value, int nr_bits) | |
58a7d328 | 961 | { |
7e0a9247 | 962 | ppc_tb_t *tb_env = cpu->env.tb_env; |
58a7d328 | 963 | |
b172c56a | 964 | if (tb_env->hdecr_timer != NULL) { |
7e0a9247 | 965 | __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, |
e81a982a | 966 | tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, |
a8dafa52 | 967 | hdecr, value, nr_bits); |
b172c56a | 968 | } |
58a7d328 JM |
969 | } |
970 | ||
a8dafa52 | 971 | void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) |
58a7d328 | 972 | { |
db70b311 | 973 | PowerPCCPU *cpu = env_archcpu(env); |
a8dafa52 | 974 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
7e0a9247 | 975 | |
a8dafa52 SJS |
976 | _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, |
977 | pcc->lrg_decr_bits); | |
58a7d328 JM |
978 | } |
979 | ||
50c680f0 | 980 | static void cpu_ppc_hdecr_cb(void *opaque) |
58a7d328 | 981 | { |
50c680f0 | 982 | PowerPCCPU *cpu = opaque; |
7e0a9247 | 983 | |
e81a982a | 984 | cpu_ppc_hdecr_excp(cpu); |
58a7d328 JM |
985 | } |
986 | ||
5cc7e69f | 987 | void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) |
58a7d328 | 988 | { |
5cc7e69f | 989 | ppc_tb_t *tb_env = env->tb_env; |
58a7d328 | 990 | |
5cc7e69f SJS |
991 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
992 | &tb_env->purr_offset, value); | |
58a7d328 | 993 | } |
58a7d328 | 994 | |
8ecc7913 JM |
995 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
996 | { | |
e2684c0b | 997 | CPUPPCState *env = opaque; |
db70b311 | 998 | PowerPCCPU *cpu = env_archcpu(env); |
c227f099 | 999 | ppc_tb_t *tb_env = env->tb_env; |
8ecc7913 JM |
1000 | |
1001 | tb_env->tb_freq = freq; | |
dbdd2506 | 1002 | tb_env->decr_freq = freq; |
8ecc7913 JM |
1003 | /* There is a bug in Linux 2.4 kernels: |
1004 | * if a decrementer exception is pending when it enables msr_ee at startup, | |
1005 | * it's not ready to handle it... | |
1006 | */ | |
a8dafa52 SJS |
1007 | _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); |
1008 | _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); | |
5cc7e69f | 1009 | cpu_ppc_store_purr(env, 0x0000000000000000ULL); |
8ecc7913 JM |
1010 | } |
1011 | ||
42043e4f | 1012 | static void timebase_save(PPCTimebase *tb) |
98a8b524 | 1013 | { |
4a7428c5 | 1014 | uint64_t ticks = cpu_get_host_ticks(); |
98a8b524 AK |
1015 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
1016 | ||
1017 | if (!first_ppc_cpu->env.tb_env) { | |
1018 | error_report("No timebase object"); | |
1019 | return; | |
1020 | } | |
1021 | ||
42043e4f | 1022 | /* not used anymore, we keep it for compatibility */ |
77bad151 | 1023 | tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); |
98a8b524 | 1024 | /* |
42043e4f | 1025 | * tb_offset is only expected to be changed by QEMU so |
98a8b524 AK |
1026 | * there is no need to update it from KVM here |
1027 | */ | |
1028 | tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; | |
d14f3397 | 1029 | |
711dfb24 GK |
1030 | tb->runstate_paused = |
1031 | runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM); | |
98a8b524 AK |
1032 | } |
1033 | ||
42043e4f | 1034 | static void timebase_load(PPCTimebase *tb) |
98a8b524 | 1035 | { |
98a8b524 AK |
1036 | CPUState *cpu; |
1037 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); | |
42043e4f | 1038 | int64_t tb_off_adj, tb_off; |
98a8b524 AK |
1039 | unsigned long freq; |
1040 | ||
1041 | if (!first_ppc_cpu->env.tb_env) { | |
1042 | error_report("No timebase object"); | |
42043e4f | 1043 | return; |
98a8b524 AK |
1044 | } |
1045 | ||
1046 | freq = first_ppc_cpu->env.tb_env->tb_freq; | |
98a8b524 | 1047 | |
42043e4f | 1048 | tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); |
98a8b524 AK |
1049 | |
1050 | tb_off = first_ppc_cpu->env.tb_env->tb_offset; | |
1051 | trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, | |
1052 | (tb_off_adj - tb_off) / freq); | |
1053 | ||
1054 | /* Set new offset to all CPUs */ | |
1055 | CPU_FOREACH(cpu) { | |
1056 | PowerPCCPU *pcpu = POWERPC_CPU(cpu); | |
1057 | pcpu->env.tb_env->tb_offset = tb_off_adj; | |
9723295a | 1058 | kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); |
42043e4f LV |
1059 | } |
1060 | } | |
1061 | ||
1062 | void cpu_ppc_clock_vm_state_change(void *opaque, int running, | |
1063 | RunState state) | |
1064 | { | |
1065 | PPCTimebase *tb = opaque; | |
1066 | ||
1067 | if (running) { | |
1068 | timebase_load(tb); | |
1069 | } else { | |
1070 | timebase_save(tb); | |
98a8b524 | 1071 | } |
42043e4f LV |
1072 | } |
1073 | ||
1074 | /* | |
d14f3397 MG |
1075 | * When migrating a running guest, read the clock just |
1076 | * before migration, so that the guest clock counts | |
1077 | * during the events between: | |
42043e4f LV |
1078 | * |
1079 | * * vm_stop() | |
1080 | * * | |
1081 | * * pre_save() | |
1082 | * | |
1083 | * This reduces clock difference on migration from 5s | |
1084 | * to 0.1s (when max_downtime == 5s), because sending the | |
1085 | * final pages of memory (which happens between vm_stop() | |
1086 | * and pre_save()) takes max_downtime. | |
1087 | */ | |
44b1ff31 | 1088 | static int timebase_pre_save(void *opaque) |
42043e4f LV |
1089 | { |
1090 | PPCTimebase *tb = opaque; | |
98a8b524 | 1091 | |
711dfb24 | 1092 | /* guest_timebase won't be overridden in case of paused guest or savevm */ |
d14f3397 MG |
1093 | if (!tb->runstate_paused) { |
1094 | timebase_save(tb); | |
1095 | } | |
44b1ff31 DDAG |
1096 | |
1097 | return 0; | |
98a8b524 AK |
1098 | } |
1099 | ||
1100 | const VMStateDescription vmstate_ppc_timebase = { | |
1101 | .name = "timebase", | |
1102 | .version_id = 1, | |
1103 | .minimum_version_id = 1, | |
1104 | .minimum_version_id_old = 1, | |
1105 | .pre_save = timebase_pre_save, | |
98a8b524 AK |
1106 | .fields = (VMStateField []) { |
1107 | VMSTATE_UINT64(guest_timebase, PPCTimebase), | |
1108 | VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), | |
1109 | VMSTATE_END_OF_LIST() | |
1110 | }, | |
1111 | }; | |
1112 | ||
9fddaa0c | 1113 | /* Set up (once) timebase frequency (in Hz) */ |
e2684c0b | 1114 | clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) |
9fddaa0c | 1115 | { |
db70b311 | 1116 | PowerPCCPU *cpu = env_archcpu(env); |
c227f099 | 1117 | ppc_tb_t *tb_env; |
9fddaa0c | 1118 | |
7267c094 | 1119 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
9fddaa0c | 1120 | env->tb_env = tb_env; |
ddd1055b | 1121 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
d0db7cad | 1122 | if (is_book3s_arch2x(env)) { |
e81a982a AG |
1123 | /* All Book3S 64bit CPUs implement level based DEC logic */ |
1124 | tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; | |
1125 | } | |
8ecc7913 | 1126 | /* Create new timer */ |
bc72ad67 | 1127 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); |
4b236b62 | 1128 | if (env->has_hv_mode) { |
bc72ad67 | 1129 | tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, |
50c680f0 | 1130 | cpu); |
b172c56a JM |
1131 | } else { |
1132 | tb_env->hdecr_timer = NULL; | |
1133 | } | |
8ecc7913 | 1134 | cpu_ppc_set_tb_clk(env, freq); |
9fddaa0c | 1135 | |
8ecc7913 | 1136 | return &cpu_ppc_set_tb_clk; |
9fddaa0c FB |
1137 | } |
1138 | ||
76a66253 | 1139 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
e2684c0b | 1140 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) |
8a84de23 JM |
1141 | { |
1142 | _cpu_ppc_store_tbu(env, value); | |
1143 | } | |
76a66253 | 1144 | |
e2684c0b | 1145 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) |
8a84de23 JM |
1146 | { |
1147 | return _cpu_ppc_load_tbu(env); | |
1148 | } | |
76a66253 | 1149 | |
e2684c0b | 1150 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) |
76a66253 JM |
1151 | { |
1152 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); | |
1153 | } | |
1154 | ||
e2684c0b | 1155 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) |
76a66253 JM |
1156 | { |
1157 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; | |
1158 | } | |
1159 | ||
636aaad7 | 1160 | /*****************************************************************************/ |
ddd1055b | 1161 | /* PowerPC 40x timers */ |
636aaad7 JM |
1162 | |
1163 | /* PIT, FIT & WDT */ | |
ddd1055b FC |
1164 | typedef struct ppc40x_timer_t ppc40x_timer_t; |
1165 | struct ppc40x_timer_t { | |
636aaad7 JM |
1166 | uint64_t pit_reload; /* PIT auto-reload value */ |
1167 | uint64_t fit_next; /* Tick for next FIT interrupt */ | |
1246b259 | 1168 | QEMUTimer *fit_timer; |
636aaad7 | 1169 | uint64_t wdt_next; /* Tick for next WDT interrupt */ |
1246b259 | 1170 | QEMUTimer *wdt_timer; |
d63cb48d EI |
1171 | |
1172 | /* 405 have the PIT, 440 have a DECR. */ | |
1173 | unsigned int decr_excp; | |
636aaad7 | 1174 | }; |
3b46e624 | 1175 | |
636aaad7 JM |
1176 | /* Fixed interval timer */ |
1177 | static void cpu_4xx_fit_cb (void *opaque) | |
1178 | { | |
7058581a | 1179 | PowerPCCPU *cpu; |
e2684c0b | 1180 | CPUPPCState *env; |
c227f099 | 1181 | ppc_tb_t *tb_env; |
ddd1055b | 1182 | ppc40x_timer_t *ppc40x_timer; |
636aaad7 JM |
1183 | uint64_t now, next; |
1184 | ||
1185 | env = opaque; | |
db70b311 | 1186 | cpu = env_archcpu(env); |
636aaad7 | 1187 | tb_env = env->tb_env; |
ddd1055b | 1188 | ppc40x_timer = tb_env->opaque; |
bc72ad67 | 1189 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
636aaad7 JM |
1190 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
1191 | case 0: | |
1192 | next = 1 << 9; | |
1193 | break; | |
1194 | case 1: | |
1195 | next = 1 << 13; | |
1196 | break; | |
1197 | case 2: | |
1198 | next = 1 << 17; | |
1199 | break; | |
1200 | case 3: | |
1201 | next = 1 << 21; | |
1202 | break; | |
1203 | default: | |
1204 | /* Cannot occur, but makes gcc happy */ | |
1205 | return; | |
1206 | } | |
73bcb24d | 1207 | next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); |
636aaad7 JM |
1208 | if (next == now) |
1209 | next++; | |
bc72ad67 | 1210 | timer_mod(ppc40x_timer->fit_timer, next); |
636aaad7 | 1211 | env->spr[SPR_40x_TSR] |= 1 << 26; |
7058581a AF |
1212 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { |
1213 | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); | |
1214 | } | |
90e189ec BS |
1215 | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
1216 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), | |
1217 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); | |
636aaad7 JM |
1218 | } |
1219 | ||
1220 | /* Programmable interval timer */ | |
e2684c0b | 1221 | static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) |
76a66253 | 1222 | { |
ddd1055b | 1223 | ppc40x_timer_t *ppc40x_timer; |
636aaad7 JM |
1224 | uint64_t now, next; |
1225 | ||
ddd1055b FC |
1226 | ppc40x_timer = tb_env->opaque; |
1227 | if (ppc40x_timer->pit_reload <= 1 || | |
4b6d0a4c JM |
1228 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
1229 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { | |
1230 | /* Stop PIT */ | |
d12d51d5 | 1231 | LOG_TB("%s: stop PIT\n", __func__); |
bc72ad67 | 1232 | timer_del(tb_env->decr_timer); |
4b6d0a4c | 1233 | } else { |
d12d51d5 | 1234 | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
ddd1055b | 1235 | __func__, ppc40x_timer->pit_reload); |
bc72ad67 | 1236 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
ddd1055b | 1237 | next = now + muldiv64(ppc40x_timer->pit_reload, |
73bcb24d | 1238 | NANOSECONDS_PER_SECOND, tb_env->decr_freq); |
4b6d0a4c JM |
1239 | if (is_excp) |
1240 | next += tb_env->decr_next - now; | |
636aaad7 JM |
1241 | if (next == now) |
1242 | next++; | |
bc72ad67 | 1243 | timer_mod(tb_env->decr_timer, next); |
636aaad7 JM |
1244 | tb_env->decr_next = next; |
1245 | } | |
4b6d0a4c JM |
1246 | } |
1247 | ||
1248 | static void cpu_4xx_pit_cb (void *opaque) | |
1249 | { | |
7058581a | 1250 | PowerPCCPU *cpu; |
e2684c0b | 1251 | CPUPPCState *env; |
c227f099 | 1252 | ppc_tb_t *tb_env; |
ddd1055b | 1253 | ppc40x_timer_t *ppc40x_timer; |
4b6d0a4c JM |
1254 | |
1255 | env = opaque; | |
db70b311 | 1256 | cpu = env_archcpu(env); |
4b6d0a4c | 1257 | tb_env = env->tb_env; |
ddd1055b | 1258 | ppc40x_timer = tb_env->opaque; |
636aaad7 | 1259 | env->spr[SPR_40x_TSR] |= 1 << 27; |
7058581a AF |
1260 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { |
1261 | ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); | |
1262 | } | |
4b6d0a4c | 1263 | start_stop_pit(env, tb_env, 1); |
90e189ec BS |
1264 | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
1265 | "%016" PRIx64 "\n", __func__, | |
1266 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), | |
1267 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), | |
1268 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], | |
ddd1055b | 1269 | ppc40x_timer->pit_reload); |
636aaad7 JM |
1270 | } |
1271 | ||
1272 | /* Watchdog timer */ | |
1273 | static void cpu_4xx_wdt_cb (void *opaque) | |
1274 | { | |
7058581a | 1275 | PowerPCCPU *cpu; |
e2684c0b | 1276 | CPUPPCState *env; |
c227f099 | 1277 | ppc_tb_t *tb_env; |
ddd1055b | 1278 | ppc40x_timer_t *ppc40x_timer; |
636aaad7 JM |
1279 | uint64_t now, next; |
1280 | ||
1281 | env = opaque; | |
db70b311 | 1282 | cpu = env_archcpu(env); |
636aaad7 | 1283 | tb_env = env->tb_env; |
ddd1055b | 1284 | ppc40x_timer = tb_env->opaque; |
bc72ad67 | 1285 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
636aaad7 JM |
1286 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
1287 | case 0: | |
1288 | next = 1 << 17; | |
1289 | break; | |
1290 | case 1: | |
1291 | next = 1 << 21; | |
1292 | break; | |
1293 | case 2: | |
1294 | next = 1 << 25; | |
1295 | break; | |
1296 | case 3: | |
1297 | next = 1 << 29; | |
1298 | break; | |
1299 | default: | |
1300 | /* Cannot occur, but makes gcc happy */ | |
1301 | return; | |
1302 | } | |
73bcb24d | 1303 | next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); |
636aaad7 JM |
1304 | if (next == now) |
1305 | next++; | |
90e189ec BS |
1306 | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
1307 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); | |
636aaad7 JM |
1308 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
1309 | case 0x0: | |
1310 | case 0x1: | |
bc72ad67 | 1311 | timer_mod(ppc40x_timer->wdt_timer, next); |
ddd1055b | 1312 | ppc40x_timer->wdt_next = next; |
a1f7f97b | 1313 | env->spr[SPR_40x_TSR] |= 1U << 31; |
636aaad7 JM |
1314 | break; |
1315 | case 0x2: | |
bc72ad67 | 1316 | timer_mod(ppc40x_timer->wdt_timer, next); |
ddd1055b | 1317 | ppc40x_timer->wdt_next = next; |
636aaad7 | 1318 | env->spr[SPR_40x_TSR] |= 1 << 30; |
7058581a AF |
1319 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { |
1320 | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); | |
1321 | } | |
636aaad7 JM |
1322 | break; |
1323 | case 0x3: | |
1324 | env->spr[SPR_40x_TSR] &= ~0x30000000; | |
1325 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; | |
1326 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { | |
1327 | case 0x0: | |
1328 | /* No reset */ | |
1329 | break; | |
1330 | case 0x1: /* Core reset */ | |
f3273ba6 | 1331 | ppc40x_core_reset(cpu); |
8ecc7913 | 1332 | break; |
636aaad7 | 1333 | case 0x2: /* Chip reset */ |
f3273ba6 | 1334 | ppc40x_chip_reset(cpu); |
8ecc7913 | 1335 | break; |
636aaad7 | 1336 | case 0x3: /* System reset */ |
f3273ba6 | 1337 | ppc40x_system_reset(cpu); |
8ecc7913 | 1338 | break; |
636aaad7 JM |
1339 | } |
1340 | } | |
76a66253 JM |
1341 | } |
1342 | ||
e2684c0b | 1343 | void store_40x_pit (CPUPPCState *env, target_ulong val) |
76a66253 | 1344 | { |
c227f099 | 1345 | ppc_tb_t *tb_env; |
ddd1055b | 1346 | ppc40x_timer_t *ppc40x_timer; |
636aaad7 JM |
1347 | |
1348 | tb_env = env->tb_env; | |
ddd1055b | 1349 | ppc40x_timer = tb_env->opaque; |
90e189ec | 1350 | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
ddd1055b | 1351 | ppc40x_timer->pit_reload = val; |
4b6d0a4c | 1352 | start_stop_pit(env, tb_env, 0); |
76a66253 JM |
1353 | } |
1354 | ||
e2684c0b | 1355 | target_ulong load_40x_pit (CPUPPCState *env) |
76a66253 | 1356 | { |
636aaad7 | 1357 | return cpu_ppc_load_decr(env); |
76a66253 JM |
1358 | } |
1359 | ||
ddd1055b | 1360 | static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) |
4b6d0a4c | 1361 | { |
e2684c0b | 1362 | CPUPPCState *env = opaque; |
c227f099 | 1363 | ppc_tb_t *tb_env = env->tb_env; |
4b6d0a4c | 1364 | |
d12d51d5 | 1365 | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
aae9366a | 1366 | freq); |
4b6d0a4c | 1367 | tb_env->tb_freq = freq; |
dbdd2506 | 1368 | tb_env->decr_freq = freq; |
4b6d0a4c JM |
1369 | /* XXX: we should also update all timers */ |
1370 | } | |
1371 | ||
e2684c0b | 1372 | clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, |
d63cb48d | 1373 | unsigned int decr_excp) |
636aaad7 | 1374 | { |
c227f099 | 1375 | ppc_tb_t *tb_env; |
ddd1055b | 1376 | ppc40x_timer_t *ppc40x_timer; |
636aaad7 | 1377 | |
7267c094 | 1378 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
8ecc7913 | 1379 | env->tb_env = tb_env; |
ddd1055b FC |
1380 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
1381 | ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); | |
8ecc7913 | 1382 | tb_env->tb_freq = freq; |
dbdd2506 | 1383 | tb_env->decr_freq = freq; |
ddd1055b | 1384 | tb_env->opaque = ppc40x_timer; |
d12d51d5 | 1385 | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
ddd1055b | 1386 | if (ppc40x_timer != NULL) { |
636aaad7 | 1387 | /* We use decr timer for PIT */ |
bc72ad67 | 1388 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); |
ddd1055b | 1389 | ppc40x_timer->fit_timer = |
bc72ad67 | 1390 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); |
ddd1055b | 1391 | ppc40x_timer->wdt_timer = |
bc72ad67 | 1392 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); |
ddd1055b | 1393 | ppc40x_timer->decr_excp = decr_excp; |
636aaad7 | 1394 | } |
8ecc7913 | 1395 | |
ddd1055b | 1396 | return &ppc_40x_set_tb_clk; |
76a66253 JM |
1397 | } |
1398 | ||
2e719ba3 JM |
1399 | /*****************************************************************************/ |
1400 | /* Embedded PowerPC Device Control Registers */ | |
c227f099 AL |
1401 | typedef struct ppc_dcrn_t ppc_dcrn_t; |
1402 | struct ppc_dcrn_t { | |
2e719ba3 JM |
1403 | dcr_read_cb dcr_read; |
1404 | dcr_write_cb dcr_write; | |
1405 | void *opaque; | |
1406 | }; | |
1407 | ||
a750fc0b JM |
1408 | /* XXX: on 460, DCR addresses are 32 bits wide, |
1409 | * using DCRIPR to get the 22 upper bits of the DCR address | |
1410 | */ | |
2e719ba3 | 1411 | #define DCRN_NB 1024 |
c227f099 AL |
1412 | struct ppc_dcr_t { |
1413 | ppc_dcrn_t dcrn[DCRN_NB]; | |
2e719ba3 JM |
1414 | int (*read_error)(int dcrn); |
1415 | int (*write_error)(int dcrn); | |
1416 | }; | |
1417 | ||
73b01960 | 1418 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
2e719ba3 | 1419 | { |
c227f099 | 1420 | ppc_dcrn_t *dcr; |
2e719ba3 JM |
1421 | |
1422 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1423 | goto error; | |
1424 | dcr = &dcr_env->dcrn[dcrn]; | |
1425 | if (dcr->dcr_read == NULL) | |
1426 | goto error; | |
1427 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); | |
1428 | ||
1429 | return 0; | |
1430 | ||
1431 | error: | |
1432 | if (dcr_env->read_error != NULL) | |
1433 | return (*dcr_env->read_error)(dcrn); | |
1434 | ||
1435 | return -1; | |
1436 | } | |
1437 | ||
73b01960 | 1438 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
2e719ba3 | 1439 | { |
c227f099 | 1440 | ppc_dcrn_t *dcr; |
2e719ba3 JM |
1441 | |
1442 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1443 | goto error; | |
1444 | dcr = &dcr_env->dcrn[dcrn]; | |
1445 | if (dcr->dcr_write == NULL) | |
1446 | goto error; | |
1447 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); | |
1448 | ||
1449 | return 0; | |
1450 | ||
1451 | error: | |
1452 | if (dcr_env->write_error != NULL) | |
1453 | return (*dcr_env->write_error)(dcrn); | |
1454 | ||
1455 | return -1; | |
1456 | } | |
1457 | ||
e2684c0b | 1458 | int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, |
2e719ba3 JM |
1459 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1460 | { | |
c227f099 AL |
1461 | ppc_dcr_t *dcr_env; |
1462 | ppc_dcrn_t *dcr; | |
2e719ba3 JM |
1463 | |
1464 | dcr_env = env->dcr_env; | |
1465 | if (dcr_env == NULL) | |
1466 | return -1; | |
1467 | if (dcrn < 0 || dcrn >= DCRN_NB) | |
1468 | return -1; | |
1469 | dcr = &dcr_env->dcrn[dcrn]; | |
1470 | if (dcr->opaque != NULL || | |
1471 | dcr->dcr_read != NULL || | |
1472 | dcr->dcr_write != NULL) | |
1473 | return -1; | |
1474 | dcr->opaque = opaque; | |
1475 | dcr->dcr_read = dcr_read; | |
1476 | dcr->dcr_write = dcr_write; | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
e2684c0b | 1481 | int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), |
2e719ba3 JM |
1482 | int (*write_error)(int dcrn)) |
1483 | { | |
c227f099 | 1484 | ppc_dcr_t *dcr_env; |
2e719ba3 | 1485 | |
7267c094 | 1486 | dcr_env = g_malloc0(sizeof(ppc_dcr_t)); |
2e719ba3 JM |
1487 | dcr_env->read_error = read_error; |
1488 | dcr_env->write_error = write_error; | |
1489 | env->dcr_env = dcr_env; | |
1490 | ||
1491 | return 0; | |
1492 | } | |
1493 | ||
64201201 | 1494 | /*****************************************************************************/ |
051e2973 | 1495 | |
4a89e204 CLG |
1496 | int ppc_cpu_pir(PowerPCCPU *cpu) |
1497 | { | |
1498 | CPUPPCState *env = &cpu->env; | |
1499 | return env->spr_cb[SPR_PIR].default_value; | |
1500 | } | |
1501 | ||
051e2973 CLG |
1502 | PowerPCCPU *ppc_get_vcpu_by_pir(int pir) |
1503 | { | |
1504 | CPUState *cs; | |
1505 | ||
1506 | CPU_FOREACH(cs) { | |
1507 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
051e2973 | 1508 | |
4a89e204 | 1509 | if (ppc_cpu_pir(cpu) == pir) { |
051e2973 CLG |
1510 | return cpu; |
1511 | } | |
1512 | } | |
1513 | ||
1514 | return NULL; | |
1515 | } | |
40177438 GK |
1516 | |
1517 | void ppc_irq_reset(PowerPCCPU *cpu) | |
1518 | { | |
1519 | CPUPPCState *env = &cpu->env; | |
1520 | ||
1521 | env->irq_input_state = 0; | |
1522 | kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); | |
1523 | } |