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04f20795 JM |
1 | /* |
2 | * QEMU PowerPC 405 shared definitions | |
5fafdf24 | 3 | * |
04f20795 | 4 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
04f20795 JM |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
121d0712 MA |
25 | #ifndef PPC405_H |
26 | #define PPC405_H | |
04f20795 | 27 | |
3b758ca2 | 28 | #include "qom/object.h" |
0d09e41a | 29 | #include "hw/ppc/ppc4xx.h" |
e9d20f37 | 30 | #include "hw/intc/ppc-uic.h" |
111913fb | 31 | #include "hw/i2c/ppc4xx_i2c.h" |
008ff9d7 | 32 | |
2841430e CLG |
33 | /* PLB to OPB bridge */ |
34 | #define TYPE_PPC405_POB "ppc405-pob" | |
35 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); | |
36 | struct Ppc405PobState { | |
37 | Ppc4xxDcrDeviceState parent_obj; | |
38 | ||
39 | uint32_t bear; | |
40 | uint32_t besr0; | |
41 | uint32_t besr1; | |
42 | }; | |
43 | ||
72beecc2 CLG |
44 | /* OPB arbitrer */ |
45 | #define TYPE_PPC405_OPBA "ppc405-opba" | |
46 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA); | |
47 | struct Ppc405OpbaState { | |
48 | SysBusDevice parent_obj; | |
49 | ||
50 | MemoryRegion io; | |
51 | uint8_t cr; | |
52 | uint8_t pr; | |
53 | }; | |
54 | ||
82c86e30 CLG |
55 | /* DMA controller */ |
56 | #define TYPE_PPC405_DMA "ppc405-dma" | |
57 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); | |
58 | struct Ppc405DmaState { | |
59 | Ppc4xxDcrDeviceState parent_obj; | |
60 | ||
61 | qemu_irq irqs[4]; | |
62 | uint32_t cr[4]; | |
63 | uint32_t ct[4]; | |
64 | uint32_t da[4]; | |
65 | uint32_t sa[4]; | |
66 | uint32_t sg[4]; | |
67 | uint32_t sr; | |
68 | uint32_t sgc; | |
69 | uint32_t slp; | |
70 | uint32_t pol; | |
71 | }; | |
72 | ||
125277c6 CLG |
73 | /* GPIO */ |
74 | #define TYPE_PPC405_GPIO "ppc405-gpio" | |
75 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); | |
76 | struct Ppc405GpioState { | |
77 | SysBusDevice parent_obj; | |
78 | ||
79 | MemoryRegion io; | |
80 | uint32_t or; | |
81 | uint32_t tcr; | |
82 | uint32_t osrh; | |
83 | uint32_t osrl; | |
84 | uint32_t tsrh; | |
85 | uint32_t tsrl; | |
86 | uint32_t odr; | |
87 | uint32_t ir; | |
88 | uint32_t rr1; | |
89 | uint32_t isr1h; | |
90 | uint32_t isr1l; | |
91 | }; | |
92 | ||
2847eb40 CLG |
93 | /* On Chip Memory */ |
94 | #define TYPE_PPC405_OCM "ppc405-ocm" | |
95 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); | |
96 | struct Ppc405OcmState { | |
97 | Ppc4xxDcrDeviceState parent_obj; | |
98 | ||
99 | MemoryRegion ram; | |
100 | MemoryRegion isarc_ram; | |
101 | MemoryRegion dsarc_ram; | |
102 | uint32_t isarc; | |
103 | uint32_t isacntl; | |
104 | uint32_t dsarc; | |
105 | uint32_t dsacntl; | |
106 | }; | |
107 | ||
269fbb5b CLG |
108 | /* General purpose timers */ |
109 | #define TYPE_PPC405_GPT "ppc405-gpt" | |
110 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); | |
111 | struct Ppc405GptState { | |
112 | SysBusDevice parent_obj; | |
113 | ||
114 | MemoryRegion iomem; | |
115 | ||
116 | int64_t tb_offset; | |
117 | uint32_t tb_freq; | |
118 | QEMUTimer *timer; | |
119 | qemu_irq irqs[5]; | |
120 | uint32_t oe; | |
121 | uint32_t ol; | |
122 | uint32_t im; | |
123 | uint32_t is; | |
124 | uint32_t ie; | |
125 | uint32_t comp[5]; | |
126 | uint32_t mask[5]; | |
127 | }; | |
128 | ||
4a7d2b7e CLG |
129 | #define TYPE_PPC405_CPC "ppc405-cpc" |
130 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); | |
131 | ||
132 | enum { | |
133 | PPC405EP_CPU_CLK = 0, | |
134 | PPC405EP_PLB_CLK = 1, | |
135 | PPC405EP_OPB_CLK = 2, | |
136 | PPC405EP_EBC_CLK = 3, | |
137 | PPC405EP_MAL_CLK = 4, | |
138 | PPC405EP_PCI_CLK = 5, | |
139 | PPC405EP_UART0_CLK = 6, | |
140 | PPC405EP_UART1_CLK = 7, | |
141 | PPC405EP_CLK_NB = 8, | |
142 | }; | |
143 | ||
144 | struct Ppc405CpcState { | |
145 | Ppc4xxDcrDeviceState parent_obj; | |
146 | ||
147 | uint32_t sysclk; | |
148 | clk_setup_t clk_setup[PPC405EP_CLK_NB]; | |
149 | uint32_t boot; | |
150 | uint32_t epctl; | |
151 | uint32_t pllmr[2]; | |
152 | uint32_t ucr; | |
153 | uint32_t srr; | |
154 | uint32_t jtagid; | |
155 | uint32_t pci; | |
156 | /* Clock and power management */ | |
157 | uint32_t er; | |
158 | uint32_t fr; | |
159 | uint32_t sr; | |
160 | }; | |
161 | ||
3b758ca2 CLG |
162 | #define TYPE_PPC405_SOC "ppc405-soc" |
163 | OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); | |
164 | ||
165 | struct Ppc405SoCState { | |
166 | /* Private */ | |
167 | DeviceState parent_obj; | |
168 | ||
169 | /* Public */ | |
b42ad437 | 170 | PowerPCCPU cpu; |
e9d20f37 | 171 | PPCUIC uic; |
4a7d2b7e | 172 | Ppc405CpcState cpc; |
269fbb5b | 173 | Ppc405GptState gpt; |
2847eb40 | 174 | Ppc405OcmState ocm; |
125277c6 | 175 | Ppc405GpioState gpio; |
82c86e30 | 176 | Ppc405DmaState dma; |
111913fb | 177 | PPC4xxI2CState i2c; |
cba58aa7 | 178 | Ppc4xxEbcState ebc; |
72beecc2 | 179 | Ppc405OpbaState opba; |
2841430e | 180 | Ppc405PobState pob; |
052c779b | 181 | Ppc4xxPlbState plb; |
da116a8a | 182 | Ppc4xxMalState mal; |
4fc30e15 | 183 | Ppc4xxSdramDdrState sdram; |
3b758ca2 CLG |
184 | }; |
185 | ||
121d0712 | 186 | #endif /* PPC405_H */ |