[mirror_qemu.git] / hw / ppc / ppc405_boards.c

/*
 * QEMU PowerPC 405 evaluation boards emulation
 *
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "ppc405.h"
#include "hw/rtc/m48t59.h"
#include "hw/block/flash.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "sysemu/block-backend.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "hw/loader.h"
#include "qemu/cutils.h"
#include "elf.h"

#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)

#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000

#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_SRAM_BASE  0xFFF00000
#define PPC405EP_SRAM_SIZE  (512 * KiB)

#define USE_FLASH_BIOS

#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);

struct Ppc405MachineState {
    /* Private */
    MachineState parent_obj;
    /* Public */

    Ppc405SoCState soc;
};

/* CPU reset handler when booting directly from a loaded kernel */
static struct boot_info {
    uint32_t entry;
    uint32_t bdloc;
    uint32_t initrd_base;
    uint32_t initrd_size;
    uint32_t cmdline_base;
    uint32_t cmdline_size;
} boot_info;

static void main_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(CPU(cpu));

    /* stack: top of sram */
    env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;

    /* Tune our boot state */
    env->gpr[3] = bi->bdloc;
    env->gpr[4] = bi->initrd_base;
    env->gpr[5] = bi->initrd_base + bi->initrd_size;
    env->gpr[6] = bi->cmdline_base;
    env->gpr[7] = bi->cmdline_size;

    env->nip = bi->entry;
}

/* Bootinfo as set-up by u-boot */
typedef struct {
    uint32_t bi_memstart;
    uint32_t bi_memsize;
    uint32_t bi_flashstart;
    uint32_t bi_flashsize;
    uint32_t bi_flashoffset; /* 0x10 */
    uint32_t bi_sramstart;
    uint32_t bi_sramsize;
    uint32_t bi_bootflags;
    uint32_t bi_ipaddr; /* 0x20 */
    uint8_t  bi_enetaddr[6];
    uint16_t bi_ethspeed;
    uint32_t bi_intfreq;
    uint32_t bi_busfreq; /* 0x30 */
    uint32_t bi_baudrate;
    uint8_t  bi_s_version[4];
    uint8_t  bi_r_version[32];
    uint32_t bi_procfreq;
    uint32_t bi_plb_busfreq;
    uint32_t bi_pci_busfreq;
    uint8_t  bi_pci_enetaddr[6];
    uint8_t  bi_pci_enetaddr2[6]; /* PPC405EP specific */
    uint32_t bi_opbfreq;
    uint32_t bi_iic_fast[2];
} ppc4xx_bd_info_t;

static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
                                        ram_addr_t ram_size)
{
        memset(bd, 0, sizeof(*bd));

        bd->bi_memstart = PPC405EP_SDRAM_BASE;
        bd->bi_memsize = ram_size;
        bd->bi_sramstart = PPC405EP_SRAM_BASE;
        bd->bi_sramsize = PPC405EP_SRAM_SIZE;
        bd->bi_bootflags = 0;
        bd->bi_intfreq = 133333333;
        bd->bi_busfreq = 33333333;
        bd->bi_baudrate = 115200;
        bd->bi_s_version[0] = 'Q';
        bd->bi_s_version[1] = 'M';
        bd->bi_s_version[2] = 'U';
        bd->bi_s_version[3] = '\0';
        bd->bi_r_version[0] = 'Q';
        bd->bi_r_version[1] = 'E';
        bd->bi_r_version[2] = 'M';
        bd->bi_r_version[3] = 'U';
        bd->bi_r_version[4] = '\0';
        bd->bi_procfreq = 133333333;
        bd->bi_plb_busfreq = 33333333;
        bd->bi_pci_busfreq = 33333333;
        bd->bi_opbfreq = 33333333;
}

static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
{
    CPUState *cs = env_cpu(env);
    ram_addr_t bdloc;
    int i, n;

    /* We put the bd structure at the top of memory */
    if (bd->bi_memsize >= 0x01000000UL) {
        bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
    } else {
        bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
    }
    stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
    stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
    stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
    stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
    stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
    stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
    stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
    stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
    stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
    for (i = 0; i < 6; i++) {
        stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
    }
    stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
    stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
    stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
    stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
    for (i = 0; i < 4; i++) {
        stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
    }
    for (i = 0; i < 32; i++) {
        stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
    }
    stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
    stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
    stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
    for (i = 0; i < 6; i++) {
        stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
    }
    n = 0x70; /* includes 2 bytes hole */
    for (i = 0; i < 6; i++) {
        stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
    }
    stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
    n += 4;
    for (i = 0; i < 2; i++) {
        stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
        n += 4;
    }

    return bdloc;
}

static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
{
    ppc4xx_bd_info_t bd;

    memset(&bd, 0, sizeof(bd));

    ppc405_set_default_bootinfo(&bd, ram_size);

    return __ppc405_set_bootinfo(env, &bd);
}

static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
{
    CPUPPCState *env = &cpu->env;
    hwaddr boot_entry;
    hwaddr kernel_base;
    int kernel_size;
    hwaddr initrd_base;
    int initrd_size;
    ram_addr_t bdloc;
    int len;

    bdloc = ppc405_set_bootinfo(env, machine->ram_size);
    boot_info.bdloc = bdloc;

    kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
                           &boot_entry, &kernel_base, NULL, NULL,
                           1, PPC_ELF_MACHINE, 0, 0);
    if (kernel_size < 0) {
        error_report("Could not load kernel '%s' : %s",
                     machine->kernel_filename, load_elf_strerror(kernel_size));
        exit(1);
    }
    boot_info.entry = boot_entry;

    /* load initrd */
    if (machine->initrd_filename) {
        initrd_base = INITRD_LOAD_ADDR;
        initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
                                          machine->ram_size - initrd_base);
        if (initrd_size < 0) {
            error_report("could not load initial ram disk '%s'",
                         machine->initrd_filename);
            exit(1);
        }

        boot_info.initrd_base = initrd_base;
        boot_info.initrd_size = initrd_size;
    }

    if (machine->kernel_cmdline) {
        len = strlen(machine->kernel_cmdline);
        bdloc -= ((len + 255) & ~255);
        cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
        boot_info.cmdline_base = bdloc;
        boot_info.cmdline_size = bdloc + len;
    }

    /* Install our custom reset handler to start from Linux */
    qemu_register_reset(main_cpu_reset, cpu);
    env->load_info = &boot_info;
}

static void ppc405_init(MachineState *machine)
{
    Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
    const char *kernel_filename = machine->kernel_filename;
    MemoryRegion *sysmem = get_system_memory();

    object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
                            TYPE_PPC405_SOC);
    object_property_set_link(OBJECT(&ppc405->soc), "dram",
                             OBJECT(machine->ram), &error_abort);
    object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
                             &error_abort);
    qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);

    /* allocate and load BIOS */
    if (machine->firmware) {
        MemoryRegion *bios = g_new(MemoryRegion, 1);
        g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
                                                   machine->firmware);
        long bios_size;

        memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
                               &error_fatal);

        if (!filename) {
            error_report("Could not find firmware '%s'", machine->firmware);
            exit(1);
        }

        bios_size = load_image_size(filename,
                                    memory_region_get_ram_ptr(bios),
                                    BIOS_SIZE);
        if (bios_size < 0) {
            error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
            exit(1);
        }

        bios_size = (bios_size + 0xfff) & ~0xfff;
        memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
    }

    /* Load kernel and initrd using U-Boot images */
    if (kernel_filename && machine->firmware) {
        target_ulong kernel_base, initrd_base;
        long kernel_size, initrd_size;

        kernel_base = KERNEL_LOAD_ADDR;
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                          machine->ram_size - kernel_base);
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (machine->initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(machine->initrd_filename,
                                              initrd_base,
                                              machine->ram_size - initrd_base);
            if (initrd_size < 0) {
                error_report("could not load initial ram disk '%s'",
                             machine->initrd_filename);
                exit(1);
            }
        }

    /* Load ELF kernel and rootfs.cpio */
    } else if (kernel_filename && !machine->firmware) {
        ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
        boot_from_kernel(machine, &ppc405->soc.cpu);
    }
}

static void ppc405_machine_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "PPC405 generic machine";
    mc->init = ppc405_init;
    mc->default_ram_size = 128 * MiB;
    mc->default_ram_id = "ppc405.ram";
    mc->deprecation_reason = "machine is old and unmaintained";
}

static const TypeInfo ppc405_machine_type = {
    .name = TYPE_PPC405_MACHINE,
    .parent = TYPE_MACHINE,
    .instance_size = sizeof(Ppc405MachineState),
    .class_init = ppc405_machine_class_init,
    .abstract = true,
};

/*****************************************************************************/
/* PPC405EP reference board (IBM) */
/*
 * Standalone board with:
 * - PowerPC 405EP CPU
 * - SDRAM (0x00000000)
 * - Flash (0xFFF80000)
 * - SRAM  (0xFFF00000)
 * - NVRAM (0xF0000000)
 * - FPGA  (0xF0300000)
 */

#define PPC405EP_NVRAM_BASE 0xF0000000
#define PPC405EP_FPGA_BASE  0xF0300000
#define PPC405EP_FLASH_BASE 0xFFF80000

#define TYPE_REF405EP_FPGA "ref405ep-fpga"
OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
struct Ref405epFpgaState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    uint8_t reg0;
    uint8_t reg1;
};

static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
    Ref405epFpgaState *fpga = opaque;
    uint32_t ret;

    switch (addr) {
    case 0x0:
        ret = fpga->reg0;
        break;
    case 0x1:
        ret = fpga->reg1;
        break;
    default:
        ret = 0;
        break;
    }

    return ret;
}

static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
                                 unsigned size)
{
    Ref405epFpgaState *fpga = opaque;

    switch (addr) {
    case 0x0:
        /* Read only */
        break;
    case 0x1:
        fpga->reg1 = value;
        break;
    default:
        break;
    }
}

static const MemoryRegionOps ref405ep_fpga_ops = {
    .read = ref405ep_fpga_readb,
    .write = ref405ep_fpga_writeb,
    .impl.min_access_size = 1,
    .impl.max_access_size = 1,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void ref405ep_fpga_reset(DeviceState *dev)
{
    Ref405epFpgaState *fpga = REF405EP_FPGA(dev);

    fpga->reg0 = 0x00;
    fpga->reg1 = 0x0F;
}

static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
{
    Ref405epFpgaState *s = REF405EP_FPGA(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
                          "fpga", 0x00000100);
    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
}

static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = ref405ep_fpga_realize;
    dc->reset = ref405ep_fpga_reset;
    /* Reason: only works as part of a ppc405 board */
    dc->user_creatable = false;
}

static const TypeInfo ref405ep_fpga_type = {
    .name = TYPE_REF405EP_FPGA,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Ref405epFpgaState),
    .class_init = ref405ep_fpga_class_init,
};

static void ref405ep_init(MachineState *machine)
{
    DeviceState *dev;
    SysBusDevice *s;
    MemoryRegion *sram = g_new(MemoryRegion, 1);

    ppc405_init(machine);

    /* allocate SRAM */
    memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE,
                           &error_fatal);
    memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);

    /* Register FPGA */
    dev = qdev_new(TYPE_REF405EP_FPGA);
    object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);

    /* Register NVRAM */
    dev = qdev_new("sysbus-m48t08");
    qdev_prop_set_int32(dev, "base-year", 1968);
    s = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(s, &error_fatal);
    sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
}

static void ref405ep_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ref405ep";
    mc->init = ref405ep_init;
}

static const TypeInfo ref405ep_type = {
    .name = MACHINE_TYPE_NAME("ref405ep"),
    .parent = TYPE_PPC405_MACHINE,
    .class_init = ref405ep_class_init,
};

static void ppc405_machine_init(void)
{
    type_register_static(&ppc405_machine_type);
    type_register_static(&ref405ep_type);
    type_register_static(&ref405ep_fpga_type);
}

type_init(ppc405_machine_init)
Commit	Line	Data
1a6c0886 JM	1	/*
1a6c0886 JM	2	* QEMU PowerPC 405 evaluation boards emulation
5fafdf24	3	*
1a6c0886	4	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	5	*
1a6c0886 JM	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
71e8a915	24
0d75590d	25	#include "qemu/osdep.h"
ab3dd749	26	#include "qemu/units.h"
da34e65c	27	#include "qapi/error.h"
2c65db5e	28	#include "qemu/datadir.h"
4771d756	29	#include "cpu.h"
0d09e41a	30	#include "hw/ppc/ppc.h"
e8a02431 MCA	31	#include "hw/qdev-properties.h"
e8a02431 MCA	32	#include "hw/sysbus.h"
47b43a1f	33	#include "ppc405.h"
819ce6b2	34	#include "hw/rtc/m48t59.h"
0d09e41a	35	#include "hw/block/flash.h"
ad9990ac	36	#include "sysemu/qtest.h"
71e8a915	37	#include "sysemu/reset.h"
4be74634	38	#include "sysemu/block-backend.h"
83c9f4ca	39	#include "hw/boards.h"
ad9990ac	40	#include "qemu/error-report.h"
83c9f4ca	41	#include "hw/loader.h"
4428dcf7	42	#include "qemu/cutils.h"
337270b2	43	#include "elf.h"
1a6c0886 JM	44
1a6c0886 JM	45	#define BIOS_FILENAME "ppc405_rom.bin"
ab3dd749	46	#define BIOS_SIZE (2 * MiB)
1a6c0886	47
82f64c23	48	#define KERNEL_LOAD_ADDR 0x01000000
1a6c0886 JM	49	#define INITRD_LOAD_ADDR 0x01800000
1a6c0886 JM	50
b5aae5f6 BZ	51	#define PPC405EP_SDRAM_BASE 0x00000000
	52	#define PPC405EP_SRAM_BASE 0xFFF00000
	53	#define PPC405EP_SRAM_SIZE (512 * KiB)
	54
1a6c0886 JM	55	#define USE_FLASH_BIOS
1a6c0886 JM	56
e67b374d CLG	57	#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
	58	OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
	59
	60	struct Ppc405MachineState {
	61	/* Private */
	62	MachineState parent_obj;
	63	/* Public */
3b758ca2 CLG	64
3b758ca2 CLG	65	Ppc405SoCState soc;
e67b374d CLG	66	};
e67b374d CLG	67
b5aae5f6	68	/* CPU reset handler when booting directly from a loaded kernel */
337270b2 CLG	69	static struct boot_info {
	70	uint32_t entry;
	71	uint32_t bdloc;
	72	uint32_t initrd_base;
	73	uint32_t initrd_size;
	74	uint32_t cmdline_base;
	75	uint32_t cmdline_size;
	76	} boot_info;
	77
	78	static void main_cpu_reset(void *opaque)
	79	{
	80	PowerPCCPU *cpu = opaque;
	81	CPUPPCState *env = &cpu->env;
	82	struct boot_info *bi = env->load_info;
	83
	84	cpu_reset(CPU(cpu));
	85
	86	/* stack: top of sram */
	87	env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
	88
	89	/* Tune our boot state */
	90	env->gpr[3] = bi->bdloc;
	91	env->gpr[4] = bi->initrd_base;
	92	env->gpr[5] = bi->initrd_base + bi->initrd_size;
	93	env->gpr[6] = bi->cmdline_base;
	94	env->gpr[7] = bi->cmdline_size;
	95
	96	env->nip = bi->entry;
	97	}
	98
b5aae5f6 BZ	99	/* Bootinfo as set-up by u-boot */
	100	typedef struct {
	101	uint32_t bi_memstart;
	102	uint32_t bi_memsize;
	103	uint32_t bi_flashstart;
	104	uint32_t bi_flashsize;
	105	uint32_t bi_flashoffset; /* 0x10 */
	106	uint32_t bi_sramstart;
	107	uint32_t bi_sramsize;
	108	uint32_t bi_bootflags;
	109	uint32_t bi_ipaddr; /* 0x20 */
	110	uint8_t bi_enetaddr[6];
	111	uint16_t bi_ethspeed;
	112	uint32_t bi_intfreq;
	113	uint32_t bi_busfreq; /* 0x30 */
	114	uint32_t bi_baudrate;
	115	uint8_t bi_s_version[4];
	116	uint8_t bi_r_version[32];
	117	uint32_t bi_procfreq;
	118	uint32_t bi_plb_busfreq;
	119	uint32_t bi_pci_busfreq;
	120	uint8_t bi_pci_enetaddr[6];
	121	uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
	122	uint32_t bi_opbfreq;
	123	uint32_t bi_iic_fast[2];
	124	} ppc4xx_bd_info_t;
	125
	126	static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
	127	ram_addr_t ram_size)
	128	{
	129	memset(bd, 0, sizeof(*bd));
	130
	131	bd->bi_memstart = PPC405EP_SDRAM_BASE;
	132	bd->bi_memsize = ram_size;
	133	bd->bi_sramstart = PPC405EP_SRAM_BASE;
	134	bd->bi_sramsize = PPC405EP_SRAM_SIZE;
	135	bd->bi_bootflags = 0;
	136	bd->bi_intfreq = 133333333;
	137	bd->bi_busfreq = 33333333;
	138	bd->bi_baudrate = 115200;
	139	bd->bi_s_version[0] = 'Q';
	140	bd->bi_s_version[1] = 'M';
	141	bd->bi_s_version[2] = 'U';
	142	bd->bi_s_version[3] = '\0';
	143	bd->bi_r_version[0] = 'Q';
	144	bd->bi_r_version[1] = 'E';
	145	bd->bi_r_version[2] = 'M';
	146	bd->bi_r_version[3] = 'U';
	147	bd->bi_r_version[4] = '\0';
	148	bd->bi_procfreq = 133333333;
	149	bd->bi_plb_busfreq = 33333333;
	150	bd->bi_pci_busfreq = 33333333;
	151	bd->bi_opbfreq = 33333333;
	152	}
	153
	154	static ram_addr_t __ppc405_set_bootinfo(CPUPPCState env, ppc4xx_bd_info_t bd)
	155	{
	156	CPUState *cs = env_cpu(env);
	157	ram_addr_t bdloc;
	158	int i, n;
	159
	160	/* We put the bd structure at the top of memory */
	161	if (bd->bi_memsize >= 0x01000000UL) {
	162	bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
163	} else {
164	bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
165	}
166	stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
167	stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
168	stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
169	stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
170	stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
171	stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
172	stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
173	stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
174	stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
175	for (i = 0; i < 6; i++) {
176	stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
177	}
178	stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
179	stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
180	stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
181	stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
182	for (i = 0; i < 4; i++) {
183	stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
184	}
185	for (i = 0; i < 32; i++) {
186	stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
187	}
188	stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
189	stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
190	stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
191	for (i = 0; i < 6; i++) {
192	stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
193	}
194	n = 0x70; /* includes 2 bytes hole */
195	for (i = 0; i < 6; i++) {
196	stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
197	}
198	stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
199	n += 4;
200	for (i = 0; i < 2; i++) {
201	stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
202	n += 4;
203	}
204
205	return bdloc;
206	}
207
208	static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
209	{
210	ppc4xx_bd_info_t bd;
211
212	memset(&bd, 0, sizeof(bd));
213
214	ppc405_set_default_bootinfo(&bd, ram_size);
215
216	return __ppc405_set_bootinfo(env, &bd);
217	}
218
337270b2 CLG	219	static void boot_from_kernel(MachineState machine, PowerPCCPU cpu)
	220	{
	221	CPUPPCState *env = &cpu->env;
	222	hwaddr boot_entry;
	223	hwaddr kernel_base;
	224	int kernel_size;
	225	hwaddr initrd_base;
	226	int initrd_size;
	227	ram_addr_t bdloc;
	228	int len;
	229
	230	bdloc = ppc405_set_bootinfo(env, machine->ram_size);
	231	boot_info.bdloc = bdloc;
	232
	233	kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
	234	&boot_entry, &kernel_base, NULL, NULL,
	235	1, PPC_ELF_MACHINE, 0, 0);
	236	if (kernel_size < 0) {
	237	error_report("Could not load kernel '%s' : %s",
	238	machine->kernel_filename, load_elf_strerror(kernel_size));
	239	exit(1);
	240	}
	241	boot_info.entry = boot_entry;
	242
	243	/* load initrd */
	244	if (machine->initrd_filename) {
	245	initrd_base = INITRD_LOAD_ADDR;
	246	initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
	247	machine->ram_size - initrd_base);
	248	if (initrd_size < 0) {
	249	error_report("could not load initial ram disk '%s'",
	250	machine->initrd_filename);
	251	exit(1);
	252	}
	253
	254	boot_info.initrd_base = initrd_base;
	255	boot_info.initrd_size = initrd_size;
	256	}
	257
	258	if (machine->kernel_cmdline) {
	259	len = strlen(machine->kernel_cmdline);
	260	bdloc -= ((len + 255) & ~255);
	261	cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
	262	boot_info.cmdline_base = bdloc;
	263	boot_info.cmdline_size = bdloc + len;
	264	}
	265
	266	/* Install our custom reset handler to start from Linux */
	267	qemu_register_reset(main_cpu_reset, cpu);
	268	env->load_info = &boot_info;
	269	}
	270
041816c6	271	static void ppc405_init(MachineState *machine)
1a6c0886	272	{
3b758ca2	273	Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
3ef96221	274	const char *kernel_filename = machine->kernel_filename;
a682fd5c	275	MemoryRegion *sysmem = get_system_memory();
1a6c0886	276
3b758ca2 CLG	277	object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
3b758ca2 CLG	278	TYPE_PPC405_SOC);
3b758ca2 CLG	279	object_property_set_link(OBJECT(&ppc405->soc), "dram",
3b758ca2 CLG	280	OBJECT(machine->ram), &error_abort);
5b0f170a CLG	281	object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
5b0f170a CLG	282	&error_abort);
3b758ca2	283	qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
a3e973e1	284
1a6c0886	285	/* allocate and load BIOS */
13d63de5 CLG	286	if (machine->firmware) {
13d63de5 CLG	287	MemoryRegion *bios = g_new(MemoryRegion, 1);
b8ff425b BB	288	g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
b8ff425b BB	289	machine->firmware);
337270b2	290	long bios_size;
13d63de5	291
34b76458	292	memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
f8ed85ac	293	&error_fatal);
e206ad48	294
13d63de5 CLG	295	if (!filename) {
	296	error_report("Could not find firmware '%s'", machine->firmware);
	297	exit(1);
	298	}
	299
	300	bios_size = load_image_size(filename,
	301	memory_region_get_ram_ptr(bios),
	302	BIOS_SIZE);
	303	if (bios_size < 0) {
	304	error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
ad9990ac	305	exit(1);
5cea8590	306	}
13d63de5 CLG	307
	308	bios_size = (bios_size + 0xfff) & ~0xfff;
	309	memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
1a6c0886	310	}
13d63de5	311
337270b2 CLG	312	/* Load kernel and initrd using U-Boot images */
	313	if (kernel_filename && machine->firmware) {
	314	target_ulong kernel_base, initrd_base;
	315	long kernel_size, initrd_size;
	316
1a6c0886	317	kernel_base = KERNEL_LOAD_ADDR;
5c130f65	318	kernel_size = load_image_targphys(kernel_filename, kernel_base,
4428dcf7	319	machine->ram_size - kernel_base);
1a6c0886	320	if (kernel_size < 0) {
6f76b817	321	error_report("could not load kernel '%s'", kernel_filename);
1a6c0886 JM	322	exit(1);
1a6c0886 JM	323	}
337270b2	324
1a6c0886	325	/* load initrd */
337270b2	326	if (machine->initrd_filename) {
1a6c0886	327	initrd_base = INITRD_LOAD_ADDR;
337270b2 CLG	328	initrd_size = load_image_targphys(machine->initrd_filename,
337270b2 CLG	329	initrd_base,
4428dcf7	330	machine->ram_size - initrd_base);
1a6c0886	331	if (initrd_size < 0) {
6f76b817	332	error_report("could not load initial ram disk '%s'",
337270b2	333	machine->initrd_filename);
1a6c0886 JM	334	exit(1);
1a6c0886 JM	335	}
1a6c0886	336	}
337270b2 CLG	337
	338	/* Load ELF kernel and rootfs.cpio */
	339	} else if (kernel_filename && !machine->firmware) {
1e545fbc	340	ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
b42ad437	341	boot_from_kernel(machine, &ppc405->soc.cpu);
1a6c0886	342	}
1a6c0886 JM	343	}
1a6c0886 JM	344
b5aae5f6 BZ	345	static void ppc405_machine_class_init(ObjectClass oc, void data)
	346	{
	347	MachineClass *mc = MACHINE_CLASS(oc);
	348
	349	mc->desc = "PPC405 generic machine";
	350	mc->init = ppc405_init;
	351	mc->default_ram_size = 128 * MiB;
	352	mc->default_ram_id = "ppc405.ram";
ed95bdd1	353	mc->deprecation_reason = "machine is old and unmaintained";
b5aae5f6 BZ	354	}
	355
	356	static const TypeInfo ppc405_machine_type = {
	357	.name = TYPE_PPC405_MACHINE,
	358	.parent = TYPE_MACHINE,
	359	.instance_size = sizeof(Ppc405MachineState),
	360	.class_init = ppc405_machine_class_init,
	361	.abstract = true,
	362	};
	363
	364	/*****************************************************************************/
	365	/* PPC405EP reference board (IBM) */
	366	/*
	367	* Standalone board with:
	368	* - PowerPC 405EP CPU
	369	* - SDRAM (0x00000000)
	370	* - Flash (0xFFF80000)
	371	* - SRAM (0xFFF00000)
	372	* - NVRAM (0xF0000000)
	373	* - FPGA (0xF0300000)
	374	*/
	375
	376	#define PPC405EP_NVRAM_BASE 0xF0000000
	377	#define PPC405EP_FPGA_BASE 0xF0300000
	378	#define PPC405EP_FLASH_BASE 0xFFF80000
	379
	380	#define TYPE_REF405EP_FPGA "ref405ep-fpga"
	381	OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
	382	struct Ref405epFpgaState {
	383	SysBusDevice parent_obj;
	384
	385	MemoryRegion iomem;
	386
	387	uint8_t reg0;
	388	uint8_t reg1;
	389	};
	390
	391	static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
	392	{
	393	Ref405epFpgaState *fpga = opaque;
	394	uint32_t ret;
	395
	396	switch (addr) {
	397	case 0x0:
	398	ret = fpga->reg0;
	399	break;
	400	case 0x1:
	401	ret = fpga->reg1;
	402	break;
	403	default:
	404	ret = 0;
	405	break;
	406	}
	407
	408	return ret;
	409	}
	410
	411	static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
	412	unsigned size)
	413	{
	414	Ref405epFpgaState *fpga = opaque;
	415
	416	switch (addr) {
	417	case 0x0:
418	/* Read only */
419	break;
420	case 0x1:
421	fpga->reg1 = value;
422	break;
423	default:
424	break;
425	}
426	}
427
428	static const MemoryRegionOps ref405ep_fpga_ops = {
429	.read = ref405ep_fpga_readb,
430	.write = ref405ep_fpga_writeb,
431	.impl.min_access_size = 1,
432	.impl.max_access_size = 1,
433	.valid.min_access_size = 1,
434	.valid.max_access_size = 4,
435	.endianness = DEVICE_BIG_ENDIAN,
436	};
437
438	static void ref405ep_fpga_reset(DeviceState *dev)
439	{
440	Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
441
442	fpga->reg0 = 0x00;
443	fpga->reg1 = 0x0F;
444	}
445
446	static void ref405ep_fpga_realize(DeviceState dev, Error *errp)
447	{
448	Ref405epFpgaState *s = REF405EP_FPGA(dev);
449
450	memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
451	"fpga", 0x00000100);
452	sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
453	}
454
455	static void ref405ep_fpga_class_init(ObjectClass oc, void data)
456	{
457	DeviceClass *dc = DEVICE_CLASS(oc);
458
459	dc->realize = ref405ep_fpga_realize;
460	dc->reset = ref405ep_fpga_reset;
461	/* Reason: only works as part of a ppc405 board */
462	dc->user_creatable = false;
463	}
464
465	static const TypeInfo ref405ep_fpga_type = {
466	.name = TYPE_REF405EP_FPGA,
467	.parent = TYPE_SYS_BUS_DEVICE,
468	.instance_size = sizeof(Ref405epFpgaState),
469	.class_init = ref405ep_fpga_class_init,
470	};
471
041816c6 CLG	472	static void ref405ep_init(MachineState *machine)
	473	{
	474	DeviceState *dev;
	475	SysBusDevice *s;
df237208	476	MemoryRegion *sram = g_new(MemoryRegion, 1);
041816c6 CLG	477
	478	ppc405_init(machine);
	479
df237208 CLG	480	/* allocate SRAM */
	481	memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE,
	482	&error_fatal);
	483	memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
	484
041816c6	485	/* Register FPGA */
ea9b3186 CLG	486	dev = qdev_new(TYPE_REF405EP_FPGA);
	487	object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
	488	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
	489	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
	490
041816c6 CLG	491	/* Register NVRAM */
	492	dev = qdev_new("sysbus-m48t08");
	493	qdev_prop_set_int32(dev, "base-year", 1968);
	494	s = SYS_BUS_DEVICE(dev);
	495	sysbus_realize_and_unref(s, &error_fatal);
	496	sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
	497	}
	498
8a661aea	499	static void ref405ep_class_init(ObjectClass oc, void data)
e264d29d	500	{
8a661aea AF	501	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	502
e264d29d EH	503	mc->desc = "ref405ep";
	504	mc->init = ref405ep_init;
	505	}
	506
8a661aea AF	507	static const TypeInfo ref405ep_type = {
8a661aea AF	508	.name = MACHINE_TYPE_NAME("ref405ep"),
e67b374d	509	.parent = TYPE_PPC405_MACHINE,
8a661aea AF	510	.class_init = ref405ep_class_init,
8a661aea AF	511	};
1a6c0886	512
8a661aea AF	513	static void ppc405_machine_init(void)
8a661aea AF	514	{
e67b374d	515	type_register_static(&ppc405_machine_type);
8a661aea	516	type_register_static(&ref405ep_type);
ea9b3186	517	type_register_static(&ref405ep_fpga_type);
8a661aea AF	518	}
8a661aea AF	519
0e6aac87	520	type_init(ppc405_machine_init)