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Commit | Line | Data |
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8ecc7913 JM |
1 | /* |
2 | * QEMU PowerPC 405 embedded processors emulation | |
5fafdf24 | 3 | * |
8ecc7913 | 4 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
8ecc7913 JM |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0d75590d | 24 | #include "qemu/osdep.h" |
ab3dd749 | 25 | #include "qemu/units.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 | 27 | #include "cpu.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
0d09e41a | 29 | #include "hw/ppc/ppc.h" |
e938ba0c | 30 | #include "hw/boards.h" |
3b09bb0f | 31 | #include "hw/i2c/ppc4xx_i2c.h" |
47b43a1f | 32 | #include "ppc405.h" |
0d09e41a | 33 | #include "hw/char/serial.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
1de7afc9 | 36 | #include "qemu/log.h" |
022c62cb | 37 | #include "exec/address-spaces.h" |
8ecc7913 | 38 | |
0d84382e AF |
39 | //#define DEBUG_OPBA |
40 | //#define DEBUG_SDRAM | |
41 | //#define DEBUG_GPIO | |
42 | //#define DEBUG_SERIAL | |
43 | //#define DEBUG_OCM | |
0d84382e | 44 | //#define DEBUG_GPT |
0d84382e | 45 | //#define DEBUG_CLOCKS |
aae9366a | 46 | //#define DEBUG_CLOCKS_LL |
8ecc7913 | 47 | |
e2684c0b | 48 | ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, |
b8d3f5d1 | 49 | uint32_t flags) |
04f20795 | 50 | { |
db70b311 | 51 | CPUState *cs = env_cpu(env); |
c227f099 | 52 | ram_addr_t bdloc; |
04f20795 JM |
53 | int i, n; |
54 | ||
55 | /* We put the bd structure at the top of memory */ | |
be58fc7c | 56 | if (bd->bi_memsize >= 0x01000000UL) |
c227f099 | 57 | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
be58fc7c | 58 | else |
c227f099 | 59 | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
ab1da857 EI |
60 | stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); |
61 | stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); | |
62 | stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); | |
63 | stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); | |
64 | stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); | |
65 | stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); | |
66 | stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); | |
67 | stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); | |
68 | stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); | |
db663d0f | 69 | for (i = 0; i < 6; i++) { |
db3be60d | 70 | stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); |
db663d0f | 71 | } |
5ce5944d | 72 | stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); |
ab1da857 EI |
73 | stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); |
74 | stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); | |
75 | stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); | |
db663d0f | 76 | for (i = 0; i < 4; i++) { |
db3be60d | 77 | stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); |
db663d0f | 78 | } |
4508d81a | 79 | for (i = 0; i < 32; i++) { |
db3be60d | 80 | stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); |
4508d81a | 81 | } |
ab1da857 EI |
82 | stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); |
83 | stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); | |
db663d0f | 84 | for (i = 0; i < 6; i++) { |
db3be60d | 85 | stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); |
db663d0f | 86 | } |
04f20795 | 87 | n = 0x6A; |
b8d3f5d1 | 88 | if (flags & 0x00000001) { |
04f20795 | 89 | for (i = 0; i < 6; i++) |
db3be60d | 90 | stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); |
04f20795 | 91 | } |
ab1da857 | 92 | stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); |
04f20795 JM |
93 | n += 4; |
94 | for (i = 0; i < 2; i++) { | |
ab1da857 | 95 | stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); |
04f20795 JM |
96 | n += 4; |
97 | } | |
98 | ||
99 | return bdloc; | |
100 | } | |
101 | ||
8ecc7913 JM |
102 | /*****************************************************************************/ |
103 | /* Shared peripherals */ | |
104 | ||
8ecc7913 JM |
105 | /*****************************************************************************/ |
106 | /* Peripheral local bus arbitrer */ | |
107 | enum { | |
4c46f372 BZ |
108 | PLB3A0_ACR = 0x077, |
109 | PLB4A0_ACR = 0x081, | |
110 | PLB0_BESR = 0x084, | |
111 | PLB0_BEAR = 0x086, | |
112 | PLB0_ACR = 0x087, | |
113 | PLB4A1_ACR = 0x089, | |
8ecc7913 JM |
114 | }; |
115 | ||
c227f099 AL |
116 | typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
117 | struct ppc4xx_plb_t { | |
8ecc7913 JM |
118 | uint32_t acr; |
119 | uint32_t bear; | |
120 | uint32_t besr; | |
121 | }; | |
122 | ||
73b01960 | 123 | static uint32_t dcr_read_plb (void *opaque, int dcrn) |
8ecc7913 | 124 | { |
c227f099 | 125 | ppc4xx_plb_t *plb; |
73b01960 | 126 | uint32_t ret; |
8ecc7913 JM |
127 | |
128 | plb = opaque; | |
129 | switch (dcrn) { | |
130 | case PLB0_ACR: | |
131 | ret = plb->acr; | |
132 | break; | |
133 | case PLB0_BEAR: | |
134 | ret = plb->bear; | |
135 | break; | |
136 | case PLB0_BESR: | |
137 | ret = plb->besr; | |
138 | break; | |
139 | default: | |
140 | /* Avoid gcc warning */ | |
141 | ret = 0; | |
142 | break; | |
143 | } | |
144 | ||
145 | return ret; | |
146 | } | |
147 | ||
73b01960 | 148 | static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 149 | { |
c227f099 | 150 | ppc4xx_plb_t *plb; |
8ecc7913 JM |
151 | |
152 | plb = opaque; | |
153 | switch (dcrn) { | |
154 | case PLB0_ACR: | |
9c02f1a2 JM |
155 | /* We don't care about the actual parameters written as |
156 | * we don't manage any priorities on the bus | |
157 | */ | |
158 | plb->acr = val & 0xF8000000; | |
8ecc7913 JM |
159 | break; |
160 | case PLB0_BEAR: | |
161 | /* Read only */ | |
162 | break; | |
163 | case PLB0_BESR: | |
164 | /* Write-clear */ | |
165 | plb->besr &= ~val; | |
166 | break; | |
167 | } | |
168 | } | |
169 | ||
170 | static void ppc4xx_plb_reset (void *opaque) | |
171 | { | |
c227f099 | 172 | ppc4xx_plb_t *plb; |
8ecc7913 JM |
173 | |
174 | plb = opaque; | |
175 | plb->acr = 0x00000000; | |
176 | plb->bear = 0x00000000; | |
177 | plb->besr = 0x00000000; | |
178 | } | |
179 | ||
97c2acb5 | 180 | void ppc4xx_plb_init(CPUPPCState *env) |
8ecc7913 | 181 | { |
c227f099 | 182 | ppc4xx_plb_t *plb; |
8ecc7913 | 183 | |
7267c094 | 184 | plb = g_malloc0(sizeof(ppc4xx_plb_t)); |
4c46f372 BZ |
185 | ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
186 | ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); | |
487414f1 AL |
187 | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
188 | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); | |
189 | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); | |
4c46f372 | 190 | ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
a08d4367 | 191 | qemu_register_reset(ppc4xx_plb_reset, plb); |
8ecc7913 JM |
192 | } |
193 | ||
194 | /*****************************************************************************/ | |
195 | /* PLB to OPB bridge */ | |
196 | enum { | |
197 | POB0_BESR0 = 0x0A0, | |
198 | POB0_BESR1 = 0x0A2, | |
199 | POB0_BEAR = 0x0A4, | |
200 | }; | |
201 | ||
c227f099 AL |
202 | typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
203 | struct ppc4xx_pob_t { | |
8ecc7913 | 204 | uint32_t bear; |
5a1972c8 SW |
205 | uint32_t besr0; |
206 | uint32_t besr1; | |
8ecc7913 JM |
207 | }; |
208 | ||
73b01960 | 209 | static uint32_t dcr_read_pob (void *opaque, int dcrn) |
8ecc7913 | 210 | { |
c227f099 | 211 | ppc4xx_pob_t *pob; |
73b01960 | 212 | uint32_t ret; |
8ecc7913 JM |
213 | |
214 | pob = opaque; | |
215 | switch (dcrn) { | |
216 | case POB0_BEAR: | |
217 | ret = pob->bear; | |
218 | break; | |
219 | case POB0_BESR0: | |
5a1972c8 SW |
220 | ret = pob->besr0; |
221 | break; | |
8ecc7913 | 222 | case POB0_BESR1: |
5a1972c8 | 223 | ret = pob->besr1; |
8ecc7913 JM |
224 | break; |
225 | default: | |
226 | /* Avoid gcc warning */ | |
227 | ret = 0; | |
228 | break; | |
229 | } | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
73b01960 | 234 | static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 235 | { |
c227f099 | 236 | ppc4xx_pob_t *pob; |
8ecc7913 JM |
237 | |
238 | pob = opaque; | |
239 | switch (dcrn) { | |
240 | case POB0_BEAR: | |
241 | /* Read only */ | |
242 | break; | |
243 | case POB0_BESR0: | |
5a1972c8 SW |
244 | /* Write-clear */ |
245 | pob->besr0 &= ~val; | |
246 | break; | |
8ecc7913 JM |
247 | case POB0_BESR1: |
248 | /* Write-clear */ | |
5a1972c8 | 249 | pob->besr1 &= ~val; |
8ecc7913 JM |
250 | break; |
251 | } | |
252 | } | |
253 | ||
254 | static void ppc4xx_pob_reset (void *opaque) | |
255 | { | |
c227f099 | 256 | ppc4xx_pob_t *pob; |
8ecc7913 JM |
257 | |
258 | pob = opaque; | |
259 | /* No error */ | |
260 | pob->bear = 0x00000000; | |
5a1972c8 SW |
261 | pob->besr0 = 0x0000000; |
262 | pob->besr1 = 0x0000000; | |
8ecc7913 JM |
263 | } |
264 | ||
e2684c0b | 265 | static void ppc4xx_pob_init(CPUPPCState *env) |
8ecc7913 | 266 | { |
c227f099 | 267 | ppc4xx_pob_t *pob; |
8ecc7913 | 268 | |
7267c094 | 269 | pob = g_malloc0(sizeof(ppc4xx_pob_t)); |
487414f1 AL |
270 | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
271 | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); | |
272 | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); | |
a08d4367 | 273 | qemu_register_reset(ppc4xx_pob_reset, pob); |
8ecc7913 JM |
274 | } |
275 | ||
276 | /*****************************************************************************/ | |
277 | /* OPB arbitrer */ | |
c227f099 AL |
278 | typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
279 | struct ppc4xx_opba_t { | |
9074e0e3 | 280 | MemoryRegion io; |
8ecc7913 JM |
281 | uint8_t cr; |
282 | uint8_t pr; | |
283 | }; | |
284 | ||
69bd18f8 | 285 | static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) |
8ecc7913 | 286 | { |
c227f099 | 287 | ppc4xx_opba_t *opba; |
8ecc7913 JM |
288 | uint32_t ret; |
289 | ||
290 | #ifdef DEBUG_OPBA | |
90e189ec | 291 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
8ecc7913 JM |
292 | #endif |
293 | opba = opaque; | |
802670e6 | 294 | switch (addr) { |
8ecc7913 JM |
295 | case 0x00: |
296 | ret = opba->cr; | |
297 | break; | |
298 | case 0x01: | |
299 | ret = opba->pr; | |
300 | break; | |
301 | default: | |
302 | ret = 0x00; | |
303 | break; | |
304 | } | |
305 | ||
306 | return ret; | |
307 | } | |
308 | ||
69bd18f8 PM |
309 | static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, |
310 | unsigned size) | |
8ecc7913 | 311 | { |
c227f099 | 312 | ppc4xx_opba_t *opba; |
8ecc7913 JM |
313 | |
314 | #ifdef DEBUG_OPBA | |
90e189ec BS |
315 | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
316 | value); | |
8ecc7913 JM |
317 | #endif |
318 | opba = opaque; | |
802670e6 | 319 | switch (addr) { |
8ecc7913 JM |
320 | case 0x00: |
321 | opba->cr = value & 0xF8; | |
322 | break; | |
323 | case 0x01: | |
324 | opba->pr = value & 0xFF; | |
325 | break; | |
326 | default: | |
327 | break; | |
328 | } | |
329 | } | |
9074e0e3 | 330 | static const MemoryRegionOps opba_ops = { |
69bd18f8 PM |
331 | .read = opba_readb, |
332 | .write = opba_writeb, | |
333 | .impl.min_access_size = 1, | |
334 | .impl.max_access_size = 1, | |
335 | .valid.min_access_size = 1, | |
336 | .valid.max_access_size = 4, | |
337 | .endianness = DEVICE_BIG_ENDIAN, | |
8ecc7913 JM |
338 | }; |
339 | ||
340 | static void ppc4xx_opba_reset (void *opaque) | |
341 | { | |
c227f099 | 342 | ppc4xx_opba_t *opba; |
8ecc7913 JM |
343 | |
344 | opba = opaque; | |
345 | opba->cr = 0x00; /* No dynamic priorities - park disabled */ | |
346 | opba->pr = 0x11; | |
347 | } | |
348 | ||
a8170e5e | 349 | static void ppc4xx_opba_init(hwaddr base) |
8ecc7913 | 350 | { |
c227f099 | 351 | ppc4xx_opba_t *opba; |
8ecc7913 | 352 | |
7267c094 | 353 | opba = g_malloc0(sizeof(ppc4xx_opba_t)); |
8ecc7913 | 354 | #ifdef DEBUG_OPBA |
90e189ec | 355 | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
8ecc7913 | 356 | #endif |
2c9b15ca | 357 | memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); |
9074e0e3 | 358 | memory_region_add_subregion(get_system_memory(), base, &opba->io); |
802670e6 | 359 | qemu_register_reset(ppc4xx_opba_reset, opba); |
8ecc7913 JM |
360 | } |
361 | ||
8ecc7913 JM |
362 | /*****************************************************************************/ |
363 | /* Code decompression controller */ | |
364 | /* XXX: TODO */ | |
365 | ||
8ecc7913 JM |
366 | /*****************************************************************************/ |
367 | /* Peripheral controller */ | |
c227f099 AL |
368 | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
369 | struct ppc4xx_ebc_t { | |
8ecc7913 JM |
370 | uint32_t addr; |
371 | uint32_t bcr[8]; | |
372 | uint32_t bap[8]; | |
373 | uint32_t bear; | |
374 | uint32_t besr0; | |
375 | uint32_t besr1; | |
376 | uint32_t cfg; | |
377 | }; | |
378 | ||
379 | enum { | |
380 | EBC0_CFGADDR = 0x012, | |
381 | EBC0_CFGDATA = 0x013, | |
382 | }; | |
383 | ||
73b01960 | 384 | static uint32_t dcr_read_ebc (void *opaque, int dcrn) |
8ecc7913 | 385 | { |
c227f099 | 386 | ppc4xx_ebc_t *ebc; |
73b01960 | 387 | uint32_t ret; |
8ecc7913 JM |
388 | |
389 | ebc = opaque; | |
390 | switch (dcrn) { | |
391 | case EBC0_CFGADDR: | |
392 | ret = ebc->addr; | |
393 | break; | |
394 | case EBC0_CFGDATA: | |
395 | switch (ebc->addr) { | |
396 | case 0x00: /* B0CR */ | |
397 | ret = ebc->bcr[0]; | |
398 | break; | |
399 | case 0x01: /* B1CR */ | |
400 | ret = ebc->bcr[1]; | |
401 | break; | |
402 | case 0x02: /* B2CR */ | |
403 | ret = ebc->bcr[2]; | |
404 | break; | |
405 | case 0x03: /* B3CR */ | |
406 | ret = ebc->bcr[3]; | |
407 | break; | |
408 | case 0x04: /* B4CR */ | |
409 | ret = ebc->bcr[4]; | |
410 | break; | |
411 | case 0x05: /* B5CR */ | |
412 | ret = ebc->bcr[5]; | |
413 | break; | |
414 | case 0x06: /* B6CR */ | |
415 | ret = ebc->bcr[6]; | |
416 | break; | |
417 | case 0x07: /* B7CR */ | |
418 | ret = ebc->bcr[7]; | |
419 | break; | |
420 | case 0x10: /* B0AP */ | |
421 | ret = ebc->bap[0]; | |
422 | break; | |
423 | case 0x11: /* B1AP */ | |
424 | ret = ebc->bap[1]; | |
425 | break; | |
426 | case 0x12: /* B2AP */ | |
427 | ret = ebc->bap[2]; | |
428 | break; | |
429 | case 0x13: /* B3AP */ | |
430 | ret = ebc->bap[3]; | |
431 | break; | |
432 | case 0x14: /* B4AP */ | |
433 | ret = ebc->bap[4]; | |
434 | break; | |
435 | case 0x15: /* B5AP */ | |
436 | ret = ebc->bap[5]; | |
437 | break; | |
438 | case 0x16: /* B6AP */ | |
439 | ret = ebc->bap[6]; | |
440 | break; | |
441 | case 0x17: /* B7AP */ | |
442 | ret = ebc->bap[7]; | |
443 | break; | |
444 | case 0x20: /* BEAR */ | |
445 | ret = ebc->bear; | |
446 | break; | |
447 | case 0x21: /* BESR0 */ | |
448 | ret = ebc->besr0; | |
449 | break; | |
450 | case 0x22: /* BESR1 */ | |
451 | ret = ebc->besr1; | |
452 | break; | |
453 | case 0x23: /* CFG */ | |
454 | ret = ebc->cfg; | |
455 | break; | |
456 | default: | |
457 | ret = 0x00000000; | |
458 | break; | |
459 | } | |
9fad3eb7 | 460 | break; |
8ecc7913 JM |
461 | default: |
462 | ret = 0x00000000; | |
463 | break; | |
464 | } | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
73b01960 | 469 | static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 470 | { |
c227f099 | 471 | ppc4xx_ebc_t *ebc; |
8ecc7913 JM |
472 | |
473 | ebc = opaque; | |
474 | switch (dcrn) { | |
475 | case EBC0_CFGADDR: | |
476 | ebc->addr = val; | |
477 | break; | |
478 | case EBC0_CFGDATA: | |
479 | switch (ebc->addr) { | |
480 | case 0x00: /* B0CR */ | |
481 | break; | |
482 | case 0x01: /* B1CR */ | |
483 | break; | |
484 | case 0x02: /* B2CR */ | |
485 | break; | |
486 | case 0x03: /* B3CR */ | |
487 | break; | |
488 | case 0x04: /* B4CR */ | |
489 | break; | |
490 | case 0x05: /* B5CR */ | |
491 | break; | |
492 | case 0x06: /* B6CR */ | |
493 | break; | |
494 | case 0x07: /* B7CR */ | |
495 | break; | |
496 | case 0x10: /* B0AP */ | |
497 | break; | |
498 | case 0x11: /* B1AP */ | |
499 | break; | |
500 | case 0x12: /* B2AP */ | |
501 | break; | |
502 | case 0x13: /* B3AP */ | |
503 | break; | |
504 | case 0x14: /* B4AP */ | |
505 | break; | |
506 | case 0x15: /* B5AP */ | |
507 | break; | |
508 | case 0x16: /* B6AP */ | |
509 | break; | |
510 | case 0x17: /* B7AP */ | |
511 | break; | |
512 | case 0x20: /* BEAR */ | |
513 | break; | |
514 | case 0x21: /* BESR0 */ | |
515 | break; | |
516 | case 0x22: /* BESR1 */ | |
517 | break; | |
518 | case 0x23: /* CFG */ | |
519 | break; | |
520 | default: | |
521 | break; | |
522 | } | |
523 | break; | |
524 | default: | |
525 | break; | |
526 | } | |
527 | } | |
528 | ||
529 | static void ebc_reset (void *opaque) | |
530 | { | |
c227f099 | 531 | ppc4xx_ebc_t *ebc; |
8ecc7913 JM |
532 | int i; |
533 | ||
534 | ebc = opaque; | |
535 | ebc->addr = 0x00000000; | |
536 | ebc->bap[0] = 0x7F8FFE80; | |
537 | ebc->bcr[0] = 0xFFE28000; | |
538 | for (i = 0; i < 8; i++) { | |
539 | ebc->bap[i] = 0x00000000; | |
540 | ebc->bcr[i] = 0x00000000; | |
541 | } | |
542 | ebc->besr0 = 0x00000000; | |
543 | ebc->besr1 = 0x00000000; | |
9c02f1a2 | 544 | ebc->cfg = 0x80400000; |
8ecc7913 JM |
545 | } |
546 | ||
97c2acb5 | 547 | void ppc405_ebc_init(CPUPPCState *env) |
8ecc7913 | 548 | { |
c227f099 | 549 | ppc4xx_ebc_t *ebc; |
8ecc7913 | 550 | |
7267c094 | 551 | ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); |
a08d4367 | 552 | qemu_register_reset(&ebc_reset, ebc); |
487414f1 AL |
553 | ppc_dcr_register(env, EBC0_CFGADDR, |
554 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
555 | ppc_dcr_register(env, EBC0_CFGDATA, | |
556 | ebc, &dcr_read_ebc, &dcr_write_ebc); | |
8ecc7913 JM |
557 | } |
558 | ||
559 | /*****************************************************************************/ | |
560 | /* DMA controller */ | |
561 | enum { | |
562 | DMA0_CR0 = 0x100, | |
563 | DMA0_CT0 = 0x101, | |
564 | DMA0_DA0 = 0x102, | |
565 | DMA0_SA0 = 0x103, | |
566 | DMA0_SG0 = 0x104, | |
567 | DMA0_CR1 = 0x108, | |
568 | DMA0_CT1 = 0x109, | |
569 | DMA0_DA1 = 0x10A, | |
570 | DMA0_SA1 = 0x10B, | |
571 | DMA0_SG1 = 0x10C, | |
572 | DMA0_CR2 = 0x110, | |
573 | DMA0_CT2 = 0x111, | |
574 | DMA0_DA2 = 0x112, | |
575 | DMA0_SA2 = 0x113, | |
576 | DMA0_SG2 = 0x114, | |
577 | DMA0_CR3 = 0x118, | |
578 | DMA0_CT3 = 0x119, | |
579 | DMA0_DA3 = 0x11A, | |
580 | DMA0_SA3 = 0x11B, | |
581 | DMA0_SG3 = 0x11C, | |
582 | DMA0_SR = 0x120, | |
583 | DMA0_SGC = 0x123, | |
584 | DMA0_SLP = 0x125, | |
585 | DMA0_POL = 0x126, | |
586 | }; | |
587 | ||
c227f099 AL |
588 | typedef struct ppc405_dma_t ppc405_dma_t; |
589 | struct ppc405_dma_t { | |
8ecc7913 JM |
590 | qemu_irq irqs[4]; |
591 | uint32_t cr[4]; | |
592 | uint32_t ct[4]; | |
593 | uint32_t da[4]; | |
594 | uint32_t sa[4]; | |
595 | uint32_t sg[4]; | |
596 | uint32_t sr; | |
597 | uint32_t sgc; | |
598 | uint32_t slp; | |
599 | uint32_t pol; | |
600 | }; | |
601 | ||
73b01960 | 602 | static uint32_t dcr_read_dma (void *opaque, int dcrn) |
8ecc7913 | 603 | { |
8ecc7913 JM |
604 | return 0; |
605 | } | |
606 | ||
73b01960 | 607 | static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 608 | { |
8ecc7913 JM |
609 | } |
610 | ||
611 | static void ppc405_dma_reset (void *opaque) | |
612 | { | |
c227f099 | 613 | ppc405_dma_t *dma; |
8ecc7913 JM |
614 | int i; |
615 | ||
616 | dma = opaque; | |
617 | for (i = 0; i < 4; i++) { | |
618 | dma->cr[i] = 0x00000000; | |
619 | dma->ct[i] = 0x00000000; | |
620 | dma->da[i] = 0x00000000; | |
621 | dma->sa[i] = 0x00000000; | |
622 | dma->sg[i] = 0x00000000; | |
623 | } | |
624 | dma->sr = 0x00000000; | |
625 | dma->sgc = 0x00000000; | |
626 | dma->slp = 0x7C000000; | |
627 | dma->pol = 0x00000000; | |
628 | } | |
629 | ||
e2684c0b | 630 | static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) |
8ecc7913 | 631 | { |
c227f099 | 632 | ppc405_dma_t *dma; |
8ecc7913 | 633 | |
7267c094 | 634 | dma = g_malloc0(sizeof(ppc405_dma_t)); |
487414f1 | 635 | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
a08d4367 | 636 | qemu_register_reset(&ppc405_dma_reset, dma); |
487414f1 AL |
637 | ppc_dcr_register(env, DMA0_CR0, |
638 | dma, &dcr_read_dma, &dcr_write_dma); | |
639 | ppc_dcr_register(env, DMA0_CT0, | |
640 | dma, &dcr_read_dma, &dcr_write_dma); | |
641 | ppc_dcr_register(env, DMA0_DA0, | |
642 | dma, &dcr_read_dma, &dcr_write_dma); | |
643 | ppc_dcr_register(env, DMA0_SA0, | |
644 | dma, &dcr_read_dma, &dcr_write_dma); | |
645 | ppc_dcr_register(env, DMA0_SG0, | |
646 | dma, &dcr_read_dma, &dcr_write_dma); | |
647 | ppc_dcr_register(env, DMA0_CR1, | |
648 | dma, &dcr_read_dma, &dcr_write_dma); | |
649 | ppc_dcr_register(env, DMA0_CT1, | |
650 | dma, &dcr_read_dma, &dcr_write_dma); | |
651 | ppc_dcr_register(env, DMA0_DA1, | |
652 | dma, &dcr_read_dma, &dcr_write_dma); | |
653 | ppc_dcr_register(env, DMA0_SA1, | |
654 | dma, &dcr_read_dma, &dcr_write_dma); | |
655 | ppc_dcr_register(env, DMA0_SG1, | |
656 | dma, &dcr_read_dma, &dcr_write_dma); | |
657 | ppc_dcr_register(env, DMA0_CR2, | |
658 | dma, &dcr_read_dma, &dcr_write_dma); | |
659 | ppc_dcr_register(env, DMA0_CT2, | |
660 | dma, &dcr_read_dma, &dcr_write_dma); | |
661 | ppc_dcr_register(env, DMA0_DA2, | |
662 | dma, &dcr_read_dma, &dcr_write_dma); | |
663 | ppc_dcr_register(env, DMA0_SA2, | |
664 | dma, &dcr_read_dma, &dcr_write_dma); | |
665 | ppc_dcr_register(env, DMA0_SG2, | |
666 | dma, &dcr_read_dma, &dcr_write_dma); | |
667 | ppc_dcr_register(env, DMA0_CR3, | |
668 | dma, &dcr_read_dma, &dcr_write_dma); | |
669 | ppc_dcr_register(env, DMA0_CT3, | |
670 | dma, &dcr_read_dma, &dcr_write_dma); | |
671 | ppc_dcr_register(env, DMA0_DA3, | |
672 | dma, &dcr_read_dma, &dcr_write_dma); | |
673 | ppc_dcr_register(env, DMA0_SA3, | |
674 | dma, &dcr_read_dma, &dcr_write_dma); | |
675 | ppc_dcr_register(env, DMA0_SG3, | |
676 | dma, &dcr_read_dma, &dcr_write_dma); | |
677 | ppc_dcr_register(env, DMA0_SR, | |
678 | dma, &dcr_read_dma, &dcr_write_dma); | |
679 | ppc_dcr_register(env, DMA0_SGC, | |
680 | dma, &dcr_read_dma, &dcr_write_dma); | |
681 | ppc_dcr_register(env, DMA0_SLP, | |
682 | dma, &dcr_read_dma, &dcr_write_dma); | |
683 | ppc_dcr_register(env, DMA0_POL, | |
684 | dma, &dcr_read_dma, &dcr_write_dma); | |
8ecc7913 JM |
685 | } |
686 | ||
687 | /*****************************************************************************/ | |
688 | /* GPIO */ | |
c227f099 AL |
689 | typedef struct ppc405_gpio_t ppc405_gpio_t; |
690 | struct ppc405_gpio_t { | |
9074e0e3 | 691 | MemoryRegion io; |
8ecc7913 JM |
692 | uint32_t or; |
693 | uint32_t tcr; | |
694 | uint32_t osrh; | |
695 | uint32_t osrl; | |
696 | uint32_t tsrh; | |
697 | uint32_t tsrl; | |
698 | uint32_t odr; | |
699 | uint32_t ir; | |
700 | uint32_t rr1; | |
701 | uint32_t isr1h; | |
702 | uint32_t isr1l; | |
703 | }; | |
704 | ||
69bd18f8 | 705 | static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) |
8ecc7913 | 706 | { |
8ecc7913 | 707 | #ifdef DEBUG_GPIO |
69bd18f8 | 708 | printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); |
8ecc7913 JM |
709 | #endif |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
69bd18f8 PM |
714 | static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, |
715 | unsigned size) | |
8ecc7913 | 716 | { |
8ecc7913 | 717 | #ifdef DEBUG_GPIO |
69bd18f8 PM |
718 | printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", |
719 | __func__, addr, size, value); | |
8ecc7913 JM |
720 | #endif |
721 | } | |
722 | ||
9074e0e3 | 723 | static const MemoryRegionOps ppc405_gpio_ops = { |
69bd18f8 PM |
724 | .read = ppc405_gpio_read, |
725 | .write = ppc405_gpio_write, | |
9074e0e3 | 726 | .endianness = DEVICE_NATIVE_ENDIAN, |
8ecc7913 JM |
727 | }; |
728 | ||
729 | static void ppc405_gpio_reset (void *opaque) | |
730 | { | |
8ecc7913 JM |
731 | } |
732 | ||
a8170e5e | 733 | static void ppc405_gpio_init(hwaddr base) |
8ecc7913 | 734 | { |
c227f099 | 735 | ppc405_gpio_t *gpio; |
8ecc7913 | 736 | |
7267c094 | 737 | gpio = g_malloc0(sizeof(ppc405_gpio_t)); |
8ecc7913 | 738 | #ifdef DEBUG_GPIO |
90e189ec | 739 | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
8ecc7913 | 740 | #endif |
2c9b15ca | 741 | memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); |
9074e0e3 | 742 | memory_region_add_subregion(get_system_memory(), base, &gpio->io); |
802670e6 | 743 | qemu_register_reset(&ppc405_gpio_reset, gpio); |
8ecc7913 JM |
744 | } |
745 | ||
746 | /*****************************************************************************/ | |
747 | /* On Chip Memory */ | |
748 | enum { | |
749 | OCM0_ISARC = 0x018, | |
750 | OCM0_ISACNTL = 0x019, | |
751 | OCM0_DSARC = 0x01A, | |
752 | OCM0_DSACNTL = 0x01B, | |
753 | }; | |
754 | ||
c227f099 AL |
755 | typedef struct ppc405_ocm_t ppc405_ocm_t; |
756 | struct ppc405_ocm_t { | |
9074e0e3 AK |
757 | MemoryRegion ram; |
758 | MemoryRegion isarc_ram; | |
759 | MemoryRegion dsarc_ram; | |
8ecc7913 JM |
760 | uint32_t isarc; |
761 | uint32_t isacntl; | |
762 | uint32_t dsarc; | |
763 | uint32_t dsacntl; | |
764 | }; | |
765 | ||
c227f099 | 766 | static void ocm_update_mappings (ppc405_ocm_t *ocm, |
8ecc7913 JM |
767 | uint32_t isarc, uint32_t isacntl, |
768 | uint32_t dsarc, uint32_t dsacntl) | |
769 | { | |
770 | #ifdef DEBUG_OCM | |
aae9366a JM |
771 | printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 |
772 | " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 | |
773 | " (%08" PRIx32 " %08" PRIx32 ")\n", | |
8ecc7913 JM |
774 | isarc, isacntl, dsarc, dsacntl, |
775 | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); | |
776 | #endif | |
777 | if (ocm->isarc != isarc || | |
778 | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { | |
779 | if (ocm->isacntl & 0x80000000) { | |
780 | /* Unmap previously assigned memory region */ | |
aae9366a | 781 | printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); |
9074e0e3 | 782 | memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); |
8ecc7913 JM |
783 | } |
784 | if (isacntl & 0x80000000) { | |
785 | /* Map new instruction memory region */ | |
786 | #ifdef DEBUG_OCM | |
aae9366a | 787 | printf("OCM map ISA %08" PRIx32 "\n", isarc); |
8ecc7913 | 788 | #endif |
9074e0e3 AK |
789 | memory_region_add_subregion(get_system_memory(), isarc, |
790 | &ocm->isarc_ram); | |
8ecc7913 JM |
791 | } |
792 | } | |
793 | if (ocm->dsarc != dsarc || | |
794 | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { | |
795 | if (ocm->dsacntl & 0x80000000) { | |
796 | /* Beware not to unmap the region we just mapped */ | |
797 | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { | |
798 | /* Unmap previously assigned memory region */ | |
799 | #ifdef DEBUG_OCM | |
aae9366a | 800 | printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); |
8ecc7913 | 801 | #endif |
9074e0e3 AK |
802 | memory_region_del_subregion(get_system_memory(), |
803 | &ocm->dsarc_ram); | |
8ecc7913 JM |
804 | } |
805 | } | |
806 | if (dsacntl & 0x80000000) { | |
807 | /* Beware not to remap the region we just mapped */ | |
808 | if (!(isacntl & 0x80000000) || dsarc != isarc) { | |
809 | /* Map new data memory region */ | |
810 | #ifdef DEBUG_OCM | |
aae9366a | 811 | printf("OCM map DSA %08" PRIx32 "\n", dsarc); |
8ecc7913 | 812 | #endif |
9074e0e3 AK |
813 | memory_region_add_subregion(get_system_memory(), dsarc, |
814 | &ocm->dsarc_ram); | |
8ecc7913 JM |
815 | } |
816 | } | |
817 | } | |
818 | } | |
819 | ||
73b01960 | 820 | static uint32_t dcr_read_ocm (void *opaque, int dcrn) |
8ecc7913 | 821 | { |
c227f099 | 822 | ppc405_ocm_t *ocm; |
73b01960 | 823 | uint32_t ret; |
8ecc7913 JM |
824 | |
825 | ocm = opaque; | |
826 | switch (dcrn) { | |
827 | case OCM0_ISARC: | |
828 | ret = ocm->isarc; | |
829 | break; | |
830 | case OCM0_ISACNTL: | |
831 | ret = ocm->isacntl; | |
832 | break; | |
833 | case OCM0_DSARC: | |
834 | ret = ocm->dsarc; | |
835 | break; | |
836 | case OCM0_DSACNTL: | |
837 | ret = ocm->dsacntl; | |
838 | break; | |
839 | default: | |
840 | ret = 0; | |
841 | break; | |
842 | } | |
843 | ||
844 | return ret; | |
845 | } | |
846 | ||
73b01960 | 847 | static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 848 | { |
c227f099 | 849 | ppc405_ocm_t *ocm; |
8ecc7913 JM |
850 | uint32_t isarc, dsarc, isacntl, dsacntl; |
851 | ||
852 | ocm = opaque; | |
853 | isarc = ocm->isarc; | |
854 | dsarc = ocm->dsarc; | |
855 | isacntl = ocm->isacntl; | |
856 | dsacntl = ocm->dsacntl; | |
857 | switch (dcrn) { | |
858 | case OCM0_ISARC: | |
859 | isarc = val & 0xFC000000; | |
860 | break; | |
861 | case OCM0_ISACNTL: | |
862 | isacntl = val & 0xC0000000; | |
863 | break; | |
864 | case OCM0_DSARC: | |
865 | isarc = val & 0xFC000000; | |
866 | break; | |
867 | case OCM0_DSACNTL: | |
868 | isacntl = val & 0xC0000000; | |
869 | break; | |
870 | } | |
871 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
872 | ocm->isarc = isarc; | |
873 | ocm->dsarc = dsarc; | |
874 | ocm->isacntl = isacntl; | |
875 | ocm->dsacntl = dsacntl; | |
876 | } | |
877 | ||
878 | static void ocm_reset (void *opaque) | |
879 | { | |
c227f099 | 880 | ppc405_ocm_t *ocm; |
8ecc7913 JM |
881 | uint32_t isarc, dsarc, isacntl, dsacntl; |
882 | ||
883 | ocm = opaque; | |
884 | isarc = 0x00000000; | |
885 | isacntl = 0x00000000; | |
886 | dsarc = 0x00000000; | |
887 | dsacntl = 0x00000000; | |
888 | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); | |
889 | ocm->isarc = isarc; | |
890 | ocm->dsarc = dsarc; | |
891 | ocm->isacntl = isacntl; | |
892 | ocm->dsacntl = dsacntl; | |
893 | } | |
894 | ||
e2684c0b | 895 | static void ppc405_ocm_init(CPUPPCState *env) |
8ecc7913 | 896 | { |
c227f099 | 897 | ppc405_ocm_t *ocm; |
8ecc7913 | 898 | |
7267c094 | 899 | ocm = g_malloc0(sizeof(ppc405_ocm_t)); |
9074e0e3 | 900 | /* XXX: Size is 4096 or 0x04000000 */ |
ab3dd749 | 901 | memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, |
f8ed85ac | 902 | &error_fatal); |
ab3dd749 PMD |
903 | memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", |
904 | &ocm->isarc_ram, 0, 4 * KiB); | |
a08d4367 | 905 | qemu_register_reset(&ocm_reset, ocm); |
487414f1 AL |
906 | ppc_dcr_register(env, OCM0_ISARC, |
907 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
908 | ppc_dcr_register(env, OCM0_ISACNTL, | |
909 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
910 | ppc_dcr_register(env, OCM0_DSARC, | |
911 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
912 | ppc_dcr_register(env, OCM0_DSACNTL, | |
913 | ocm, &dcr_read_ocm, &dcr_write_ocm); | |
8ecc7913 JM |
914 | } |
915 | ||
9c02f1a2 JM |
916 | /*****************************************************************************/ |
917 | /* General purpose timers */ | |
c227f099 AL |
918 | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
919 | struct ppc4xx_gpt_t { | |
9074e0e3 | 920 | MemoryRegion iomem; |
9c02f1a2 JM |
921 | int64_t tb_offset; |
922 | uint32_t tb_freq; | |
1246b259 | 923 | QEMUTimer *timer; |
9c02f1a2 JM |
924 | qemu_irq irqs[5]; |
925 | uint32_t oe; | |
926 | uint32_t ol; | |
927 | uint32_t im; | |
928 | uint32_t is; | |
929 | uint32_t ie; | |
930 | uint32_t comp[5]; | |
931 | uint32_t mask[5]; | |
932 | }; | |
933 | ||
c227f099 | 934 | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
9c02f1a2 JM |
935 | { |
936 | /* XXX: TODO */ | |
937 | return 0; | |
938 | } | |
939 | ||
c227f099 | 940 | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
9c02f1a2 JM |
941 | { |
942 | /* XXX: TODO */ | |
943 | } | |
944 | ||
c227f099 | 945 | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
9c02f1a2 JM |
946 | { |
947 | uint32_t mask; | |
948 | int i; | |
949 | ||
950 | mask = 0x80000000; | |
951 | for (i = 0; i < 5; i++) { | |
952 | if (gpt->oe & mask) { | |
953 | /* Output is enabled */ | |
954 | if (ppc4xx_gpt_compare(gpt, i)) { | |
955 | /* Comparison is OK */ | |
956 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); | |
957 | } else { | |
958 | /* Comparison is KO */ | |
959 | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); | |
960 | } | |
961 | } | |
962 | mask = mask >> 1; | |
963 | } | |
9c02f1a2 JM |
964 | } |
965 | ||
c227f099 | 966 | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
9c02f1a2 JM |
967 | { |
968 | uint32_t mask; | |
969 | int i; | |
970 | ||
971 | mask = 0x00008000; | |
972 | for (i = 0; i < 5; i++) { | |
973 | if (gpt->is & gpt->im & mask) | |
974 | qemu_irq_raise(gpt->irqs[i]); | |
975 | else | |
976 | qemu_irq_lower(gpt->irqs[i]); | |
977 | mask = mask >> 1; | |
978 | } | |
9c02f1a2 JM |
979 | } |
980 | ||
c227f099 | 981 | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
9c02f1a2 JM |
982 | { |
983 | /* XXX: TODO */ | |
984 | } | |
985 | ||
69bd18f8 | 986 | static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) |
9c02f1a2 | 987 | { |
c227f099 | 988 | ppc4xx_gpt_t *gpt; |
9c02f1a2 JM |
989 | uint32_t ret; |
990 | int idx; | |
991 | ||
992 | #ifdef DEBUG_GPT | |
90e189ec | 993 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
9c02f1a2 JM |
994 | #endif |
995 | gpt = opaque; | |
802670e6 | 996 | switch (addr) { |
9c02f1a2 JM |
997 | case 0x00: |
998 | /* Time base counter */ | |
bc72ad67 | 999 | ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, |
73bcb24d | 1000 | gpt->tb_freq, NANOSECONDS_PER_SECOND); |
9c02f1a2 JM |
1001 | break; |
1002 | case 0x10: | |
1003 | /* Output enable */ | |
1004 | ret = gpt->oe; | |
1005 | break; | |
1006 | case 0x14: | |
1007 | /* Output level */ | |
1008 | ret = gpt->ol; | |
1009 | break; | |
1010 | case 0x18: | |
1011 | /* Interrupt mask */ | |
1012 | ret = gpt->im; | |
1013 | break; | |
1014 | case 0x1C: | |
1015 | case 0x20: | |
1016 | /* Interrupt status */ | |
1017 | ret = gpt->is; | |
1018 | break; | |
1019 | case 0x24: | |
1020 | /* Interrupt enable */ | |
1021 | ret = gpt->ie; | |
1022 | break; | |
1023 | case 0x80 ... 0x90: | |
1024 | /* Compare timer */ | |
802670e6 | 1025 | idx = (addr - 0x80) >> 2; |
9c02f1a2 JM |
1026 | ret = gpt->comp[idx]; |
1027 | break; | |
1028 | case 0xC0 ... 0xD0: | |
1029 | /* Compare mask */ | |
802670e6 | 1030 | idx = (addr - 0xC0) >> 2; |
9c02f1a2 JM |
1031 | ret = gpt->mask[idx]; |
1032 | break; | |
1033 | default: | |
1034 | ret = -1; | |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | return ret; | |
1039 | } | |
1040 | ||
69bd18f8 PM |
1041 | static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, |
1042 | unsigned size) | |
9c02f1a2 | 1043 | { |
c227f099 | 1044 | ppc4xx_gpt_t *gpt; |
9c02f1a2 JM |
1045 | int idx; |
1046 | ||
1047 | #ifdef DEBUG_I2C | |
90e189ec BS |
1048 | printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, |
1049 | value); | |
9c02f1a2 JM |
1050 | #endif |
1051 | gpt = opaque; | |
802670e6 | 1052 | switch (addr) { |
9c02f1a2 JM |
1053 | case 0x00: |
1054 | /* Time base counter */ | |
73bcb24d | 1055 | gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) |
bc72ad67 | 1056 | - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
9c02f1a2 JM |
1057 | ppc4xx_gpt_compute_timer(gpt); |
1058 | break; | |
1059 | case 0x10: | |
1060 | /* Output enable */ | |
1061 | gpt->oe = value & 0xF8000000; | |
1062 | ppc4xx_gpt_set_outputs(gpt); | |
1063 | break; | |
1064 | case 0x14: | |
1065 | /* Output level */ | |
1066 | gpt->ol = value & 0xF8000000; | |
1067 | ppc4xx_gpt_set_outputs(gpt); | |
1068 | break; | |
1069 | case 0x18: | |
1070 | /* Interrupt mask */ | |
1071 | gpt->im = value & 0x0000F800; | |
1072 | break; | |
1073 | case 0x1C: | |
1074 | /* Interrupt status set */ | |
1075 | gpt->is |= value & 0x0000F800; | |
1076 | ppc4xx_gpt_set_irqs(gpt); | |
1077 | break; | |
1078 | case 0x20: | |
1079 | /* Interrupt status clear */ | |
1080 | gpt->is &= ~(value & 0x0000F800); | |
1081 | ppc4xx_gpt_set_irqs(gpt); | |
1082 | break; | |
1083 | case 0x24: | |
1084 | /* Interrupt enable */ | |
1085 | gpt->ie = value & 0x0000F800; | |
1086 | ppc4xx_gpt_set_irqs(gpt); | |
1087 | break; | |
1088 | case 0x80 ... 0x90: | |
1089 | /* Compare timer */ | |
802670e6 | 1090 | idx = (addr - 0x80) >> 2; |
9c02f1a2 JM |
1091 | gpt->comp[idx] = value & 0xF8000000; |
1092 | ppc4xx_gpt_compute_timer(gpt); | |
1093 | break; | |
1094 | case 0xC0 ... 0xD0: | |
1095 | /* Compare mask */ | |
802670e6 | 1096 | idx = (addr - 0xC0) >> 2; |
9c02f1a2 JM |
1097 | gpt->mask[idx] = value & 0xF8000000; |
1098 | ppc4xx_gpt_compute_timer(gpt); | |
1099 | break; | |
1100 | } | |
1101 | } | |
1102 | ||
9074e0e3 | 1103 | static const MemoryRegionOps gpt_ops = { |
69bd18f8 PM |
1104 | .read = ppc4xx_gpt_read, |
1105 | .write = ppc4xx_gpt_write, | |
1106 | .valid.min_access_size = 4, | |
1107 | .valid.max_access_size = 4, | |
9074e0e3 | 1108 | .endianness = DEVICE_NATIVE_ENDIAN, |
9c02f1a2 JM |
1109 | }; |
1110 | ||
1111 | static void ppc4xx_gpt_cb (void *opaque) | |
1112 | { | |
c227f099 | 1113 | ppc4xx_gpt_t *gpt; |
9c02f1a2 JM |
1114 | |
1115 | gpt = opaque; | |
1116 | ppc4xx_gpt_set_irqs(gpt); | |
1117 | ppc4xx_gpt_set_outputs(gpt); | |
1118 | ppc4xx_gpt_compute_timer(gpt); | |
1119 | } | |
1120 | ||
1121 | static void ppc4xx_gpt_reset (void *opaque) | |
1122 | { | |
c227f099 | 1123 | ppc4xx_gpt_t *gpt; |
9c02f1a2 JM |
1124 | int i; |
1125 | ||
1126 | gpt = opaque; | |
bc72ad67 | 1127 | timer_del(gpt->timer); |
9c02f1a2 JM |
1128 | gpt->oe = 0x00000000; |
1129 | gpt->ol = 0x00000000; | |
1130 | gpt->im = 0x00000000; | |
1131 | gpt->is = 0x00000000; | |
1132 | gpt->ie = 0x00000000; | |
1133 | for (i = 0; i < 5; i++) { | |
1134 | gpt->comp[i] = 0x00000000; | |
1135 | gpt->mask[i] = 0x00000000; | |
1136 | } | |
1137 | } | |
1138 | ||
a8170e5e | 1139 | static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) |
9c02f1a2 | 1140 | { |
c227f099 | 1141 | ppc4xx_gpt_t *gpt; |
9c02f1a2 JM |
1142 | int i; |
1143 | ||
7267c094 | 1144 | gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); |
802670e6 | 1145 | for (i = 0; i < 5; i++) { |
487414f1 | 1146 | gpt->irqs[i] = irqs[i]; |
802670e6 | 1147 | } |
bc72ad67 | 1148 | gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); |
9c02f1a2 | 1149 | #ifdef DEBUG_GPT |
90e189ec | 1150 | printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); |
9c02f1a2 | 1151 | #endif |
2c9b15ca | 1152 | memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); |
9074e0e3 | 1153 | memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); |
a08d4367 | 1154 | qemu_register_reset(ppc4xx_gpt_reset, gpt); |
9c02f1a2 JM |
1155 | } |
1156 | ||
8ecc7913 JM |
1157 | /*****************************************************************************/ |
1158 | /* PowerPC 405CR */ | |
1159 | enum { | |
1160 | PPC405CR_CPC0_PLLMR = 0x0B0, | |
1161 | PPC405CR_CPC0_CR0 = 0x0B1, | |
1162 | PPC405CR_CPC0_CR1 = 0x0B2, | |
1163 | PPC405CR_CPC0_PSR = 0x0B4, | |
1164 | PPC405CR_CPC0_JTAGID = 0x0B5, | |
1165 | PPC405CR_CPC0_ER = 0x0B9, | |
1166 | PPC405CR_CPC0_FR = 0x0BA, | |
1167 | PPC405CR_CPC0_SR = 0x0BB, | |
1168 | }; | |
1169 | ||
04f20795 JM |
1170 | enum { |
1171 | PPC405CR_CPU_CLK = 0, | |
1172 | PPC405CR_TMR_CLK = 1, | |
1173 | PPC405CR_PLB_CLK = 2, | |
1174 | PPC405CR_SDRAM_CLK = 3, | |
1175 | PPC405CR_OPB_CLK = 4, | |
1176 | PPC405CR_EXT_CLK = 5, | |
1177 | PPC405CR_UART_CLK = 6, | |
1178 | PPC405CR_CLK_NB = 7, | |
1179 | }; | |
1180 | ||
c227f099 AL |
1181 | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
1182 | struct ppc405cr_cpc_t { | |
1183 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; | |
8ecc7913 JM |
1184 | uint32_t sysclk; |
1185 | uint32_t psr; | |
1186 | uint32_t cr0; | |
1187 | uint32_t cr1; | |
1188 | uint32_t jtagid; | |
1189 | uint32_t pllmr; | |
1190 | uint32_t er; | |
1191 | uint32_t fr; | |
1192 | }; | |
1193 | ||
c227f099 | 1194 | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
8ecc7913 JM |
1195 | { |
1196 | uint64_t VCO_out, PLL_out; | |
1197 | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; | |
1198 | int M, D0, D1, D2; | |
1199 | ||
1200 | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ | |
1201 | if (cpc->pllmr & 0x80000000) { | |
1202 | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ | |
1203 | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ | |
1204 | M = D0 * D1 * D2; | |
fb6971c1 | 1205 | VCO_out = (uint64_t)cpc->sysclk * M; |
8ecc7913 JM |
1206 | if (VCO_out < 400000000 || VCO_out > 800000000) { |
1207 | /* PLL cannot lock */ | |
1208 | cpc->pllmr &= ~0x80000000; | |
1209 | goto bypass_pll; | |
1210 | } | |
1211 | PLL_out = VCO_out / D2; | |
1212 | } else { | |
1213 | /* Bypass PLL */ | |
1214 | bypass_pll: | |
1215 | M = D0; | |
fb6971c1 | 1216 | PLL_out = (uint64_t)cpc->sysclk * M; |
8ecc7913 JM |
1217 | } |
1218 | CPU_clk = PLL_out; | |
1219 | if (cpc->cr1 & 0x00800000) | |
1220 | TMR_clk = cpc->sysclk; /* Should have a separate clock */ | |
1221 | else | |
1222 | TMR_clk = CPU_clk; | |
1223 | PLB_clk = CPU_clk / D0; | |
1224 | SDRAM_clk = PLB_clk; | |
1225 | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; | |
1226 | OPB_clk = PLB_clk / D0; | |
1227 | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; | |
1228 | EXT_clk = PLB_clk / D0; | |
1229 | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; | |
1230 | UART_clk = CPU_clk / D0; | |
1231 | /* Setup CPU clocks */ | |
04f20795 | 1232 | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
8ecc7913 | 1233 | /* Setup time-base clock */ |
04f20795 | 1234 | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
8ecc7913 | 1235 | /* Setup PLB clock */ |
04f20795 | 1236 | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
8ecc7913 | 1237 | /* Setup SDRAM clock */ |
04f20795 | 1238 | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
8ecc7913 | 1239 | /* Setup OPB clock */ |
04f20795 | 1240 | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
8ecc7913 | 1241 | /* Setup external clock */ |
04f20795 | 1242 | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
8ecc7913 | 1243 | /* Setup UART clock */ |
04f20795 | 1244 | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
8ecc7913 JM |
1245 | } |
1246 | ||
73b01960 | 1247 | static uint32_t dcr_read_crcpc (void *opaque, int dcrn) |
8ecc7913 | 1248 | { |
c227f099 | 1249 | ppc405cr_cpc_t *cpc; |
73b01960 | 1250 | uint32_t ret; |
8ecc7913 JM |
1251 | |
1252 | cpc = opaque; | |
1253 | switch (dcrn) { | |
1254 | case PPC405CR_CPC0_PLLMR: | |
1255 | ret = cpc->pllmr; | |
1256 | break; | |
1257 | case PPC405CR_CPC0_CR0: | |
1258 | ret = cpc->cr0; | |
1259 | break; | |
1260 | case PPC405CR_CPC0_CR1: | |
1261 | ret = cpc->cr1; | |
1262 | break; | |
1263 | case PPC405CR_CPC0_PSR: | |
1264 | ret = cpc->psr; | |
1265 | break; | |
1266 | case PPC405CR_CPC0_JTAGID: | |
1267 | ret = cpc->jtagid; | |
1268 | break; | |
1269 | case PPC405CR_CPC0_ER: | |
1270 | ret = cpc->er; | |
1271 | break; | |
1272 | case PPC405CR_CPC0_FR: | |
1273 | ret = cpc->fr; | |
1274 | break; | |
1275 | case PPC405CR_CPC0_SR: | |
1276 | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000; | |
1277 | break; | |
1278 | default: | |
1279 | /* Avoid gcc warning */ | |
1280 | ret = 0; | |
1281 | break; | |
1282 | } | |
1283 | ||
1284 | return ret; | |
1285 | } | |
1286 | ||
73b01960 | 1287 | static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 1288 | { |
c227f099 | 1289 | ppc405cr_cpc_t *cpc; |
8ecc7913 JM |
1290 | |
1291 | cpc = opaque; | |
1292 | switch (dcrn) { | |
1293 | case PPC405CR_CPC0_PLLMR: | |
1294 | cpc->pllmr = val & 0xFFF77C3F; | |
1295 | break; | |
1296 | case PPC405CR_CPC0_CR0: | |
1297 | cpc->cr0 = val & 0x0FFFFFFE; | |
1298 | break; | |
1299 | case PPC405CR_CPC0_CR1: | |
1300 | cpc->cr1 = val & 0x00800000; | |
1301 | break; | |
1302 | case PPC405CR_CPC0_PSR: | |
1303 | /* Read-only */ | |
1304 | break; | |
1305 | case PPC405CR_CPC0_JTAGID: | |
1306 | /* Read-only */ | |
1307 | break; | |
1308 | case PPC405CR_CPC0_ER: | |
1309 | cpc->er = val & 0xBFFC0000; | |
1310 | break; | |
1311 | case PPC405CR_CPC0_FR: | |
1312 | cpc->fr = val & 0xBFFC0000; | |
1313 | break; | |
1314 | case PPC405CR_CPC0_SR: | |
1315 | /* Read-only */ | |
1316 | break; | |
1317 | } | |
1318 | } | |
1319 | ||
1320 | static void ppc405cr_cpc_reset (void *opaque) | |
1321 | { | |
c227f099 | 1322 | ppc405cr_cpc_t *cpc; |
8ecc7913 JM |
1323 | int D; |
1324 | ||
1325 | cpc = opaque; | |
1326 | /* Compute PLLMR value from PSR settings */ | |
1327 | cpc->pllmr = 0x80000000; | |
1328 | /* PFWD */ | |
1329 | switch ((cpc->psr >> 30) & 3) { | |
1330 | case 0: | |
1331 | /* Bypass */ | |
1332 | cpc->pllmr &= ~0x80000000; | |
1333 | break; | |
1334 | case 1: | |
1335 | /* Divide by 3 */ | |
1336 | cpc->pllmr |= 5 << 16; | |
1337 | break; | |
1338 | case 2: | |
1339 | /* Divide by 4 */ | |
1340 | cpc->pllmr |= 4 << 16; | |
1341 | break; | |
1342 | case 3: | |
1343 | /* Divide by 6 */ | |
1344 | cpc->pllmr |= 2 << 16; | |
1345 | break; | |
1346 | } | |
1347 | /* PFBD */ | |
1348 | D = (cpc->psr >> 28) & 3; | |
1349 | cpc->pllmr |= (D + 1) << 20; | |
1350 | /* PT */ | |
1351 | D = (cpc->psr >> 25) & 7; | |
1352 | switch (D) { | |
1353 | case 0x2: | |
1354 | cpc->pllmr |= 0x13; | |
1355 | break; | |
1356 | case 0x4: | |
1357 | cpc->pllmr |= 0x15; | |
1358 | break; | |
1359 | case 0x5: | |
1360 | cpc->pllmr |= 0x16; | |
1361 | break; | |
1362 | default: | |
1363 | break; | |
1364 | } | |
1365 | /* PDC */ | |
1366 | D = (cpc->psr >> 23) & 3; | |
1367 | cpc->pllmr |= D << 26; | |
1368 | /* ODP */ | |
1369 | D = (cpc->psr >> 21) & 3; | |
1370 | cpc->pllmr |= D << 10; | |
1371 | /* EBPD */ | |
1372 | D = (cpc->psr >> 17) & 3; | |
1373 | cpc->pllmr |= D << 24; | |
1374 | cpc->cr0 = 0x0000003C; | |
1375 | cpc->cr1 = 0x2B0D8800; | |
1376 | cpc->er = 0x00000000; | |
1377 | cpc->fr = 0x00000000; | |
1378 | ppc405cr_clk_setup(cpc); | |
1379 | } | |
1380 | ||
c227f099 | 1381 | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
8ecc7913 JM |
1382 | { |
1383 | int D; | |
1384 | ||
1385 | /* XXX: this should be read from IO pins */ | |
1386 | cpc->psr = 0x00000000; /* 8 bits ROM */ | |
1387 | /* PFWD */ | |
1388 | D = 0x2; /* Divide by 4 */ | |
1389 | cpc->psr |= D << 30; | |
1390 | /* PFBD */ | |
1391 | D = 0x1; /* Divide by 2 */ | |
1392 | cpc->psr |= D << 28; | |
1393 | /* PDC */ | |
1394 | D = 0x1; /* Divide by 2 */ | |
1395 | cpc->psr |= D << 23; | |
1396 | /* PT */ | |
1397 | D = 0x5; /* M = 16 */ | |
1398 | cpc->psr |= D << 25; | |
1399 | /* ODP */ | |
1400 | D = 0x1; /* Divide by 2 */ | |
1401 | cpc->psr |= D << 21; | |
1402 | /* EBDP */ | |
1403 | D = 0x2; /* Divide by 4 */ | |
1404 | cpc->psr |= D << 17; | |
1405 | } | |
1406 | ||
e2684c0b | 1407 | static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], |
8ecc7913 JM |
1408 | uint32_t sysclk) |
1409 | { | |
c227f099 | 1410 | ppc405cr_cpc_t *cpc; |
8ecc7913 | 1411 | |
7267c094 | 1412 | cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); |
487414f1 | 1413 | memcpy(cpc->clk_setup, clk_setup, |
c227f099 | 1414 | PPC405CR_CLK_NB * sizeof(clk_setup_t)); |
487414f1 AL |
1415 | cpc->sysclk = sysclk; |
1416 | cpc->jtagid = 0x42051049; | |
1417 | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, | |
1418 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1419 | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, | |
1420 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1421 | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, | |
1422 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1423 | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, | |
1424 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1425 | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, | |
1426 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1427 | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, | |
1428 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1429 | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, | |
1430 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1431 | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, | |
1432 | &dcr_read_crcpc, &dcr_write_crcpc); | |
1433 | ppc405cr_clk_init(cpc); | |
a08d4367 | 1434 | qemu_register_reset(ppc405cr_cpc_reset, cpc); |
8ecc7913 JM |
1435 | } |
1436 | ||
e2684c0b | 1437 | CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, |
52ce55a1 | 1438 | MemoryRegion ram_memories[4], |
a8170e5e AK |
1439 | hwaddr ram_bases[4], |
1440 | hwaddr ram_sizes[4], | |
52ce55a1 RH |
1441 | uint32_t sysclk, qemu_irq **picp, |
1442 | int do_init) | |
8ecc7913 | 1443 | { |
c227f099 | 1444 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
8ecc7913 | 1445 | qemu_irq dma_irqs[4]; |
2f9859fb | 1446 | PowerPCCPU *cpu; |
e2684c0b | 1447 | CPUPPCState *env; |
8ecc7913 | 1448 | qemu_irq *pic, *irqs; |
8ecc7913 JM |
1449 | |
1450 | memset(clk_setup, 0, sizeof(clk_setup)); | |
9391b8c5 IM |
1451 | cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), |
1452 | &clk_setup[PPC405CR_CPU_CLK], | |
04f20795 | 1453 | &clk_setup[PPC405CR_TMR_CLK], sysclk); |
2f9859fb | 1454 | env = &cpu->env; |
8ecc7913 | 1455 | /* Memory mapped devices registers */ |
8ecc7913 JM |
1456 | /* PLB arbitrer */ |
1457 | ppc4xx_plb_init(env); | |
1458 | /* PLB to OPB bridge */ | |
1459 | ppc4xx_pob_init(env); | |
1460 | /* OBP arbitrer */ | |
802670e6 | 1461 | ppc4xx_opba_init(0xef600600); |
8ecc7913 | 1462 | /* Universal interrupt controller */ |
c4f46986 | 1463 | irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); |
8ecc7913 | 1464 | irqs[PPCUIC_OUTPUT_INT] = |
b48d7d69 | 1465 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
8ecc7913 | 1466 | irqs[PPCUIC_OUTPUT_CINT] = |
b48d7d69 | 1467 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
8ecc7913 JM |
1468 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
1469 | *picp = pic; | |
1470 | /* SDRAM controller */ | |
b6dcbe08 AK |
1471 | ppc4xx_sdram_init(env, pic[14], 1, ram_memories, |
1472 | ram_bases, ram_sizes, do_init); | |
8ecc7913 JM |
1473 | /* External bus controller */ |
1474 | ppc405_ebc_init(env); | |
1475 | /* DMA controller */ | |
04f20795 JM |
1476 | dma_irqs[0] = pic[26]; |
1477 | dma_irqs[1] = pic[25]; | |
1478 | dma_irqs[2] = pic[24]; | |
1479 | dma_irqs[3] = pic[23]; | |
8ecc7913 JM |
1480 | ppc405_dma_init(env, dma_irqs); |
1481 | /* Serial ports */ | |
9bca0edb | 1482 | if (serial_hd(0) != NULL) { |
52ce55a1 | 1483 | serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], |
9bca0edb | 1484 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
39186d8a | 1485 | DEVICE_BIG_ENDIAN); |
8ecc7913 | 1486 | } |
9bca0edb | 1487 | if (serial_hd(1) != NULL) { |
52ce55a1 | 1488 | serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], |
9bca0edb | 1489 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
39186d8a | 1490 | DEVICE_BIG_ENDIAN); |
8ecc7913 JM |
1491 | } |
1492 | /* IIC controller */ | |
3b09bb0f | 1493 | sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); |
8ecc7913 | 1494 | /* GPIO */ |
802670e6 | 1495 | ppc405_gpio_init(0xef600700); |
8ecc7913 JM |
1496 | /* CPU control */ |
1497 | ppc405cr_cpc_init(env, clk_setup, sysclk); | |
8ecc7913 JM |
1498 | |
1499 | return env; | |
1500 | } | |
1501 | ||
1502 | /*****************************************************************************/ | |
1503 | /* PowerPC 405EP */ | |
1504 | /* CPU control */ | |
1505 | enum { | |
1506 | PPC405EP_CPC0_PLLMR0 = 0x0F0, | |
1507 | PPC405EP_CPC0_BOOT = 0x0F1, | |
1508 | PPC405EP_CPC0_EPCTL = 0x0F3, | |
1509 | PPC405EP_CPC0_PLLMR1 = 0x0F4, | |
1510 | PPC405EP_CPC0_UCR = 0x0F5, | |
1511 | PPC405EP_CPC0_SRR = 0x0F6, | |
1512 | PPC405EP_CPC0_JTAGID = 0x0F7, | |
1513 | PPC405EP_CPC0_PCI = 0x0F9, | |
9c02f1a2 JM |
1514 | #if 0 |
1515 | PPC405EP_CPC0_ER = xxx, | |
1516 | PPC405EP_CPC0_FR = xxx, | |
1517 | PPC405EP_CPC0_SR = xxx, | |
1518 | #endif | |
8ecc7913 JM |
1519 | }; |
1520 | ||
04f20795 JM |
1521 | enum { |
1522 | PPC405EP_CPU_CLK = 0, | |
1523 | PPC405EP_PLB_CLK = 1, | |
1524 | PPC405EP_OPB_CLK = 2, | |
1525 | PPC405EP_EBC_CLK = 3, | |
1526 | PPC405EP_MAL_CLK = 4, | |
1527 | PPC405EP_PCI_CLK = 5, | |
1528 | PPC405EP_UART0_CLK = 6, | |
1529 | PPC405EP_UART1_CLK = 7, | |
1530 | PPC405EP_CLK_NB = 8, | |
1531 | }; | |
1532 | ||
c227f099 AL |
1533 | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
1534 | struct ppc405ep_cpc_t { | |
8ecc7913 | 1535 | uint32_t sysclk; |
c227f099 | 1536 | clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
8ecc7913 JM |
1537 | uint32_t boot; |
1538 | uint32_t epctl; | |
1539 | uint32_t pllmr[2]; | |
1540 | uint32_t ucr; | |
1541 | uint32_t srr; | |
1542 | uint32_t jtagid; | |
1543 | uint32_t pci; | |
9c02f1a2 JM |
1544 | /* Clock and power management */ |
1545 | uint32_t er; | |
1546 | uint32_t fr; | |
1547 | uint32_t sr; | |
8ecc7913 JM |
1548 | }; |
1549 | ||
c227f099 | 1550 | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
8ecc7913 JM |
1551 | { |
1552 | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; | |
1553 | uint32_t UART0_clk, UART1_clk; | |
1554 | uint64_t VCO_out, PLL_out; | |
1555 | int M, D; | |
1556 | ||
1557 | VCO_out = 0; | |
1558 | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { | |
1559 | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ | |
aae9366a JM |
1560 | #ifdef DEBUG_CLOCKS_LL |
1561 | printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); | |
1562 | #endif | |
8ecc7913 | 1563 | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
aae9366a JM |
1564 | #ifdef DEBUG_CLOCKS_LL |
1565 | printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); | |
1566 | #endif | |
fb6971c1 | 1567 | VCO_out = (uint64_t)cpc->sysclk * M * D; |
8ecc7913 JM |
1568 | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
1569 | /* Error - unlock the PLL */ | |
1570 | printf("VCO out of range %" PRIu64 "\n", VCO_out); | |
1571 | #if 0 | |
1572 | cpc->pllmr[1] &= ~0x80000000; | |
1573 | goto pll_bypass; | |
1574 | #endif | |
1575 | } | |
1576 | PLL_out = VCO_out / D; | |
9c02f1a2 JM |
1577 | /* Pretend the PLL is locked */ |
1578 | cpc->boot |= 0x00000001; | |
8ecc7913 JM |
1579 | } else { |
1580 | #if 0 | |
1581 | pll_bypass: | |
1582 | #endif | |
1583 | PLL_out = cpc->sysclk; | |
9c02f1a2 JM |
1584 | if (cpc->pllmr[1] & 0x40000000) { |
1585 | /* Pretend the PLL is not locked */ | |
1586 | cpc->boot &= ~0x00000001; | |
1587 | } | |
8ecc7913 JM |
1588 | } |
1589 | /* Now, compute all other clocks */ | |
1590 | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ | |
aae9366a JM |
1591 | #ifdef DEBUG_CLOCKS_LL |
1592 | printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); | |
8ecc7913 JM |
1593 | #endif |
1594 | CPU_clk = PLL_out / D; | |
1595 | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ | |
aae9366a JM |
1596 | #ifdef DEBUG_CLOCKS_LL |
1597 | printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); | |
8ecc7913 JM |
1598 | #endif |
1599 | PLB_clk = CPU_clk / D; | |
1600 | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ | |
aae9366a JM |
1601 | #ifdef DEBUG_CLOCKS_LL |
1602 | printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); | |
8ecc7913 JM |
1603 | #endif |
1604 | OPB_clk = PLB_clk / D; | |
1605 | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ | |
aae9366a JM |
1606 | #ifdef DEBUG_CLOCKS_LL |
1607 | printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); | |
8ecc7913 JM |
1608 | #endif |
1609 | EBC_clk = PLB_clk / D; | |
1610 | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ | |
aae9366a JM |
1611 | #ifdef DEBUG_CLOCKS_LL |
1612 | printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); | |
8ecc7913 JM |
1613 | #endif |
1614 | MAL_clk = PLB_clk / D; | |
1615 | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ | |
aae9366a JM |
1616 | #ifdef DEBUG_CLOCKS_LL |
1617 | printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); | |
8ecc7913 JM |
1618 | #endif |
1619 | PCI_clk = PLB_clk / D; | |
1620 | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ | |
aae9366a JM |
1621 | #ifdef DEBUG_CLOCKS_LL |
1622 | printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); | |
8ecc7913 JM |
1623 | #endif |
1624 | UART0_clk = PLL_out / D; | |
1625 | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ | |
aae9366a JM |
1626 | #ifdef DEBUG_CLOCKS_LL |
1627 | printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); | |
8ecc7913 JM |
1628 | #endif |
1629 | UART1_clk = PLL_out / D; | |
1630 | #ifdef DEBUG_CLOCKS | |
aae9366a | 1631 | printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 |
8ecc7913 | 1632 | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
aae9366a JM |
1633 | printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 |
1634 | " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 | |
1635 | " UART1 %" PRIu32 "\n", | |
8ecc7913 JM |
1636 | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
1637 | UART0_clk, UART1_clk); | |
1638 | #endif | |
1639 | /* Setup CPU clocks */ | |
04f20795 | 1640 | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
8ecc7913 | 1641 | /* Setup PLB clock */ |
04f20795 | 1642 | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
8ecc7913 | 1643 | /* Setup OPB clock */ |
04f20795 | 1644 | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
8ecc7913 | 1645 | /* Setup external clock */ |
04f20795 | 1646 | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
8ecc7913 | 1647 | /* Setup MAL clock */ |
04f20795 | 1648 | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
8ecc7913 | 1649 | /* Setup PCI clock */ |
04f20795 | 1650 | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
8ecc7913 | 1651 | /* Setup UART0 clock */ |
04f20795 | 1652 | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
8ecc7913 | 1653 | /* Setup UART1 clock */ |
04f20795 | 1654 | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
8ecc7913 JM |
1655 | } |
1656 | ||
73b01960 | 1657 | static uint32_t dcr_read_epcpc (void *opaque, int dcrn) |
8ecc7913 | 1658 | { |
c227f099 | 1659 | ppc405ep_cpc_t *cpc; |
73b01960 | 1660 | uint32_t ret; |
8ecc7913 JM |
1661 | |
1662 | cpc = opaque; | |
1663 | switch (dcrn) { | |
1664 | case PPC405EP_CPC0_BOOT: | |
1665 | ret = cpc->boot; | |
1666 | break; | |
1667 | case PPC405EP_CPC0_EPCTL: | |
1668 | ret = cpc->epctl; | |
1669 | break; | |
1670 | case PPC405EP_CPC0_PLLMR0: | |
1671 | ret = cpc->pllmr[0]; | |
1672 | break; | |
1673 | case PPC405EP_CPC0_PLLMR1: | |
1674 | ret = cpc->pllmr[1]; | |
1675 | break; | |
1676 | case PPC405EP_CPC0_UCR: | |
1677 | ret = cpc->ucr; | |
1678 | break; | |
1679 | case PPC405EP_CPC0_SRR: | |
1680 | ret = cpc->srr; | |
1681 | break; | |
1682 | case PPC405EP_CPC0_JTAGID: | |
1683 | ret = cpc->jtagid; | |
1684 | break; | |
1685 | case PPC405EP_CPC0_PCI: | |
1686 | ret = cpc->pci; | |
1687 | break; | |
1688 | default: | |
1689 | /* Avoid gcc warning */ | |
1690 | ret = 0; | |
1691 | break; | |
1692 | } | |
1693 | ||
1694 | return ret; | |
1695 | } | |
1696 | ||
73b01960 | 1697 | static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) |
8ecc7913 | 1698 | { |
c227f099 | 1699 | ppc405ep_cpc_t *cpc; |
8ecc7913 JM |
1700 | |
1701 | cpc = opaque; | |
1702 | switch (dcrn) { | |
1703 | case PPC405EP_CPC0_BOOT: | |
1704 | /* Read-only register */ | |
1705 | break; | |
1706 | case PPC405EP_CPC0_EPCTL: | |
1707 | /* Don't care for now */ | |
1708 | cpc->epctl = val & 0xC00000F3; | |
1709 | break; | |
1710 | case PPC405EP_CPC0_PLLMR0: | |
1711 | cpc->pllmr[0] = val & 0x00633333; | |
1712 | ppc405ep_compute_clocks(cpc); | |
1713 | break; | |
1714 | case PPC405EP_CPC0_PLLMR1: | |
1715 | cpc->pllmr[1] = val & 0xC0F73FFF; | |
1716 | ppc405ep_compute_clocks(cpc); | |
1717 | break; | |
1718 | case PPC405EP_CPC0_UCR: | |
1719 | /* UART control - don't care for now */ | |
1720 | cpc->ucr = val & 0x003F7F7F; | |
1721 | break; | |
1722 | case PPC405EP_CPC0_SRR: | |
1723 | cpc->srr = val; | |
1724 | break; | |
1725 | case PPC405EP_CPC0_JTAGID: | |
1726 | /* Read-only */ | |
1727 | break; | |
1728 | case PPC405EP_CPC0_PCI: | |
1729 | cpc->pci = val; | |
1730 | break; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | static void ppc405ep_cpc_reset (void *opaque) | |
1735 | { | |
c227f099 | 1736 | ppc405ep_cpc_t *cpc = opaque; |
8ecc7913 JM |
1737 | |
1738 | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ | |
1739 | cpc->epctl = 0x00000000; | |
1740 | cpc->pllmr[0] = 0x00011010; | |
1741 | cpc->pllmr[1] = 0x40000000; | |
1742 | cpc->ucr = 0x00000000; | |
1743 | cpc->srr = 0x00040000; | |
1744 | cpc->pci = 0x00000000; | |
9c02f1a2 JM |
1745 | cpc->er = 0x00000000; |
1746 | cpc->fr = 0x00000000; | |
1747 | cpc->sr = 0x00000000; | |
8ecc7913 JM |
1748 | ppc405ep_compute_clocks(cpc); |
1749 | } | |
1750 | ||
1751 | /* XXX: sysclk should be between 25 and 100 MHz */ | |
e2684c0b | 1752 | static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], |
8ecc7913 JM |
1753 | uint32_t sysclk) |
1754 | { | |
c227f099 | 1755 | ppc405ep_cpc_t *cpc; |
8ecc7913 | 1756 | |
7267c094 | 1757 | cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); |
487414f1 | 1758 | memcpy(cpc->clk_setup, clk_setup, |
c227f099 | 1759 | PPC405EP_CLK_NB * sizeof(clk_setup_t)); |
487414f1 AL |
1760 | cpc->jtagid = 0x20267049; |
1761 | cpc->sysclk = sysclk; | |
a08d4367 | 1762 | qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
487414f1 AL |
1763 | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
1764 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1765 | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, | |
1766 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1767 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, | |
1768 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1769 | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, | |
1770 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1771 | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, | |
1772 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1773 | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, | |
1774 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1775 | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, | |
1776 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1777 | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, | |
1778 | &dcr_read_epcpc, &dcr_write_epcpc); | |
9c02f1a2 | 1779 | #if 0 |
487414f1 AL |
1780 | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, |
1781 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1782 | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, | |
1783 | &dcr_read_epcpc, &dcr_write_epcpc); | |
1784 | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, | |
1785 | &dcr_read_epcpc, &dcr_write_epcpc); | |
9c02f1a2 | 1786 | #endif |
8ecc7913 JM |
1787 | } |
1788 | ||
e2684c0b | 1789 | CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, |
52ce55a1 | 1790 | MemoryRegion ram_memories[2], |
a8170e5e AK |
1791 | hwaddr ram_bases[2], |
1792 | hwaddr ram_sizes[2], | |
52ce55a1 RH |
1793 | uint32_t sysclk, qemu_irq **picp, |
1794 | int do_init) | |
8ecc7913 | 1795 | { |
c227f099 | 1796 | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
9c02f1a2 | 1797 | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2f9859fb | 1798 | PowerPCCPU *cpu; |
e2684c0b | 1799 | CPUPPCState *env; |
8ecc7913 | 1800 | qemu_irq *pic, *irqs; |
8ecc7913 JM |
1801 | |
1802 | memset(clk_setup, 0, sizeof(clk_setup)); | |
1803 | /* init CPUs */ | |
9391b8c5 IM |
1804 | cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), |
1805 | &clk_setup[PPC405EP_CPU_CLK], | |
9c02f1a2 | 1806 | &tlb_clk_setup, sysclk); |
2f9859fb | 1807 | env = &cpu->env; |
9c02f1a2 JM |
1808 | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
1809 | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; | |
8ecc7913 JM |
1810 | /* Internal devices init */ |
1811 | /* Memory mapped devices registers */ | |
8ecc7913 JM |
1812 | /* PLB arbitrer */ |
1813 | ppc4xx_plb_init(env); | |
1814 | /* PLB to OPB bridge */ | |
1815 | ppc4xx_pob_init(env); | |
1816 | /* OBP arbitrer */ | |
802670e6 | 1817 | ppc4xx_opba_init(0xef600600); |
d715ea96 | 1818 | /* Initialize timers */ |
a34a92b9 | 1819 | ppc_booke_timers_init(cpu, sysclk, 0); |
8ecc7913 | 1820 | /* Universal interrupt controller */ |
c4f46986 | 1821 | irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); |
8ecc7913 | 1822 | irqs[PPCUIC_OUTPUT_INT] = |
b48d7d69 | 1823 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
8ecc7913 | 1824 | irqs[PPCUIC_OUTPUT_CINT] = |
b48d7d69 | 1825 | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
8ecc7913 JM |
1826 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
1827 | *picp = pic; | |
1828 | /* SDRAM controller */ | |
7d37435b | 1829 | /* XXX 405EP has no ECC interrupt */ |
b6dcbe08 AK |
1830 | ppc4xx_sdram_init(env, pic[17], 2, ram_memories, |
1831 | ram_bases, ram_sizes, do_init); | |
8ecc7913 JM |
1832 | /* External bus controller */ |
1833 | ppc405_ebc_init(env); | |
1834 | /* DMA controller */ | |
923e5e33 AJ |
1835 | dma_irqs[0] = pic[5]; |
1836 | dma_irqs[1] = pic[6]; | |
1837 | dma_irqs[2] = pic[7]; | |
1838 | dma_irqs[3] = pic[8]; | |
8ecc7913 JM |
1839 | ppc405_dma_init(env, dma_irqs); |
1840 | /* IIC controller */ | |
3b09bb0f | 1841 | sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); |
8ecc7913 | 1842 | /* GPIO */ |
802670e6 | 1843 | ppc405_gpio_init(0xef600700); |
8ecc7913 | 1844 | /* Serial ports */ |
9bca0edb | 1845 | if (serial_hd(0) != NULL) { |
52ce55a1 | 1846 | serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], |
9bca0edb | 1847 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
39186d8a | 1848 | DEVICE_BIG_ENDIAN); |
8ecc7913 | 1849 | } |
9bca0edb | 1850 | if (serial_hd(1) != NULL) { |
52ce55a1 | 1851 | serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], |
9bca0edb | 1852 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
39186d8a | 1853 | DEVICE_BIG_ENDIAN); |
8ecc7913 JM |
1854 | } |
1855 | /* OCM */ | |
5c130f65 | 1856 | ppc405_ocm_init(env); |
9c02f1a2 | 1857 | /* GPT */ |
923e5e33 AJ |
1858 | gpt_irqs[0] = pic[19]; |
1859 | gpt_irqs[1] = pic[20]; | |
1860 | gpt_irqs[2] = pic[21]; | |
1861 | gpt_irqs[3] = pic[22]; | |
1862 | gpt_irqs[4] = pic[23]; | |
802670e6 | 1863 | ppc4xx_gpt_init(0xef600000, gpt_irqs); |
8ecc7913 | 1864 | /* PCI */ |
923e5e33 | 1865 | /* Uses pic[3], pic[16], pic[18] */ |
9c02f1a2 | 1866 | /* MAL */ |
923e5e33 AJ |
1867 | mal_irqs[0] = pic[11]; |
1868 | mal_irqs[1] = pic[12]; | |
1869 | mal_irqs[2] = pic[13]; | |
1870 | mal_irqs[3] = pic[14]; | |
04534280 | 1871 | ppc4xx_mal_init(env, 4, 2, mal_irqs); |
9c02f1a2 | 1872 | /* Ethernet */ |
923e5e33 | 1873 | /* Uses pic[9], pic[15], pic[17] */ |
8ecc7913 JM |
1874 | /* CPU control */ |
1875 | ppc405ep_cpc_init(env, clk_setup, sysclk); | |
8ecc7913 JM |
1876 | |
1877 | return env; | |
1878 | } |