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include/qemu/osdep.h: Don't include qapi/error.h
[mirror_qemu.git] / hw / ppc / ppc405_uc.c
CommitLineData
8ecc7913
JM		 1/*
2 * QEMU PowerPC 405 embedded processors emulation
5fafdf24 3 *
8ecc7913 4 * Copyright (c) 2007 Jocelyn Mayer
5fafdf24 5 *
8ecc7913
JM		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
0d75590d 24#include "qemu/osdep.h"
da34e65c 25#include "qapi/error.h"
83c9f4ca 26#include "hw/hw.h"
0d09e41a 27#include "hw/ppc/ppc.h"
e938ba0c 28#include "hw/boards.h"
47b43a1f 29#include "ppc405.h"
0d09e41a 30#include "hw/char/serial.h"
1de7afc9 31#include "qemu/timer.h"
9c17d615 32#include "sysemu/sysemu.h"
1de7afc9 33#include "qemu/log.h"
022c62cb 34#include "exec/address-spaces.h"
8ecc7913 35
0d84382e
AF		 36//#define DEBUG_OPBA
37//#define DEBUG_SDRAM
38//#define DEBUG_GPIO
39//#define DEBUG_SERIAL
40//#define DEBUG_OCM
9c02f1a2 41//#define DEBUG_I2C
0d84382e
AF		 42//#define DEBUG_GPT
43//#define DEBUG_MAL
44//#define DEBUG_CLOCKS
aae9366a 45//#define DEBUG_CLOCKS_LL
8ecc7913 46
e2684c0b 47ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
b8d3f5d1 48 uint32_t flags)
04f20795 49{
33276f1b 50 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 51 ram_addr_t bdloc;
04f20795
JM		 52 int i, n;
53
54 /* We put the bd structure at the top of memory */
be58fc7c 55 if (bd->bi_memsize >= 0x01000000UL)
c227f099 56 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
be58fc7c 57 else
c227f099 58 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
ab1da857
EI		 59 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
60 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
61 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
62 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
63 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
64 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
65 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
66 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
67 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
db663d0f 68 for (i = 0; i < 6; i++) {
db3be60d 69 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
db663d0f 70 }
5ce5944d 71 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
ab1da857
EI		 72 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
73 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
74 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
db663d0f 75 for (i = 0; i < 4; i++) {
db3be60d 76 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
db663d0f 77 }
4508d81a 78 for (i = 0; i < 32; i++) {
db3be60d 79 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
4508d81a 80 }
ab1da857
EI		 81 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
82 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
db663d0f 83 for (i = 0; i < 6; i++) {
db3be60d 84 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
db663d0f 85 }
04f20795 86 n = 0x6A;
b8d3f5d1 87 if (flags & 0x00000001) {
04f20795 88 for (i = 0; i < 6; i++)
db3be60d 89 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
04f20795 90 }
ab1da857 91 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
04f20795
JM		 92 n += 4;
93 for (i = 0; i < 2; i++) {
ab1da857 94 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
04f20795
JM		 95 n += 4;
96 }
97
98 return bdloc;
99}
100
8ecc7913
JM		 101/*****************************************************************************/
102/* Shared peripherals */
103
8ecc7913
JM		 104/*****************************************************************************/
105/* Peripheral local bus arbitrer */
106enum {
107 PLB0_BESR = 0x084,
108 PLB0_BEAR = 0x086,
109 PLB0_ACR = 0x087,
110};
111
c227f099
AL		 112typedef struct ppc4xx_plb_t ppc4xx_plb_t;
113struct ppc4xx_plb_t {
8ecc7913
JM		 114 uint32_t acr;
115 uint32_t bear;
116 uint32_t besr;
117};
118
73b01960 119static uint32_t dcr_read_plb (void *opaque, int dcrn)
8ecc7913 120{
c227f099 121 ppc4xx_plb_t *plb;
73b01960 122 uint32_t ret;
8ecc7913
JM		 123
124 plb = opaque;
125 switch (dcrn) {
126 case PLB0_ACR:
127 ret = plb->acr;
128 break;
129 case PLB0_BEAR:
130 ret = plb->bear;
131 break;
132 case PLB0_BESR:
133 ret = plb->besr;
134 break;
135 default:
136 /* Avoid gcc warning */
137 ret = 0;
138 break;
139 }
140
141 return ret;
142}
143
73b01960 144static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
8ecc7913 145{
c227f099 146 ppc4xx_plb_t *plb;
8ecc7913
JM		 147
148 plb = opaque;
149 switch (dcrn) {
150 case PLB0_ACR:
9c02f1a2
JM		 151 /* We don't care about the actual parameters written as
152 * we don't manage any priorities on the bus
153 */
154 plb->acr = val & 0xF8000000;
8ecc7913
JM		 155 break;
156 case PLB0_BEAR:
157 /* Read only */
158 break;
159 case PLB0_BESR:
160 /* Write-clear */
161 plb->besr &= ~val;
162 break;
163 }
164}
165
166static void ppc4xx_plb_reset (void *opaque)
167{
c227f099 168 ppc4xx_plb_t *plb;
8ecc7913
JM		 169
170 plb = opaque;
171 plb->acr = 0x00000000;
172 plb->bear = 0x00000000;
173 plb->besr = 0x00000000;
174}
175
e2684c0b 176static void ppc4xx_plb_init(CPUPPCState *env)
8ecc7913 177{
c227f099 178 ppc4xx_plb_t *plb;
8ecc7913 179
7267c094 180 plb = g_malloc0(sizeof(ppc4xx_plb_t));
487414f1
AL		 181 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
182 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
183 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
a08d4367 184 qemu_register_reset(ppc4xx_plb_reset, plb);
8ecc7913
JM		 185}
186
187/*****************************************************************************/
188/* PLB to OPB bridge */
189enum {
190 POB0_BESR0 = 0x0A0,
191 POB0_BESR1 = 0x0A2,
192 POB0_BEAR = 0x0A4,
193};
194
c227f099
AL		 195typedef struct ppc4xx_pob_t ppc4xx_pob_t;
196struct ppc4xx_pob_t {
8ecc7913 197 uint32_t bear;
5a1972c8
SW		 198 uint32_t besr0;
199 uint32_t besr1;
8ecc7913
JM		 200};
201
73b01960 202static uint32_t dcr_read_pob (void *opaque, int dcrn)
8ecc7913 203{
c227f099 204 ppc4xx_pob_t *pob;
73b01960 205 uint32_t ret;
8ecc7913
JM		 206
207 pob = opaque;
208 switch (dcrn) {
209 case POB0_BEAR:
210 ret = pob->bear;
211 break;
212 case POB0_BESR0:
5a1972c8
SW		 213 ret = pob->besr0;
214 break;
8ecc7913 215 case POB0_BESR1:
5a1972c8 216 ret = pob->besr1;
8ecc7913
JM		 217 break;
218 default:
219 /* Avoid gcc warning */
220 ret = 0;
221 break;
222 }
223
224 return ret;
225}
226
73b01960 227static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
8ecc7913 228{
c227f099 229 ppc4xx_pob_t *pob;
8ecc7913
JM		 230
231 pob = opaque;
232 switch (dcrn) {
233 case POB0_BEAR:
234 /* Read only */
235 break;
236 case POB0_BESR0:
5a1972c8
SW		 237 /* Write-clear */
238 pob->besr0 &= ~val;
239 break;
8ecc7913
JM		 240 case POB0_BESR1:
241 /* Write-clear */
5a1972c8 242 pob->besr1 &= ~val;
8ecc7913
JM		 243 break;
244 }
245}
246
247static void ppc4xx_pob_reset (void *opaque)
248{
c227f099 249 ppc4xx_pob_t *pob;
8ecc7913
JM		 250
251 pob = opaque;
252 /* No error */
253 pob->bear = 0x00000000;
5a1972c8
SW		 254 pob->besr0 = 0x0000000;
255 pob->besr1 = 0x0000000;
8ecc7913
JM		 256}
257
e2684c0b 258static void ppc4xx_pob_init(CPUPPCState *env)
8ecc7913 259{
c227f099 260 ppc4xx_pob_t *pob;
8ecc7913 261
7267c094 262 pob = g_malloc0(sizeof(ppc4xx_pob_t));
487414f1
AL		 263 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
264 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
265 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
a08d4367 266 qemu_register_reset(ppc4xx_pob_reset, pob);
8ecc7913
JM		 267}
268
269/*****************************************************************************/
270/* OPB arbitrer */
c227f099
AL		 271typedef struct ppc4xx_opba_t ppc4xx_opba_t;
272struct ppc4xx_opba_t {
9074e0e3 273 MemoryRegion io;
8ecc7913
JM		 274 uint8_t cr;
275 uint8_t pr;
276};
277
a8170e5e 278static uint32_t opba_readb (void *opaque, hwaddr addr)
8ecc7913 279{
c227f099 280 ppc4xx_opba_t *opba;
8ecc7913
JM		 281 uint32_t ret;
282
283#ifdef DEBUG_OPBA
90e189ec 284 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 285#endif
286 opba = opaque;
802670e6 287 switch (addr) {
8ecc7913
JM		 288 case 0x00:
289 ret = opba->cr;
290 break;
291 case 0x01:
292 ret = opba->pr;
293 break;
294 default:
295 ret = 0x00;
296 break;
297 }
298
299 return ret;
300}
301
302static void opba_writeb (void *opaque,
a8170e5e 303 hwaddr addr, uint32_t value)
8ecc7913 304{
c227f099 305 ppc4xx_opba_t *opba;
8ecc7913
JM		 306
307#ifdef DEBUG_OPBA
90e189ec
BS		 308 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
309 value);
8ecc7913
JM		 310#endif
311 opba = opaque;
802670e6 312 switch (addr) {
8ecc7913
JM		 313 case 0x00:
314 opba->cr = value & 0xF8;
315 break;
316 case 0x01:
317 opba->pr = value & 0xFF;
318 break;
319 default:
320 break;
321 }
322}
323
a8170e5e 324static uint32_t opba_readw (void *opaque, hwaddr addr)
8ecc7913
JM		 325{
326 uint32_t ret;
327
328#ifdef DEBUG_OPBA
90e189ec 329 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 330#endif
331 ret = opba_readb(opaque, addr) << 8;
332 ret |= opba_readb(opaque, addr + 1);
333
334 return ret;
335}
336
337static void opba_writew (void *opaque,
a8170e5e 338 hwaddr addr, uint32_t value)
8ecc7913
JM		 339{
340#ifdef DEBUG_OPBA
90e189ec
BS		 341 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
342 value);
8ecc7913
JM		 343#endif
344 opba_writeb(opaque, addr, value >> 8);
345 opba_writeb(opaque, addr + 1, value);
346}
347
a8170e5e 348static uint32_t opba_readl (void *opaque, hwaddr addr)
8ecc7913
JM		 349{
350 uint32_t ret;
351
352#ifdef DEBUG_OPBA
90e189ec 353 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 354#endif
355 ret = opba_readb(opaque, addr) << 24;
356 ret |= opba_readb(opaque, addr + 1) << 16;
357
358 return ret;
359}
360
361static void opba_writel (void *opaque,
a8170e5e 362 hwaddr addr, uint32_t value)
8ecc7913
JM		 363{
364#ifdef DEBUG_OPBA
90e189ec
BS		 365 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
366 value);
8ecc7913
JM		 367#endif
368 opba_writeb(opaque, addr, value >> 24);
369 opba_writeb(opaque, addr + 1, value >> 16);
370}
371
9074e0e3
AK		 372static const MemoryRegionOps opba_ops = {
373 .old_mmio = {
374 .read = { opba_readb, opba_readw, opba_readl, },
375 .write = { opba_writeb, opba_writew, opba_writel, },
376 },
377 .endianness = DEVICE_NATIVE_ENDIAN,
8ecc7913
JM		 378};
379
380static void ppc4xx_opba_reset (void *opaque)
381{
c227f099 382 ppc4xx_opba_t *opba;
8ecc7913
JM		 383
384 opba = opaque;
385 opba->cr = 0x00; /* No dynamic priorities - park disabled */
386 opba->pr = 0x11;
387}
388
a8170e5e 389static void ppc4xx_opba_init(hwaddr base)
8ecc7913 390{
c227f099 391 ppc4xx_opba_t *opba;
8ecc7913 392
7267c094 393 opba = g_malloc0(sizeof(ppc4xx_opba_t));
8ecc7913 394#ifdef DEBUG_OPBA
90e189ec 395 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
8ecc7913 396#endif
2c9b15ca 397 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
9074e0e3 398 memory_region_add_subregion(get_system_memory(), base, &opba->io);
802670e6 399 qemu_register_reset(ppc4xx_opba_reset, opba);
8ecc7913
JM		 400}
401
8ecc7913
JM		 402/*****************************************************************************/
403/* Code decompression controller */
404/* XXX: TODO */
405
8ecc7913
JM		 406/*****************************************************************************/
407/* Peripheral controller */
c227f099
AL		 408typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
409struct ppc4xx_ebc_t {
8ecc7913
JM		 410 uint32_t addr;
411 uint32_t bcr[8];
412 uint32_t bap[8];
413 uint32_t bear;
414 uint32_t besr0;
415 uint32_t besr1;
416 uint32_t cfg;
417};
418
419enum {
420 EBC0_CFGADDR = 0x012,
421 EBC0_CFGDATA = 0x013,
422};
423
73b01960 424static uint32_t dcr_read_ebc (void *opaque, int dcrn)
8ecc7913 425{
c227f099 426 ppc4xx_ebc_t *ebc;
73b01960 427 uint32_t ret;
8ecc7913
JM		 428
429 ebc = opaque;
430 switch (dcrn) {
431 case EBC0_CFGADDR:
432 ret = ebc->addr;
433 break;
434 case EBC0_CFGDATA:
435 switch (ebc->addr) {
436 case 0x00: /* B0CR */
437 ret = ebc->bcr[0];
438 break;
439 case 0x01: /* B1CR */
440 ret = ebc->bcr[1];
441 break;
442 case 0x02: /* B2CR */
443 ret = ebc->bcr[2];
444 break;
445 case 0x03: /* B3CR */
446 ret = ebc->bcr[3];
447 break;
448 case 0x04: /* B4CR */
449 ret = ebc->bcr[4];
450 break;
451 case 0x05: /* B5CR */
452 ret = ebc->bcr[5];
453 break;
454 case 0x06: /* B6CR */
455 ret = ebc->bcr[6];
456 break;
457 case 0x07: /* B7CR */
458 ret = ebc->bcr[7];
459 break;
460 case 0x10: /* B0AP */
461 ret = ebc->bap[0];
462 break;
463 case 0x11: /* B1AP */
464 ret = ebc->bap[1];
465 break;
466 case 0x12: /* B2AP */
467 ret = ebc->bap[2];
468 break;
469 case 0x13: /* B3AP */
470 ret = ebc->bap[3];
471 break;
472 case 0x14: /* B4AP */
473 ret = ebc->bap[4];
474 break;
475 case 0x15: /* B5AP */
476 ret = ebc->bap[5];
477 break;
478 case 0x16: /* B6AP */
479 ret = ebc->bap[6];
480 break;
481 case 0x17: /* B7AP */
482 ret = ebc->bap[7];
483 break;
484 case 0x20: /* BEAR */
485 ret = ebc->bear;
486 break;
487 case 0x21: /* BESR0 */
488 ret = ebc->besr0;
489 break;
490 case 0x22: /* BESR1 */
491 ret = ebc->besr1;
492 break;
493 case 0x23: /* CFG */
494 ret = ebc->cfg;
495 break;
496 default:
497 ret = 0x00000000;
498 break;
499 }
9fad3eb7 500 break;
8ecc7913
JM		 501 default:
502 ret = 0x00000000;
503 break;
504 }
505
506 return ret;
507}
508
73b01960 509static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
8ecc7913 510{
c227f099 511 ppc4xx_ebc_t *ebc;
8ecc7913
JM		 512
513 ebc = opaque;
514 switch (dcrn) {
515 case EBC0_CFGADDR:
516 ebc->addr = val;
517 break;
518 case EBC0_CFGDATA:
519 switch (ebc->addr) {
520 case 0x00: /* B0CR */
521 break;
522 case 0x01: /* B1CR */
523 break;
524 case 0x02: /* B2CR */
525 break;
526 case 0x03: /* B3CR */
527 break;
528 case 0x04: /* B4CR */
529 break;
530 case 0x05: /* B5CR */
531 break;
532 case 0x06: /* B6CR */
533 break;
534 case 0x07: /* B7CR */
535 break;
536 case 0x10: /* B0AP */
537 break;
538 case 0x11: /* B1AP */
539 break;
540 case 0x12: /* B2AP */
541 break;
542 case 0x13: /* B3AP */
543 break;
544 case 0x14: /* B4AP */
545 break;
546 case 0x15: /* B5AP */
547 break;
548 case 0x16: /* B6AP */
549 break;
550 case 0x17: /* B7AP */
551 break;
552 case 0x20: /* BEAR */
553 break;
554 case 0x21: /* BESR0 */
555 break;
556 case 0x22: /* BESR1 */
557 break;
558 case 0x23: /* CFG */
559 break;
560 default:
561 break;
562 }
563 break;
564 default:
565 break;
566 }
567}
568
569static void ebc_reset (void *opaque)
570{
c227f099 571 ppc4xx_ebc_t *ebc;
8ecc7913
JM		 572 int i;
573
574 ebc = opaque;
575 ebc->addr = 0x00000000;
576 ebc->bap[0] = 0x7F8FFE80;
577 ebc->bcr[0] = 0xFFE28000;
578 for (i = 0; i < 8; i++) {
579 ebc->bap[i] = 0x00000000;
580 ebc->bcr[i] = 0x00000000;
581 }
582 ebc->besr0 = 0x00000000;
583 ebc->besr1 = 0x00000000;
9c02f1a2 584 ebc->cfg = 0x80400000;
8ecc7913
JM		 585}
586
e2684c0b 587static void ppc405_ebc_init(CPUPPCState *env)
8ecc7913 588{
c227f099 589 ppc4xx_ebc_t *ebc;
8ecc7913 590
7267c094 591 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
a08d4367 592 qemu_register_reset(&ebc_reset, ebc);
487414f1
AL		 593 ppc_dcr_register(env, EBC0_CFGADDR,
594 ebc, &dcr_read_ebc, &dcr_write_ebc);
595 ppc_dcr_register(env, EBC0_CFGDATA,
596 ebc, &dcr_read_ebc, &dcr_write_ebc);
8ecc7913
JM		 597}
598
599/*****************************************************************************/
600/* DMA controller */
601enum {
602 DMA0_CR0 = 0x100,
603 DMA0_CT0 = 0x101,
604 DMA0_DA0 = 0x102,
605 DMA0_SA0 = 0x103,
606 DMA0_SG0 = 0x104,
607 DMA0_CR1 = 0x108,
608 DMA0_CT1 = 0x109,
609 DMA0_DA1 = 0x10A,
610 DMA0_SA1 = 0x10B,
611 DMA0_SG1 = 0x10C,
612 DMA0_CR2 = 0x110,
613 DMA0_CT2 = 0x111,
614 DMA0_DA2 = 0x112,
615 DMA0_SA2 = 0x113,
616 DMA0_SG2 = 0x114,
617 DMA0_CR3 = 0x118,
618 DMA0_CT3 = 0x119,
619 DMA0_DA3 = 0x11A,
620 DMA0_SA3 = 0x11B,
621 DMA0_SG3 = 0x11C,
622 DMA0_SR = 0x120,
623 DMA0_SGC = 0x123,
624 DMA0_SLP = 0x125,
625 DMA0_POL = 0x126,
626};
627
c227f099
AL		 628typedef struct ppc405_dma_t ppc405_dma_t;
629struct ppc405_dma_t {
8ecc7913
JM		 630 qemu_irq irqs[4];
631 uint32_t cr[4];
632 uint32_t ct[4];
633 uint32_t da[4];
634 uint32_t sa[4];
635 uint32_t sg[4];
636 uint32_t sr;
637 uint32_t sgc;
638 uint32_t slp;
639 uint32_t pol;
640};
641
73b01960 642static uint32_t dcr_read_dma (void *opaque, int dcrn)
8ecc7913 643{
8ecc7913
JM		 644 return 0;
645}
646
73b01960 647static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
8ecc7913 648{
8ecc7913
JM		 649}
650
651static void ppc405_dma_reset (void *opaque)
652{
c227f099 653 ppc405_dma_t *dma;
8ecc7913
JM		 654 int i;
655
656 dma = opaque;
657 for (i = 0; i < 4; i++) {
658 dma->cr[i] = 0x00000000;
659 dma->ct[i] = 0x00000000;
660 dma->da[i] = 0x00000000;
661 dma->sa[i] = 0x00000000;
662 dma->sg[i] = 0x00000000;
663 }
664 dma->sr = 0x00000000;
665 dma->sgc = 0x00000000;
666 dma->slp = 0x7C000000;
667 dma->pol = 0x00000000;
668}
669
e2684c0b 670static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
8ecc7913 671{
c227f099 672 ppc405_dma_t *dma;
8ecc7913 673
7267c094 674 dma = g_malloc0(sizeof(ppc405_dma_t));
487414f1 675 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
a08d4367 676 qemu_register_reset(&ppc405_dma_reset, dma);
487414f1
AL		 677 ppc_dcr_register(env, DMA0_CR0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_CT0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_DA0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SA0,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SG0,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CR1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_CT1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_DA1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SA1,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_SG1,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CR2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_CT2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_DA2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SA2,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_SG2,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_CR3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_CT3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_DA3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SA3,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SG3,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SR,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_SGC,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 ppc_dcr_register(env, DMA0_SLP,
722 dma, &dcr_read_dma, &dcr_write_dma);
723 ppc_dcr_register(env, DMA0_POL,
724 dma, &dcr_read_dma, &dcr_write_dma);
8ecc7913
JM		 725}
726
727/*****************************************************************************/
728/* GPIO */
c227f099
AL		 729typedef struct ppc405_gpio_t ppc405_gpio_t;
730struct ppc405_gpio_t {
9074e0e3 731 MemoryRegion io;
8ecc7913
JM		 732 uint32_t or;
733 uint32_t tcr;
734 uint32_t osrh;
735 uint32_t osrl;
736 uint32_t tsrh;
737 uint32_t tsrl;
738 uint32_t odr;
739 uint32_t ir;
740 uint32_t rr1;
741 uint32_t isr1h;
742 uint32_t isr1l;
743};
744
a8170e5e 745static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
8ecc7913 746{
8ecc7913 747#ifdef DEBUG_GPIO
90e189ec 748 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 749#endif
750
751 return 0;
752}
753
754static void ppc405_gpio_writeb (void *opaque,
a8170e5e 755 hwaddr addr, uint32_t value)
8ecc7913 756{
8ecc7913 757#ifdef DEBUG_GPIO
90e189ec
BS		 758 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
759 value);
8ecc7913
JM		 760#endif
761}
762
a8170e5e 763static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
8ecc7913 764{
8ecc7913 765#ifdef DEBUG_GPIO
90e189ec 766 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 767#endif
768
769 return 0;
770}
771
772static void ppc405_gpio_writew (void *opaque,
a8170e5e 773 hwaddr addr, uint32_t value)
8ecc7913 774{
8ecc7913 775#ifdef DEBUG_GPIO
90e189ec
BS		 776 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
777 value);
8ecc7913
JM		 778#endif
779}
780
a8170e5e 781static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
8ecc7913 782{
8ecc7913 783#ifdef DEBUG_GPIO
90e189ec 784 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 785#endif
786
787 return 0;
788}
789
790static void ppc405_gpio_writel (void *opaque,
a8170e5e 791 hwaddr addr, uint32_t value)
8ecc7913 792{
8ecc7913 793#ifdef DEBUG_GPIO
90e189ec
BS		 794 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
795 value);
8ecc7913
JM		 796#endif
797}
798
9074e0e3
AK		 799static const MemoryRegionOps ppc405_gpio_ops = {
800 .old_mmio = {
801 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
802 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
803 },
804 .endianness = DEVICE_NATIVE_ENDIAN,
8ecc7913
JM		 805};
806
807static void ppc405_gpio_reset (void *opaque)
808{
8ecc7913
JM		 809}
810
a8170e5e 811static void ppc405_gpio_init(hwaddr base)
8ecc7913 812{
c227f099 813 ppc405_gpio_t *gpio;
8ecc7913 814
7267c094 815 gpio = g_malloc0(sizeof(ppc405_gpio_t));
8ecc7913 816#ifdef DEBUG_GPIO
90e189ec 817 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
8ecc7913 818#endif
2c9b15ca 819 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
9074e0e3 820 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
802670e6 821 qemu_register_reset(&ppc405_gpio_reset, gpio);
8ecc7913
JM		 822}
823
824/*****************************************************************************/
825/* On Chip Memory */
826enum {
827 OCM0_ISARC = 0x018,
828 OCM0_ISACNTL = 0x019,
829 OCM0_DSARC = 0x01A,
830 OCM0_DSACNTL = 0x01B,
831};
832
c227f099
AL		 833typedef struct ppc405_ocm_t ppc405_ocm_t;
834struct ppc405_ocm_t {
9074e0e3
AK		 835 MemoryRegion ram;
836 MemoryRegion isarc_ram;
837 MemoryRegion dsarc_ram;
8ecc7913
JM		 838 uint32_t isarc;
839 uint32_t isacntl;
840 uint32_t dsarc;
841 uint32_t dsacntl;
842};
843
c227f099 844static void ocm_update_mappings (ppc405_ocm_t *ocm,
8ecc7913
JM		 845 uint32_t isarc, uint32_t isacntl,
846 uint32_t dsarc, uint32_t dsacntl)
847{
848#ifdef DEBUG_OCM
aae9366a
JM		 849 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
850 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
851 " (%08" PRIx32 " %08" PRIx32 ")\n",
8ecc7913
JM		 852 isarc, isacntl, dsarc, dsacntl,
853 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
854#endif
855 if (ocm->isarc != isarc ||
856 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
857 if (ocm->isacntl & 0x80000000) {
858 /* Unmap previously assigned memory region */
aae9366a 859 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
9074e0e3 860 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
8ecc7913
JM		 861 }
862 if (isacntl & 0x80000000) {
863 /* Map new instruction memory region */
864#ifdef DEBUG_OCM
aae9366a 865 printf("OCM map ISA %08" PRIx32 "\n", isarc);
8ecc7913 866#endif
9074e0e3
AK		 867 memory_region_add_subregion(get_system_memory(), isarc,
868 &ocm->isarc_ram);
8ecc7913
JM		 869 }
870 }
871 if (ocm->dsarc != dsarc ||
872 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
873 if (ocm->dsacntl & 0x80000000) {
874 /* Beware not to unmap the region we just mapped */
875 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
876 /* Unmap previously assigned memory region */
877#ifdef DEBUG_OCM
aae9366a 878 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
8ecc7913 879#endif
9074e0e3
AK		 880 memory_region_del_subregion(get_system_memory(),
881 &ocm->dsarc_ram);
8ecc7913
JM		 882 }
883 }
884 if (dsacntl & 0x80000000) {
885 /* Beware not to remap the region we just mapped */
886 if (!(isacntl & 0x80000000) || dsarc != isarc) {
887 /* Map new data memory region */
888#ifdef DEBUG_OCM
aae9366a 889 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
8ecc7913 890#endif
9074e0e3
AK		 891 memory_region_add_subregion(get_system_memory(), dsarc,
892 &ocm->dsarc_ram);
8ecc7913
JM		 893 }
894 }
895 }
896}
897
73b01960 898static uint32_t dcr_read_ocm (void *opaque, int dcrn)
8ecc7913 899{
c227f099 900 ppc405_ocm_t *ocm;
73b01960 901 uint32_t ret;
8ecc7913
JM		 902
903 ocm = opaque;
904 switch (dcrn) {
905 case OCM0_ISARC:
906 ret = ocm->isarc;
907 break;
908 case OCM0_ISACNTL:
909 ret = ocm->isacntl;
910 break;
911 case OCM0_DSARC:
912 ret = ocm->dsarc;
913 break;
914 case OCM0_DSACNTL:
915 ret = ocm->dsacntl;
916 break;
917 default:
918 ret = 0;
919 break;
920 }
921
922 return ret;
923}
924
73b01960 925static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
8ecc7913 926{
c227f099 927 ppc405_ocm_t *ocm;
8ecc7913
JM		 928 uint32_t isarc, dsarc, isacntl, dsacntl;
929
930 ocm = opaque;
931 isarc = ocm->isarc;
932 dsarc = ocm->dsarc;
933 isacntl = ocm->isacntl;
934 dsacntl = ocm->dsacntl;
935 switch (dcrn) {
936 case OCM0_ISARC:
937 isarc = val & 0xFC000000;
938 break;
939 case OCM0_ISACNTL:
940 isacntl = val & 0xC0000000;
941 break;
942 case OCM0_DSARC:
943 isarc = val & 0xFC000000;
944 break;
945 case OCM0_DSACNTL:
946 isacntl = val & 0xC0000000;
947 break;
948 }
949 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
950 ocm->isarc = isarc;
951 ocm->dsarc = dsarc;
952 ocm->isacntl = isacntl;
953 ocm->dsacntl = dsacntl;
954}
955
956static void ocm_reset (void *opaque)
957{
c227f099 958 ppc405_ocm_t *ocm;
8ecc7913
JM		 959 uint32_t isarc, dsarc, isacntl, dsacntl;
960
961 ocm = opaque;
962 isarc = 0x00000000;
963 isacntl = 0x00000000;
964 dsarc = 0x00000000;
965 dsacntl = 0x00000000;
966 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
967 ocm->isarc = isarc;
968 ocm->dsarc = dsarc;
969 ocm->isacntl = isacntl;
970 ocm->dsacntl = dsacntl;
971}
972
e2684c0b 973static void ppc405_ocm_init(CPUPPCState *env)
8ecc7913 974{
c227f099 975 ppc405_ocm_t *ocm;
8ecc7913 976
7267c094 977 ocm = g_malloc0(sizeof(ppc405_ocm_t));
9074e0e3 978 /* XXX: Size is 4096 or 0x04000000 */
49946538 979 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
f8ed85ac 980 &error_fatal);
e206ad48 981 vmstate_register_ram_global(&ocm->isarc_ram);
2c9b15ca 982 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
9074e0e3 983 0, 4096);
a08d4367 984 qemu_register_reset(&ocm_reset, ocm);
487414f1
AL		 985 ppc_dcr_register(env, OCM0_ISARC,
986 ocm, &dcr_read_ocm, &dcr_write_ocm);
987 ppc_dcr_register(env, OCM0_ISACNTL,
988 ocm, &dcr_read_ocm, &dcr_write_ocm);
989 ppc_dcr_register(env, OCM0_DSARC,
990 ocm, &dcr_read_ocm, &dcr_write_ocm);
991 ppc_dcr_register(env, OCM0_DSACNTL,
992 ocm, &dcr_read_ocm, &dcr_write_ocm);
8ecc7913
JM		 993}
994
995/*****************************************************************************/
996/* I2C controller */
c227f099
AL		 997typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
998struct ppc4xx_i2c_t {
9c02f1a2 999 qemu_irq irq;
9074e0e3 1000 MemoryRegion iomem;
8ecc7913
JM		 1001 uint8_t mdata;
1002 uint8_t lmadr;
1003 uint8_t hmadr;
1004 uint8_t cntl;
1005 uint8_t mdcntl;
1006 uint8_t sts;
1007 uint8_t extsts;
1008 uint8_t sdata;
1009 uint8_t lsadr;
1010 uint8_t hsadr;
1011 uint8_t clkdiv;
1012 uint8_t intrmsk;
1013 uint8_t xfrcnt;
1014 uint8_t xtcntlss;
1015 uint8_t directcntl;
1016};
1017
a8170e5e 1018static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
8ecc7913 1019{
c227f099 1020 ppc4xx_i2c_t *i2c;
8ecc7913
JM		 1021 uint32_t ret;
1022
1023#ifdef DEBUG_I2C
90e189ec 1024 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 1025#endif
1026 i2c = opaque;
802670e6 1027 switch (addr) {
8ecc7913
JM		 1028 case 0x00:
1029 // i2c_readbyte(&i2c->mdata);
1030 ret = i2c->mdata;
1031 break;
1032 case 0x02:
1033 ret = i2c->sdata;
1034 break;
1035 case 0x04:
1036 ret = i2c->lmadr;
1037 break;
1038 case 0x05:
1039 ret = i2c->hmadr;
1040 break;
1041 case 0x06:
1042 ret = i2c->cntl;
1043 break;
1044 case 0x07:
1045 ret = i2c->mdcntl;
1046 break;
1047 case 0x08:
1048 ret = i2c->sts;
1049 break;
1050 case 0x09:
1051 ret = i2c->extsts;
1052 break;
1053 case 0x0A:
1054 ret = i2c->lsadr;
1055 break;
1056 case 0x0B:
1057 ret = i2c->hsadr;
1058 break;
1059 case 0x0C:
1060 ret = i2c->clkdiv;
1061 break;
1062 case 0x0D:
1063 ret = i2c->intrmsk;
1064 break;
1065 case 0x0E:
1066 ret = i2c->xfrcnt;
1067 break;
1068 case 0x0F:
1069 ret = i2c->xtcntlss;
1070 break;
1071 case 0x10:
1072 ret = i2c->directcntl;
1073 break;
1074 default:
1075 ret = 0x00;
1076 break;
1077 }
1078#ifdef DEBUG_I2C
90e189ec 1079 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
8ecc7913
JM		 1080#endif
1081
1082 return ret;
1083}
1084
1085static void ppc4xx_i2c_writeb (void *opaque,
a8170e5e 1086 hwaddr addr, uint32_t value)
8ecc7913 1087{
c227f099 1088 ppc4xx_i2c_t *i2c;
8ecc7913
JM		 1089
1090#ifdef DEBUG_I2C
90e189ec
BS		 1091 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1092 value);
8ecc7913
JM		 1093#endif
1094 i2c = opaque;
802670e6 1095 switch (addr) {
8ecc7913
JM		 1096 case 0x00:
1097 i2c->mdata = value;
1098 // i2c_sendbyte(&i2c->mdata);
1099 break;
1100 case 0x02:
1101 i2c->sdata = value;
1102 break;
1103 case 0x04:
1104 i2c->lmadr = value;
1105 break;
1106 case 0x05:
1107 i2c->hmadr = value;
1108 break;
1109 case 0x06:
1110 i2c->cntl = value;
1111 break;
1112 case 0x07:
1113 i2c->mdcntl = value & 0xDF;
1114 break;
1115 case 0x08:
1116 i2c->sts &= ~(value & 0x0A);
1117 break;
1118 case 0x09:
1119 i2c->extsts &= ~(value & 0x8F);
1120 break;
1121 case 0x0A:
1122 i2c->lsadr = value;
1123 break;
1124 case 0x0B:
1125 i2c->hsadr = value;
1126 break;
1127 case 0x0C:
1128 i2c->clkdiv = value;
1129 break;
1130 case 0x0D:
1131 i2c->intrmsk = value;
1132 break;
1133 case 0x0E:
1134 i2c->xfrcnt = value & 0x77;
1135 break;
1136 case 0x0F:
1137 i2c->xtcntlss = value;
1138 break;
1139 case 0x10:
1140 i2c->directcntl = value & 0x7;
1141 break;
1142 }
1143}
1144
a8170e5e 1145static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
8ecc7913
JM		 1146{
1147 uint32_t ret;
1148
1149#ifdef DEBUG_I2C
90e189ec 1150 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 1151#endif
1152 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1153 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1154
1155 return ret;
1156}
1157
1158static void ppc4xx_i2c_writew (void *opaque,
a8170e5e 1159 hwaddr addr, uint32_t value)
8ecc7913
JM		 1160{
1161#ifdef DEBUG_I2C
90e189ec
BS		 1162 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1163 value);
8ecc7913
JM		 1164#endif
1165 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1166 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1167}
1168
a8170e5e 1169static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
8ecc7913
JM		 1170{
1171 uint32_t ret;
1172
1173#ifdef DEBUG_I2C
90e189ec 1174 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
8ecc7913
JM		 1175#endif
1176 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1177 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1178 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1179 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1180
1181 return ret;
1182}
1183
1184static void ppc4xx_i2c_writel (void *opaque,
a8170e5e 1185 hwaddr addr, uint32_t value)
8ecc7913
JM		 1186{
1187#ifdef DEBUG_I2C
90e189ec
BS		 1188 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1189 value);
8ecc7913
JM		 1190#endif
1191 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1192 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1193 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1194 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1195}
1196
9074e0e3
AK		 1197static const MemoryRegionOps i2c_ops = {
1198 .old_mmio = {
1199 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1200 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1201 },
1202 .endianness = DEVICE_NATIVE_ENDIAN,
8ecc7913
JM		 1203};
1204
1205static void ppc4xx_i2c_reset (void *opaque)
1206{
c227f099 1207 ppc4xx_i2c_t *i2c;
8ecc7913
JM		 1208
1209 i2c = opaque;
1210 i2c->mdata = 0x00;
1211 i2c->sdata = 0x00;
1212 i2c->cntl = 0x00;
1213 i2c->mdcntl = 0x00;
1214 i2c->sts = 0x00;
1215 i2c->extsts = 0x00;
1216 i2c->clkdiv = 0x00;
1217 i2c->xfrcnt = 0x00;
1218 i2c->directcntl = 0x0F;
1219}
1220
a8170e5e 1221static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
8ecc7913 1222{
c227f099 1223 ppc4xx_i2c_t *i2c;
8ecc7913 1224
7267c094 1225 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
487414f1 1226 i2c->irq = irq;
8ecc7913 1227#ifdef DEBUG_I2C
90e189ec 1228 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
8ecc7913 1229#endif
2c9b15ca 1230 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
9074e0e3 1231 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
a08d4367 1232 qemu_register_reset(ppc4xx_i2c_reset, i2c);
8ecc7913
JM		 1233}
1234
9c02f1a2
JM		 1235/*****************************************************************************/
1236/* General purpose timers */
c227f099
AL		 1237typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1238struct ppc4xx_gpt_t {
9074e0e3 1239 MemoryRegion iomem;
9c02f1a2
JM		 1240 int64_t tb_offset;
1241 uint32_t tb_freq;
1246b259 1242 QEMUTimer *timer;
9c02f1a2
JM		 1243 qemu_irq irqs[5];
1244 uint32_t oe;
1245 uint32_t ol;
1246 uint32_t im;
1247 uint32_t is;
1248 uint32_t ie;
1249 uint32_t comp[5];
1250 uint32_t mask[5];
1251};
1252
a8170e5e 1253static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
9c02f1a2
JM		 1254{
1255#ifdef DEBUG_GPT
90e189ec 1256 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
9c02f1a2
JM		 1257#endif
1258 /* XXX: generate a bus fault */
1259 return -1;
1260}
1261
1262static void ppc4xx_gpt_writeb (void *opaque,
a8170e5e 1263 hwaddr addr, uint32_t value)
9c02f1a2
JM		 1264{
1265#ifdef DEBUG_I2C
90e189ec
BS		 1266 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1267 value);
9c02f1a2
JM		 1268#endif
1269 /* XXX: generate a bus fault */
1270}
1271
a8170e5e 1272static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
9c02f1a2
JM		 1273{
1274#ifdef DEBUG_GPT
90e189ec 1275 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
9c02f1a2
JM		 1276#endif
1277 /* XXX: generate a bus fault */
1278 return -1;
1279}
1280
1281static void ppc4xx_gpt_writew (void *opaque,
a8170e5e 1282 hwaddr addr, uint32_t value)
9c02f1a2
JM		 1283{
1284#ifdef DEBUG_I2C
90e189ec
BS		 1285 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1286 value);
9c02f1a2
JM		 1287#endif
1288 /* XXX: generate a bus fault */
1289}
1290
c227f099 1291static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
9c02f1a2
JM		 1292{
1293 /* XXX: TODO */
1294 return 0;
1295}
1296
c227f099 1297static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
9c02f1a2
JM		 1298{
1299 /* XXX: TODO */
1300}
1301
c227f099 1302static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
9c02f1a2
JM		 1303{
1304 uint32_t mask;
1305 int i;
1306
1307 mask = 0x80000000;
1308 for (i = 0; i < 5; i++) {
1309 if (gpt->oe & mask) {
1310 /* Output is enabled */
1311 if (ppc4xx_gpt_compare(gpt, i)) {
1312 /* Comparison is OK */
1313 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1314 } else {
1315 /* Comparison is KO */
1316 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1317 }
1318 }
1319 mask = mask >> 1;
1320 }
9c02f1a2
JM		 1321}
1322
c227f099 1323static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
9c02f1a2
JM		 1324{
1325 uint32_t mask;
1326 int i;
1327
1328 mask = 0x00008000;
1329 for (i = 0; i < 5; i++) {
1330 if (gpt->is & gpt->im & mask)
1331 qemu_irq_raise(gpt->irqs[i]);
1332 else
1333 qemu_irq_lower(gpt->irqs[i]);
1334 mask = mask >> 1;
1335 }
9c02f1a2
JM		 1336}
1337
c227f099 1338static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
9c02f1a2
JM		 1339{
1340 /* XXX: TODO */
1341}
1342
a8170e5e 1343static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
9c02f1a2 1344{
c227f099 1345 ppc4xx_gpt_t *gpt;
9c02f1a2
JM		 1346 uint32_t ret;
1347 int idx;
1348
1349#ifdef DEBUG_GPT
90e189ec 1350 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
9c02f1a2
JM		 1351#endif
1352 gpt = opaque;
802670e6 1353 switch (addr) {
9c02f1a2
JM		 1354 case 0x00:
1355 /* Time base counter */
bc72ad67 1356 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
6ee093c9 1357 gpt->tb_freq, get_ticks_per_sec());
9c02f1a2
JM		 1358 break;
1359 case 0x10:
1360 /* Output enable */
1361 ret = gpt->oe;
1362 break;
1363 case 0x14:
1364 /* Output level */
1365 ret = gpt->ol;
1366 break;
1367 case 0x18:
1368 /* Interrupt mask */
1369 ret = gpt->im;
1370 break;
1371 case 0x1C:
1372 case 0x20:
1373 /* Interrupt status */
1374 ret = gpt->is;
1375 break;
1376 case 0x24:
1377 /* Interrupt enable */
1378 ret = gpt->ie;
1379 break;
1380 case 0x80 ... 0x90:
1381 /* Compare timer */
802670e6 1382 idx = (addr - 0x80) >> 2;
9c02f1a2
JM		 1383 ret = gpt->comp[idx];
1384 break;
1385 case 0xC0 ... 0xD0:
1386 /* Compare mask */
802670e6 1387 idx = (addr - 0xC0) >> 2;
9c02f1a2
JM		 1388 ret = gpt->mask[idx];
1389 break;
1390 default:
1391 ret = -1;
1392 break;
1393 }
1394
1395 return ret;
1396}
1397
1398static void ppc4xx_gpt_writel (void *opaque,
a8170e5e 1399 hwaddr addr, uint32_t value)
9c02f1a2 1400{
c227f099 1401 ppc4xx_gpt_t *gpt;
9c02f1a2
JM		 1402 int idx;
1403
1404#ifdef DEBUG_I2C
90e189ec
BS		 1405 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1406 value);
9c02f1a2
JM		 1407#endif
1408 gpt = opaque;
802670e6 1409 switch (addr) {
9c02f1a2
JM		 1410 case 0x00:
1411 /* Time base counter */
6ee093c9 1412 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
bc72ad67 1413 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
9c02f1a2
JM		 1414 ppc4xx_gpt_compute_timer(gpt);
1415 break;
1416 case 0x10:
1417 /* Output enable */
1418 gpt->oe = value & 0xF8000000;
1419 ppc4xx_gpt_set_outputs(gpt);
1420 break;
1421 case 0x14:
1422 /* Output level */
1423 gpt->ol = value & 0xF8000000;
1424 ppc4xx_gpt_set_outputs(gpt);
1425 break;
1426 case 0x18:
1427 /* Interrupt mask */
1428 gpt->im = value & 0x0000F800;
1429 break;
1430 case 0x1C:
1431 /* Interrupt status set */
1432 gpt->is |= value & 0x0000F800;
1433 ppc4xx_gpt_set_irqs(gpt);
1434 break;
1435 case 0x20:
1436 /* Interrupt status clear */
1437 gpt->is &= ~(value & 0x0000F800);
1438 ppc4xx_gpt_set_irqs(gpt);
1439 break;
1440 case 0x24:
1441 /* Interrupt enable */
1442 gpt->ie = value & 0x0000F800;
1443 ppc4xx_gpt_set_irqs(gpt);
1444 break;
1445 case 0x80 ... 0x90:
1446 /* Compare timer */
802670e6 1447 idx = (addr - 0x80) >> 2;
9c02f1a2
JM		 1448 gpt->comp[idx] = value & 0xF8000000;
1449 ppc4xx_gpt_compute_timer(gpt);
1450 break;
1451 case 0xC0 ... 0xD0:
1452 /* Compare mask */
802670e6 1453 idx = (addr - 0xC0) >> 2;
9c02f1a2
JM		 1454 gpt->mask[idx] = value & 0xF8000000;
1455 ppc4xx_gpt_compute_timer(gpt);
1456 break;
1457 }
1458}
1459
9074e0e3
AK		 1460static const MemoryRegionOps gpt_ops = {
1461 .old_mmio = {
1462 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1463 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1464 },
1465 .endianness = DEVICE_NATIVE_ENDIAN,
9c02f1a2
JM		 1466};
1467
1468static void ppc4xx_gpt_cb (void *opaque)
1469{
c227f099 1470 ppc4xx_gpt_t *gpt;
9c02f1a2
JM		 1471
1472 gpt = opaque;
1473 ppc4xx_gpt_set_irqs(gpt);
1474 ppc4xx_gpt_set_outputs(gpt);
1475 ppc4xx_gpt_compute_timer(gpt);
1476}
1477
1478static void ppc4xx_gpt_reset (void *opaque)
1479{
c227f099 1480 ppc4xx_gpt_t *gpt;
9c02f1a2
JM		 1481 int i;
1482
1483 gpt = opaque;
bc72ad67 1484 timer_del(gpt->timer);
9c02f1a2
JM		 1485 gpt->oe = 0x00000000;
1486 gpt->ol = 0x00000000;
1487 gpt->im = 0x00000000;
1488 gpt->is = 0x00000000;
1489 gpt->ie = 0x00000000;
1490 for (i = 0; i < 5; i++) {
1491 gpt->comp[i] = 0x00000000;
1492 gpt->mask[i] = 0x00000000;
1493 }
1494}
1495
a8170e5e 1496static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
9c02f1a2 1497{
c227f099 1498 ppc4xx_gpt_t *gpt;
9c02f1a2
JM		 1499 int i;
1500
7267c094 1501 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
802670e6 1502 for (i = 0; i < 5; i++) {
487414f1 1503 gpt->irqs[i] = irqs[i];
802670e6 1504 }
bc72ad67 1505 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
9c02f1a2 1506#ifdef DEBUG_GPT
90e189ec 1507 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
9c02f1a2 1508#endif
2c9b15ca 1509 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
9074e0e3 1510 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
a08d4367 1511 qemu_register_reset(ppc4xx_gpt_reset, gpt);
9c02f1a2
JM		 1512}
1513
1514/*****************************************************************************/
1515/* MAL */
1516enum {
1517 MAL0_CFG = 0x180,
1518 MAL0_ESR = 0x181,
1519 MAL0_IER = 0x182,
1520 MAL0_TXCASR = 0x184,
1521 MAL0_TXCARR = 0x185,
1522 MAL0_TXEOBISR = 0x186,
1523 MAL0_TXDEIR = 0x187,
1524 MAL0_RXCASR = 0x190,
1525 MAL0_RXCARR = 0x191,
1526 MAL0_RXEOBISR = 0x192,
1527 MAL0_RXDEIR = 0x193,
1528 MAL0_TXCTP0R = 0x1A0,
1529 MAL0_TXCTP1R = 0x1A1,
1530 MAL0_TXCTP2R = 0x1A2,
1531 MAL0_TXCTP3R = 0x1A3,
1532 MAL0_RXCTP0R = 0x1C0,
1533 MAL0_RXCTP1R = 0x1C1,
1534 MAL0_RCBS0 = 0x1E0,
1535 MAL0_RCBS1 = 0x1E1,
1536};
1537
c227f099
AL		 1538typedef struct ppc40x_mal_t ppc40x_mal_t;
1539struct ppc40x_mal_t {
9c02f1a2
JM		 1540 qemu_irq irqs[4];
1541 uint32_t cfg;
1542 uint32_t esr;
1543 uint32_t ier;
1544 uint32_t txcasr;
1545 uint32_t txcarr;
1546 uint32_t txeobisr;
1547 uint32_t txdeir;
1548 uint32_t rxcasr;
1549 uint32_t rxcarr;
1550 uint32_t rxeobisr;
1551 uint32_t rxdeir;
1552 uint32_t txctpr[4];
1553 uint32_t rxctpr[2];
1554 uint32_t rcbs[2];
1555};
1556
1557static void ppc40x_mal_reset (void *opaque);
1558
73b01960 1559static uint32_t dcr_read_mal (void *opaque, int dcrn)
9c02f1a2 1560{
c227f099 1561 ppc40x_mal_t *mal;
73b01960 1562 uint32_t ret;
9c02f1a2
JM		 1563
1564 mal = opaque;
1565 switch (dcrn) {
1566 case MAL0_CFG:
1567 ret = mal->cfg;
1568 break;
1569 case MAL0_ESR:
1570 ret = mal->esr;
1571 break;
1572 case MAL0_IER:
1573 ret = mal->ier;
1574 break;
1575 case MAL0_TXCASR:
1576 ret = mal->txcasr;
1577 break;
1578 case MAL0_TXCARR:
1579 ret = mal->txcarr;
1580 break;
1581 case MAL0_TXEOBISR:
1582 ret = mal->txeobisr;
1583 break;
1584 case MAL0_TXDEIR:
1585 ret = mal->txdeir;
1586 break;
1587 case MAL0_RXCASR:
1588 ret = mal->rxcasr;
1589 break;
1590 case MAL0_RXCARR:
1591 ret = mal->rxcarr;
1592 break;
1593 case MAL0_RXEOBISR:
1594 ret = mal->rxeobisr;
1595 break;
1596 case MAL0_RXDEIR:
1597 ret = mal->rxdeir;
1598 break;
1599 case MAL0_TXCTP0R:
1600 ret = mal->txctpr[0];
1601 break;
1602 case MAL0_TXCTP1R:
1603 ret = mal->txctpr[1];
1604 break;
1605 case MAL0_TXCTP2R:
1606 ret = mal->txctpr[2];
1607 break;
1608 case MAL0_TXCTP3R:
1609 ret = mal->txctpr[3];
1610 break;
1611 case MAL0_RXCTP0R:
1612 ret = mal->rxctpr[0];
1613 break;
1614 case MAL0_RXCTP1R:
1615 ret = mal->rxctpr[1];
1616 break;
1617 case MAL0_RCBS0:
1618 ret = mal->rcbs[0];
1619 break;
1620 case MAL0_RCBS1:
1621 ret = mal->rcbs[1];
1622 break;
1623 default:
1624 ret = 0;
1625 break;
1626 }
1627
1628 return ret;
1629}
1630
73b01960 1631static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
9c02f1a2 1632{
c227f099 1633 ppc40x_mal_t *mal;
9c02f1a2
JM		 1634 int idx;
1635
1636 mal = opaque;
1637 switch (dcrn) {
1638 case MAL0_CFG:
1639 if (val & 0x80000000)
1640 ppc40x_mal_reset(mal);
1641 mal->cfg = val & 0x00FFC087;
1642 break;
1643 case MAL0_ESR:
1644 /* Read/clear */
1645 mal->esr &= ~val;
1646 break;
1647 case MAL0_IER:
1648 mal->ier = val & 0x0000001F;
1649 break;
1650 case MAL0_TXCASR:
1651 mal->txcasr = val & 0xF0000000;
1652 break;
1653 case MAL0_TXCARR:
1654 mal->txcarr = val & 0xF0000000;
1655 break;
1656 case MAL0_TXEOBISR:
1657 /* Read/clear */
1658 mal->txeobisr &= ~val;
1659 break;
1660 case MAL0_TXDEIR:
1661 /* Read/clear */
1662 mal->txdeir &= ~val;
1663 break;
1664 case MAL0_RXCASR:
1665 mal->rxcasr = val & 0xC0000000;
1666 break;
1667 case MAL0_RXCARR:
1668 mal->rxcarr = val & 0xC0000000;
1669 break;
1670 case MAL0_RXEOBISR:
1671 /* Read/clear */
1672 mal->rxeobisr &= ~val;
1673 break;
1674 case MAL0_RXDEIR:
1675 /* Read/clear */
1676 mal->rxdeir &= ~val;
1677 break;
1678 case MAL0_TXCTP0R:
1679 idx = 0;
1680 goto update_tx_ptr;
1681 case MAL0_TXCTP1R:
1682 idx = 1;
1683 goto update_tx_ptr;
1684 case MAL0_TXCTP2R:
1685 idx = 2;
1686 goto update_tx_ptr;
1687 case MAL0_TXCTP3R:
1688 idx = 3;
1689 update_tx_ptr:
1690 mal->txctpr[idx] = val;
1691 break;
1692 case MAL0_RXCTP0R:
1693 idx = 0;
1694 goto update_rx_ptr;
1695 case MAL0_RXCTP1R:
1696 idx = 1;
1697 update_rx_ptr:
1698 mal->rxctpr[idx] = val;
1699 break;
1700 case MAL0_RCBS0:
1701 idx = 0;
1702 goto update_rx_size;
1703 case MAL0_RCBS1:
1704 idx = 1;
1705 update_rx_size:
1706 mal->rcbs[idx] = val & 0x000000FF;
1707 break;
1708 }
1709}
1710
1711static void ppc40x_mal_reset (void *opaque)
1712{
c227f099 1713 ppc40x_mal_t *mal;
9c02f1a2
JM		 1714
1715 mal = opaque;
1716 mal->cfg = 0x0007C000;
1717 mal->esr = 0x00000000;
1718 mal->ier = 0x00000000;
1719 mal->rxcasr = 0x00000000;
1720 mal->rxdeir = 0x00000000;
1721 mal->rxeobisr = 0x00000000;
1722 mal->txcasr = 0x00000000;
1723 mal->txdeir = 0x00000000;
1724 mal->txeobisr = 0x00000000;
1725}
1726
e2684c0b 1727static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
9c02f1a2 1728{
c227f099 1729 ppc40x_mal_t *mal;
9c02f1a2
JM		 1730 int i;
1731
7267c094 1732 mal = g_malloc0(sizeof(ppc40x_mal_t));
487414f1
AL		 1733 for (i = 0; i < 4; i++)
1734 mal->irqs[i] = irqs[i];
a08d4367 1735 qemu_register_reset(&ppc40x_mal_reset, mal);
487414f1
AL		 1736 ppc_dcr_register(env, MAL0_CFG,
1737 mal, &dcr_read_mal, &dcr_write_mal);
1738 ppc_dcr_register(env, MAL0_ESR,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_IER,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_TXCASR,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_TXCARR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_TXEOBISR,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_TXDEIR,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_RXCASR,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_RXCARR,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_RXEOBISR,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_RXDEIR,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_TXCTP0R,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_TXCTP1R,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_TXCTP2R,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_TXCTP3R,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_RXCTP0R,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_RXCTP1R,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 ppc_dcr_register(env, MAL0_RCBS0,
1771 mal, &dcr_read_mal, &dcr_write_mal);
1772 ppc_dcr_register(env, MAL0_RCBS1,
1773 mal, &dcr_read_mal, &dcr_write_mal);
9c02f1a2
JM		 1774}
1775
8ecc7913
JM		 1776/*****************************************************************************/
1777/* SPR */
f3273ba6 1778void ppc40x_core_reset(PowerPCCPU *cpu)
8ecc7913 1779{
f3273ba6 1780 CPUPPCState *env = &cpu->env;
8ecc7913
JM		 1781 target_ulong dbsr;
1782
1783 printf("Reset PowerPC core\n");
c3affe56 1784 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
8ecc7913
JM		 1785 dbsr = env->spr[SPR_40x_DBSR];
1786 dbsr &= ~0x00000300;
1787 dbsr |= 0x00000100;
1788 env->spr[SPR_40x_DBSR] = dbsr;
8ecc7913
JM		 1789}
1790
f3273ba6 1791void ppc40x_chip_reset(PowerPCCPU *cpu)
8ecc7913 1792{
f3273ba6 1793 CPUPPCState *env = &cpu->env;
8ecc7913
JM		 1794 target_ulong dbsr;
1795
1796 printf("Reset PowerPC chip\n");
c3affe56 1797 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
8ecc7913
JM		 1798 /* XXX: TODO reset all internal peripherals */
1799 dbsr = env->spr[SPR_40x_DBSR];
1800 dbsr &= ~0x00000300;
04f20795 1801 dbsr |= 0x00000200;
8ecc7913 1802 env->spr[SPR_40x_DBSR] = dbsr;
8ecc7913
JM		 1803}
1804
f3273ba6 1805void ppc40x_system_reset(PowerPCCPU *cpu)
8ecc7913
JM		 1806{
1807 printf("Reset PowerPC system\n");
1808 qemu_system_reset_request();
1809}
1810
e2684c0b 1811void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
8ecc7913 1812{
f3273ba6
AF		 1813 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1814
8ecc7913
JM		 1815 switch ((val >> 28) & 0x3) {
1816 case 0x0:
1817 /* No action */
1818 break;
1819 case 0x1:
1820 /* Core reset */
f3273ba6 1821 ppc40x_core_reset(cpu);
8ecc7913
JM		 1822 break;
1823 case 0x2:
1824 /* Chip reset */
f3273ba6 1825 ppc40x_chip_reset(cpu);
8ecc7913
JM		 1826 break;
1827 case 0x3:
1828 /* System reset */
f3273ba6 1829 ppc40x_system_reset(cpu);
8ecc7913
JM		 1830 break;
1831 }
1832}
1833
1834/*****************************************************************************/
1835/* PowerPC 405CR */
1836enum {
1837 PPC405CR_CPC0_PLLMR = 0x0B0,
1838 PPC405CR_CPC0_CR0 = 0x0B1,
1839 PPC405CR_CPC0_CR1 = 0x0B2,
1840 PPC405CR_CPC0_PSR = 0x0B4,
1841 PPC405CR_CPC0_JTAGID = 0x0B5,
1842 PPC405CR_CPC0_ER = 0x0B9,
1843 PPC405CR_CPC0_FR = 0x0BA,
1844 PPC405CR_CPC0_SR = 0x0BB,
1845};
1846
04f20795
JM		 1847enum {
1848 PPC405CR_CPU_CLK = 0,
1849 PPC405CR_TMR_CLK = 1,
1850 PPC405CR_PLB_CLK = 2,
1851 PPC405CR_SDRAM_CLK = 3,
1852 PPC405CR_OPB_CLK = 4,
1853 PPC405CR_EXT_CLK = 5,
1854 PPC405CR_UART_CLK = 6,
1855 PPC405CR_CLK_NB = 7,
1856};
1857
c227f099
AL		 1858typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1859struct ppc405cr_cpc_t {
1860 clk_setup_t clk_setup[PPC405CR_CLK_NB];
8ecc7913
JM		 1861 uint32_t sysclk;
1862 uint32_t psr;
1863 uint32_t cr0;
1864 uint32_t cr1;
1865 uint32_t jtagid;
1866 uint32_t pllmr;
1867 uint32_t er;
1868 uint32_t fr;
1869};
1870
c227f099 1871static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
8ecc7913
JM		 1872{
1873 uint64_t VCO_out, PLL_out;
1874 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1875 int M, D0, D1, D2;
1876
1877 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1878 if (cpc->pllmr & 0x80000000) {
1879 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1880 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1881 M = D0 * D1 * D2;
1882 VCO_out = cpc->sysclk * M;
1883 if (VCO_out < 400000000 || VCO_out > 800000000) {
1884 /* PLL cannot lock */
1885 cpc->pllmr &= ~0x80000000;
1886 goto bypass_pll;
1887 }
1888 PLL_out = VCO_out / D2;
1889 } else {
1890 /* Bypass PLL */
1891 bypass_pll:
1892 M = D0;
1893 PLL_out = cpc->sysclk * M;
1894 }
1895 CPU_clk = PLL_out;
1896 if (cpc->cr1 & 0x00800000)
1897 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1898 else
1899 TMR_clk = CPU_clk;
1900 PLB_clk = CPU_clk / D0;
1901 SDRAM_clk = PLB_clk;
1902 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1903 OPB_clk = PLB_clk / D0;
1904 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1905 EXT_clk = PLB_clk / D0;
1906 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1907 UART_clk = CPU_clk / D0;
1908 /* Setup CPU clocks */
04f20795 1909 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
8ecc7913 1910 /* Setup time-base clock */
04f20795 1911 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
8ecc7913 1912 /* Setup PLB clock */
04f20795 1913 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
8ecc7913 1914 /* Setup SDRAM clock */
04f20795 1915 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
8ecc7913 1916 /* Setup OPB clock */
04f20795 1917 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
8ecc7913 1918 /* Setup external clock */
04f20795 1919 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
8ecc7913 1920 /* Setup UART clock */
04f20795 1921 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
8ecc7913
JM		 1922}
1923
73b01960 1924static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
8ecc7913 1925{
c227f099 1926 ppc405cr_cpc_t *cpc;
73b01960 1927 uint32_t ret;
8ecc7913
JM		 1928
1929 cpc = opaque;
1930 switch (dcrn) {
1931 case PPC405CR_CPC0_PLLMR:
1932 ret = cpc->pllmr;
1933 break;
1934 case PPC405CR_CPC0_CR0:
1935 ret = cpc->cr0;
1936 break;
1937 case PPC405CR_CPC0_CR1:
1938 ret = cpc->cr1;
1939 break;
1940 case PPC405CR_CPC0_PSR:
1941 ret = cpc->psr;
1942 break;
1943 case PPC405CR_CPC0_JTAGID:
1944 ret = cpc->jtagid;
1945 break;
1946 case PPC405CR_CPC0_ER:
1947 ret = cpc->er;
1948 break;
1949 case PPC405CR_CPC0_FR:
1950 ret = cpc->fr;
1951 break;
1952 case PPC405CR_CPC0_SR:
1953 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1954 break;
1955 default:
1956 /* Avoid gcc warning */
1957 ret = 0;
1958 break;
1959 }
1960
1961 return ret;
1962}
1963
73b01960 1964static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
8ecc7913 1965{
c227f099 1966 ppc405cr_cpc_t *cpc;
8ecc7913
JM		 1967
1968 cpc = opaque;
1969 switch (dcrn) {
1970 case PPC405CR_CPC0_PLLMR:
1971 cpc->pllmr = val & 0xFFF77C3F;
1972 break;
1973 case PPC405CR_CPC0_CR0:
1974 cpc->cr0 = val & 0x0FFFFFFE;
1975 break;
1976 case PPC405CR_CPC0_CR1:
1977 cpc->cr1 = val & 0x00800000;
1978 break;
1979 case PPC405CR_CPC0_PSR:
1980 /* Read-only */
1981 break;
1982 case PPC405CR_CPC0_JTAGID:
1983 /* Read-only */
1984 break;
1985 case PPC405CR_CPC0_ER:
1986 cpc->er = val & 0xBFFC0000;
1987 break;
1988 case PPC405CR_CPC0_FR:
1989 cpc->fr = val & 0xBFFC0000;
1990 break;
1991 case PPC405CR_CPC0_SR:
1992 /* Read-only */
1993 break;
1994 }
1995}
1996
1997static void ppc405cr_cpc_reset (void *opaque)
1998{
c227f099 1999 ppc405cr_cpc_t *cpc;
8ecc7913
JM		 2000 int D;
2001
2002 cpc = opaque;
2003 /* Compute PLLMR value from PSR settings */
2004 cpc->pllmr = 0x80000000;
2005 /* PFWD */
2006 switch ((cpc->psr >> 30) & 3) {
2007 case 0:
2008 /* Bypass */
2009 cpc->pllmr &= ~0x80000000;
2010 break;
2011 case 1:
2012 /* Divide by 3 */
2013 cpc->pllmr |= 5 << 16;
2014 break;
2015 case 2:
2016 /* Divide by 4 */
2017 cpc->pllmr |= 4 << 16;
2018 break;
2019 case 3:
2020 /* Divide by 6 */
2021 cpc->pllmr |= 2 << 16;
2022 break;
2023 }
2024 /* PFBD */
2025 D = (cpc->psr >> 28) & 3;
2026 cpc->pllmr |= (D + 1) << 20;
2027 /* PT */
2028 D = (cpc->psr >> 25) & 7;
2029 switch (D) {
2030 case 0x2:
2031 cpc->pllmr |= 0x13;
2032 break;
2033 case 0x4:
2034 cpc->pllmr |= 0x15;
2035 break;
2036 case 0x5:
2037 cpc->pllmr |= 0x16;
2038 break;
2039 default:
2040 break;
2041 }
2042 /* PDC */
2043 D = (cpc->psr >> 23) & 3;
2044 cpc->pllmr |= D << 26;
2045 /* ODP */
2046 D = (cpc->psr >> 21) & 3;
2047 cpc->pllmr |= D << 10;
2048 /* EBPD */
2049 D = (cpc->psr >> 17) & 3;
2050 cpc->pllmr |= D << 24;
2051 cpc->cr0 = 0x0000003C;
2052 cpc->cr1 = 0x2B0D8800;
2053 cpc->er = 0x00000000;
2054 cpc->fr = 0x00000000;
2055 ppc405cr_clk_setup(cpc);
2056}
2057
c227f099 2058static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
8ecc7913
JM		 2059{
2060 int D;
2061
2062 /* XXX: this should be read from IO pins */
2063 cpc->psr = 0x00000000; /* 8 bits ROM */
2064 /* PFWD */
2065 D = 0x2; /* Divide by 4 */
2066 cpc->psr |= D << 30;
2067 /* PFBD */
2068 D = 0x1; /* Divide by 2 */
2069 cpc->psr |= D << 28;
2070 /* PDC */
2071 D = 0x1; /* Divide by 2 */
2072 cpc->psr |= D << 23;
2073 /* PT */
2074 D = 0x5; /* M = 16 */
2075 cpc->psr |= D << 25;
2076 /* ODP */
2077 D = 0x1; /* Divide by 2 */
2078 cpc->psr |= D << 21;
2079 /* EBDP */
2080 D = 0x2; /* Divide by 4 */
2081 cpc->psr |= D << 17;
2082}
2083
e2684c0b 2084static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
8ecc7913
JM		 2085 uint32_t sysclk)
2086{
c227f099 2087 ppc405cr_cpc_t *cpc;
8ecc7913 2088
7267c094 2089 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
487414f1 2090 memcpy(cpc->clk_setup, clk_setup,
c227f099 2091 PPC405CR_CLK_NB * sizeof(clk_setup_t));
487414f1
AL		 2092 cpc->sysclk = sysclk;
2093 cpc->jtagid = 0x42051049;
2094 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2095 &dcr_read_crcpc, &dcr_write_crcpc);
2096 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2097 &dcr_read_crcpc, &dcr_write_crcpc);
2098 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2099 &dcr_read_crcpc, &dcr_write_crcpc);
2100 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2101 &dcr_read_crcpc, &dcr_write_crcpc);
2102 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2103 &dcr_read_crcpc, &dcr_write_crcpc);
2104 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2107 &dcr_read_crcpc, &dcr_write_crcpc);
2108 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2109 &dcr_read_crcpc, &dcr_write_crcpc);
2110 ppc405cr_clk_init(cpc);
a08d4367 2111 qemu_register_reset(ppc405cr_cpc_reset, cpc);
8ecc7913
JM		 2112}
2113
e2684c0b 2114CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
52ce55a1 2115 MemoryRegion ram_memories[4],
a8170e5e
AK		 2116 hwaddr ram_bases[4],
2117 hwaddr ram_sizes[4],
52ce55a1
RH		 2118 uint32_t sysclk, qemu_irq **picp,
2119 int do_init)
8ecc7913 2120{
c227f099 2121 clk_setup_t clk_setup[PPC405CR_CLK_NB];
8ecc7913 2122 qemu_irq dma_irqs[4];
2f9859fb 2123 PowerPCCPU *cpu;
e2684c0b 2124 CPUPPCState *env;
8ecc7913 2125 qemu_irq *pic, *irqs;
8ecc7913
JM		 2126
2127 memset(clk_setup, 0, sizeof(clk_setup));
2f9859fb 2128 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
04f20795 2129 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2f9859fb 2130 env = &cpu->env;
8ecc7913 2131 /* Memory mapped devices registers */
8ecc7913
JM		 2132 /* PLB arbitrer */
2133 ppc4xx_plb_init(env);
2134 /* PLB to OPB bridge */
2135 ppc4xx_pob_init(env);
2136 /* OBP arbitrer */
802670e6 2137 ppc4xx_opba_init(0xef600600);
8ecc7913 2138 /* Universal interrupt controller */
7267c094 2139 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
8ecc7913 2140 irqs[PPCUIC_OUTPUT_INT] =
b48d7d69 2141 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
8ecc7913 2142 irqs[PPCUIC_OUTPUT_CINT] =
b48d7d69 2143 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
8ecc7913
JM		 2144 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2145 *picp = pic;
2146 /* SDRAM controller */
b6dcbe08
AK		 2147 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2148 ram_bases, ram_sizes, do_init);
8ecc7913
JM		 2149 /* External bus controller */
2150 ppc405_ebc_init(env);
2151 /* DMA controller */
04f20795
JM		 2152 dma_irqs[0] = pic[26];
2153 dma_irqs[1] = pic[25];
2154 dma_irqs[2] = pic[24];
2155 dma_irqs[3] = pic[23];
8ecc7913
JM		 2156 ppc405_dma_init(env, dma_irqs);
2157 /* Serial ports */
2158 if (serial_hds[0] != NULL) {
52ce55a1 2159 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
39186d8a
RH		 2160 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2161 DEVICE_BIG_ENDIAN);
8ecc7913
JM		 2162 }
2163 if (serial_hds[1] != NULL) {
52ce55a1 2164 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
39186d8a
RH		 2165 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2166 DEVICE_BIG_ENDIAN);
8ecc7913
JM		 2167 }
2168 /* IIC controller */
802670e6 2169 ppc405_i2c_init(0xef600500, pic[2]);
8ecc7913 2170 /* GPIO */
802670e6 2171 ppc405_gpio_init(0xef600700);
8ecc7913
JM		 2172 /* CPU control */
2173 ppc405cr_cpc_init(env, clk_setup, sysclk);
8ecc7913
JM		 2174
2175 return env;
2176}
2177
2178/*****************************************************************************/
2179/* PowerPC 405EP */
2180/* CPU control */
2181enum {
2182 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2183 PPC405EP_CPC0_BOOT = 0x0F1,
2184 PPC405EP_CPC0_EPCTL = 0x0F3,
2185 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2186 PPC405EP_CPC0_UCR = 0x0F5,
2187 PPC405EP_CPC0_SRR = 0x0F6,
2188 PPC405EP_CPC0_JTAGID = 0x0F7,
2189 PPC405EP_CPC0_PCI = 0x0F9,
9c02f1a2
JM		 2190#if 0
2191 PPC405EP_CPC0_ER = xxx,
2192 PPC405EP_CPC0_FR = xxx,
2193 PPC405EP_CPC0_SR = xxx,
2194#endif
8ecc7913
JM		 2195};
2196
04f20795
JM		 2197enum {
2198 PPC405EP_CPU_CLK = 0,
2199 PPC405EP_PLB_CLK = 1,
2200 PPC405EP_OPB_CLK = 2,
2201 PPC405EP_EBC_CLK = 3,
2202 PPC405EP_MAL_CLK = 4,
2203 PPC405EP_PCI_CLK = 5,
2204 PPC405EP_UART0_CLK = 6,
2205 PPC405EP_UART1_CLK = 7,
2206 PPC405EP_CLK_NB = 8,
2207};
2208
c227f099
AL		 2209typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2210struct ppc405ep_cpc_t {
8ecc7913 2211 uint32_t sysclk;
c227f099 2212 clk_setup_t clk_setup[PPC405EP_CLK_NB];
8ecc7913
JM		 2213 uint32_t boot;
2214 uint32_t epctl;
2215 uint32_t pllmr[2];
2216 uint32_t ucr;
2217 uint32_t srr;
2218 uint32_t jtagid;
2219 uint32_t pci;
9c02f1a2
JM		 2220 /* Clock and power management */
2221 uint32_t er;
2222 uint32_t fr;
2223 uint32_t sr;
8ecc7913
JM		 2224};
2225
c227f099 2226static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
8ecc7913
JM		 2227{
2228 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2229 uint32_t UART0_clk, UART1_clk;
2230 uint64_t VCO_out, PLL_out;
2231 int M, D;
2232
2233 VCO_out = 0;
2234 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2235 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
aae9366a
JM		 2236#ifdef DEBUG_CLOCKS_LL
2237 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2238#endif
8ecc7913 2239 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
aae9366a
JM		 2240#ifdef DEBUG_CLOCKS_LL
2241 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2242#endif
8ecc7913
JM		 2243 VCO_out = cpc->sysclk * M * D;
2244 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2245 /* Error - unlock the PLL */
2246 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2247#if 0
2248 cpc->pllmr[1] &= ~0x80000000;
2249 goto pll_bypass;
2250#endif
2251 }
2252 PLL_out = VCO_out / D;
9c02f1a2
JM		 2253 /* Pretend the PLL is locked */
2254 cpc->boot |= 0x00000001;
8ecc7913
JM		 2255 } else {
2256#if 0
2257 pll_bypass:
2258#endif
2259 PLL_out = cpc->sysclk;
9c02f1a2
JM		 2260 if (cpc->pllmr[1] & 0x40000000) {
2261 /* Pretend the PLL is not locked */
2262 cpc->boot &= ~0x00000001;
2263 }
8ecc7913
JM		 2264 }
2265 /* Now, compute all other clocks */
2266 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
aae9366a
JM		 2267#ifdef DEBUG_CLOCKS_LL
2268 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
8ecc7913
JM		 2269#endif
2270 CPU_clk = PLL_out / D;
2271 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
aae9366a
JM		 2272#ifdef DEBUG_CLOCKS_LL
2273 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
8ecc7913
JM		 2274#endif
2275 PLB_clk = CPU_clk / D;
2276 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
aae9366a
JM		 2277#ifdef DEBUG_CLOCKS_LL
2278 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
8ecc7913
JM		 2279#endif
2280 OPB_clk = PLB_clk / D;
2281 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
aae9366a
JM		 2282#ifdef DEBUG_CLOCKS_LL
2283 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
8ecc7913
JM		 2284#endif
2285 EBC_clk = PLB_clk / D;
2286 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
aae9366a
JM		 2287#ifdef DEBUG_CLOCKS_LL
2288 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
8ecc7913
JM		 2289#endif
2290 MAL_clk = PLB_clk / D;
2291 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
aae9366a
JM		 2292#ifdef DEBUG_CLOCKS_LL
2293 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
8ecc7913
JM		 2294#endif
2295 PCI_clk = PLB_clk / D;
2296 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
aae9366a
JM		 2297#ifdef DEBUG_CLOCKS_LL
2298 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
8ecc7913
JM		 2299#endif
2300 UART0_clk = PLL_out / D;
2301 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
aae9366a
JM		 2302#ifdef DEBUG_CLOCKS_LL
2303 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
8ecc7913
JM		 2304#endif
2305 UART1_clk = PLL_out / D;
2306#ifdef DEBUG_CLOCKS
aae9366a 2307 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
8ecc7913 2308 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
aae9366a
JM		 2309 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2310 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2311 " UART1 %" PRIu32 "\n",
8ecc7913
JM		 2312 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2313 UART0_clk, UART1_clk);
2314#endif
2315 /* Setup CPU clocks */
04f20795 2316 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
8ecc7913 2317 /* Setup PLB clock */
04f20795 2318 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
8ecc7913 2319 /* Setup OPB clock */
04f20795 2320 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
8ecc7913 2321 /* Setup external clock */
04f20795 2322 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
8ecc7913 2323 /* Setup MAL clock */
04f20795 2324 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
8ecc7913 2325 /* Setup PCI clock */
04f20795 2326 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
8ecc7913 2327 /* Setup UART0 clock */
04f20795 2328 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
8ecc7913 2329 /* Setup UART1 clock */
04f20795 2330 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
8ecc7913
JM		 2331}
2332
73b01960 2333static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
8ecc7913 2334{
c227f099 2335 ppc405ep_cpc_t *cpc;
73b01960 2336 uint32_t ret;
8ecc7913
JM		 2337
2338 cpc = opaque;
2339 switch (dcrn) {
2340 case PPC405EP_CPC0_BOOT:
2341 ret = cpc->boot;
2342 break;
2343 case PPC405EP_CPC0_EPCTL:
2344 ret = cpc->epctl;
2345 break;
2346 case PPC405EP_CPC0_PLLMR0:
2347 ret = cpc->pllmr[0];
2348 break;
2349 case PPC405EP_CPC0_PLLMR1:
2350 ret = cpc->pllmr[1];
2351 break;
2352 case PPC405EP_CPC0_UCR:
2353 ret = cpc->ucr;
2354 break;
2355 case PPC405EP_CPC0_SRR:
2356 ret = cpc->srr;
2357 break;
2358 case PPC405EP_CPC0_JTAGID:
2359 ret = cpc->jtagid;
2360 break;
2361 case PPC405EP_CPC0_PCI:
2362 ret = cpc->pci;
2363 break;
2364 default:
2365 /* Avoid gcc warning */
2366 ret = 0;
2367 break;
2368 }
2369
2370 return ret;
2371}
2372
73b01960 2373static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
8ecc7913 2374{
c227f099 2375 ppc405ep_cpc_t *cpc;
8ecc7913
JM		 2376
2377 cpc = opaque;
2378 switch (dcrn) {
2379 case PPC405EP_CPC0_BOOT:
2380 /* Read-only register */
2381 break;
2382 case PPC405EP_CPC0_EPCTL:
2383 /* Don't care for now */
2384 cpc->epctl = val & 0xC00000F3;
2385 break;
2386 case PPC405EP_CPC0_PLLMR0:
2387 cpc->pllmr[0] = val & 0x00633333;
2388 ppc405ep_compute_clocks(cpc);
2389 break;
2390 case PPC405EP_CPC0_PLLMR1:
2391 cpc->pllmr[1] = val & 0xC0F73FFF;
2392 ppc405ep_compute_clocks(cpc);
2393 break;
2394 case PPC405EP_CPC0_UCR:
2395 /* UART control - don't care for now */
2396 cpc->ucr = val & 0x003F7F7F;
2397 break;
2398 case PPC405EP_CPC0_SRR:
2399 cpc->srr = val;
2400 break;
2401 case PPC405EP_CPC0_JTAGID:
2402 /* Read-only */
2403 break;
2404 case PPC405EP_CPC0_PCI:
2405 cpc->pci = val;
2406 break;
2407 }
2408}
2409
2410static void ppc405ep_cpc_reset (void *opaque)
2411{
c227f099 2412 ppc405ep_cpc_t *cpc = opaque;
8ecc7913
JM		 2413
2414 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2415 cpc->epctl = 0x00000000;
2416 cpc->pllmr[0] = 0x00011010;
2417 cpc->pllmr[1] = 0x40000000;
2418 cpc->ucr = 0x00000000;
2419 cpc->srr = 0x00040000;
2420 cpc->pci = 0x00000000;
9c02f1a2
JM		 2421 cpc->er = 0x00000000;
2422 cpc->fr = 0x00000000;
2423 cpc->sr = 0x00000000;
8ecc7913
JM		 2424 ppc405ep_compute_clocks(cpc);
2425}
2426
2427/* XXX: sysclk should be between 25 and 100 MHz */
e2684c0b 2428static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
8ecc7913
JM		 2429 uint32_t sysclk)
2430{
c227f099 2431 ppc405ep_cpc_t *cpc;
8ecc7913 2432
7267c094 2433 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
487414f1 2434 memcpy(cpc->clk_setup, clk_setup,
c227f099 2435 PPC405EP_CLK_NB * sizeof(clk_setup_t));
487414f1
AL		 2436 cpc->jtagid = 0x20267049;
2437 cpc->sysclk = sysclk;
a08d4367 2438 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
487414f1
AL		 2439 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2446 &dcr_read_epcpc, &dcr_write_epcpc);
2447 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2453 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2454 &dcr_read_epcpc, &dcr_write_epcpc);
9c02f1a2 2455#if 0
487414f1
AL		 2456 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2459 &dcr_read_epcpc, &dcr_write_epcpc);
2460 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2461 &dcr_read_epcpc, &dcr_write_epcpc);
9c02f1a2 2462#endif
8ecc7913
JM		 2463}
2464
e2684c0b 2465CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
52ce55a1 2466 MemoryRegion ram_memories[2],
a8170e5e
AK		 2467 hwaddr ram_bases[2],
2468 hwaddr ram_sizes[2],
52ce55a1
RH		 2469 uint32_t sysclk, qemu_irq **picp,
2470 int do_init)
8ecc7913 2471{
c227f099 2472 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
9c02f1a2 2473 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2f9859fb 2474 PowerPCCPU *cpu;
e2684c0b 2475 CPUPPCState *env;
8ecc7913 2476 qemu_irq *pic, *irqs;
8ecc7913
JM		 2477
2478 memset(clk_setup, 0, sizeof(clk_setup));
2479 /* init CPUs */
2f9859fb 2480 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
9c02f1a2 2481 &tlb_clk_setup, sysclk);
2f9859fb 2482 env = &cpu->env;
9c02f1a2
JM		 2483 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2484 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
8ecc7913
JM		 2485 /* Internal devices init */
2486 /* Memory mapped devices registers */
8ecc7913
JM		 2487 /* PLB arbitrer */
2488 ppc4xx_plb_init(env);
2489 /* PLB to OPB bridge */
2490 ppc4xx_pob_init(env);
2491 /* OBP arbitrer */
802670e6 2492 ppc4xx_opba_init(0xef600600);
d715ea96 2493 /* Initialize timers */
a34a92b9 2494 ppc_booke_timers_init(cpu, sysclk, 0);
8ecc7913 2495 /* Universal interrupt controller */
7267c094 2496 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
8ecc7913 2497 irqs[PPCUIC_OUTPUT_INT] =
b48d7d69 2498 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
8ecc7913 2499 irqs[PPCUIC_OUTPUT_CINT] =
b48d7d69 2500 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
8ecc7913
JM		 2501 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2502 *picp = pic;
2503 /* SDRAM controller */
923e5e33 2504 /* XXX 405EP has no ECC interrupt */
b6dcbe08
AK		 2505 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2506 ram_bases, ram_sizes, do_init);
8ecc7913
JM		 2507 /* External bus controller */
2508 ppc405_ebc_init(env);
2509 /* DMA controller */
923e5e33
AJ		 2510 dma_irqs[0] = pic[5];
2511 dma_irqs[1] = pic[6];
2512 dma_irqs[2] = pic[7];
2513 dma_irqs[3] = pic[8];
8ecc7913
JM		 2514 ppc405_dma_init(env, dma_irqs);
2515 /* IIC controller */
802670e6 2516 ppc405_i2c_init(0xef600500, pic[2]);
8ecc7913 2517 /* GPIO */
802670e6 2518 ppc405_gpio_init(0xef600700);
8ecc7913
JM		 2519 /* Serial ports */
2520 if (serial_hds[0] != NULL) {
52ce55a1 2521 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
39186d8a
RH		 2522 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2523 DEVICE_BIG_ENDIAN);
8ecc7913
JM		 2524 }
2525 if (serial_hds[1] != NULL) {
52ce55a1 2526 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
39186d8a
RH		 2527 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2528 DEVICE_BIG_ENDIAN);
8ecc7913
JM		 2529 }
2530 /* OCM */
5c130f65 2531 ppc405_ocm_init(env);
9c02f1a2 2532 /* GPT */
923e5e33
AJ		 2533 gpt_irqs[0] = pic[19];
2534 gpt_irqs[1] = pic[20];
2535 gpt_irqs[2] = pic[21];
2536 gpt_irqs[3] = pic[22];
2537 gpt_irqs[4] = pic[23];
802670e6 2538 ppc4xx_gpt_init(0xef600000, gpt_irqs);
8ecc7913 2539 /* PCI */
923e5e33 2540 /* Uses pic[3], pic[16], pic[18] */
9c02f1a2 2541 /* MAL */
923e5e33
AJ		 2542 mal_irqs[0] = pic[11];
2543 mal_irqs[1] = pic[12];
2544 mal_irqs[2] = pic[13];
2545 mal_irqs[3] = pic[14];
9c02f1a2
JM		 2546 ppc405_mal_init(env, mal_irqs);
2547 /* Ethernet */
923e5e33 2548 /* Uses pic[9], pic[15], pic[17] */
8ecc7913
JM		 2549 /* CPU control */
2550 ppc405ep_cpc_init(env, clk_setup, sysclk);
8ecc7913
JM		 2551
2552 return env;
2553}
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