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Commit | Line | Data |
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2c9fade2 | 1 | /* |
5cbdb3a3 | 2 | * QEMU PowerPC 440 Bamboo board emulation |
2c9fade2 AJ |
3 | * |
4 | * Copyright 2007 IBM Corporation. | |
5 | * Authors: | |
acd1bf90 AG |
6 | * Jerone Young <jyoung5@us.ibm.com> |
7 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
8 | * Hollis Blanchard <hollisb@us.ibm.com> | |
2c9fade2 AJ |
9 | * |
10 | * This work is licensed under the GNU GPL license version 2 or later. | |
11 | * | |
12 | */ | |
13 | ||
0d75590d | 14 | #include "qemu/osdep.h" |
ab3dd749 | 15 | #include "qemu/units.h" |
6f76b817 | 16 | #include "qemu/error-report.h" |
2c9fade2 | 17 | #include "qemu-common.h" |
64b47457 | 18 | #include "qemu/error-report.h" |
1422e32d | 19 | #include "net/net.h" |
83c9f4ca PB |
20 | #include "hw/pci/pci.h" |
21 | #include "hw/boards.h" | |
9c17d615 | 22 | #include "sysemu/kvm.h" |
2c9fade2 | 23 | #include "kvm_ppc.h" |
9c17d615 | 24 | #include "sysemu/device_tree.h" |
83c9f4ca | 25 | #include "hw/loader.h" |
ca20cf32 | 26 | #include "elf.h" |
022c62cb | 27 | #include "exec/address-spaces.h" |
0d09e41a PB |
28 | #include "hw/char/serial.h" |
29 | #include "hw/ppc/ppc.h" | |
47b43a1f | 30 | #include "ppc405.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
64b47457 | 32 | #include "sysemu/qtest.h" |
71e8a915 | 33 | #include "sysemu/reset.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
2c9fade2 AJ |
35 | |
36 | #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" | |
37 | ||
ceee6da6 HB |
38 | /* from u-boot */ |
39 | #define KERNEL_ADDR 0x1000000 | |
40 | #define FDT_ADDR 0x1800000 | |
41 | #define RAMDISK_ADDR 0x1900000 | |
42 | ||
3960b04d AG |
43 | #define PPC440EP_PCI_CONFIG 0xeec00000 |
44 | #define PPC440EP_PCI_INTACK 0xeed00000 | |
45 | #define PPC440EP_PCI_SPECIAL 0xeed00000 | |
46 | #define PPC440EP_PCI_REGS 0xef400000 | |
47 | #define PPC440EP_PCI_IO 0xe8000000 | |
48 | #define PPC440EP_PCI_IOLEN 0x00010000 | |
49 | ||
50 | #define PPC440EP_SDRAM_NR_BANKS 4 | |
51 | ||
7d8ccf58 | 52 | static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { |
ab3dd749 | 53 | 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 |
3960b04d AG |
54 | }; |
55 | ||
a8170e5e | 56 | static hwaddr entry; |
b10a04b5 | 57 | |
a8170e5e | 58 | static int bamboo_load_device_tree(hwaddr addr, |
2c9fade2 | 59 | uint32_t ramsize, |
a8170e5e AK |
60 | hwaddr initrd_base, |
61 | hwaddr initrd_size, | |
2c9fade2 AJ |
62 | const char *kernel_cmdline) |
63 | { | |
dbf916d8 | 64 | int ret = -1; |
5232fa59 | 65 | uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; |
5cea8590 | 66 | char *filename; |
7ec632b4 | 67 | int fdt_size; |
dbf916d8 | 68 | void *fdt; |
7dadd40c AG |
69 | uint32_t tb_freq = 400000000; |
70 | uint32_t clock_freq = 400000000; | |
2c9fade2 | 71 | |
5cea8590 PB |
72 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
73 | if (!filename) { | |
400431ef | 74 | return -1; |
5cea8590 PB |
75 | } |
76 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 77 | g_free(filename); |
5cea8590 | 78 | if (fdt == NULL) { |
400431ef | 79 | return -1; |
5cea8590 | 80 | } |
2c9fade2 AJ |
81 | |
82 | /* Manipulate device tree in memory. */ | |
83 | ||
5a4348d1 PC |
84 | ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, |
85 | sizeof(mem_reg_property)); | |
2c9fade2 AJ |
86 | if (ret < 0) |
87 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
88 | ||
5a4348d1 PC |
89 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
90 | initrd_base); | |
2c9fade2 AJ |
91 | if (ret < 0) |
92 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
93 | ||
5a4348d1 PC |
94 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
95 | (initrd_base + initrd_size)); | |
2c9fade2 AJ |
96 | if (ret < 0) |
97 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
98 | ||
5a4348d1 PC |
99 | ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
100 | kernel_cmdline); | |
2c9fade2 AJ |
101 | if (ret < 0) |
102 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
103 | ||
7dadd40c AG |
104 | /* Copy data from the host device tree into the guest. Since the guest can |
105 | * directly access the timebase without host involvement, we must expose | |
106 | * the correct frequencies. */ | |
a489f7f7 | 107 | if (kvm_enabled()) { |
7dadd40c AG |
108 | tb_freq = kvmppc_get_tbfreq(); |
109 | clock_freq = kvmppc_get_clockfreq(); | |
a489f7f7 | 110 | } |
2c9fade2 | 111 | |
5a4348d1 PC |
112 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", |
113 | clock_freq); | |
114 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", | |
115 | tb_freq); | |
2c9fade2 | 116 | |
fe1479aa | 117 | rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
7267c094 | 118 | g_free(fdt); |
fe1479aa | 119 | return 0; |
2c9fade2 AJ |
120 | } |
121 | ||
72718e9a | 122 | /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ |
e2684c0b | 123 | static void mmubooke_create_initial_mapping(CPUPPCState *env, |
72718e9a | 124 | target_ulong va, |
a8170e5e | 125 | hwaddr pa) |
72718e9a AG |
126 | { |
127 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; | |
128 | ||
129 | tlb->attr = 0; | |
130 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
a1f7f97b | 131 | tlb->size = 1U << 31; /* up to 0x80000000 */ |
72718e9a AG |
132 | tlb->EPN = va & TARGET_PAGE_MASK; |
133 | tlb->RPN = pa & TARGET_PAGE_MASK; | |
134 | tlb->PID = 0; | |
135 | ||
136 | tlb = &env->tlb.tlbe[1]; | |
137 | tlb->attr = 0; | |
138 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
a1f7f97b | 139 | tlb->size = 1U << 31; /* up to 0xffffffff */ |
72718e9a AG |
140 | tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; |
141 | tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; | |
142 | tlb->PID = 0; | |
143 | } | |
144 | ||
b10a04b5 AG |
145 | static void main_cpu_reset(void *opaque) |
146 | { | |
182fbbf2 AF |
147 | PowerPCCPU *cpu = opaque; |
148 | CPUPPCState *env = &cpu->env; | |
b10a04b5 | 149 | |
182fbbf2 | 150 | cpu_reset(CPU(cpu)); |
ab3dd749 | 151 | env->gpr[1] = (16 * MiB) - 8; |
b10a04b5 AG |
152 | env->gpr[3] = FDT_ADDR; |
153 | env->nip = entry; | |
72718e9a AG |
154 | |
155 | /* Create a mapping for the kernel. */ | |
156 | mmubooke_create_initial_mapping(env, 0, 0); | |
b10a04b5 AG |
157 | } |
158 | ||
3ef96221 | 159 | static void bamboo_init(MachineState *machine) |
2c9fade2 | 160 | { |
3ef96221 MA |
161 | const char *kernel_filename = machine->kernel_filename; |
162 | const char *kernel_cmdline = machine->kernel_cmdline; | |
163 | const char *initrd_filename = machine->initrd_filename; | |
2c9fade2 | 164 | unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; |
3e9f0113 | 165 | MemoryRegion *address_space_mem = get_system_memory(); |
68501502 | 166 | MemoryRegion *isa = g_new(MemoryRegion, 1); |
30f8ec76 | 167 | MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); |
a8170e5e AK |
168 | hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
169 | hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; | |
34ba1dc8 AG |
170 | qemu_irq *pic; |
171 | qemu_irq *irqs; | |
2c9fade2 | 172 | PCIBus *pcibus; |
322164e0 | 173 | PowerPCCPU *cpu; |
e2684c0b | 174 | CPUPPCState *env; |
2c9fade2 AJ |
175 | uint64_t elf_entry; |
176 | uint64_t elf_lowaddr; | |
f831f955 | 177 | hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
2c9fade2 | 178 | target_long initrd_size = 0; |
34ba1dc8 | 179 | DeviceState *dev; |
ceee6da6 | 180 | int success; |
2c9fade2 AJ |
181 | int i; |
182 | ||
376d7a2a | 183 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
322164e0 | 184 | env = &cpu->env; |
34ba1dc8 | 185 | |
00469dc3 | 186 | if (env->mmu_model != POWERPC_MMU_BOOKE) { |
6f76b817 AF |
187 | error_report("MMU model %i not supported by this machine", |
188 | env->mmu_model); | |
00469dc3 VP |
189 | exit(1); |
190 | } | |
191 | ||
182fbbf2 | 192 | qemu_register_reset(main_cpu_reset, cpu); |
a34a92b9 | 193 | ppc_booke_timers_init(cpu, 400000000, 0); |
34ba1dc8 AG |
194 | ppc_dcr_init(env, NULL, NULL); |
195 | ||
196 | /* interrupt controller */ | |
30f8ec76 | 197 | irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); |
34ba1dc8 AG |
198 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
199 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; | |
200 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); | |
201 | ||
202 | /* SDRAM controller */ | |
203 | memset(ram_bases, 0, sizeof(ram_bases)); | |
204 | memset(ram_sizes, 0, sizeof(ram_sizes)); | |
b28f0188 | 205 | ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, |
a0258e4a | 206 | ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); |
34ba1dc8 AG |
207 | /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ |
208 | ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, | |
209 | ram_bases, ram_sizes, 1); | |
210 | ||
211 | /* PCI */ | |
42c281a2 AF |
212 | dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, |
213 | PPC440EP_PCI_CONFIG, | |
34ba1dc8 AG |
214 | pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], |
215 | pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], | |
216 | NULL); | |
217 | pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); | |
218 | if (!pcibus) { | |
6f76b817 | 219 | error_report("couldn't create PCI controller"); |
34ba1dc8 AG |
220 | exit(1); |
221 | } | |
222 | ||
68501502 PB |
223 | memory_region_init_alias(isa, NULL, "isa_mmio", |
224 | get_system_io(), 0, PPC440EP_PCI_IOLEN); | |
225 | memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); | |
34ba1dc8 | 226 | |
9bca0edb | 227 | if (serial_hd(0) != NULL) { |
34ba1dc8 | 228 | serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], |
9bca0edb | 229 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
34ba1dc8 AG |
230 | DEVICE_BIG_ENDIAN); |
231 | } | |
9bca0edb | 232 | if (serial_hd(1) != NULL) { |
34ba1dc8 | 233 | serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], |
9bca0edb | 234 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
34ba1dc8 AG |
235 | DEVICE_BIG_ENDIAN); |
236 | } | |
2c9fade2 AJ |
237 | |
238 | if (pcibus) { | |
2c9fade2 AJ |
239 | /* Register network interfaces. */ |
240 | for (i = 0; i < nb_nics; i++) { | |
cb457d76 AL |
241 | /* There are no PCI NICs on the Bamboo board, but there are |
242 | * PCI slots, so we can pick whatever default model we want. */ | |
29b358f9 | 243 | pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); |
2c9fade2 AJ |
244 | } |
245 | } | |
246 | ||
247 | /* Load kernel. */ | |
248 | if (kernel_filename) { | |
25bda50a MF |
249 | success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, |
250 | NULL, NULL); | |
ceee6da6 | 251 | if (success < 0) { |
4366e1db | 252 | success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, |
6cdda0ff | 253 | &elf_lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE, |
7ef295ea | 254 | 0, 0); |
2c9fade2 AJ |
255 | entry = elf_entry; |
256 | loadaddr = elf_lowaddr; | |
257 | } | |
258 | /* XXX try again as binary */ | |
ceee6da6 | 259 | if (success < 0) { |
6f76b817 | 260 | error_report("could not load kernel '%s'", kernel_filename); |
2c9fade2 AJ |
261 | exit(1); |
262 | } | |
263 | } | |
264 | ||
265 | /* Load initrd. */ | |
266 | if (initrd_filename) { | |
ceee6da6 | 267 | initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, |
a0258e4a | 268 | machine->ram_size - RAMDISK_ADDR); |
2c9fade2 AJ |
269 | |
270 | if (initrd_size < 0) { | |
6f76b817 AF |
271 | error_report("could not load ram disk '%s' at %x", |
272 | initrd_filename, RAMDISK_ADDR); | |
2c9fade2 AJ |
273 | exit(1); |
274 | } | |
275 | } | |
276 | ||
277 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
278 | if (kernel_filename) { | |
a0258e4a | 279 | if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, |
ceee6da6 | 280 | initrd_size, kernel_cmdline) < 0) { |
6f76b817 | 281 | error_report("couldn't load device tree"); |
2c9fade2 AJ |
282 | exit(1); |
283 | } | |
2c9fade2 | 284 | } |
2c9fade2 AJ |
285 | } |
286 | ||
e264d29d | 287 | static void bamboo_machine_init(MachineClass *mc) |
f80f9ec9 | 288 | { |
e264d29d EH |
289 | mc->desc = "bamboo"; |
290 | mc->init = bamboo_init; | |
376d7a2a | 291 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); |
b28f0188 | 292 | mc->default_ram_id = "ppc4xx.sdram"; |
f80f9ec9 AL |
293 | } |
294 | ||
e264d29d | 295 | DEFINE_MACHINE("bamboo", bamboo_machine_init) |