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Commit | Line | Data |
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2c9fade2 | 1 | /* |
5cbdb3a3 | 2 | * QEMU PowerPC 440 Bamboo board emulation |
2c9fade2 AJ |
3 | * |
4 | * Copyright 2007 IBM Corporation. | |
5 | * Authors: | |
2d94af4b GZ |
6 | * Jerone Young <jyoung5@us.ibm.com> |
7 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
8 | * Hollis Blanchard <hollisb@us.ibm.com> | |
2c9fade2 AJ |
9 | * |
10 | * This work is licensed under the GNU GPL license version 2 or later. | |
11 | * | |
12 | */ | |
13 | ||
0d75590d | 14 | #include "qemu/osdep.h" |
ab3dd749 | 15 | #include "qemu/units.h" |
6f76b817 | 16 | #include "qemu/error-report.h" |
2c65db5e | 17 | #include "qemu/datadir.h" |
64b47457 | 18 | #include "qemu/error-report.h" |
1422e32d | 19 | #include "net/net.h" |
83c9f4ca PB |
20 | #include "hw/pci/pci.h" |
21 | #include "hw/boards.h" | |
9c17d615 | 22 | #include "sysemu/kvm.h" |
2c9fade2 | 23 | #include "kvm_ppc.h" |
9c17d615 | 24 | #include "sysemu/device_tree.h" |
83c9f4ca | 25 | #include "hw/loader.h" |
ca20cf32 | 26 | #include "elf.h" |
0d09e41a PB |
27 | #include "hw/char/serial.h" |
28 | #include "hw/ppc/ppc.h" | |
47b43a1f | 29 | #include "ppc405.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
71e8a915 | 31 | #include "sysemu/reset.h" |
83c9f4ca | 32 | #include "hw/sysbus.h" |
0270d74e PM |
33 | #include "hw/intc/ppc-uic.h" |
34 | #include "hw/qdev-properties.h" | |
35 | #include "qapi/error.h" | |
2c9fade2 AJ |
36 | |
37 | #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" | |
38 | ||
ceee6da6 HB |
39 | /* from u-boot */ |
40 | #define KERNEL_ADDR 0x1000000 | |
41 | #define FDT_ADDR 0x1800000 | |
42 | #define RAMDISK_ADDR 0x1900000 | |
43 | ||
3960b04d AG |
44 | #define PPC440EP_PCI_CONFIG 0xeec00000 |
45 | #define PPC440EP_PCI_INTACK 0xeed00000 | |
46 | #define PPC440EP_PCI_SPECIAL 0xeed00000 | |
47 | #define PPC440EP_PCI_REGS 0xef400000 | |
48 | #define PPC440EP_PCI_IO 0xe8000000 | |
49 | #define PPC440EP_PCI_IOLEN 0x00010000 | |
50 | ||
51 | #define PPC440EP_SDRAM_NR_BANKS 4 | |
52 | ||
7d8ccf58 | 53 | static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { |
ab3dd749 | 54 | 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 |
3960b04d AG |
55 | }; |
56 | ||
a8170e5e | 57 | static hwaddr entry; |
b10a04b5 | 58 | |
a8170e5e | 59 | static int bamboo_load_device_tree(hwaddr addr, |
2c9fade2 | 60 | uint32_t ramsize, |
a8170e5e AK |
61 | hwaddr initrd_base, |
62 | hwaddr initrd_size, | |
2c9fade2 AJ |
63 | const char *kernel_cmdline) |
64 | { | |
dbf916d8 | 65 | int ret = -1; |
5232fa59 | 66 | uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; |
5cea8590 | 67 | char *filename; |
7ec632b4 | 68 | int fdt_size; |
dbf916d8 | 69 | void *fdt; |
7dadd40c AG |
70 | uint32_t tb_freq = 400000000; |
71 | uint32_t clock_freq = 400000000; | |
2c9fade2 | 72 | |
5cea8590 PB |
73 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
74 | if (!filename) { | |
400431ef | 75 | return -1; |
5cea8590 PB |
76 | } |
77 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 78 | g_free(filename); |
5cea8590 | 79 | if (fdt == NULL) { |
400431ef | 80 | return -1; |
5cea8590 | 81 | } |
2c9fade2 AJ |
82 | |
83 | /* Manipulate device tree in memory. */ | |
84 | ||
5a4348d1 PC |
85 | ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, |
86 | sizeof(mem_reg_property)); | |
2c9fade2 AJ |
87 | if (ret < 0) |
88 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
89 | ||
5a4348d1 PC |
90 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
91 | initrd_base); | |
2c9fade2 AJ |
92 | if (ret < 0) |
93 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
94 | ||
5a4348d1 PC |
95 | ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
96 | (initrd_base + initrd_size)); | |
2c9fade2 AJ |
97 | if (ret < 0) |
98 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
99 | ||
5a4348d1 PC |
100 | ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
101 | kernel_cmdline); | |
2c9fade2 AJ |
102 | if (ret < 0) |
103 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
104 | ||
7dadd40c AG |
105 | /* Copy data from the host device tree into the guest. Since the guest can |
106 | * directly access the timebase without host involvement, we must expose | |
107 | * the correct frequencies. */ | |
a489f7f7 | 108 | if (kvm_enabled()) { |
7dadd40c AG |
109 | tb_freq = kvmppc_get_tbfreq(); |
110 | clock_freq = kvmppc_get_clockfreq(); | |
a489f7f7 | 111 | } |
2c9fade2 | 112 | |
5a4348d1 PC |
113 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", |
114 | clock_freq); | |
115 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", | |
116 | tb_freq); | |
2c9fade2 | 117 | |
fe1479aa | 118 | rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
7267c094 | 119 | g_free(fdt); |
fe1479aa | 120 | return 0; |
2c9fade2 AJ |
121 | } |
122 | ||
72718e9a | 123 | /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ |
e2684c0b | 124 | static void mmubooke_create_initial_mapping(CPUPPCState *env, |
72718e9a | 125 | target_ulong va, |
a8170e5e | 126 | hwaddr pa) |
72718e9a AG |
127 | { |
128 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; | |
129 | ||
130 | tlb->attr = 0; | |
131 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
a1f7f97b | 132 | tlb->size = 1U << 31; /* up to 0x80000000 */ |
72718e9a AG |
133 | tlb->EPN = va & TARGET_PAGE_MASK; |
134 | tlb->RPN = pa & TARGET_PAGE_MASK; | |
135 | tlb->PID = 0; | |
136 | ||
137 | tlb = &env->tlb.tlbe[1]; | |
138 | tlb->attr = 0; | |
139 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
a1f7f97b | 140 | tlb->size = 1U << 31; /* up to 0xffffffff */ |
72718e9a AG |
141 | tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; |
142 | tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; | |
143 | tlb->PID = 0; | |
144 | } | |
145 | ||
b10a04b5 AG |
146 | static void main_cpu_reset(void *opaque) |
147 | { | |
182fbbf2 AF |
148 | PowerPCCPU *cpu = opaque; |
149 | CPUPPCState *env = &cpu->env; | |
b10a04b5 | 150 | |
182fbbf2 | 151 | cpu_reset(CPU(cpu)); |
ab3dd749 | 152 | env->gpr[1] = (16 * MiB) - 8; |
b10a04b5 AG |
153 | env->gpr[3] = FDT_ADDR; |
154 | env->nip = entry; | |
72718e9a AG |
155 | |
156 | /* Create a mapping for the kernel. */ | |
157 | mmubooke_create_initial_mapping(env, 0, 0); | |
b10a04b5 AG |
158 | } |
159 | ||
3ef96221 | 160 | static void bamboo_init(MachineState *machine) |
2c9fade2 | 161 | { |
3ef96221 MA |
162 | const char *kernel_filename = machine->kernel_filename; |
163 | const char *kernel_cmdline = machine->kernel_cmdline; | |
164 | const char *initrd_filename = machine->initrd_filename; | |
2c9fade2 | 165 | unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; |
3e9f0113 | 166 | MemoryRegion *address_space_mem = get_system_memory(); |
68501502 | 167 | MemoryRegion *isa = g_new(MemoryRegion, 1); |
30f8ec76 | 168 | MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); |
a8170e5e AK |
169 | hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
170 | hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; | |
2c9fade2 | 171 | PCIBus *pcibus; |
322164e0 | 172 | PowerPCCPU *cpu; |
e2684c0b | 173 | CPUPPCState *env; |
2c9fade2 | 174 | target_long initrd_size = 0; |
34ba1dc8 | 175 | DeviceState *dev; |
0270d74e PM |
176 | DeviceState *uicdev; |
177 | SysBusDevice *uicsbd; | |
ceee6da6 | 178 | int success; |
2c9fade2 AJ |
179 | int i; |
180 | ||
376d7a2a | 181 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
322164e0 | 182 | env = &cpu->env; |
34ba1dc8 | 183 | |
00469dc3 | 184 | if (env->mmu_model != POWERPC_MMU_BOOKE) { |
6f76b817 AF |
185 | error_report("MMU model %i not supported by this machine", |
186 | env->mmu_model); | |
00469dc3 VP |
187 | exit(1); |
188 | } | |
189 | ||
182fbbf2 | 190 | qemu_register_reset(main_cpu_reset, cpu); |
a34a92b9 | 191 | ppc_booke_timers_init(cpu, 400000000, 0); |
34ba1dc8 AG |
192 | ppc_dcr_init(env, NULL, NULL); |
193 | ||
194 | /* interrupt controller */ | |
0270d74e PM |
195 | uicdev = qdev_new(TYPE_PPC_UIC); |
196 | uicsbd = SYS_BUS_DEVICE(uicdev); | |
197 | ||
198 | object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), | |
199 | &error_fatal); | |
200 | sysbus_realize_and_unref(uicsbd, &error_fatal); | |
201 | ||
202 | sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, | |
47b60fc6 | 203 | qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); |
0270d74e | 204 | sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, |
47b60fc6 | 205 | qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); |
34ba1dc8 AG |
206 | |
207 | /* SDRAM controller */ | |
208 | memset(ram_bases, 0, sizeof(ram_bases)); | |
209 | memset(ram_sizes, 0, sizeof(ram_sizes)); | |
b28f0188 | 210 | ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, |
a0258e4a | 211 | ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); |
34ba1dc8 | 212 | /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ |
0270d74e PM |
213 | ppc4xx_sdram_init(env, |
214 | qdev_get_gpio_in(uicdev, 14), | |
215 | PPC440EP_SDRAM_NR_BANKS, ram_memories, | |
34ba1dc8 AG |
216 | ram_bases, ram_sizes, 1); |
217 | ||
218 | /* PCI */ | |
42c281a2 AF |
219 | dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, |
220 | PPC440EP_PCI_CONFIG, | |
0270d74e PM |
221 | qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), |
222 | qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), | |
223 | qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), | |
224 | qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), | |
34ba1dc8 AG |
225 | NULL); |
226 | pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); | |
227 | if (!pcibus) { | |
6f76b817 | 228 | error_report("couldn't create PCI controller"); |
34ba1dc8 AG |
229 | exit(1); |
230 | } | |
231 | ||
68501502 PB |
232 | memory_region_init_alias(isa, NULL, "isa_mmio", |
233 | get_system_io(), 0, PPC440EP_PCI_IOLEN); | |
234 | memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); | |
34ba1dc8 | 235 | |
9bca0edb | 236 | if (serial_hd(0) != NULL) { |
0270d74e PM |
237 | serial_mm_init(address_space_mem, 0xef600300, 0, |
238 | qdev_get_gpio_in(uicdev, 0), | |
9bca0edb | 239 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
34ba1dc8 AG |
240 | DEVICE_BIG_ENDIAN); |
241 | } | |
9bca0edb | 242 | if (serial_hd(1) != NULL) { |
0270d74e PM |
243 | serial_mm_init(address_space_mem, 0xef600400, 0, |
244 | qdev_get_gpio_in(uicdev, 1), | |
9bca0edb | 245 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
34ba1dc8 AG |
246 | DEVICE_BIG_ENDIAN); |
247 | } | |
2c9fade2 AJ |
248 | |
249 | if (pcibus) { | |
2c9fade2 AJ |
250 | /* Register network interfaces. */ |
251 | for (i = 0; i < nb_nics; i++) { | |
cb457d76 AL |
252 | /* There are no PCI NICs on the Bamboo board, but there are |
253 | * PCI slots, so we can pick whatever default model we want. */ | |
29b358f9 | 254 | pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); |
2c9fade2 AJ |
255 | } |
256 | } | |
257 | ||
258 | /* Load kernel. */ | |
259 | if (kernel_filename) { | |
617160c9 | 260 | hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
25bda50a MF |
261 | success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, |
262 | NULL, NULL); | |
ceee6da6 | 263 | if (success < 0) { |
617160c9 | 264 | uint64_t elf_entry; |
4366e1db | 265 | success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, |
617160c9 | 266 | NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); |
2c9fade2 | 267 | entry = elf_entry; |
2c9fade2 AJ |
268 | } |
269 | /* XXX try again as binary */ | |
ceee6da6 | 270 | if (success < 0) { |
6f76b817 | 271 | error_report("could not load kernel '%s'", kernel_filename); |
2c9fade2 AJ |
272 | exit(1); |
273 | } | |
274 | } | |
275 | ||
276 | /* Load initrd. */ | |
277 | if (initrd_filename) { | |
ceee6da6 | 278 | initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, |
a0258e4a | 279 | machine->ram_size - RAMDISK_ADDR); |
2c9fade2 AJ |
280 | |
281 | if (initrd_size < 0) { | |
6f76b817 AF |
282 | error_report("could not load ram disk '%s' at %x", |
283 | initrd_filename, RAMDISK_ADDR); | |
2c9fade2 AJ |
284 | exit(1); |
285 | } | |
286 | } | |
287 | ||
288 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
289 | if (kernel_filename) { | |
a0258e4a | 290 | if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, |
ceee6da6 | 291 | initrd_size, kernel_cmdline) < 0) { |
6f76b817 | 292 | error_report("couldn't load device tree"); |
2c9fade2 AJ |
293 | exit(1); |
294 | } | |
2c9fade2 | 295 | } |
2c9fade2 AJ |
296 | } |
297 | ||
e264d29d | 298 | static void bamboo_machine_init(MachineClass *mc) |
f80f9ec9 | 299 | { |
e264d29d EH |
300 | mc->desc = "bamboo"; |
301 | mc->init = bamboo_init; | |
376d7a2a | 302 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); |
b28f0188 | 303 | mc->default_ram_id = "ppc4xx.sdram"; |
f80f9ec9 AL |
304 | } |
305 | ||
e264d29d | 306 | DEFINE_MACHINE("bamboo", bamboo_machine_init) |