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58d5b22b BZ |
1 | /* |
2 | * QEMU PowerPC 440 embedded processors emulation | |
3 | * | |
4 | * Copyright (c) 2012 François Revol | |
5 | * Copyright (c) 2016-2018 BALATON Zoltan | |
6 | * | |
7 | * This work is licensed under the GNU GPL license version 2 or later. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include "qemu/osdep.h" | |
fc6b3cf9 | 12 | #include "qemu/units.h" |
58d5b22b | 13 | #include "qemu-common.h" |
58d5b22b BZ |
14 | #include "qemu/error-report.h" |
15 | #include "qapi/error.h" | |
3c409c19 | 16 | #include "qemu/log.h" |
58d5b22b BZ |
17 | #include "cpu.h" |
18 | #include "hw/hw.h" | |
19 | #include "exec/address-spaces.h" | |
20 | #include "exec/memory.h" | |
21 | #include "hw/ppc/ppc.h" | |
22 | #include "hw/pci/pci.h" | |
23 | #include "sysemu/block-backend.h" | |
72a56a1f | 24 | #include "ppc440.h" |
58d5b22b BZ |
25 | |
26 | /*****************************************************************************/ | |
27 | /* L2 Cache as SRAM */ | |
28 | /* FIXME:fix names */ | |
29 | enum { | |
30 | DCR_L2CACHE_BASE = 0x30, | |
31 | DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, | |
32 | DCR_L2CACHE_CMD, | |
33 | DCR_L2CACHE_ADDR, | |
34 | DCR_L2CACHE_DATA, | |
35 | DCR_L2CACHE_STAT, | |
36 | DCR_L2CACHE_CVER, | |
37 | DCR_L2CACHE_SNP0, | |
38 | DCR_L2CACHE_SNP1, | |
39 | DCR_L2CACHE_END = DCR_L2CACHE_SNP1, | |
40 | }; | |
41 | ||
42 | /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ | |
43 | enum { | |
44 | DCR_ISRAM0_BASE = 0x20, | |
45 | DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, | |
46 | DCR_ISRAM0_SB1CR, | |
47 | DCR_ISRAM0_SB2CR, | |
48 | DCR_ISRAM0_SB3CR, | |
49 | DCR_ISRAM0_BEAR, | |
50 | DCR_ISRAM0_BESR0, | |
51 | DCR_ISRAM0_BESR1, | |
52 | DCR_ISRAM0_PMEG, | |
53 | DCR_ISRAM0_CID, | |
54 | DCR_ISRAM0_REVID, | |
55 | DCR_ISRAM0_DPC, | |
56 | DCR_ISRAM0_END = DCR_ISRAM0_DPC | |
57 | }; | |
58 | ||
59 | enum { | |
60 | DCR_ISRAM1_BASE = 0xb0, | |
61 | DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, | |
62 | /* single bank */ | |
63 | DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, | |
64 | DCR_ISRAM1_BESR0, | |
65 | DCR_ISRAM1_BESR1, | |
66 | DCR_ISRAM1_PMEG, | |
67 | DCR_ISRAM1_CID, | |
68 | DCR_ISRAM1_REVID, | |
69 | DCR_ISRAM1_DPC, | |
70 | DCR_ISRAM1_END = DCR_ISRAM1_DPC | |
71 | }; | |
72 | ||
73 | typedef struct ppc4xx_l2sram_t { | |
74 | MemoryRegion bank[4]; | |
75 | uint32_t l2cache[8]; | |
76 | uint32_t isram0[11]; | |
77 | } ppc4xx_l2sram_t; | |
78 | ||
79 | #ifdef MAP_L2SRAM | |
80 | static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, | |
81 | uint32_t isarc, uint32_t isacntl, | |
82 | uint32_t dsarc, uint32_t dsacntl) | |
83 | { | |
84 | if (l2sram->isarc != isarc || | |
85 | (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { | |
86 | if (l2sram->isacntl & 0x80000000) { | |
87 | /* Unmap previously assigned memory region */ | |
88 | memory_region_del_subregion(get_system_memory(), | |
89 | &l2sram->isarc_ram); | |
90 | } | |
91 | if (isacntl & 0x80000000) { | |
92 | /* Map new instruction memory region */ | |
93 | memory_region_add_subregion(get_system_memory(), isarc, | |
94 | &l2sram->isarc_ram); | |
95 | } | |
96 | } | |
97 | if (l2sram->dsarc != dsarc || | |
98 | (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { | |
99 | if (l2sram->dsacntl & 0x80000000) { | |
100 | /* Beware not to unmap the region we just mapped */ | |
101 | if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { | |
102 | /* Unmap previously assigned memory region */ | |
103 | memory_region_del_subregion(get_system_memory(), | |
104 | &l2sram->dsarc_ram); | |
105 | } | |
106 | } | |
107 | if (dsacntl & 0x80000000) { | |
108 | /* Beware not to remap the region we just mapped */ | |
109 | if (!(isacntl & 0x80000000) || dsarc != isarc) { | |
110 | /* Map new data memory region */ | |
111 | memory_region_add_subregion(get_system_memory(), dsarc, | |
112 | &l2sram->dsarc_ram); | |
113 | } | |
114 | } | |
115 | } | |
116 | } | |
117 | #endif | |
118 | ||
119 | static uint32_t dcr_read_l2sram(void *opaque, int dcrn) | |
120 | { | |
121 | ppc4xx_l2sram_t *l2sram = opaque; | |
122 | uint32_t ret = 0; | |
123 | ||
124 | switch (dcrn) { | |
125 | case DCR_L2CACHE_CFG: | |
126 | case DCR_L2CACHE_CMD: | |
127 | case DCR_L2CACHE_ADDR: | |
128 | case DCR_L2CACHE_DATA: | |
129 | case DCR_L2CACHE_STAT: | |
130 | case DCR_L2CACHE_CVER: | |
131 | case DCR_L2CACHE_SNP0: | |
132 | case DCR_L2CACHE_SNP1: | |
133 | ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; | |
134 | break; | |
135 | ||
136 | case DCR_ISRAM0_SB0CR: | |
137 | case DCR_ISRAM0_SB1CR: | |
138 | case DCR_ISRAM0_SB2CR: | |
139 | case DCR_ISRAM0_SB3CR: | |
140 | case DCR_ISRAM0_BEAR: | |
141 | case DCR_ISRAM0_BESR0: | |
142 | case DCR_ISRAM0_BESR1: | |
143 | case DCR_ISRAM0_PMEG: | |
144 | case DCR_ISRAM0_CID: | |
145 | case DCR_ISRAM0_REVID: | |
146 | case DCR_ISRAM0_DPC: | |
147 | ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; | |
148 | break; | |
149 | ||
150 | default: | |
151 | break; | |
152 | } | |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
157 | static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) | |
158 | { | |
159 | /*ppc4xx_l2sram_t *l2sram = opaque;*/ | |
160 | /* FIXME: Actually handle L2 cache mapping */ | |
161 | ||
162 | switch (dcrn) { | |
163 | case DCR_L2CACHE_CFG: | |
164 | case DCR_L2CACHE_CMD: | |
165 | case DCR_L2CACHE_ADDR: | |
166 | case DCR_L2CACHE_DATA: | |
167 | case DCR_L2CACHE_STAT: | |
168 | case DCR_L2CACHE_CVER: | |
169 | case DCR_L2CACHE_SNP0: | |
170 | case DCR_L2CACHE_SNP1: | |
171 | /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ | |
172 | break; | |
173 | ||
174 | case DCR_ISRAM0_SB0CR: | |
175 | case DCR_ISRAM0_SB1CR: | |
176 | case DCR_ISRAM0_SB2CR: | |
177 | case DCR_ISRAM0_SB3CR: | |
178 | case DCR_ISRAM0_BEAR: | |
179 | case DCR_ISRAM0_BESR0: | |
180 | case DCR_ISRAM0_BESR1: | |
181 | case DCR_ISRAM0_PMEG: | |
182 | case DCR_ISRAM0_CID: | |
183 | case DCR_ISRAM0_REVID: | |
184 | case DCR_ISRAM0_DPC: | |
185 | /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ | |
186 | break; | |
187 | ||
188 | case DCR_ISRAM1_SB0CR: | |
189 | case DCR_ISRAM1_BEAR: | |
190 | case DCR_ISRAM1_BESR0: | |
191 | case DCR_ISRAM1_BESR1: | |
192 | case DCR_ISRAM1_PMEG: | |
193 | case DCR_ISRAM1_CID: | |
194 | case DCR_ISRAM1_REVID: | |
195 | case DCR_ISRAM1_DPC: | |
196 | /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ | |
197 | break; | |
198 | } | |
199 | /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ | |
200 | } | |
201 | ||
202 | static void l2sram_reset(void *opaque) | |
203 | { | |
204 | ppc4xx_l2sram_t *l2sram = opaque; | |
205 | ||
206 | memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); | |
207 | l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; | |
208 | memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); | |
209 | /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ | |
210 | } | |
211 | ||
212 | void ppc4xx_l2sram_init(CPUPPCState *env) | |
213 | { | |
214 | ppc4xx_l2sram_t *l2sram; | |
215 | ||
216 | l2sram = g_malloc0(sizeof(*l2sram)); | |
217 | /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ | |
218 | memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", | |
d23b6caa | 219 | 64 * KiB, &error_abort); |
58d5b22b | 220 | memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", |
d23b6caa | 221 | 64 * KiB, &error_abort); |
58d5b22b | 222 | memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", |
d23b6caa | 223 | 64 * KiB, &error_abort); |
58d5b22b | 224 | memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", |
d23b6caa | 225 | 64 * KiB, &error_abort); |
58d5b22b BZ |
226 | qemu_register_reset(&l2sram_reset, l2sram); |
227 | ppc_dcr_register(env, DCR_L2CACHE_CFG, | |
228 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
229 | ppc_dcr_register(env, DCR_L2CACHE_CMD, | |
230 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
231 | ppc_dcr_register(env, DCR_L2CACHE_ADDR, | |
232 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
233 | ppc_dcr_register(env, DCR_L2CACHE_DATA, | |
234 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
235 | ppc_dcr_register(env, DCR_L2CACHE_STAT, | |
236 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
237 | ppc_dcr_register(env, DCR_L2CACHE_CVER, | |
238 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
239 | ppc_dcr_register(env, DCR_L2CACHE_SNP0, | |
240 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
241 | ppc_dcr_register(env, DCR_L2CACHE_SNP1, | |
242 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
243 | ||
244 | ppc_dcr_register(env, DCR_ISRAM0_SB0CR, | |
245 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
246 | ppc_dcr_register(env, DCR_ISRAM0_SB1CR, | |
247 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
248 | ppc_dcr_register(env, DCR_ISRAM0_SB2CR, | |
249 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
250 | ppc_dcr_register(env, DCR_ISRAM0_SB3CR, | |
251 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
252 | ppc_dcr_register(env, DCR_ISRAM0_PMEG, | |
253 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
254 | ppc_dcr_register(env, DCR_ISRAM0_DPC, | |
255 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
256 | ||
257 | ppc_dcr_register(env, DCR_ISRAM1_SB0CR, | |
258 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
259 | ppc_dcr_register(env, DCR_ISRAM1_PMEG, | |
260 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
261 | ppc_dcr_register(env, DCR_ISRAM1_DPC, | |
262 | l2sram, &dcr_read_l2sram, &dcr_write_l2sram); | |
263 | } | |
264 | ||
265 | /*****************************************************************************/ | |
266 | /* Clocking Power on Reset */ | |
267 | enum { | |
268 | CPR0_CFGADDR = 0xC, | |
269 | CPR0_CFGDATA = 0xD, | |
270 | ||
271 | CPR0_PLLD = 0x060, | |
272 | CPR0_PLBED = 0x080, | |
273 | CPR0_OPBD = 0x0C0, | |
274 | CPR0_PERD = 0x0E0, | |
275 | CPR0_AHBD = 0x100, | |
276 | }; | |
277 | ||
278 | typedef struct ppc4xx_cpr_t { | |
279 | uint32_t addr; | |
280 | } ppc4xx_cpr_t; | |
281 | ||
282 | static uint32_t dcr_read_cpr(void *opaque, int dcrn) | |
283 | { | |
284 | ppc4xx_cpr_t *cpr = opaque; | |
285 | uint32_t ret = 0; | |
286 | ||
287 | switch (dcrn) { | |
288 | case CPR0_CFGADDR: | |
289 | ret = cpr->addr; | |
290 | break; | |
291 | case CPR0_CFGDATA: | |
292 | switch (cpr->addr) { | |
293 | case CPR0_PLLD: | |
294 | ret = (0xb5 << 24) | (1 << 16) | (9 << 8); | |
295 | break; | |
296 | case CPR0_PLBED: | |
297 | ret = (5 << 24); | |
298 | break; | |
299 | case CPR0_OPBD: | |
300 | ret = (2 << 24); | |
301 | break; | |
302 | case CPR0_PERD: | |
303 | case CPR0_AHBD: | |
304 | ret = (1 << 24); | |
305 | break; | |
306 | default: | |
307 | break; | |
308 | } | |
309 | break; | |
310 | default: | |
311 | break; | |
312 | } | |
313 | ||
314 | return ret; | |
315 | } | |
316 | ||
317 | static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) | |
318 | { | |
319 | ppc4xx_cpr_t *cpr = opaque; | |
320 | ||
321 | switch (dcrn) { | |
322 | case CPR0_CFGADDR: | |
323 | cpr->addr = val; | |
324 | break; | |
325 | case CPR0_CFGDATA: | |
326 | break; | |
327 | default: | |
328 | break; | |
329 | } | |
330 | } | |
331 | ||
332 | static void ppc4xx_cpr_reset(void *opaque) | |
333 | { | |
334 | ppc4xx_cpr_t *cpr = opaque; | |
335 | ||
336 | cpr->addr = 0; | |
337 | } | |
338 | ||
339 | void ppc4xx_cpr_init(CPUPPCState *env) | |
340 | { | |
341 | ppc4xx_cpr_t *cpr; | |
342 | ||
343 | cpr = g_malloc0(sizeof(*cpr)); | |
344 | ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); | |
345 | ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); | |
346 | qemu_register_reset(ppc4xx_cpr_reset, cpr); | |
347 | } | |
348 | ||
349 | /*****************************************************************************/ | |
350 | /* System DCRs */ | |
351 | typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; | |
352 | struct ppc4xx_sdr_t { | |
353 | uint32_t addr; | |
354 | }; | |
355 | ||
356 | enum { | |
357 | SDR0_CFGADDR = 0x00e, | |
358 | SDR0_CFGDATA, | |
359 | SDR0_STRP0 = 0x020, | |
360 | SDR0_STRP1, | |
361 | SDR0_102 = 0x66, | |
362 | SDR0_103, | |
363 | SDR0_128 = 0x80, | |
364 | SDR0_ECID3 = 0x083, | |
365 | SDR0_DDR0 = 0x0e1, | |
366 | SDR0_USB0 = 0x320, | |
367 | }; | |
368 | ||
369 | enum { | |
370 | PESDR0_LOOP = 0x303, | |
371 | PESDR0_RCSSET, | |
372 | PESDR0_RCSSTS, | |
373 | PESDR0_RSTSTA = 0x310, | |
374 | PESDR1_LOOP = 0x343, | |
375 | PESDR1_RCSSET, | |
376 | PESDR1_RCSSTS, | |
377 | PESDR1_RSTSTA = 0x365, | |
378 | }; | |
379 | ||
380 | #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) | |
381 | #define SDR0_DDR0_DDRM_DDR1 0x20000000 | |
382 | #define SDR0_DDR0_DDRM_DDR2 0x40000000 | |
383 | ||
384 | static uint32_t dcr_read_sdr(void *opaque, int dcrn) | |
385 | { | |
386 | ppc4xx_sdr_t *sdr = opaque; | |
387 | uint32_t ret = 0; | |
388 | ||
389 | switch (dcrn) { | |
390 | case SDR0_CFGADDR: | |
391 | ret = sdr->addr; | |
392 | break; | |
393 | case SDR0_CFGDATA: | |
394 | switch (sdr->addr) { | |
395 | case SDR0_STRP0: | |
f8815532 | 396 | ret = (0xb5 << 8) | (1 << 4) | 9; |
58d5b22b BZ |
397 | break; |
398 | case SDR0_STRP1: | |
399 | ret = (5 << 29) | (2 << 26) | (1 << 24); | |
400 | break; | |
401 | case SDR0_ECID3: | |
402 | ret = 1 << 20; /* No Security/Kasumi support */ | |
403 | break; | |
404 | case SDR0_DDR0: | |
405 | ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; | |
406 | break; | |
407 | case PESDR0_RCSSET: | |
408 | case PESDR1_RCSSET: | |
409 | ret = (1 << 24) | (1 << 16); | |
410 | break; | |
411 | case PESDR0_RCSSTS: | |
412 | case PESDR1_RCSSTS: | |
413 | ret = (1 << 16) | (1 << 12); | |
414 | break; | |
415 | case PESDR0_RSTSTA: | |
416 | case PESDR1_RSTSTA: | |
417 | ret = 1; | |
418 | break; | |
419 | case PESDR0_LOOP: | |
420 | case PESDR1_LOOP: | |
421 | ret = 1 << 12; | |
422 | break; | |
423 | default: | |
424 | break; | |
425 | } | |
426 | break; | |
427 | default: | |
428 | break; | |
429 | } | |
430 | ||
431 | return ret; | |
432 | } | |
433 | ||
434 | static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) | |
435 | { | |
436 | ppc4xx_sdr_t *sdr = opaque; | |
437 | ||
438 | switch (dcrn) { | |
439 | case SDR0_CFGADDR: | |
440 | sdr->addr = val; | |
441 | break; | |
442 | case SDR0_CFGDATA: | |
443 | switch (sdr->addr) { | |
444 | case 0x00: /* B0CR */ | |
445 | break; | |
446 | default: | |
447 | break; | |
448 | } | |
449 | break; | |
450 | default: | |
451 | break; | |
452 | } | |
453 | } | |
454 | ||
455 | static void sdr_reset(void *opaque) | |
456 | { | |
457 | ppc4xx_sdr_t *sdr = opaque; | |
458 | ||
459 | sdr->addr = 0; | |
460 | } | |
461 | ||
462 | void ppc4xx_sdr_init(CPUPPCState *env) | |
463 | { | |
464 | ppc4xx_sdr_t *sdr; | |
465 | ||
466 | sdr = g_malloc0(sizeof(*sdr)); | |
467 | qemu_register_reset(&sdr_reset, sdr); | |
468 | ppc_dcr_register(env, SDR0_CFGADDR, | |
469 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
470 | ppc_dcr_register(env, SDR0_CFGDATA, | |
471 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
472 | ppc_dcr_register(env, SDR0_102, | |
473 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
474 | ppc_dcr_register(env, SDR0_103, | |
475 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
476 | ppc_dcr_register(env, SDR0_128, | |
477 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
478 | ppc_dcr_register(env, SDR0_USB0, | |
479 | sdr, &dcr_read_sdr, &dcr_write_sdr); | |
480 | } | |
481 | ||
482 | /*****************************************************************************/ | |
483 | /* SDRAM controller */ | |
484 | typedef struct ppc4xx_sdram_t { | |
485 | uint32_t addr; | |
486 | int nbanks; | |
487 | MemoryRegion containers[4]; /* used for clipping */ | |
488 | MemoryRegion *ram_memories; | |
489 | hwaddr ram_bases[4]; | |
490 | hwaddr ram_sizes[4]; | |
491 | uint32_t bcr[4]; | |
492 | } ppc4xx_sdram_t; | |
493 | ||
494 | enum { | |
495 | SDRAM0_CFGADDR = 0x10, | |
496 | SDRAM0_CFGDATA, | |
497 | SDRAM_R0BAS = 0x40, | |
498 | SDRAM_R1BAS, | |
499 | SDRAM_R2BAS, | |
500 | SDRAM_R3BAS, | |
501 | SDRAM_CONF1HB = 0x45, | |
502 | SDRAM_PLBADDULL = 0x4a, | |
503 | SDRAM_CONF1LL = 0x4b, | |
504 | SDRAM_CONFPATHB = 0x4f, | |
505 | SDRAM_PLBADDUHB = 0x50, | |
506 | }; | |
507 | ||
508 | /* XXX: TOFIX: some patches have made this code become inconsistent: | |
509 | * there are type inconsistencies, mixing hwaddr, target_ulong | |
510 | * and uint32_t | |
511 | */ | |
512 | static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) | |
513 | { | |
514 | uint32_t bcr; | |
515 | ||
516 | switch (ram_size) { | |
d23b6caa | 517 | case (8 * MiB): |
58d5b22b BZ |
518 | bcr = 0xffc0; |
519 | break; | |
d23b6caa | 520 | case (16 * MiB): |
58d5b22b BZ |
521 | bcr = 0xff80; |
522 | break; | |
d23b6caa | 523 | case (32 * MiB): |
58d5b22b BZ |
524 | bcr = 0xff00; |
525 | break; | |
d23b6caa | 526 | case (64 * MiB): |
58d5b22b BZ |
527 | bcr = 0xfe00; |
528 | break; | |
d23b6caa | 529 | case (128 * MiB): |
58d5b22b BZ |
530 | bcr = 0xfc00; |
531 | break; | |
d23b6caa | 532 | case (256 * MiB): |
58d5b22b BZ |
533 | bcr = 0xf800; |
534 | break; | |
d23b6caa | 535 | case (512 * MiB): |
58d5b22b BZ |
536 | bcr = 0xf000; |
537 | break; | |
d23b6caa | 538 | case (1 * GiB): |
58d5b22b BZ |
539 | bcr = 0xe000; |
540 | break; | |
541 | default: | |
542 | error_report("invalid RAM size " TARGET_FMT_plx, ram_size); | |
543 | return 0; | |
544 | } | |
545 | bcr |= ram_base & 0xFF800000; | |
546 | bcr |= 1; | |
547 | ||
548 | return bcr; | |
549 | } | |
550 | ||
551 | static inline hwaddr sdram_base(uint32_t bcr) | |
552 | { | |
553 | return bcr & 0xFF800000; | |
554 | } | |
555 | ||
556 | static target_ulong sdram_size(uint32_t bcr) | |
557 | { | |
558 | target_ulong size; | |
559 | int sh; | |
560 | ||
561 | sh = 1024 - ((bcr >> 6) & 0x3ff); | |
09a333ee | 562 | size = 8 * MiB * sh; |
58d5b22b BZ |
563 | |
564 | return size; | |
565 | } | |
566 | ||
567 | static void sdram_set_bcr(ppc4xx_sdram_t *sdram, | |
568 | uint32_t *bcrp, uint32_t bcr, int enabled) | |
569 | { | |
570 | unsigned n = bcrp - sdram->bcr; | |
571 | ||
572 | if (*bcrp & 1) { | |
573 | /* Unmap RAM */ | |
574 | memory_region_del_subregion(get_system_memory(), | |
575 | &sdram->containers[n]); | |
576 | memory_region_del_subregion(&sdram->containers[n], | |
577 | &sdram->ram_memories[n]); | |
578 | object_unparent(OBJECT(&sdram->containers[n])); | |
579 | } | |
580 | *bcrp = bcr & 0xFFDEE001; | |
581 | if (enabled && (bcr & 1)) { | |
582 | memory_region_init(&sdram->containers[n], NULL, "sdram-containers", | |
583 | sdram_size(bcr)); | |
584 | memory_region_add_subregion(&sdram->containers[n], 0, | |
585 | &sdram->ram_memories[n]); | |
586 | memory_region_add_subregion(get_system_memory(), | |
587 | sdram_base(bcr), | |
588 | &sdram->containers[n]); | |
589 | } | |
590 | } | |
591 | ||
592 | static void sdram_map_bcr(ppc4xx_sdram_t *sdram) | |
593 | { | |
594 | int i; | |
595 | ||
596 | for (i = 0; i < sdram->nbanks; i++) { | |
597 | if (sdram->ram_sizes[i] != 0) { | |
598 | sdram_set_bcr(sdram, | |
599 | &sdram->bcr[i], | |
600 | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), | |
601 | 1); | |
602 | } else { | |
603 | sdram_set_bcr(sdram, &sdram->bcr[i], 0, 0); | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | static uint32_t dcr_read_sdram(void *opaque, int dcrn) | |
609 | { | |
610 | ppc4xx_sdram_t *sdram = opaque; | |
611 | uint32_t ret = 0; | |
612 | ||
613 | switch (dcrn) { | |
614 | case SDRAM_R0BAS: | |
615 | case SDRAM_R1BAS: | |
616 | case SDRAM_R2BAS: | |
617 | case SDRAM_R3BAS: | |
618 | ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS], | |
619 | sdram->ram_sizes[dcrn - SDRAM_R0BAS]); | |
620 | break; | |
621 | case SDRAM_CONF1HB: | |
622 | case SDRAM_CONF1LL: | |
623 | case SDRAM_CONFPATHB: | |
624 | case SDRAM_PLBADDULL: | |
625 | case SDRAM_PLBADDUHB: | |
626 | break; | |
627 | case SDRAM0_CFGADDR: | |
628 | ret = sdram->addr; | |
629 | break; | |
630 | case SDRAM0_CFGDATA: | |
631 | switch (sdram->addr) { | |
632 | case 0x14: /* SDRAM_MCSTAT (405EX) */ | |
633 | case 0x1F: | |
634 | ret = 0x80000000; | |
635 | break; | |
636 | case 0x21: /* SDRAM_MCOPT2 */ | |
637 | ret = 0x08000000; | |
638 | break; | |
639 | case 0x40: /* SDRAM_MB0CF */ | |
640 | ret = 0x00008001; | |
641 | break; | |
642 | case 0x7A: /* SDRAM_DLCR */ | |
643 | ret = 0x02000000; | |
644 | break; | |
645 | case 0xE1: /* SDR0_DDR0 */ | |
646 | ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; | |
647 | break; | |
648 | default: | |
649 | break; | |
650 | } | |
651 | break; | |
652 | default: | |
653 | break; | |
654 | } | |
655 | ||
656 | return ret; | |
657 | } | |
658 | ||
659 | static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) | |
660 | { | |
661 | ppc4xx_sdram_t *sdram = opaque; | |
662 | ||
663 | switch (dcrn) { | |
664 | case SDRAM_R0BAS: | |
665 | case SDRAM_R1BAS: | |
666 | case SDRAM_R2BAS: | |
667 | case SDRAM_R3BAS: | |
668 | case SDRAM_CONF1HB: | |
669 | case SDRAM_CONF1LL: | |
670 | case SDRAM_CONFPATHB: | |
671 | case SDRAM_PLBADDULL: | |
672 | case SDRAM_PLBADDUHB: | |
673 | break; | |
674 | case SDRAM0_CFGADDR: | |
675 | sdram->addr = val; | |
676 | break; | |
677 | case SDRAM0_CFGDATA: | |
678 | switch (sdram->addr) { | |
679 | case 0x00: /* B0CR */ | |
680 | break; | |
681 | default: | |
682 | break; | |
683 | } | |
684 | break; | |
685 | default: | |
686 | break; | |
687 | } | |
688 | } | |
689 | ||
690 | static void sdram_reset(void *opaque) | |
691 | { | |
692 | ppc4xx_sdram_t *sdram = opaque; | |
693 | ||
694 | sdram->addr = 0; | |
695 | } | |
696 | ||
697 | void ppc440_sdram_init(CPUPPCState *env, int nbanks, | |
698 | MemoryRegion *ram_memories, | |
699 | hwaddr *ram_bases, hwaddr *ram_sizes, | |
700 | int do_init) | |
701 | { | |
702 | ppc4xx_sdram_t *sdram; | |
703 | ||
704 | sdram = g_malloc0(sizeof(*sdram)); | |
705 | sdram->nbanks = nbanks; | |
706 | sdram->ram_memories = ram_memories; | |
707 | memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); | |
708 | memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); | |
709 | qemu_register_reset(&sdram_reset, sdram); | |
710 | ppc_dcr_register(env, SDRAM0_CFGADDR, | |
711 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
712 | ppc_dcr_register(env, SDRAM0_CFGDATA, | |
713 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
714 | if (do_init) { | |
715 | sdram_map_bcr(sdram); | |
716 | } | |
717 | ||
718 | ppc_dcr_register(env, SDRAM_R0BAS, | |
719 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
720 | ppc_dcr_register(env, SDRAM_R1BAS, | |
721 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
722 | ppc_dcr_register(env, SDRAM_R2BAS, | |
723 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
724 | ppc_dcr_register(env, SDRAM_R3BAS, | |
725 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
726 | ppc_dcr_register(env, SDRAM_CONF1HB, | |
727 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
728 | ppc_dcr_register(env, SDRAM_PLBADDULL, | |
729 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
730 | ppc_dcr_register(env, SDRAM_CONF1LL, | |
731 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
732 | ppc_dcr_register(env, SDRAM_CONFPATHB, | |
733 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
734 | ppc_dcr_register(env, SDRAM_PLBADDUHB, | |
735 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
736 | } | |
737 | ||
738 | /*****************************************************************************/ | |
739 | /* PLB to AHB bridge */ | |
740 | enum { | |
741 | AHB_TOP = 0xA4, | |
742 | AHB_BOT = 0xA5, | |
743 | }; | |
744 | ||
745 | typedef struct ppc4xx_ahb_t { | |
746 | uint32_t top; | |
747 | uint32_t bot; | |
748 | } ppc4xx_ahb_t; | |
749 | ||
750 | static uint32_t dcr_read_ahb(void *opaque, int dcrn) | |
751 | { | |
752 | ppc4xx_ahb_t *ahb = opaque; | |
753 | uint32_t ret = 0; | |
754 | ||
755 | switch (dcrn) { | |
756 | case AHB_TOP: | |
757 | ret = ahb->top; | |
758 | break; | |
759 | case AHB_BOT: | |
760 | ret = ahb->bot; | |
761 | break; | |
762 | default: | |
763 | break; | |
764 | } | |
765 | ||
766 | return ret; | |
767 | } | |
768 | ||
769 | static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) | |
770 | { | |
771 | ppc4xx_ahb_t *ahb = opaque; | |
772 | ||
773 | switch (dcrn) { | |
774 | case AHB_TOP: | |
775 | ahb->top = val; | |
776 | break; | |
777 | case AHB_BOT: | |
778 | ahb->bot = val; | |
779 | break; | |
780 | } | |
781 | } | |
782 | ||
783 | static void ppc4xx_ahb_reset(void *opaque) | |
784 | { | |
785 | ppc4xx_ahb_t *ahb = opaque; | |
786 | ||
787 | /* No error */ | |
788 | ahb->top = 0; | |
789 | ahb->bot = 0; | |
790 | } | |
791 | ||
792 | void ppc4xx_ahb_init(CPUPPCState *env) | |
793 | { | |
794 | ppc4xx_ahb_t *ahb; | |
795 | ||
796 | ahb = g_malloc0(sizeof(*ahb)); | |
797 | ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); | |
798 | ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); | |
799 | qemu_register_reset(ppc4xx_ahb_reset, ahb); | |
800 | } | |
801 | ||
3c409c19 BZ |
802 | /*****************************************************************************/ |
803 | /* DMA controller */ | |
804 | ||
805 | #define DMA0_CR_CE (1 << 31) | |
806 | #define DMA0_CR_PW (1 << 26 | 1 << 25) | |
807 | #define DMA0_CR_DAI (1 << 24) | |
808 | #define DMA0_CR_SAI (1 << 23) | |
809 | #define DMA0_CR_DEC (1 << 2) | |
810 | ||
811 | enum { | |
812 | DMA0_CR = 0x00, | |
813 | DMA0_CT, | |
814 | DMA0_SAH, | |
815 | DMA0_SAL, | |
816 | DMA0_DAH, | |
817 | DMA0_DAL, | |
818 | DMA0_SGH, | |
819 | DMA0_SGL, | |
820 | ||
821 | DMA0_SR = 0x20, | |
822 | DMA0_SGC = 0x23, | |
823 | DMA0_SLP = 0x25, | |
824 | DMA0_POL = 0x26, | |
825 | }; | |
826 | ||
827 | typedef struct { | |
828 | uint32_t cr; | |
829 | uint32_t ct; | |
830 | uint64_t sa; | |
831 | uint64_t da; | |
832 | uint64_t sg; | |
833 | } PPC4xxDmaChnl; | |
834 | ||
835 | typedef struct { | |
836 | int base; | |
837 | PPC4xxDmaChnl ch[4]; | |
838 | uint32_t sr; | |
839 | } PPC4xxDmaState; | |
840 | ||
841 | static uint32_t dcr_read_dma(void *opaque, int dcrn) | |
842 | { | |
843 | PPC4xxDmaState *dma = opaque; | |
844 | uint32_t val = 0; | |
845 | int addr = dcrn - dma->base; | |
846 | int chnl = addr / 8; | |
847 | ||
848 | switch (addr) { | |
849 | case 0x00 ... 0x1f: | |
850 | switch (addr % 8) { | |
851 | case DMA0_CR: | |
852 | val = dma->ch[chnl].cr; | |
853 | break; | |
854 | case DMA0_CT: | |
855 | val = dma->ch[chnl].ct; | |
856 | break; | |
857 | case DMA0_SAH: | |
858 | val = dma->ch[chnl].sa >> 32; | |
859 | break; | |
860 | case DMA0_SAL: | |
861 | val = dma->ch[chnl].sa; | |
862 | break; | |
863 | case DMA0_DAH: | |
864 | val = dma->ch[chnl].da >> 32; | |
865 | break; | |
866 | case DMA0_DAL: | |
867 | val = dma->ch[chnl].da; | |
868 | break; | |
869 | case DMA0_SGH: | |
870 | val = dma->ch[chnl].sg >> 32; | |
871 | break; | |
872 | case DMA0_SGL: | |
873 | val = dma->ch[chnl].sg; | |
874 | break; | |
875 | } | |
876 | break; | |
877 | case DMA0_SR: | |
878 | val = dma->sr; | |
879 | break; | |
880 | default: | |
881 | qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", | |
882 | __func__, dcrn, chnl, addr); | |
883 | } | |
884 | ||
885 | return val; | |
886 | } | |
887 | ||
888 | static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) | |
889 | { | |
890 | PPC4xxDmaState *dma = opaque; | |
891 | int addr = dcrn - dma->base; | |
892 | int chnl = addr / 8; | |
893 | ||
894 | switch (addr) { | |
895 | case 0x00 ... 0x1f: | |
896 | switch (addr % 8) { | |
897 | case DMA0_CR: | |
898 | dma->ch[chnl].cr = val; | |
899 | if (val & DMA0_CR_CE) { | |
900 | int count = dma->ch[chnl].ct & 0xffff; | |
901 | ||
902 | if (count) { | |
903 | int width, i, sidx, didx; | |
904 | uint8_t *rptr, *wptr; | |
905 | hwaddr rlen, wlen; | |
906 | ||
907 | sidx = didx = 0; | |
908 | width = 1 << ((val & DMA0_CR_PW) >> 25); | |
909 | rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0); | |
910 | wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1); | |
911 | if (rptr && wptr) { | |
912 | if (!(val & DMA0_CR_DEC) && | |
913 | val & DMA0_CR_SAI && val & DMA0_CR_DAI) { | |
914 | /* optimise common case */ | |
915 | memmove(wptr, rptr, count * width); | |
916 | sidx = didx = count * width; | |
917 | } else { | |
918 | /* do it the slow way */ | |
919 | for (sidx = didx = i = 0; i < count; i++) { | |
920 | uint64_t v = ldn_le_p(rptr + sidx, width); | |
921 | stn_le_p(wptr + didx, width, v); | |
922 | if (val & DMA0_CR_SAI) { | |
923 | sidx += width; | |
924 | } | |
925 | if (val & DMA0_CR_DAI) { | |
926 | didx += width; | |
927 | } | |
928 | } | |
929 | } | |
930 | } | |
931 | if (wptr) { | |
932 | cpu_physical_memory_unmap(wptr, wlen, 1, didx); | |
933 | } | |
7aeb1e51 | 934 | if (rptr) { |
3c409c19 BZ |
935 | cpu_physical_memory_unmap(rptr, rlen, 0, sidx); |
936 | } | |
937 | } | |
938 | } | |
939 | break; | |
940 | case DMA0_CT: | |
941 | dma->ch[chnl].ct = val; | |
942 | break; | |
943 | case DMA0_SAH: | |
944 | dma->ch[chnl].sa &= 0xffffffffULL; | |
945 | dma->ch[chnl].sa |= (uint64_t)val << 32; | |
946 | break; | |
947 | case DMA0_SAL: | |
948 | dma->ch[chnl].sa &= 0xffffffff00000000ULL; | |
949 | dma->ch[chnl].sa |= val; | |
950 | break; | |
951 | case DMA0_DAH: | |
952 | dma->ch[chnl].da &= 0xffffffffULL; | |
953 | dma->ch[chnl].da |= (uint64_t)val << 32; | |
954 | break; | |
955 | case DMA0_DAL: | |
956 | dma->ch[chnl].da &= 0xffffffff00000000ULL; | |
957 | dma->ch[chnl].da |= val; | |
958 | break; | |
959 | case DMA0_SGH: | |
960 | dma->ch[chnl].sg &= 0xffffffffULL; | |
961 | dma->ch[chnl].sg |= (uint64_t)val << 32; | |
962 | break; | |
963 | case DMA0_SGL: | |
964 | dma->ch[chnl].sg &= 0xffffffff00000000ULL; | |
965 | dma->ch[chnl].sg |= val; | |
966 | break; | |
967 | } | |
968 | break; | |
969 | case DMA0_SR: | |
970 | dma->sr &= ~val; | |
971 | break; | |
972 | default: | |
973 | qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", | |
974 | __func__, dcrn, chnl, addr); | |
975 | } | |
976 | } | |
977 | ||
978 | static void ppc4xx_dma_reset(void *opaque) | |
979 | { | |
980 | PPC4xxDmaState *dma = opaque; | |
981 | int dma_base = dma->base; | |
982 | ||
983 | memset(dma, 0, sizeof(*dma)); | |
984 | dma->base = dma_base; | |
985 | } | |
986 | ||
987 | void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) | |
988 | { | |
989 | PPC4xxDmaState *dma; | |
990 | int i; | |
991 | ||
992 | dma = g_malloc0(sizeof(*dma)); | |
993 | dma->base = dcr_base; | |
994 | qemu_register_reset(&ppc4xx_dma_reset, dma); | |
995 | for (i = 0; i < 4; i++) { | |
996 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR, | |
997 | dma, &dcr_read_dma, &dcr_write_dma); | |
998 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT, | |
999 | dma, &dcr_read_dma, &dcr_write_dma); | |
1000 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH, | |
1001 | dma, &dcr_read_dma, &dcr_write_dma); | |
1002 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL, | |
1003 | dma, &dcr_read_dma, &dcr_write_dma); | |
1004 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH, | |
1005 | dma, &dcr_read_dma, &dcr_write_dma); | |
1006 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL, | |
1007 | dma, &dcr_read_dma, &dcr_write_dma); | |
1008 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH, | |
1009 | dma, &dcr_read_dma, &dcr_write_dma); | |
1010 | ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL, | |
1011 | dma, &dcr_read_dma, &dcr_write_dma); | |
1012 | } | |
1013 | ppc_dcr_register(env, dcr_base + DMA0_SR, | |
1014 | dma, &dcr_read_dma, &dcr_write_dma); | |
1015 | ppc_dcr_register(env, dcr_base + DMA0_SGC, | |
1016 | dma, &dcr_read_dma, &dcr_write_dma); | |
1017 | ppc_dcr_register(env, dcr_base + DMA0_SLP, | |
1018 | dma, &dcr_read_dma, &dcr_write_dma); | |
1019 | ppc_dcr_register(env, dcr_base + DMA0_POL, | |
1020 | dma, &dcr_read_dma, &dcr_write_dma); | |
1021 | } | |
1022 | ||
58d5b22b BZ |
1023 | /*****************************************************************************/ |
1024 | /* PCI Express controller */ | |
1025 | /* FIXME: This is not complete and does not work, only implemented partially | |
1026 | * to allow firmware and guests to find an empty bus. Cards should use PCI. | |
1027 | */ | |
1028 | #include "hw/pci/pcie_host.h" | |
1029 | ||
1030 | #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" | |
1031 | #define PPC460EX_PCIE_HOST(obj) \ | |
1032 | OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST) | |
1033 | ||
1034 | typedef struct PPC460EXPCIEState { | |
1035 | PCIExpressHost host; | |
1036 | ||
1037 | MemoryRegion iomem; | |
1038 | qemu_irq irq[4]; | |
1039 | int32_t dcrn_base; | |
1040 | ||
1041 | uint64_t cfg_base; | |
1042 | uint32_t cfg_mask; | |
1043 | uint64_t msg_base; | |
1044 | uint32_t msg_mask; | |
1045 | uint64_t omr1_base; | |
1046 | uint64_t omr1_mask; | |
1047 | uint64_t omr2_base; | |
1048 | uint64_t omr2_mask; | |
1049 | uint64_t omr3_base; | |
1050 | uint64_t omr3_mask; | |
1051 | uint64_t reg_base; | |
1052 | uint32_t reg_mask; | |
1053 | uint32_t special; | |
1054 | uint32_t cfg; | |
1055 | } PPC460EXPCIEState; | |
1056 | ||
1057 | #define DCRN_PCIE0_BASE 0x100 | |
1058 | #define DCRN_PCIE1_BASE 0x120 | |
1059 | ||
1060 | enum { | |
1061 | PEGPL_CFGBAH = 0x0, | |
1062 | PEGPL_CFGBAL, | |
1063 | PEGPL_CFGMSK, | |
1064 | PEGPL_MSGBAH, | |
1065 | PEGPL_MSGBAL, | |
1066 | PEGPL_MSGMSK, | |
1067 | PEGPL_OMR1BAH, | |
1068 | PEGPL_OMR1BAL, | |
1069 | PEGPL_OMR1MSKH, | |
1070 | PEGPL_OMR1MSKL, | |
1071 | PEGPL_OMR2BAH, | |
1072 | PEGPL_OMR2BAL, | |
1073 | PEGPL_OMR2MSKH, | |
1074 | PEGPL_OMR2MSKL, | |
1075 | PEGPL_OMR3BAH, | |
1076 | PEGPL_OMR3BAL, | |
1077 | PEGPL_OMR3MSKH, | |
1078 | PEGPL_OMR3MSKL, | |
1079 | PEGPL_REGBAH, | |
1080 | PEGPL_REGBAL, | |
1081 | PEGPL_REGMSK, | |
1082 | PEGPL_SPECIAL, | |
1083 | PEGPL_CFG, | |
1084 | }; | |
1085 | ||
1086 | static uint32_t dcr_read_pcie(void *opaque, int dcrn) | |
1087 | { | |
1088 | PPC460EXPCIEState *state = opaque; | |
1089 | uint32_t ret = 0; | |
1090 | ||
1091 | switch (dcrn - state->dcrn_base) { | |
1092 | case PEGPL_CFGBAH: | |
1093 | ret = state->cfg_base >> 32; | |
1094 | break; | |
1095 | case PEGPL_CFGBAL: | |
1096 | ret = state->cfg_base; | |
1097 | break; | |
1098 | case PEGPL_CFGMSK: | |
1099 | ret = state->cfg_mask; | |
1100 | break; | |
1101 | case PEGPL_MSGBAH: | |
1102 | ret = state->msg_base >> 32; | |
1103 | break; | |
1104 | case PEGPL_MSGBAL: | |
1105 | ret = state->msg_base; | |
1106 | break; | |
1107 | case PEGPL_MSGMSK: | |
1108 | ret = state->msg_mask; | |
1109 | break; | |
1110 | case PEGPL_OMR1BAH: | |
1111 | ret = state->omr1_base >> 32; | |
1112 | break; | |
1113 | case PEGPL_OMR1BAL: | |
1114 | ret = state->omr1_base; | |
1115 | break; | |
1116 | case PEGPL_OMR1MSKH: | |
1117 | ret = state->omr1_mask >> 32; | |
1118 | break; | |
1119 | case PEGPL_OMR1MSKL: | |
1120 | ret = state->omr1_mask; | |
1121 | break; | |
1122 | case PEGPL_OMR2BAH: | |
1123 | ret = state->omr2_base >> 32; | |
1124 | break; | |
1125 | case PEGPL_OMR2BAL: | |
1126 | ret = state->omr2_base; | |
1127 | break; | |
1128 | case PEGPL_OMR2MSKH: | |
1129 | ret = state->omr2_mask >> 32; | |
1130 | break; | |
1131 | case PEGPL_OMR2MSKL: | |
1132 | ret = state->omr3_mask; | |
1133 | break; | |
1134 | case PEGPL_OMR3BAH: | |
1135 | ret = state->omr3_base >> 32; | |
1136 | break; | |
1137 | case PEGPL_OMR3BAL: | |
1138 | ret = state->omr3_base; | |
1139 | break; | |
1140 | case PEGPL_OMR3MSKH: | |
1141 | ret = state->omr3_mask >> 32; | |
1142 | break; | |
1143 | case PEGPL_OMR3MSKL: | |
1144 | ret = state->omr3_mask; | |
1145 | break; | |
1146 | case PEGPL_REGBAH: | |
1147 | ret = state->reg_base >> 32; | |
1148 | break; | |
1149 | case PEGPL_REGBAL: | |
1150 | ret = state->reg_base; | |
1151 | break; | |
1152 | case PEGPL_REGMSK: | |
1153 | ret = state->reg_mask; | |
1154 | break; | |
1155 | case PEGPL_SPECIAL: | |
1156 | ret = state->special; | |
1157 | break; | |
1158 | case PEGPL_CFG: | |
1159 | ret = state->cfg; | |
1160 | break; | |
1161 | } | |
1162 | ||
1163 | return ret; | |
1164 | } | |
1165 | ||
1166 | static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) | |
1167 | { | |
1168 | PPC460EXPCIEState *s = opaque; | |
1169 | uint64_t size; | |
1170 | ||
1171 | switch (dcrn - s->dcrn_base) { | |
1172 | case PEGPL_CFGBAH: | |
1173 | s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); | |
1174 | break; | |
1175 | case PEGPL_CFGBAL: | |
1176 | s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; | |
1177 | break; | |
1178 | case PEGPL_CFGMSK: | |
1179 | s->cfg_mask = val; | |
1180 | size = ~(val & 0xfffffffe) + 1; | |
1181 | qemu_mutex_lock_iothread(); | |
1182 | pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); | |
1183 | qemu_mutex_unlock_iothread(); | |
1184 | break; | |
1185 | case PEGPL_MSGBAH: | |
1186 | s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); | |
1187 | break; | |
1188 | case PEGPL_MSGBAL: | |
1189 | s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; | |
1190 | break; | |
1191 | case PEGPL_MSGMSK: | |
1192 | s->msg_mask = val; | |
1193 | break; | |
1194 | case PEGPL_OMR1BAH: | |
1195 | s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); | |
1196 | break; | |
1197 | case PEGPL_OMR1BAL: | |
1198 | s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; | |
1199 | break; | |
1200 | case PEGPL_OMR1MSKH: | |
1201 | s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); | |
1202 | break; | |
1203 | case PEGPL_OMR1MSKL: | |
1204 | s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; | |
1205 | break; | |
1206 | case PEGPL_OMR2BAH: | |
1207 | s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); | |
1208 | break; | |
1209 | case PEGPL_OMR2BAL: | |
1210 | s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; | |
1211 | break; | |
1212 | case PEGPL_OMR2MSKH: | |
1213 | s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); | |
1214 | break; | |
1215 | case PEGPL_OMR2MSKL: | |
1216 | s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; | |
1217 | break; | |
1218 | case PEGPL_OMR3BAH: | |
1219 | s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); | |
1220 | break; | |
1221 | case PEGPL_OMR3BAL: | |
1222 | s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; | |
1223 | break; | |
1224 | case PEGPL_OMR3MSKH: | |
1225 | s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); | |
1226 | break; | |
1227 | case PEGPL_OMR3MSKL: | |
1228 | s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; | |
1229 | break; | |
1230 | case PEGPL_REGBAH: | |
1231 | s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); | |
1232 | break; | |
1233 | case PEGPL_REGBAL: | |
1234 | s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; | |
1235 | break; | |
1236 | case PEGPL_REGMSK: | |
1237 | s->reg_mask = val; | |
1238 | /* FIXME: how is size encoded? */ | |
1239 | size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); | |
1240 | break; | |
1241 | case PEGPL_SPECIAL: | |
1242 | s->special = val; | |
1243 | break; | |
1244 | case PEGPL_CFG: | |
1245 | s->cfg = val; | |
1246 | break; | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | static void ppc460ex_set_irq(void *opaque, int irq_num, int level) | |
1251 | { | |
1252 | PPC460EXPCIEState *s = opaque; | |
1253 | qemu_set_irq(s->irq[irq_num], level); | |
1254 | } | |
1255 | ||
1256 | static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) | |
1257 | { | |
1258 | PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); | |
1259 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); | |
1260 | int i, id; | |
1261 | char buf[16]; | |
1262 | ||
1263 | switch (s->dcrn_base) { | |
1264 | case DCRN_PCIE0_BASE: | |
1265 | id = 0; | |
1266 | break; | |
1267 | case DCRN_PCIE1_BASE: | |
1268 | id = 1; | |
1269 | break; | |
ff22e0eb BZ |
1270 | default: |
1271 | error_setg(errp, "invalid PCIe DCRN base"); | |
1272 | return; | |
58d5b22b BZ |
1273 | } |
1274 | snprintf(buf, sizeof(buf), "pcie%d-io", id); | |
1275 | memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); | |
1276 | for (i = 0; i < 4; i++) { | |
1277 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); | |
1278 | } | |
1279 | snprintf(buf, sizeof(buf), "pcie.%d", id); | |
1280 | pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, | |
1281 | pci_swizzle_map_irq_fn, s, &s->iomem, | |
1282 | get_system_io(), 0, 4, TYPE_PCIE_BUS); | |
1283 | } | |
1284 | ||
1285 | static Property ppc460ex_pcie_props[] = { | |
1286 | DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), | |
1287 | DEFINE_PROP_END_OF_LIST(), | |
1288 | }; | |
1289 | ||
1290 | static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) | |
1291 | { | |
1292 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1293 | ||
1294 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
1295 | dc->realize = ppc460ex_pcie_realize; | |
1296 | dc->props = ppc460ex_pcie_props; | |
1297 | dc->hotpluggable = false; | |
1298 | } | |
1299 | ||
1300 | static const TypeInfo ppc460ex_pcie_host_info = { | |
1301 | .name = TYPE_PPC460EX_PCIE_HOST, | |
1302 | .parent = TYPE_PCIE_HOST_BRIDGE, | |
1303 | .instance_size = sizeof(PPC460EXPCIEState), | |
1304 | .class_init = ppc460ex_pcie_class_init, | |
1305 | }; | |
1306 | ||
1307 | static void ppc460ex_pcie_register(void) | |
1308 | { | |
1309 | type_register_static(&ppc460ex_pcie_host_info); | |
1310 | } | |
1311 | ||
1312 | type_init(ppc460ex_pcie_register) | |
1313 | ||
1314 | static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) | |
1315 | { | |
1316 | ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, | |
1317 | &dcr_read_pcie, &dcr_write_pcie); | |
1318 | ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, | |
1319 | &dcr_read_pcie, &dcr_write_pcie); | |
1320 | ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, | |
1321 | &dcr_read_pcie, &dcr_write_pcie); | |
1322 | ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, | |
1323 | &dcr_read_pcie, &dcr_write_pcie); | |
1324 | ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, | |
1325 | &dcr_read_pcie, &dcr_write_pcie); | |
1326 | ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, | |
1327 | &dcr_read_pcie, &dcr_write_pcie); | |
1328 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, | |
1329 | &dcr_read_pcie, &dcr_write_pcie); | |
1330 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, | |
1331 | &dcr_read_pcie, &dcr_write_pcie); | |
1332 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, | |
1333 | &dcr_read_pcie, &dcr_write_pcie); | |
1334 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, | |
1335 | &dcr_read_pcie, &dcr_write_pcie); | |
1336 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, | |
1337 | &dcr_read_pcie, &dcr_write_pcie); | |
1338 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, | |
1339 | &dcr_read_pcie, &dcr_write_pcie); | |
1340 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, | |
1341 | &dcr_read_pcie, &dcr_write_pcie); | |
1342 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, | |
1343 | &dcr_read_pcie, &dcr_write_pcie); | |
1344 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, | |
1345 | &dcr_read_pcie, &dcr_write_pcie); | |
1346 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, | |
1347 | &dcr_read_pcie, &dcr_write_pcie); | |
1348 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, | |
1349 | &dcr_read_pcie, &dcr_write_pcie); | |
1350 | ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, | |
1351 | &dcr_read_pcie, &dcr_write_pcie); | |
1352 | ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, | |
1353 | &dcr_read_pcie, &dcr_write_pcie); | |
1354 | ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, | |
1355 | &dcr_read_pcie, &dcr_write_pcie); | |
1356 | ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, | |
1357 | &dcr_read_pcie, &dcr_write_pcie); | |
1358 | ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, | |
1359 | &dcr_read_pcie, &dcr_write_pcie); | |
1360 | ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, | |
1361 | &dcr_read_pcie, &dcr_write_pcie); | |
1362 | } | |
1363 | ||
1364 | void ppc460ex_pcie_init(CPUPPCState *env) | |
1365 | { | |
1366 | DeviceState *dev; | |
1367 | ||
1368 | dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); | |
1369 | qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); | |
1370 | qdev_init_nofail(dev); | |
1371 | object_property_set_bool(OBJECT(dev), true, "realized", NULL); | |
1372 | ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); | |
1373 | ||
1374 | dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); | |
1375 | qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); | |
1376 | qdev_init_nofail(dev); | |
1377 | object_property_set_bool(OBJECT(dev), true, "realized", NULL); | |
1378 | ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); | |
1379 | } |