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Commit | Line | Data |
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008ff9d7 JM |
1 | /* |
2 | * QEMU PowerPC 4xx embedded processors shared devices emulation | |
3 | * | |
4 | * Copyright (c) 2007 Jocelyn Mayer | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
71e8a915 | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
ab3dd749 | 26 | #include "qemu/units.h" |
71e8a915 | 27 | #include "sysemu/reset.h" |
33c11879 | 28 | #include "cpu.h" |
64552b6b | 29 | #include "hw/irq.h" |
0d09e41a PB |
30 | #include "hw/ppc/ppc.h" |
31 | #include "hw/ppc/ppc4xx.h" | |
e938ba0c | 32 | #include "hw/boards.h" |
1de7afc9 | 33 | #include "qemu/log.h" |
022c62cb | 34 | #include "exec/address-spaces.h" |
ab3dd749 | 35 | #include "qemu/error-report.h" |
008ff9d7 | 36 | |
a0557225 | 37 | /*#define DEBUG_UIC*/ |
d12d51d5 AL |
38 | |
39 | #ifdef DEBUG_UIC | |
93fcfe39 | 40 | # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
d12d51d5 AL |
41 | #else |
42 | # define LOG_UIC(...) do { } while (0) | |
43 | #endif | |
44 | ||
1bba0dc9 AF |
45 | static void ppc4xx_reset(void *opaque) |
46 | { | |
90cb09d9 | 47 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 48 | |
90cb09d9 | 49 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
50 | } |
51 | ||
008ff9d7 | 52 | /*****************************************************************************/ |
60b14d95 | 53 | /* Generic PowerPC 4xx processor instantiation */ |
9391b8c5 | 54 | PowerPCCPU *ppc4xx_init(const char *cpu_type, |
2f9859fb AF |
55 | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
56 | uint32_t sysclk) | |
008ff9d7 | 57 | { |
57274713 | 58 | PowerPCCPU *cpu; |
e2684c0b | 59 | CPUPPCState *env; |
008ff9d7 JM |
60 | |
61 | /* init CPUs */ | |
9391b8c5 | 62 | cpu = POWERPC_CPU(cpu_create(cpu_type)); |
57274713 AF |
63 | env = &cpu->env; |
64 | ||
008ff9d7 JM |
65 | cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
66 | cpu_clk->opaque = env; | |
67 | /* Set time-base frequency to sysclk */ | |
ddd1055b | 68 | tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT); |
008ff9d7 JM |
69 | tb_clk->opaque = env; |
70 | ppc_dcr_init(env, NULL, NULL); | |
71 | /* Register qemu callbacks */ | |
90cb09d9 | 72 | qemu_register_reset(ppc4xx_reset, cpu); |
008ff9d7 | 73 | |
2f9859fb | 74 | return cpu; |
008ff9d7 JM |
75 | } |
76 | ||
008ff9d7 JM |
77 | /*****************************************************************************/ |
78 | /* "Universal" Interrupt controller */ | |
79 | enum { | |
80 | DCR_UICSR = 0x000, | |
81 | DCR_UICSRS = 0x001, | |
82 | DCR_UICER = 0x002, | |
83 | DCR_UICCR = 0x003, | |
84 | DCR_UICPR = 0x004, | |
85 | DCR_UICTR = 0x005, | |
86 | DCR_UICMSR = 0x006, | |
87 | DCR_UICVR = 0x007, | |
88 | DCR_UICVCR = 0x008, | |
89 | DCR_UICMAX = 0x009, | |
90 | }; | |
91 | ||
92 | #define UIC_MAX_IRQ 32 | |
c227f099 AL |
93 | typedef struct ppcuic_t ppcuic_t; |
94 | struct ppcuic_t { | |
008ff9d7 JM |
95 | uint32_t dcr_base; |
96 | int use_vectors; | |
4c54e875 | 97 | uint32_t level; /* Remembers the state of level-triggered interrupts. */ |
008ff9d7 JM |
98 | uint32_t uicsr; /* Status register */ |
99 | uint32_t uicer; /* Enable register */ | |
100 | uint32_t uiccr; /* Critical register */ | |
101 | uint32_t uicpr; /* Polarity register */ | |
102 | uint32_t uictr; /* Triggering register */ | |
103 | uint32_t uicvcr; /* Vector configuration register */ | |
104 | uint32_t uicvr; | |
105 | qemu_irq *irqs; | |
106 | }; | |
107 | ||
c227f099 | 108 | static void ppcuic_trigger_irq (ppcuic_t *uic) |
008ff9d7 JM |
109 | { |
110 | uint32_t ir, cr; | |
111 | int start, end, inc, i; | |
112 | ||
113 | /* Trigger interrupt if any is pending */ | |
114 | ir = uic->uicsr & uic->uicer & (~uic->uiccr); | |
115 | cr = uic->uicsr & uic->uicer & uic->uiccr; | |
d12d51d5 | 116 | LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
aae9366a JM |
117 | " uiccr %08" PRIx32 "\n" |
118 | " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", | |
119 | __func__, uic->uicsr, uic->uicer, uic->uiccr, | |
008ff9d7 | 120 | uic->uicsr & uic->uicer, ir, cr); |
008ff9d7 | 121 | if (ir != 0x0000000) { |
d12d51d5 | 122 | LOG_UIC("Raise UIC interrupt\n"); |
008ff9d7 JM |
123 | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
124 | } else { | |
d12d51d5 | 125 | LOG_UIC("Lower UIC interrupt\n"); |
008ff9d7 JM |
126 | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
127 | } | |
128 | /* Trigger critical interrupt if any is pending and update vector */ | |
129 | if (cr != 0x0000000) { | |
130 | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); | |
131 | if (uic->use_vectors) { | |
132 | /* Compute critical IRQ vector */ | |
133 | if (uic->uicvcr & 1) { | |
134 | start = 31; | |
135 | end = 0; | |
136 | inc = -1; | |
137 | } else { | |
138 | start = 0; | |
139 | end = 31; | |
140 | inc = 1; | |
141 | } | |
142 | uic->uicvr = uic->uicvcr & 0xFFFFFFFC; | |
143 | for (i = start; i <= end; i += inc) { | |
144 | if (cr & (1 << i)) { | |
145 | uic->uicvr += (i - start) * 512 * inc; | |
146 | break; | |
147 | } | |
148 | } | |
149 | } | |
d12d51d5 | 150 | LOG_UIC("Raise UIC critical interrupt - " |
aae9366a | 151 | "vector %08" PRIx32 "\n", uic->uicvr); |
008ff9d7 | 152 | } else { |
d12d51d5 | 153 | LOG_UIC("Lower UIC critical interrupt\n"); |
008ff9d7 JM |
154 | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
155 | uic->uicvr = 0x00000000; | |
156 | } | |
157 | } | |
158 | ||
159 | static void ppcuic_set_irq (void *opaque, int irq_num, int level) | |
160 | { | |
c227f099 | 161 | ppcuic_t *uic; |
008ff9d7 JM |
162 | uint32_t mask, sr; |
163 | ||
164 | uic = opaque; | |
a1f7f97b | 165 | mask = 1U << (31-irq_num); |
d12d51d5 | 166 | LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 |
aae9366a JM |
167 | " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
168 | __func__, irq_num, level, | |
008ff9d7 | 169 | uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
008ff9d7 JM |
170 | if (irq_num < 0 || irq_num > 31) |
171 | return; | |
172 | sr = uic->uicsr; | |
50bf72b3 | 173 | |
008ff9d7 JM |
174 | /* Update status register */ |
175 | if (uic->uictr & mask) { | |
176 | /* Edge sensitive interrupt */ | |
177 | if (level == 1) | |
178 | uic->uicsr |= mask; | |
179 | } else { | |
180 | /* Level sensitive interrupt */ | |
4c54e875 | 181 | if (level == 1) { |
008ff9d7 | 182 | uic->uicsr |= mask; |
4c54e875 AJ |
183 | uic->level |= mask; |
184 | } else { | |
008ff9d7 | 185 | uic->uicsr &= ~mask; |
4c54e875 AJ |
186 | uic->level &= ~mask; |
187 | } | |
008ff9d7 | 188 | } |
d12d51d5 | 189 | LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " |
aae9366a | 190 | "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
008ff9d7 JM |
191 | if (sr != uic->uicsr) |
192 | ppcuic_trigger_irq(uic); | |
193 | } | |
194 | ||
73b01960 | 195 | static uint32_t dcr_read_uic (void *opaque, int dcrn) |
008ff9d7 | 196 | { |
c227f099 | 197 | ppcuic_t *uic; |
73b01960 | 198 | uint32_t ret; |
008ff9d7 JM |
199 | |
200 | uic = opaque; | |
201 | dcrn -= uic->dcr_base; | |
202 | switch (dcrn) { | |
203 | case DCR_UICSR: | |
204 | case DCR_UICSRS: | |
205 | ret = uic->uicsr; | |
206 | break; | |
207 | case DCR_UICER: | |
208 | ret = uic->uicer; | |
209 | break; | |
210 | case DCR_UICCR: | |
211 | ret = uic->uiccr; | |
212 | break; | |
213 | case DCR_UICPR: | |
214 | ret = uic->uicpr; | |
215 | break; | |
216 | case DCR_UICTR: | |
217 | ret = uic->uictr; | |
218 | break; | |
219 | case DCR_UICMSR: | |
220 | ret = uic->uicsr & uic->uicer; | |
221 | break; | |
222 | case DCR_UICVR: | |
223 | if (!uic->use_vectors) | |
224 | goto no_read; | |
225 | ret = uic->uicvr; | |
226 | break; | |
227 | case DCR_UICVCR: | |
228 | if (!uic->use_vectors) | |
229 | goto no_read; | |
230 | ret = uic->uicvcr; | |
231 | break; | |
232 | default: | |
233 | no_read: | |
234 | ret = 0x00000000; | |
235 | break; | |
236 | } | |
237 | ||
238 | return ret; | |
239 | } | |
240 | ||
73b01960 | 241 | static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) |
008ff9d7 | 242 | { |
c227f099 | 243 | ppcuic_t *uic; |
008ff9d7 JM |
244 | |
245 | uic = opaque; | |
246 | dcrn -= uic->dcr_base; | |
73b01960 | 247 | LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); |
008ff9d7 JM |
248 | switch (dcrn) { |
249 | case DCR_UICSR: | |
250 | uic->uicsr &= ~val; | |
4c54e875 | 251 | uic->uicsr |= uic->level; |
008ff9d7 JM |
252 | ppcuic_trigger_irq(uic); |
253 | break; | |
254 | case DCR_UICSRS: | |
255 | uic->uicsr |= val; | |
256 | ppcuic_trigger_irq(uic); | |
257 | break; | |
258 | case DCR_UICER: | |
259 | uic->uicer = val; | |
260 | ppcuic_trigger_irq(uic); | |
261 | break; | |
262 | case DCR_UICCR: | |
263 | uic->uiccr = val; | |
264 | ppcuic_trigger_irq(uic); | |
265 | break; | |
266 | case DCR_UICPR: | |
267 | uic->uicpr = val; | |
008ff9d7 JM |
268 | break; |
269 | case DCR_UICTR: | |
270 | uic->uictr = val; | |
271 | ppcuic_trigger_irq(uic); | |
272 | break; | |
273 | case DCR_UICMSR: | |
274 | break; | |
275 | case DCR_UICVR: | |
276 | break; | |
277 | case DCR_UICVCR: | |
278 | uic->uicvcr = val & 0xFFFFFFFD; | |
279 | ppcuic_trigger_irq(uic); | |
280 | break; | |
281 | } | |
282 | } | |
283 | ||
284 | static void ppcuic_reset (void *opaque) | |
285 | { | |
c227f099 | 286 | ppcuic_t *uic; |
008ff9d7 JM |
287 | |
288 | uic = opaque; | |
289 | uic->uiccr = 0x00000000; | |
290 | uic->uicer = 0x00000000; | |
291 | uic->uicpr = 0x00000000; | |
292 | uic->uicsr = 0x00000000; | |
293 | uic->uictr = 0x00000000; | |
294 | if (uic->use_vectors) { | |
295 | uic->uicvcr = 0x00000000; | |
296 | uic->uicvr = 0x0000000; | |
297 | } | |
298 | } | |
299 | ||
e2684c0b | 300 | qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, |
008ff9d7 JM |
301 | uint32_t dcr_base, int has_ssr, int has_vr) |
302 | { | |
c227f099 | 303 | ppcuic_t *uic; |
008ff9d7 JM |
304 | int i; |
305 | ||
7267c094 | 306 | uic = g_malloc0(sizeof(ppcuic_t)); |
487414f1 AL |
307 | uic->dcr_base = dcr_base; |
308 | uic->irqs = irqs; | |
309 | if (has_vr) | |
310 | uic->use_vectors = 1; | |
311 | for (i = 0; i < DCR_UICMAX; i++) { | |
312 | ppc_dcr_register(env, dcr_base + i, uic, | |
313 | &dcr_read_uic, &dcr_write_uic); | |
008ff9d7 | 314 | } |
a08d4367 | 315 | qemu_register_reset(ppcuic_reset, uic); |
008ff9d7 JM |
316 | |
317 | return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); | |
318 | } | |
61b24405 AJ |
319 | |
320 | /*****************************************************************************/ | |
321 | /* SDRAM controller */ | |
c227f099 AL |
322 | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
323 | struct ppc4xx_sdram_t { | |
61b24405 AJ |
324 | uint32_t addr; |
325 | int nbanks; | |
b6dcbe08 AK |
326 | MemoryRegion containers[4]; /* used for clipping */ |
327 | MemoryRegion *ram_memories; | |
a8170e5e AK |
328 | hwaddr ram_bases[4]; |
329 | hwaddr ram_sizes[4]; | |
61b24405 AJ |
330 | uint32_t besr0; |
331 | uint32_t besr1; | |
332 | uint32_t bear; | |
333 | uint32_t cfg; | |
334 | uint32_t status; | |
335 | uint32_t rtr; | |
336 | uint32_t pmit; | |
337 | uint32_t bcr[4]; | |
338 | uint32_t tr; | |
339 | uint32_t ecccfg; | |
340 | uint32_t eccesr; | |
341 | qemu_irq irq; | |
342 | }; | |
343 | ||
344 | enum { | |
345 | SDRAM0_CFGADDR = 0x010, | |
346 | SDRAM0_CFGDATA = 0x011, | |
347 | }; | |
348 | ||
349 | /* XXX: TOFIX: some patches have made this code become inconsistent: | |
a8170e5e | 350 | * there are type inconsistencies, mixing hwaddr, target_ulong |
61b24405 AJ |
351 | * and uint32_t |
352 | */ | |
a8170e5e AK |
353 | static uint32_t sdram_bcr (hwaddr ram_base, |
354 | hwaddr ram_size) | |
61b24405 AJ |
355 | { |
356 | uint32_t bcr; | |
357 | ||
358 | switch (ram_size) { | |
ab3dd749 | 359 | case 4 * MiB: |
61b24405 AJ |
360 | bcr = 0x00000000; |
361 | break; | |
ab3dd749 | 362 | case 8 * MiB: |
61b24405 AJ |
363 | bcr = 0x00020000; |
364 | break; | |
ab3dd749 | 365 | case 16 * MiB: |
61b24405 AJ |
366 | bcr = 0x00040000; |
367 | break; | |
ab3dd749 | 368 | case 32 * MiB: |
61b24405 AJ |
369 | bcr = 0x00060000; |
370 | break; | |
ab3dd749 | 371 | case 64 * MiB: |
61b24405 AJ |
372 | bcr = 0x00080000; |
373 | break; | |
ab3dd749 | 374 | case 128 * MiB: |
61b24405 AJ |
375 | bcr = 0x000A0000; |
376 | break; | |
ab3dd749 | 377 | case 256 * MiB: |
61b24405 AJ |
378 | bcr = 0x000C0000; |
379 | break; | |
380 | default: | |
90e189ec BS |
381 | printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__, |
382 | ram_size); | |
61b24405 AJ |
383 | return 0x00000000; |
384 | } | |
385 | bcr |= ram_base & 0xFF800000; | |
386 | bcr |= 1; | |
387 | ||
388 | return bcr; | |
389 | } | |
390 | ||
a8170e5e | 391 | static inline hwaddr sdram_base(uint32_t bcr) |
61b24405 AJ |
392 | { |
393 | return bcr & 0xFF800000; | |
394 | } | |
395 | ||
396 | static target_ulong sdram_size (uint32_t bcr) | |
397 | { | |
398 | target_ulong size; | |
399 | int sh; | |
400 | ||
401 | sh = (bcr >> 17) & 0x7; | |
402 | if (sh == 7) | |
403 | size = -1; | |
404 | else | |
ab3dd749 | 405 | size = (4 * MiB) << sh; |
61b24405 AJ |
406 | |
407 | return size; | |
408 | } | |
409 | ||
70812bf7 BZ |
410 | static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, |
411 | uint32_t bcr, int enabled) | |
61b24405 | 412 | { |
70812bf7 | 413 | if (sdram->bcr[i] & 0x00000001) { |
61b24405 AJ |
414 | /* Unmap RAM */ |
415 | #ifdef DEBUG_SDRAM | |
90e189ec | 416 | printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
70812bf7 | 417 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
61b24405 | 418 | #endif |
b6dcbe08 | 419 | memory_region_del_subregion(get_system_memory(), |
70812bf7 BZ |
420 | &sdram->containers[i]); |
421 | memory_region_del_subregion(&sdram->containers[i], | |
422 | &sdram->ram_memories[i]); | |
423 | object_unparent(OBJECT(&sdram->containers[i])); | |
61b24405 | 424 | } |
70812bf7 | 425 | sdram->bcr[i] = bcr & 0xFFDEE001; |
61b24405 AJ |
426 | if (enabled && (bcr & 0x00000001)) { |
427 | #ifdef DEBUG_SDRAM | |
90e189ec | 428 | printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
61b24405 AJ |
429 | __func__, sdram_base(bcr), sdram_size(bcr)); |
430 | #endif | |
70812bf7 | 431 | memory_region_init(&sdram->containers[i], NULL, "sdram-containers", |
b6dcbe08 | 432 | sdram_size(bcr)); |
70812bf7 BZ |
433 | memory_region_add_subregion(&sdram->containers[i], 0, |
434 | &sdram->ram_memories[i]); | |
b6dcbe08 AK |
435 | memory_region_add_subregion(get_system_memory(), |
436 | sdram_base(bcr), | |
70812bf7 | 437 | &sdram->containers[i]); |
61b24405 AJ |
438 | } |
439 | } | |
440 | ||
c227f099 | 441 | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
61b24405 AJ |
442 | { |
443 | int i; | |
444 | ||
445 | for (i = 0; i < sdram->nbanks; i++) { | |
446 | if (sdram->ram_sizes[i] != 0) { | |
70812bf7 BZ |
447 | sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i], |
448 | sdram->ram_sizes[i]), 1); | |
61b24405 | 449 | } else { |
70812bf7 | 450 | sdram_set_bcr(sdram, i, 0x00000000, 0); |
61b24405 AJ |
451 | } |
452 | } | |
453 | } | |
454 | ||
c227f099 | 455 | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
61b24405 AJ |
456 | { |
457 | int i; | |
458 | ||
459 | for (i = 0; i < sdram->nbanks; i++) { | |
460 | #ifdef DEBUG_SDRAM | |
90e189ec | 461 | printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
61b24405 AJ |
462 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
463 | #endif | |
b6dcbe08 AK |
464 | memory_region_del_subregion(get_system_memory(), |
465 | &sdram->ram_memories[i]); | |
61b24405 AJ |
466 | } |
467 | } | |
468 | ||
73b01960 | 469 | static uint32_t dcr_read_sdram (void *opaque, int dcrn) |
61b24405 | 470 | { |
c227f099 | 471 | ppc4xx_sdram_t *sdram; |
73b01960 | 472 | uint32_t ret; |
61b24405 AJ |
473 | |
474 | sdram = opaque; | |
475 | switch (dcrn) { | |
476 | case SDRAM0_CFGADDR: | |
477 | ret = sdram->addr; | |
478 | break; | |
479 | case SDRAM0_CFGDATA: | |
480 | switch (sdram->addr) { | |
481 | case 0x00: /* SDRAM_BESR0 */ | |
482 | ret = sdram->besr0; | |
483 | break; | |
484 | case 0x08: /* SDRAM_BESR1 */ | |
485 | ret = sdram->besr1; | |
486 | break; | |
487 | case 0x10: /* SDRAM_BEAR */ | |
488 | ret = sdram->bear; | |
489 | break; | |
490 | case 0x20: /* SDRAM_CFG */ | |
491 | ret = sdram->cfg; | |
492 | break; | |
493 | case 0x24: /* SDRAM_STATUS */ | |
494 | ret = sdram->status; | |
495 | break; | |
496 | case 0x30: /* SDRAM_RTR */ | |
497 | ret = sdram->rtr; | |
498 | break; | |
499 | case 0x34: /* SDRAM_PMIT */ | |
500 | ret = sdram->pmit; | |
501 | break; | |
502 | case 0x40: /* SDRAM_B0CR */ | |
503 | ret = sdram->bcr[0]; | |
504 | break; | |
505 | case 0x44: /* SDRAM_B1CR */ | |
506 | ret = sdram->bcr[1]; | |
507 | break; | |
508 | case 0x48: /* SDRAM_B2CR */ | |
509 | ret = sdram->bcr[2]; | |
510 | break; | |
511 | case 0x4C: /* SDRAM_B3CR */ | |
512 | ret = sdram->bcr[3]; | |
513 | break; | |
514 | case 0x80: /* SDRAM_TR */ | |
515 | ret = -1; /* ? */ | |
516 | break; | |
517 | case 0x94: /* SDRAM_ECCCFG */ | |
518 | ret = sdram->ecccfg; | |
519 | break; | |
520 | case 0x98: /* SDRAM_ECCESR */ | |
521 | ret = sdram->eccesr; | |
522 | break; | |
523 | default: /* Error */ | |
524 | ret = -1; | |
525 | break; | |
526 | } | |
527 | break; | |
528 | default: | |
529 | /* Avoid gcc warning */ | |
530 | ret = 0x00000000; | |
531 | break; | |
532 | } | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
73b01960 | 537 | static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) |
61b24405 | 538 | { |
c227f099 | 539 | ppc4xx_sdram_t *sdram; |
61b24405 AJ |
540 | |
541 | sdram = opaque; | |
542 | switch (dcrn) { | |
543 | case SDRAM0_CFGADDR: | |
544 | sdram->addr = val; | |
545 | break; | |
546 | case SDRAM0_CFGDATA: | |
547 | switch (sdram->addr) { | |
548 | case 0x00: /* SDRAM_BESR0 */ | |
549 | sdram->besr0 &= ~val; | |
550 | break; | |
551 | case 0x08: /* SDRAM_BESR1 */ | |
552 | sdram->besr1 &= ~val; | |
553 | break; | |
554 | case 0x10: /* SDRAM_BEAR */ | |
555 | sdram->bear = val; | |
556 | break; | |
557 | case 0x20: /* SDRAM_CFG */ | |
558 | val &= 0xFFE00000; | |
559 | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { | |
560 | #ifdef DEBUG_SDRAM | |
561 | printf("%s: enable SDRAM controller\n", __func__); | |
562 | #endif | |
563 | /* validate all RAM mappings */ | |
564 | sdram_map_bcr(sdram); | |
565 | sdram->status &= ~0x80000000; | |
566 | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { | |
567 | #ifdef DEBUG_SDRAM | |
568 | printf("%s: disable SDRAM controller\n", __func__); | |
569 | #endif | |
570 | /* invalidate all RAM mappings */ | |
571 | sdram_unmap_bcr(sdram); | |
572 | sdram->status |= 0x80000000; | |
573 | } | |
574 | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) | |
575 | sdram->status |= 0x40000000; | |
576 | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) | |
577 | sdram->status &= ~0x40000000; | |
578 | sdram->cfg = val; | |
579 | break; | |
580 | case 0x24: /* SDRAM_STATUS */ | |
581 | /* Read-only register */ | |
582 | break; | |
583 | case 0x30: /* SDRAM_RTR */ | |
584 | sdram->rtr = val & 0x3FF80000; | |
585 | break; | |
586 | case 0x34: /* SDRAM_PMIT */ | |
587 | sdram->pmit = (val & 0xF8000000) | 0x07C00000; | |
588 | break; | |
589 | case 0x40: /* SDRAM_B0CR */ | |
70812bf7 | 590 | sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); |
61b24405 AJ |
591 | break; |
592 | case 0x44: /* SDRAM_B1CR */ | |
70812bf7 | 593 | sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); |
61b24405 AJ |
594 | break; |
595 | case 0x48: /* SDRAM_B2CR */ | |
70812bf7 | 596 | sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); |
61b24405 AJ |
597 | break; |
598 | case 0x4C: /* SDRAM_B3CR */ | |
70812bf7 | 599 | sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); |
61b24405 AJ |
600 | break; |
601 | case 0x80: /* SDRAM_TR */ | |
602 | sdram->tr = val & 0x018FC01F; | |
603 | break; | |
604 | case 0x94: /* SDRAM_ECCCFG */ | |
605 | sdram->ecccfg = val & 0x00F00000; | |
606 | break; | |
607 | case 0x98: /* SDRAM_ECCESR */ | |
608 | val &= 0xFFF0F000; | |
609 | if (sdram->eccesr == 0 && val != 0) | |
610 | qemu_irq_raise(sdram->irq); | |
611 | else if (sdram->eccesr != 0 && val == 0) | |
612 | qemu_irq_lower(sdram->irq); | |
613 | sdram->eccesr = val; | |
614 | break; | |
615 | default: /* Error */ | |
616 | break; | |
617 | } | |
618 | break; | |
619 | } | |
620 | } | |
621 | ||
622 | static void sdram_reset (void *opaque) | |
623 | { | |
c227f099 | 624 | ppc4xx_sdram_t *sdram; |
61b24405 AJ |
625 | |
626 | sdram = opaque; | |
627 | sdram->addr = 0x00000000; | |
628 | sdram->bear = 0x00000000; | |
629 | sdram->besr0 = 0x00000000; /* No error */ | |
630 | sdram->besr1 = 0x00000000; /* No error */ | |
631 | sdram->cfg = 0x00000000; | |
632 | sdram->ecccfg = 0x00000000; /* No ECC */ | |
633 | sdram->eccesr = 0x00000000; /* No error */ | |
634 | sdram->pmit = 0x07C00000; | |
635 | sdram->rtr = 0x05F00000; | |
636 | sdram->tr = 0x00854009; | |
637 | /* We pre-initialize RAM banks */ | |
638 | sdram->status = 0x00000000; | |
639 | sdram->cfg = 0x00800000; | |
61b24405 AJ |
640 | } |
641 | ||
e2684c0b | 642 | void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, |
b6dcbe08 | 643 | MemoryRegion *ram_memories, |
a8170e5e AK |
644 | hwaddr *ram_bases, |
645 | hwaddr *ram_sizes, | |
61b24405 AJ |
646 | int do_init) |
647 | { | |
c227f099 | 648 | ppc4xx_sdram_t *sdram; |
61b24405 | 649 | |
7267c094 | 650 | sdram = g_malloc0(sizeof(ppc4xx_sdram_t)); |
487414f1 AL |
651 | sdram->irq = irq; |
652 | sdram->nbanks = nbanks; | |
b6dcbe08 | 653 | sdram->ram_memories = ram_memories; |
a8170e5e | 654 | memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); |
487414f1 | 655 | memcpy(sdram->ram_bases, ram_bases, |
a8170e5e AK |
656 | nbanks * sizeof(hwaddr)); |
657 | memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); | |
487414f1 | 658 | memcpy(sdram->ram_sizes, ram_sizes, |
a8170e5e | 659 | nbanks * sizeof(hwaddr)); |
a08d4367 | 660 | qemu_register_reset(&sdram_reset, sdram); |
487414f1 AL |
661 | ppc_dcr_register(env, SDRAM0_CFGADDR, |
662 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
663 | ppc_dcr_register(env, SDRAM0_CFGDATA, | |
664 | sdram, &dcr_read_sdram, &dcr_write_sdram); | |
665 | if (do_init) | |
666 | sdram_map_bcr(sdram); | |
61b24405 | 667 | } |
b7da58fd | 668 | |
b28f0188 IM |
669 | /* |
670 | * Split RAM between SDRAM banks. | |
b7da58fd | 671 | * |
a0258e4a IM |
672 | * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] |
673 | * and must be 0-terminated. | |
b7da58fd AJ |
674 | * |
675 | * The 4xx SDRAM controller supports a small number of banks, and each bank | |
676 | * must be one of a small set of sizes. The number of banks and the supported | |
b28f0188 IM |
677 | * sizes varies by SoC. |
678 | */ | |
679 | void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, | |
a0258e4a IM |
680 | MemoryRegion ram_memories[], |
681 | hwaddr ram_bases[], hwaddr ram_sizes[], | |
682 | const ram_addr_t sdram_bank_sizes[]) | |
b7da58fd | 683 | { |
b28f0188 | 684 | ram_addr_t size_left = memory_region_size(ram); |
b6dcbe08 | 685 | ram_addr_t base = 0; |
7d8ccf58 | 686 | ram_addr_t bank_size; |
b7da58fd AJ |
687 | int i; |
688 | int j; | |
689 | ||
690 | for (i = 0; i < nr_banks; i++) { | |
691 | for (j = 0; sdram_bank_sizes[j] != 0; j++) { | |
e206ad48 | 692 | bank_size = sdram_bank_sizes[j]; |
5c130f65 | 693 | if (bank_size <= size_left) { |
b28f0188 IM |
694 | char name[32]; |
695 | ||
a0258e4a IM |
696 | ram_bases[i] = base; |
697 | ram_sizes[i] = bank_size; | |
698 | base += bank_size; | |
5c130f65 | 699 | size_left -= bank_size; |
b28f0188 IM |
700 | snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); |
701 | memory_region_init_alias(&ram_memories[i], NULL, name, ram, | |
702 | ram_bases[i], ram_sizes[i]); | |
a0258e4a | 703 | break; |
b7da58fd AJ |
704 | } |
705 | } | |
5c130f65 | 706 | if (!size_left) { |
b7da58fd AJ |
707 | /* No need to use the remaining banks. */ |
708 | break; | |
709 | } | |
710 | } | |
711 | ||
e206ad48 | 712 | if (size_left) { |
b28f0188 | 713 | ram_addr_t used_size = memory_region_size(ram) - size_left; |
a0258e4a IM |
714 | GString *s = g_string_new(NULL); |
715 | ||
716 | for (i = 0; sdram_bank_sizes[i]; i++) { | |
717 | g_string_append_printf(s, "%" PRIi64 "%s", | |
718 | sdram_bank_sizes[i] / MiB, | |
0f1eddf5 | 719 | sdram_bank_sizes[i + 1] ? ", " : ""); |
a0258e4a | 720 | } |
0f1eddf5 MA |
721 | error_report("at most %d bank%s of %s MiB each supported", |
722 | nr_banks, nr_banks == 1 ? "" : "s", s->str); | |
723 | error_printf("Possible valid RAM size: %" PRIi64 " MiB \n", | |
a0258e4a IM |
724 | used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); |
725 | ||
726 | g_string_free(s, true); | |
727 | exit(EXIT_FAILURE); | |
e206ad48 | 728 | } |
b7da58fd | 729 | } |
517284a7 BZ |
730 | |
731 | /*****************************************************************************/ | |
732 | /* MAL */ | |
04534280 | 733 | |
517284a7 BZ |
734 | enum { |
735 | MAL0_CFG = 0x180, | |
736 | MAL0_ESR = 0x181, | |
737 | MAL0_IER = 0x182, | |
738 | MAL0_TXCASR = 0x184, | |
739 | MAL0_TXCARR = 0x185, | |
740 | MAL0_TXEOBISR = 0x186, | |
741 | MAL0_TXDEIR = 0x187, | |
742 | MAL0_RXCASR = 0x190, | |
743 | MAL0_RXCARR = 0x191, | |
744 | MAL0_RXEOBISR = 0x192, | |
745 | MAL0_RXDEIR = 0x193, | |
746 | MAL0_TXCTP0R = 0x1A0, | |
517284a7 | 747 | MAL0_RXCTP0R = 0x1C0, |
517284a7 BZ |
748 | MAL0_RCBS0 = 0x1E0, |
749 | MAL0_RCBS1 = 0x1E1, | |
750 | }; | |
751 | ||
04534280 BZ |
752 | typedef struct ppc4xx_mal_t ppc4xx_mal_t; |
753 | struct ppc4xx_mal_t { | |
517284a7 BZ |
754 | qemu_irq irqs[4]; |
755 | uint32_t cfg; | |
756 | uint32_t esr; | |
757 | uint32_t ier; | |
758 | uint32_t txcasr; | |
759 | uint32_t txcarr; | |
760 | uint32_t txeobisr; | |
761 | uint32_t txdeir; | |
762 | uint32_t rxcasr; | |
763 | uint32_t rxcarr; | |
764 | uint32_t rxeobisr; | |
765 | uint32_t rxdeir; | |
04534280 BZ |
766 | uint32_t *txctpr; |
767 | uint32_t *rxctpr; | |
768 | uint32_t *rcbs; | |
769 | uint8_t txcnum; | |
770 | uint8_t rxcnum; | |
517284a7 BZ |
771 | }; |
772 | ||
04534280 BZ |
773 | static void ppc4xx_mal_reset(void *opaque) |
774 | { | |
775 | ppc4xx_mal_t *mal; | |
776 | ||
777 | mal = opaque; | |
778 | mal->cfg = 0x0007C000; | |
779 | mal->esr = 0x00000000; | |
780 | mal->ier = 0x00000000; | |
781 | mal->rxcasr = 0x00000000; | |
782 | mal->rxdeir = 0x00000000; | |
783 | mal->rxeobisr = 0x00000000; | |
784 | mal->txcasr = 0x00000000; | |
785 | mal->txdeir = 0x00000000; | |
786 | mal->txeobisr = 0x00000000; | |
787 | } | |
517284a7 BZ |
788 | |
789 | static uint32_t dcr_read_mal(void *opaque, int dcrn) | |
790 | { | |
04534280 | 791 | ppc4xx_mal_t *mal; |
517284a7 BZ |
792 | uint32_t ret; |
793 | ||
794 | mal = opaque; | |
795 | switch (dcrn) { | |
796 | case MAL0_CFG: | |
797 | ret = mal->cfg; | |
798 | break; | |
799 | case MAL0_ESR: | |
800 | ret = mal->esr; | |
801 | break; | |
802 | case MAL0_IER: | |
803 | ret = mal->ier; | |
804 | break; | |
805 | case MAL0_TXCASR: | |
806 | ret = mal->txcasr; | |
807 | break; | |
808 | case MAL0_TXCARR: | |
809 | ret = mal->txcarr; | |
810 | break; | |
811 | case MAL0_TXEOBISR: | |
812 | ret = mal->txeobisr; | |
813 | break; | |
814 | case MAL0_TXDEIR: | |
815 | ret = mal->txdeir; | |
816 | break; | |
817 | case MAL0_RXCASR: | |
818 | ret = mal->rxcasr; | |
819 | break; | |
820 | case MAL0_RXCARR: | |
821 | ret = mal->rxcarr; | |
822 | break; | |
823 | case MAL0_RXEOBISR: | |
824 | ret = mal->rxeobisr; | |
825 | break; | |
826 | case MAL0_RXDEIR: | |
827 | ret = mal->rxdeir; | |
828 | break; | |
517284a7 BZ |
829 | default: |
830 | ret = 0; | |
831 | break; | |
832 | } | |
04534280 BZ |
833 | if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { |
834 | ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; | |
835 | } | |
836 | if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { | |
837 | ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; | |
838 | } | |
839 | if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { | |
840 | ret = mal->rcbs[dcrn - MAL0_RCBS0]; | |
841 | } | |
517284a7 BZ |
842 | |
843 | return ret; | |
844 | } | |
845 | ||
846 | static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) | |
847 | { | |
04534280 | 848 | ppc4xx_mal_t *mal; |
517284a7 BZ |
849 | |
850 | mal = opaque; | |
851 | switch (dcrn) { | |
852 | case MAL0_CFG: | |
853 | if (val & 0x80000000) { | |
04534280 | 854 | ppc4xx_mal_reset(mal); |
517284a7 BZ |
855 | } |
856 | mal->cfg = val & 0x00FFC087; | |
857 | break; | |
858 | case MAL0_ESR: | |
859 | /* Read/clear */ | |
860 | mal->esr &= ~val; | |
861 | break; | |
862 | case MAL0_IER: | |
863 | mal->ier = val & 0x0000001F; | |
864 | break; | |
865 | case MAL0_TXCASR: | |
866 | mal->txcasr = val & 0xF0000000; | |
867 | break; | |
868 | case MAL0_TXCARR: | |
869 | mal->txcarr = val & 0xF0000000; | |
870 | break; | |
871 | case MAL0_TXEOBISR: | |
872 | /* Read/clear */ | |
873 | mal->txeobisr &= ~val; | |
874 | break; | |
875 | case MAL0_TXDEIR: | |
876 | /* Read/clear */ | |
877 | mal->txdeir &= ~val; | |
878 | break; | |
879 | case MAL0_RXCASR: | |
880 | mal->rxcasr = val & 0xC0000000; | |
881 | break; | |
882 | case MAL0_RXCARR: | |
883 | mal->rxcarr = val & 0xC0000000; | |
884 | break; | |
885 | case MAL0_RXEOBISR: | |
886 | /* Read/clear */ | |
887 | mal->rxeobisr &= ~val; | |
888 | break; | |
889 | case MAL0_RXDEIR: | |
890 | /* Read/clear */ | |
891 | mal->rxdeir &= ~val; | |
892 | break; | |
04534280 BZ |
893 | } |
894 | if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { | |
895 | mal->txctpr[dcrn - MAL0_TXCTP0R] = val; | |
896 | } | |
897 | if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { | |
898 | mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; | |
899 | } | |
900 | if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { | |
901 | mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; | |
517284a7 BZ |
902 | } |
903 | } | |
904 | ||
04534280 BZ |
905 | void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, |
906 | qemu_irq irqs[4]) | |
517284a7 | 907 | { |
04534280 | 908 | ppc4xx_mal_t *mal; |
517284a7 BZ |
909 | int i; |
910 | ||
04534280 BZ |
911 | assert(txcnum <= 32 && rxcnum <= 32); |
912 | mal = g_malloc0(sizeof(*mal)); | |
913 | mal->txcnum = txcnum; | |
914 | mal->rxcnum = rxcnum; | |
915 | mal->txctpr = g_new0(uint32_t, txcnum); | |
916 | mal->rxctpr = g_new0(uint32_t, rxcnum); | |
917 | mal->rcbs = g_new0(uint32_t, rxcnum); | |
517284a7 BZ |
918 | for (i = 0; i < 4; i++) { |
919 | mal->irqs[i] = irqs[i]; | |
920 | } | |
04534280 | 921 | qemu_register_reset(&ppc4xx_mal_reset, mal); |
517284a7 BZ |
922 | ppc_dcr_register(env, MAL0_CFG, |
923 | mal, &dcr_read_mal, &dcr_write_mal); | |
924 | ppc_dcr_register(env, MAL0_ESR, | |
925 | mal, &dcr_read_mal, &dcr_write_mal); | |
926 | ppc_dcr_register(env, MAL0_IER, | |
927 | mal, &dcr_read_mal, &dcr_write_mal); | |
928 | ppc_dcr_register(env, MAL0_TXCASR, | |
929 | mal, &dcr_read_mal, &dcr_write_mal); | |
930 | ppc_dcr_register(env, MAL0_TXCARR, | |
931 | mal, &dcr_read_mal, &dcr_write_mal); | |
932 | ppc_dcr_register(env, MAL0_TXEOBISR, | |
933 | mal, &dcr_read_mal, &dcr_write_mal); | |
934 | ppc_dcr_register(env, MAL0_TXDEIR, | |
935 | mal, &dcr_read_mal, &dcr_write_mal); | |
936 | ppc_dcr_register(env, MAL0_RXCASR, | |
937 | mal, &dcr_read_mal, &dcr_write_mal); | |
938 | ppc_dcr_register(env, MAL0_RXCARR, | |
939 | mal, &dcr_read_mal, &dcr_write_mal); | |
940 | ppc_dcr_register(env, MAL0_RXEOBISR, | |
941 | mal, &dcr_read_mal, &dcr_write_mal); | |
942 | ppc_dcr_register(env, MAL0_RXDEIR, | |
943 | mal, &dcr_read_mal, &dcr_write_mal); | |
04534280 BZ |
944 | for (i = 0; i < txcnum; i++) { |
945 | ppc_dcr_register(env, MAL0_TXCTP0R + i, | |
946 | mal, &dcr_read_mal, &dcr_write_mal); | |
947 | } | |
948 | for (i = 0; i < rxcnum; i++) { | |
949 | ppc_dcr_register(env, MAL0_RXCTP0R + i, | |
950 | mal, &dcr_read_mal, &dcr_write_mal); | |
951 | } | |
952 | for (i = 0; i < rxcnum; i++) { | |
953 | ppc_dcr_register(env, MAL0_RCBS0 + i, | |
954 | mal, &dcr_read_mal, &dcr_write_mal); | |
955 | } | |
517284a7 | 956 | } |