[mirror_qemu.git] / hw / ppc / ppc4xx_pci.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Copyright IBM Corp. 2008
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

/* This file implements emulation of the 32-bit PCI controller found in some
 * 4xx SoCs, such as the 440EP. */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/reset.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"
#include "trace.h"
#include "qom/object.h"

struct PCIMasterMap {
    uint32_t la;
    uint32_t ma;
    uint32_t pcila;
    uint32_t pciha;
};

struct PCITargetMap {
    uint32_t ms;
    uint32_t la;
};

OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)

#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2

struct PPC4xxPCIState {
    PCIHostState parent_obj;

    struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
    struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
    qemu_irq irq[PCI_NUM_PINS];

    MemoryRegion container;
    MemoryRegion iomem;
};

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
 * PCI accesses. */
#define PCIL0_PMM0LA        0x0
#define PCIL0_PMM0MA        0x4
#define PCIL0_PMM0PCILA     0x8
#define PCIL0_PMM0PCIHA     0xc
#define PCIL0_PMM1LA        0x10
#define PCIL0_PMM1MA        0x14
#define PCIL0_PMM1PCILA     0x18
#define PCIL0_PMM1PCIHA     0x1c
#define PCIL0_PMM2LA        0x20
#define PCIL0_PMM2MA        0x24
#define PCIL0_PMM2PCILA     0x28
#define PCIL0_PMM2PCIHA     0x2c

/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
 * PLB accesses. */
#define PCIL0_PTM1MS        0x30
#define PCIL0_PTM1LA        0x34
#define PCIL0_PTM2MS        0x38
#define PCIL0_PTM2LA        0x3c
#define PCI_REG_BASE        0x800000
#define PCI_REG_SIZE        0x40

#define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)

static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
                                  uint64_t value, unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;

    /* We ignore all target attempts at PCI configuration, effectively
     * assuming a bidirectional 1:1 mapping of PLB and PCI space. */

    switch (offset) {
    case PCIL0_PMM0LA:
        pci->pmm[0].la = value;
        break;
    case PCIL0_PMM0MA:
        pci->pmm[0].ma = value;
        break;
    case PCIL0_PMM0PCIHA:
        pci->pmm[0].pciha = value;
        break;
    case PCIL0_PMM0PCILA:
        pci->pmm[0].pcila = value;
        break;

    case PCIL0_PMM1LA:
        pci->pmm[1].la = value;
        break;
    case PCIL0_PMM1MA:
        pci->pmm[1].ma = value;
        break;
    case PCIL0_PMM1PCIHA:
        pci->pmm[1].pciha = value;
        break;
    case PCIL0_PMM1PCILA:
        pci->pmm[1].pcila = value;
        break;

    case PCIL0_PMM2LA:
        pci->pmm[2].la = value;
        break;
    case PCIL0_PMM2MA:
        pci->pmm[2].ma = value;
        break;
    case PCIL0_PMM2PCIHA:
        pci->pmm[2].pciha = value;
        break;
    case PCIL0_PMM2PCILA:
        pci->pmm[2].pcila = value;
        break;

    case PCIL0_PTM1MS:
        pci->ptm[0].ms = value;
        break;
    case PCIL0_PTM1LA:
        pci->ptm[0].la = value;
        break;
    case PCIL0_PTM2MS:
        pci->ptm[1].ms = value;
        break;
    case PCIL0_PTM2LA:
        pci->ptm[1].la = value;
        break;

    default:
        printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        break;
    }
}

static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
                                     unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;
    uint32_t value;

    switch (offset) {
    case PCIL0_PMM0LA:
        value = pci->pmm[0].la;
        break;
    case PCIL0_PMM0MA:
        value = pci->pmm[0].ma;
        break;
    case PCIL0_PMM0PCIHA:
        value = pci->pmm[0].pciha;
        break;
    case PCIL0_PMM0PCILA:
        value = pci->pmm[0].pcila;
        break;

    case PCIL0_PMM1LA:
        value = pci->pmm[1].la;
        break;
    case PCIL0_PMM1MA:
        value = pci->pmm[1].ma;
        break;
    case PCIL0_PMM1PCIHA:
        value = pci->pmm[1].pciha;
        break;
    case PCIL0_PMM1PCILA:
        value = pci->pmm[1].pcila;
        break;

    case PCIL0_PMM2LA:
        value = pci->pmm[2].la;
        break;
    case PCIL0_PMM2MA:
        value = pci->pmm[2].ma;
        break;
    case PCIL0_PMM2PCIHA:
        value = pci->pmm[2].pciha;
        break;
    case PCIL0_PMM2PCILA:
        value = pci->pmm[2].pcila;
        break;

    case PCIL0_PTM1MS:
        value = pci->ptm[0].ms;
        break;
    case PCIL0_PTM1LA:
        value = pci->ptm[0].la;
        break;
    case PCIL0_PTM2MS:
        value = pci->ptm[1].ms;
        break;
    case PCIL0_PTM2LA:
        value = pci->ptm[1].la;
        break;

    default:
        printf("%s: invalid PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        value = 0;
    }

    return value;
}

static const MemoryRegionOps pci_reg_ops = {
    .read = ppc4xx_pci_reg_read4,
    .write = ppc4xx_pci_reg_write4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc4xx_pci_reset(void *opaque)
{
    struct PPC4xxPCIState *pci = opaque;

    memset(pci->pmm, 0, sizeof(pci->pmm));
    memset(pci->ptm, 0, sizeof(pci->ptm));
}

/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 * may need further refactoring for other boards. */
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot = pci_dev->devfn >> 3;

    trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);

    return slot - 1;
}

static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irqs = opaque;

    trace_ppc4xx_pci_set_irq(irq_num);
    assert(irq_num >= 0);
    qemu_set_irq(pci_irqs[irq_num], level);
}

static const VMStateDescription vmstate_pci_master_map = {
    .name = "pci_master_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(la, struct PCIMasterMap),
        VMSTATE_UINT32(ma, struct PCIMasterMap),
        VMSTATE_UINT32(pcila, struct PCIMasterMap),
        VMSTATE_UINT32(pciha, struct PCIMasterMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_target_map = {
    .name = "pci_target_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(ms, struct PCITargetMap),
        VMSTATE_UINT32(la, struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppc4xx_pci = {
    .name = "ppc4xx_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
                             vmstate_pci_master_map,
                             struct PCIMasterMap),
        VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
                             vmstate_pci_target_map,
                             struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

/* XXX Interrupt acknowledge cycles not supported. */
static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    PPC4xxPCIState *s;
    PCIHostState *h;
    PCIBus *b;
    int i;

    h = PCI_HOST_BRIDGE(dev);
    s = PPC4xx_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(sbd, &s->irq[i]);
    }

    b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
                              ppc4xx_pci_map_irq, s->irq, get_system_memory(),
                              get_system_io(), 0, ARRAY_SIZE(s->irq),
                              TYPE_PCI_BUS);
    h->bus = b;

    pci_create_simple(b, 0, "ppc4xx-host-bridge");

    /* XXX split into 2 memory regions, one for config space, one for regs */
    memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
                          "pci.reg", PCI_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
    sysbus_init_mmio(sbd, &s->container);
    qemu_register_reset(ppc4xx_pci_reset, s);
}

static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc        = "Host bridge";
    k->vendor_id    = PCI_VENDOR_ID_IBM;
    k->device_id    = PCI_DEVICE_ID_IBM_440GX;
    k->class_id     = PCI_CLASS_BRIDGE_OTHER;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo ppc4xx_host_bridge_info = {
    .name          = "ppc4xx-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = ppc4xx_host_bridge_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = ppc4xx_pcihost_realize;
    dc->vmsd = &vmstate_ppc4xx_pci;
}

static const TypeInfo ppc4xx_pcihost_info = {
    .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPC4xxPCIState),
    .class_init    = ppc4xx_pcihost_class_init,
};

static void ppc4xx_pci_register_types(void)
{
    type_register_static(&ppc4xx_pcihost_info);
    type_register_static(&ppc4xx_host_bridge_info);
}

type_init(ppc4xx_pci_register_types)
Commit	Line	Data
825bb581 AJ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
8167ee88	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
825bb581 AJ	13	*
	14	* Copyright IBM Corp. 2008
	15	*
	16	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	17	*/
	18
	19	/* This file implements emulation of the 32-bit PCI controller found in some
	20	* 4xx SoCs, such as the 440EP. */
	21
0d75590d	22	#include "qemu/osdep.h"
64552b6b	23	#include "hw/irq.h"
0d09e41a PB	24	#include "hw/ppc/ppc.h"
0d09e41a PB	25	#include "hw/ppc/ppc4xx.h"
d6454270	26	#include "migration/vmstate.h"
0b8fa32f	27	#include "qemu/module.h"
71e8a915	28	#include "sysemu/reset.h"
83c9f4ca PB	29	#include "hw/pci/pci.h"
83c9f4ca PB	30	#include "hw/pci/pci_host.h"
022c62cb	31	#include "exec/address-spaces.h"
f4af7d44	32	#include "trace.h"
db1015e9	33	#include "qom/object.h"
825bb581 AJ	34
	35	struct PCIMasterMap {
	36	uint32_t la;
	37	uint32_t ma;
	38	uint32_t pcila;
	39	uint32_t pciha;
	40	};
	41
	42	struct PCITargetMap {
	43	uint32_t ms;
	44	uint32_t la;
	45	};
	46
8063396b	47	OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
42c281a2	48
825bb581 AJ	49	#define PPC4xx_PCI_NR_PMMS 3
	50	#define PPC4xx_PCI_NR_PTMS 2
	51
	52	struct PPC4xxPCIState {
67c332fd	53	PCIHostState parent_obj;
623f7c21	54
825bb581 AJ	55	struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
825bb581 AJ	56	struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
0a755372	57	qemu_irq irq[PCI_NUM_PINS];
825bb581	58
623f7c21 AG	59	MemoryRegion container;
623f7c21 AG	60	MemoryRegion iomem;
825bb581	61	};
825bb581 AJ	62
	63	#define PCIC0_CFGADDR 0x0
	64	#define PCIC0_CFGDATA 0x4
	65
	66	/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
	67	* PCI accesses. */
	68	#define PCIL0_PMM0LA 0x0
	69	#define PCIL0_PMM0MA 0x4
	70	#define PCIL0_PMM0PCILA 0x8
	71	#define PCIL0_PMM0PCIHA 0xc
	72	#define PCIL0_PMM1LA 0x10
	73	#define PCIL0_PMM1MA 0x14
	74	#define PCIL0_PMM1PCILA 0x18
	75	#define PCIL0_PMM1PCIHA 0x1c
	76	#define PCIL0_PMM2LA 0x20
	77	#define PCIL0_PMM2MA 0x24
	78	#define PCIL0_PMM2PCILA 0x28
	79	#define PCIL0_PMM2PCIHA 0x2c
	80
	81	/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
	82	* PLB accesses. */
	83	#define PCIL0_PTM1MS 0x30
	84	#define PCIL0_PTM1LA 0x34
	85	#define PCIL0_PTM2MS 0x38
	86	#define PCIL0_PTM2LA 0x3c
623f7c21	87	#define PCI_REG_BASE 0x800000
825bb581 AJ	88	#define PCI_REG_SIZE 0x40
825bb581 AJ	89
623f7c21	90	#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
825bb581	91
a8170e5e	92	static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
da726e5e	93	uint64_t value, unsigned size)
825bb581 AJ	94	{
	95	struct PPC4xxPCIState *pci = opaque;
	96
825bb581 AJ	97	/* We ignore all target attempts at PCI configuration, effectively
	98	* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
	99
	100	switch (offset) {
	101	case PCIL0_PMM0LA:
	102	pci->pmm[0].la = value;
	103	break;
	104	case PCIL0_PMM0MA:
	105	pci->pmm[0].ma = value;
	106	break;
	107	case PCIL0_PMM0PCIHA:
	108	pci->pmm[0].pciha = value;
	109	break;
	110	case PCIL0_PMM0PCILA:
	111	pci->pmm[0].pcila = value;
	112	break;
	113
	114	case PCIL0_PMM1LA:
	115	pci->pmm[1].la = value;
	116	break;
	117	case PCIL0_PMM1MA:
	118	pci->pmm[1].ma = value;
	119	break;
	120	case PCIL0_PMM1PCIHA:
	121	pci->pmm[1].pciha = value;
	122	break;
	123	case PCIL0_PMM1PCILA:
	124	pci->pmm[1].pcila = value;
	125	break;
	126
	127	case PCIL0_PMM2LA:
	128	pci->pmm[2].la = value;
	129	break;
	130	case PCIL0_PMM2MA:
	131	pci->pmm[2].ma = value;
	132	break;
	133	case PCIL0_PMM2PCIHA:
	134	pci->pmm[2].pciha = value;
	135	break;
	136	case PCIL0_PMM2PCILA:
	137	pci->pmm[2].pcila = value;
	138	break;
	139
	140	case PCIL0_PTM1MS:
	141	pci->ptm[0].ms = value;
	142	break;
	143	case PCIL0_PTM1LA:
	144	pci->ptm[0].la = value;
	145	break;
	146	case PCIL0_PTM2MS:
	147	pci->ptm[1].ms = value;
	148	break;
	149	case PCIL0_PTM2LA:
	150	pci->ptm[1].la = value;
	151	break;
	152
	153	default:
	154	printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
	155	(unsigned long)offset);
	156	break;
	157	}
	158	}
	159
a8170e5e	160	static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
da726e5e	161	unsigned size)
825bb581 AJ	162	{
	163	struct PPC4xxPCIState *pci = opaque;
	164	uint32_t value;
	165
	166	switch (offset) {
	167	case PCIL0_PMM0LA:
	168	value = pci->pmm[0].la;
	169	break;
	170	case PCIL0_PMM0MA:
	171	value = pci->pmm[0].ma;
	172	break;
	173	case PCIL0_PMM0PCIHA:
	174	value = pci->pmm[0].pciha;
	175	break;
	176	case PCIL0_PMM0PCILA:
	177	value = pci->pmm[0].pcila;
	178	break;
	179
	180	case PCIL0_PMM1LA:
	181	value = pci->pmm[1].la;
	182	break;
	183	case PCIL0_PMM1MA:
	184	value = pci->pmm[1].ma;
	185	break;
	186	case PCIL0_PMM1PCIHA:
	187	value = pci->pmm[1].pciha;
	188	break;
	189	case PCIL0_PMM1PCILA:
	190	value = pci->pmm[1].pcila;
	191	break;
	192
	193	case PCIL0_PMM2LA:
	194	value = pci->pmm[2].la;
	195	break;
	196	case PCIL0_PMM2MA:
	197	value = pci->pmm[2].ma;
	198	break;
	199	case PCIL0_PMM2PCIHA:
	200	value = pci->pmm[2].pciha;
	201	break;
	202	case PCIL0_PMM2PCILA:
	203	value = pci->pmm[2].pcila;
	204	break;
	205
	206	case PCIL0_PTM1MS:
	207	value = pci->ptm[0].ms;
	208	break;
	209	case PCIL0_PTM1LA:
	210	value = pci->ptm[0].la;
	211	break;
	212	case PCIL0_PTM2MS:
	213	value = pci->ptm[1].ms;
	214	break;
	215	case PCIL0_PTM2LA:
	216	value = pci->ptm[1].la;
	217	break;
	218
	219	default:
	220	printf("%s: invalid PCI internal register 0x%lx\n", __func__,
	221	(unsigned long)offset);
	222	value = 0;
	223	}
	224
825bb581 AJ	225	return value;
	226	}
	227
da726e5e AK	228	static const MemoryRegionOps pci_reg_ops = {
	229	.read = ppc4xx_pci_reg_read4,
	230	.write = ppc4xx_pci_reg_write4,
	231	.endianness = DEVICE_LITTLE_ENDIAN,
825bb581 AJ	232	};
	233
	234	static void ppc4xx_pci_reset(void *opaque)
	235	{
	236	struct PPC4xxPCIState *pci = opaque;
	237
	238	memset(pci->pmm, 0, sizeof(pci->pmm));
	239	memset(pci->ptm, 0, sizeof(pci->ptm));
	240	}
	241
	242	/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
	243	* may need further refactoring for other boards. */
	244	static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	245	{
	246	int slot = pci_dev->devfn >> 3;
	247
f4af7d44	248	trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
825bb581 AJ	249
	250	return slot - 1;
	251	}
	252
5d4e84c8	253	static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
825bb581	254	{
5d4e84c8 JQ	255	qemu_irq *pci_irqs = opaque;
5d4e84c8 JQ	256
f4af7d44	257	trace_ppc4xx_pci_set_irq(irq_num);
f5f23931	258	assert(irq_num >= 0);
825bb581 AJ	259	qemu_set_irq(pci_irqs[irq_num], level);
	260	}
	261
b605f222 JQ	262	static const VMStateDescription vmstate_pci_master_map = {
	263	.name = "pci_master_map",
	264	.version_id = 0,
	265	.minimum_version_id = 0,
3aff6c2f	266	.fields = (VMStateField[]) {
b605f222 JQ	267	VMSTATE_UINT32(la, struct PCIMasterMap),
	268	VMSTATE_UINT32(ma, struct PCIMasterMap),
	269	VMSTATE_UINT32(pcila, struct PCIMasterMap),
	270	VMSTATE_UINT32(pciha, struct PCIMasterMap),
	271	VMSTATE_END_OF_LIST()
825bb581	272	}
b605f222	273	};
825bb581	274
b605f222 JQ	275	static const VMStateDescription vmstate_pci_target_map = {
	276	.name = "pci_target_map",
	277	.version_id = 0,
	278	.minimum_version_id = 0,
3aff6c2f	279	.fields = (VMStateField[]) {
b605f222 JQ	280	VMSTATE_UINT32(ms, struct PCITargetMap),
	281	VMSTATE_UINT32(la, struct PCITargetMap),
	282	VMSTATE_END_OF_LIST()
825bb581	283	}
b605f222	284	};
825bb581	285
b605f222 JQ	286	static const VMStateDescription vmstate_ppc4xx_pci = {
	287	.name = "ppc4xx_pci",
	288	.version_id = 1,
	289	.minimum_version_id = 1,
3aff6c2f	290	.fields = (VMStateField[]) {
b605f222 JQ	291	VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
	292	vmstate_pci_master_map,
	293	struct PCIMasterMap),
	294	VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
	295	vmstate_pci_target_map,
	296	struct PCITargetMap),
	297	VMSTATE_END_OF_LIST()
825bb581	298	}
b605f222	299	};
825bb581 AJ	300
825bb581 AJ	301	/* XXX Interrupt acknowledge cycles not supported. */
95ba5567	302	static void ppc4xx_pcihost_realize(DeviceState dev, Error *errp)
623f7c21	303	{
95ba5567	304	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
623f7c21 AG	305	PPC4xxPCIState *s;
	306	PCIHostState *h;
	307	PCIBus *b;
	308	int i;
	309
8558d942	310	h = PCI_HOST_BRIDGE(dev);
42c281a2	311	s = PPC4xx_PCI_HOST_BRIDGE(dev);
623f7c21 AG	312
623f7c21 AG	313	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
95ba5567	314	sysbus_init_irq(sbd, &s->irq[i]);
623f7c21 AG	315	}
623f7c21 AG	316
95ba5567	317	b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
1115ff6d	318	ppc4xx_pci_map_irq, s->irq, get_system_memory(),
4192920c PMD	319	get_system_io(), 0, ARRAY_SIZE(s->irq),
4192920c PMD	320	TYPE_PCI_BUS);
42c281a2	321	h->bus = b;
623f7c21 AG	322
	323	pci_create_simple(b, 0, "ppc4xx-host-bridge");
	324
	325	/* XXX split into 2 memory regions, one for config space, one for regs */
40c5dce9 PB	326	memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
40c5dce9 PB	327	memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
623f7c21	328	"pci-conf-idx", 4);
40c5dce9	329	memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
623f7c21	330	"pci-conf-data", 4);
40c5dce9	331	memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
623f7c21 AG	332	"pci.reg", PCI_REG_SIZE);
	333	memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
	334	memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
	335	memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
95ba5567	336	sysbus_init_mmio(sbd, &s->container);
623f7c21	337	qemu_register_reset(ppc4xx_pci_reset, s);
623f7c21 AG	338	}
623f7c21 AG	339
40021f08 AL	340	static void ppc4xx_host_bridge_class_init(ObjectClass klass, void data)
	341	{
	342	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2	343	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	344
39bffca2	345	dc->desc = "Host bridge";
40021f08 AL	346	k->vendor_id = PCI_VENDOR_ID_IBM;
	347	k->device_id = PCI_DEVICE_ID_IBM_440GX;
	348	k->class_id = PCI_CLASS_BRIDGE_OTHER;
08c58f92 MA	349	/*
	350	* PCI-facing part of the host bridge, not usable without the
	351	* host-facing part, which can't be device_add'ed, yet.
	352	*/
e90f2a8c	353	dc->user_creatable = false;
40021f08 AL	354	}
40021f08 AL	355
4240abff	356	static const TypeInfo ppc4xx_host_bridge_info = {
39bffca2 AL	357	.name = "ppc4xx-host-bridge",
	358	.parent = TYPE_PCI_DEVICE,
	359	.instance_size = sizeof(PCIDevice),
	360	.class_init = ppc4xx_host_bridge_class_init,
fd3b02c8 EH	361	.interfaces = (InterfaceInfo[]) {
	362	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	363	{ },
	364	},
623f7c21 AG	365	};
623f7c21 AG	366
999e12bb AL	367	static void ppc4xx_pcihost_class_init(ObjectClass klass, void data)
999e12bb AL	368	{
39bffca2	369	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	370
95ba5567	371	dc->realize = ppc4xx_pcihost_realize;
39bffca2	372	dc->vmsd = &vmstate_ppc4xx_pci;
999e12bb AL	373	}
999e12bb AL	374
4240abff	375	static const TypeInfo ppc4xx_pcihost_info = {
42c281a2	376	.name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
8558d942	377	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	378	.instance_size = sizeof(PPC4xxPCIState),
39bffca2 AL	379	.class_init = ppc4xx_pcihost_class_init,
623f7c21 AG	380	};
623f7c21 AG	381
83f7d43a	382	static void ppc4xx_pci_register_types(void)
825bb581	383	{
39bffca2 AL	384	type_register_static(&ppc4xx_pcihost_info);
39bffca2 AL	385	type_register_static(&ppc4xx_host_bridge_info);
825bb581	386	}
83f7d43a AF	387
83f7d43a AF	388	type_init(ppc4xx_pci_register_types)