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825bb581 AJ |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 12 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
825bb581 AJ |
13 | * |
14 | * Copyright IBM Corp. 2008 | |
15 | * | |
16 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
17 | */ | |
18 | ||
19 | /* This file implements emulation of the 32-bit PCI controller found in some | |
20 | * 4xx SoCs, such as the 440EP. */ | |
21 | ||
0d75590d | 22 | #include "qemu/osdep.h" |
64552b6b | 23 | #include "hw/irq.h" |
0d09e41a PB |
24 | #include "hw/ppc/ppc.h" |
25 | #include "hw/ppc/ppc4xx.h" | |
d6454270 | 26 | #include "migration/vmstate.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
71e8a915 | 28 | #include "sysemu/reset.h" |
83c9f4ca PB |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_host.h" | |
022c62cb | 31 | #include "exec/address-spaces.h" |
f4af7d44 | 32 | #include "trace.h" |
825bb581 AJ |
33 | |
34 | struct PCIMasterMap { | |
35 | uint32_t la; | |
36 | uint32_t ma; | |
37 | uint32_t pcila; | |
38 | uint32_t pciha; | |
39 | }; | |
40 | ||
41 | struct PCITargetMap { | |
42 | uint32_t ms; | |
43 | uint32_t la; | |
44 | }; | |
45 | ||
42c281a2 AF |
46 | #define PPC4xx_PCI_HOST_BRIDGE(obj) \ |
47 | OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE) | |
48 | ||
825bb581 AJ |
49 | #define PPC4xx_PCI_NR_PMMS 3 |
50 | #define PPC4xx_PCI_NR_PTMS 2 | |
51 | ||
52 | struct PPC4xxPCIState { | |
67c332fd | 53 | PCIHostState parent_obj; |
623f7c21 | 54 | |
825bb581 AJ |
55 | struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; |
56 | struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; | |
623f7c21 | 57 | qemu_irq irq[4]; |
825bb581 | 58 | |
623f7c21 AG |
59 | MemoryRegion container; |
60 | MemoryRegion iomem; | |
825bb581 AJ |
61 | }; |
62 | typedef struct PPC4xxPCIState PPC4xxPCIState; | |
63 | ||
64 | #define PCIC0_CFGADDR 0x0 | |
65 | #define PCIC0_CFGDATA 0x4 | |
66 | ||
67 | /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to | |
68 | * PCI accesses. */ | |
69 | #define PCIL0_PMM0LA 0x0 | |
70 | #define PCIL0_PMM0MA 0x4 | |
71 | #define PCIL0_PMM0PCILA 0x8 | |
72 | #define PCIL0_PMM0PCIHA 0xc | |
73 | #define PCIL0_PMM1LA 0x10 | |
74 | #define PCIL0_PMM1MA 0x14 | |
75 | #define PCIL0_PMM1PCILA 0x18 | |
76 | #define PCIL0_PMM1PCIHA 0x1c | |
77 | #define PCIL0_PMM2LA 0x20 | |
78 | #define PCIL0_PMM2MA 0x24 | |
79 | #define PCIL0_PMM2PCILA 0x28 | |
80 | #define PCIL0_PMM2PCIHA 0x2c | |
81 | ||
82 | /* PCI Target Map (PTM) registers specify which PCI addresses are translated to | |
83 | * PLB accesses. */ | |
84 | #define PCIL0_PTM1MS 0x30 | |
85 | #define PCIL0_PTM1LA 0x34 | |
86 | #define PCIL0_PTM2MS 0x38 | |
87 | #define PCIL0_PTM2LA 0x3c | |
623f7c21 | 88 | #define PCI_REG_BASE 0x800000 |
825bb581 AJ |
89 | #define PCI_REG_SIZE 0x40 |
90 | ||
623f7c21 | 91 | #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE) |
825bb581 | 92 | |
a8170e5e | 93 | static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, |
da726e5e | 94 | uint64_t value, unsigned size) |
825bb581 AJ |
95 | { |
96 | struct PPC4xxPCIState *pci = opaque; | |
97 | ||
825bb581 AJ |
98 | /* We ignore all target attempts at PCI configuration, effectively |
99 | * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ | |
100 | ||
101 | switch (offset) { | |
102 | case PCIL0_PMM0LA: | |
103 | pci->pmm[0].la = value; | |
104 | break; | |
105 | case PCIL0_PMM0MA: | |
106 | pci->pmm[0].ma = value; | |
107 | break; | |
108 | case PCIL0_PMM0PCIHA: | |
109 | pci->pmm[0].pciha = value; | |
110 | break; | |
111 | case PCIL0_PMM0PCILA: | |
112 | pci->pmm[0].pcila = value; | |
113 | break; | |
114 | ||
115 | case PCIL0_PMM1LA: | |
116 | pci->pmm[1].la = value; | |
117 | break; | |
118 | case PCIL0_PMM1MA: | |
119 | pci->pmm[1].ma = value; | |
120 | break; | |
121 | case PCIL0_PMM1PCIHA: | |
122 | pci->pmm[1].pciha = value; | |
123 | break; | |
124 | case PCIL0_PMM1PCILA: | |
125 | pci->pmm[1].pcila = value; | |
126 | break; | |
127 | ||
128 | case PCIL0_PMM2LA: | |
129 | pci->pmm[2].la = value; | |
130 | break; | |
131 | case PCIL0_PMM2MA: | |
132 | pci->pmm[2].ma = value; | |
133 | break; | |
134 | case PCIL0_PMM2PCIHA: | |
135 | pci->pmm[2].pciha = value; | |
136 | break; | |
137 | case PCIL0_PMM2PCILA: | |
138 | pci->pmm[2].pcila = value; | |
139 | break; | |
140 | ||
141 | case PCIL0_PTM1MS: | |
142 | pci->ptm[0].ms = value; | |
143 | break; | |
144 | case PCIL0_PTM1LA: | |
145 | pci->ptm[0].la = value; | |
146 | break; | |
147 | case PCIL0_PTM2MS: | |
148 | pci->ptm[1].ms = value; | |
149 | break; | |
150 | case PCIL0_PTM2LA: | |
151 | pci->ptm[1].la = value; | |
152 | break; | |
153 | ||
154 | default: | |
155 | printf("%s: unhandled PCI internal register 0x%lx\n", __func__, | |
156 | (unsigned long)offset); | |
157 | break; | |
158 | } | |
159 | } | |
160 | ||
a8170e5e | 161 | static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset, |
da726e5e | 162 | unsigned size) |
825bb581 AJ |
163 | { |
164 | struct PPC4xxPCIState *pci = opaque; | |
165 | uint32_t value; | |
166 | ||
167 | switch (offset) { | |
168 | case PCIL0_PMM0LA: | |
169 | value = pci->pmm[0].la; | |
170 | break; | |
171 | case PCIL0_PMM0MA: | |
172 | value = pci->pmm[0].ma; | |
173 | break; | |
174 | case PCIL0_PMM0PCIHA: | |
175 | value = pci->pmm[0].pciha; | |
176 | break; | |
177 | case PCIL0_PMM0PCILA: | |
178 | value = pci->pmm[0].pcila; | |
179 | break; | |
180 | ||
181 | case PCIL0_PMM1LA: | |
182 | value = pci->pmm[1].la; | |
183 | break; | |
184 | case PCIL0_PMM1MA: | |
185 | value = pci->pmm[1].ma; | |
186 | break; | |
187 | case PCIL0_PMM1PCIHA: | |
188 | value = pci->pmm[1].pciha; | |
189 | break; | |
190 | case PCIL0_PMM1PCILA: | |
191 | value = pci->pmm[1].pcila; | |
192 | break; | |
193 | ||
194 | case PCIL0_PMM2LA: | |
195 | value = pci->pmm[2].la; | |
196 | break; | |
197 | case PCIL0_PMM2MA: | |
198 | value = pci->pmm[2].ma; | |
199 | break; | |
200 | case PCIL0_PMM2PCIHA: | |
201 | value = pci->pmm[2].pciha; | |
202 | break; | |
203 | case PCIL0_PMM2PCILA: | |
204 | value = pci->pmm[2].pcila; | |
205 | break; | |
206 | ||
207 | case PCIL0_PTM1MS: | |
208 | value = pci->ptm[0].ms; | |
209 | break; | |
210 | case PCIL0_PTM1LA: | |
211 | value = pci->ptm[0].la; | |
212 | break; | |
213 | case PCIL0_PTM2MS: | |
214 | value = pci->ptm[1].ms; | |
215 | break; | |
216 | case PCIL0_PTM2LA: | |
217 | value = pci->ptm[1].la; | |
218 | break; | |
219 | ||
220 | default: | |
221 | printf("%s: invalid PCI internal register 0x%lx\n", __func__, | |
222 | (unsigned long)offset); | |
223 | value = 0; | |
224 | } | |
225 | ||
825bb581 AJ |
226 | return value; |
227 | } | |
228 | ||
da726e5e AK |
229 | static const MemoryRegionOps pci_reg_ops = { |
230 | .read = ppc4xx_pci_reg_read4, | |
231 | .write = ppc4xx_pci_reg_write4, | |
232 | .endianness = DEVICE_LITTLE_ENDIAN, | |
825bb581 AJ |
233 | }; |
234 | ||
235 | static void ppc4xx_pci_reset(void *opaque) | |
236 | { | |
237 | struct PPC4xxPCIState *pci = opaque; | |
238 | ||
239 | memset(pci->pmm, 0, sizeof(pci->pmm)); | |
240 | memset(pci->ptm, 0, sizeof(pci->ptm)); | |
241 | } | |
242 | ||
243 | /* On Bamboo, all pins from each slot are tied to a single board IRQ. This | |
244 | * may need further refactoring for other boards. */ | |
245 | static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) | |
246 | { | |
247 | int slot = pci_dev->devfn >> 3; | |
248 | ||
f4af7d44 | 249 | trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot); |
825bb581 AJ |
250 | |
251 | return slot - 1; | |
252 | } | |
253 | ||
5d4e84c8 | 254 | static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) |
825bb581 | 255 | { |
5d4e84c8 JQ |
256 | qemu_irq *pci_irqs = opaque; |
257 | ||
f4af7d44 | 258 | trace_ppc4xx_pci_set_irq(irq_num); |
d49bc1fb AG |
259 | if (irq_num < 0) { |
260 | fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); | |
261 | return; | |
262 | } | |
825bb581 AJ |
263 | qemu_set_irq(pci_irqs[irq_num], level); |
264 | } | |
265 | ||
b605f222 JQ |
266 | static const VMStateDescription vmstate_pci_master_map = { |
267 | .name = "pci_master_map", | |
268 | .version_id = 0, | |
269 | .minimum_version_id = 0, | |
3aff6c2f | 270 | .fields = (VMStateField[]) { |
b605f222 JQ |
271 | VMSTATE_UINT32(la, struct PCIMasterMap), |
272 | VMSTATE_UINT32(ma, struct PCIMasterMap), | |
273 | VMSTATE_UINT32(pcila, struct PCIMasterMap), | |
274 | VMSTATE_UINT32(pciha, struct PCIMasterMap), | |
275 | VMSTATE_END_OF_LIST() | |
825bb581 | 276 | } |
b605f222 | 277 | }; |
825bb581 | 278 | |
b605f222 JQ |
279 | static const VMStateDescription vmstate_pci_target_map = { |
280 | .name = "pci_target_map", | |
281 | .version_id = 0, | |
282 | .minimum_version_id = 0, | |
3aff6c2f | 283 | .fields = (VMStateField[]) { |
b605f222 JQ |
284 | VMSTATE_UINT32(ms, struct PCITargetMap), |
285 | VMSTATE_UINT32(la, struct PCITargetMap), | |
286 | VMSTATE_END_OF_LIST() | |
825bb581 | 287 | } |
b605f222 | 288 | }; |
825bb581 | 289 | |
b605f222 JQ |
290 | static const VMStateDescription vmstate_ppc4xx_pci = { |
291 | .name = "ppc4xx_pci", | |
292 | .version_id = 1, | |
293 | .minimum_version_id = 1, | |
3aff6c2f | 294 | .fields = (VMStateField[]) { |
b605f222 JQ |
295 | VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, |
296 | vmstate_pci_master_map, | |
297 | struct PCIMasterMap), | |
298 | VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, | |
299 | vmstate_pci_target_map, | |
300 | struct PCITargetMap), | |
301 | VMSTATE_END_OF_LIST() | |
825bb581 | 302 | } |
b605f222 | 303 | }; |
825bb581 AJ |
304 | |
305 | /* XXX Interrupt acknowledge cycles not supported. */ | |
95ba5567 | 306 | static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp) |
623f7c21 | 307 | { |
95ba5567 | 308 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
623f7c21 AG |
309 | PPC4xxPCIState *s; |
310 | PCIHostState *h; | |
311 | PCIBus *b; | |
312 | int i; | |
313 | ||
8558d942 | 314 | h = PCI_HOST_BRIDGE(dev); |
42c281a2 | 315 | s = PPC4xx_PCI_HOST_BRIDGE(dev); |
623f7c21 AG |
316 | |
317 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
95ba5567 | 318 | sysbus_init_irq(sbd, &s->irq[i]); |
623f7c21 AG |
319 | } |
320 | ||
95ba5567 | 321 | b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq, |
1115ff6d DG |
322 | ppc4xx_pci_map_irq, s->irq, get_system_memory(), |
323 | get_system_io(), 0, 4, TYPE_PCI_BUS); | |
42c281a2 | 324 | h->bus = b; |
623f7c21 AG |
325 | |
326 | pci_create_simple(b, 0, "ppc4xx-host-bridge"); | |
327 | ||
328 | /* XXX split into 2 memory regions, one for config space, one for regs */ | |
40c5dce9 PB |
329 | memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE); |
330 | memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h, | |
623f7c21 | 331 | "pci-conf-idx", 4); |
40c5dce9 | 332 | memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h, |
623f7c21 | 333 | "pci-conf-data", 4); |
40c5dce9 | 334 | memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s, |
623f7c21 AG |
335 | "pci.reg", PCI_REG_SIZE); |
336 | memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); | |
337 | memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); | |
338 | memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); | |
95ba5567 | 339 | sysbus_init_mmio(sbd, &s->container); |
623f7c21 | 340 | qemu_register_reset(ppc4xx_pci_reset, s); |
623f7c21 AG |
341 | } |
342 | ||
40021f08 AL |
343 | static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) |
344 | { | |
345 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 346 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 347 | |
39bffca2 | 348 | dc->desc = "Host bridge"; |
40021f08 AL |
349 | k->vendor_id = PCI_VENDOR_ID_IBM; |
350 | k->device_id = PCI_DEVICE_ID_IBM_440GX; | |
351 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
08c58f92 MA |
352 | /* |
353 | * PCI-facing part of the host bridge, not usable without the | |
354 | * host-facing part, which can't be device_add'ed, yet. | |
355 | */ | |
e90f2a8c | 356 | dc->user_creatable = false; |
40021f08 AL |
357 | } |
358 | ||
4240abff | 359 | static const TypeInfo ppc4xx_host_bridge_info = { |
39bffca2 AL |
360 | .name = "ppc4xx-host-bridge", |
361 | .parent = TYPE_PCI_DEVICE, | |
362 | .instance_size = sizeof(PCIDevice), | |
363 | .class_init = ppc4xx_host_bridge_class_init, | |
fd3b02c8 EH |
364 | .interfaces = (InterfaceInfo[]) { |
365 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
366 | { }, | |
367 | }, | |
623f7c21 AG |
368 | }; |
369 | ||
999e12bb AL |
370 | static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) |
371 | { | |
39bffca2 | 372 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 373 | |
95ba5567 | 374 | dc->realize = ppc4xx_pcihost_realize; |
39bffca2 | 375 | dc->vmsd = &vmstate_ppc4xx_pci; |
999e12bb AL |
376 | } |
377 | ||
4240abff | 378 | static const TypeInfo ppc4xx_pcihost_info = { |
42c281a2 | 379 | .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, |
8558d942 | 380 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
381 | .instance_size = sizeof(PPC4xxPCIState), |
382 | .class_init = ppc4xx_pcihost_class_init, | |
623f7c21 AG |
383 | }; |
384 | ||
83f7d43a | 385 | static void ppc4xx_pci_register_types(void) |
825bb581 | 386 | { |
39bffca2 AL |
387 | type_register_static(&ppc4xx_pcihost_info); |
388 | type_register_static(&ppc4xx_host_bridge_info); | |
825bb581 | 389 | } |
83f7d43a AF |
390 | |
391 | type_init(ppc4xx_pci_register_types) |