[mirror_qemu.git] / hw / ppc / ppc4xx_pci.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Copyright IBM Corp. 2008
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

/* This file implements emulation of the 32-bit PCI controller found in some
 * 4xx SoCs, such as the 440EP. */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"

#undef DEBUG
#ifdef DEBUG
#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif /* DEBUG */

struct PCIMasterMap {
    uint32_t la;
    uint32_t ma;
    uint32_t pcila;
    uint32_t pciha;
};

struct PCITargetMap {
    uint32_t ms;
    uint32_t la;
};

#define PPC4xx_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)

#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2

struct PPC4xxPCIState {
    PCIHostState parent_obj;

    struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
    struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
    qemu_irq irq[4];

    MemoryRegion container;
    MemoryRegion iomem;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
 * PCI accesses. */
#define PCIL0_PMM0LA        0x0
#define PCIL0_PMM0MA        0x4
#define PCIL0_PMM0PCILA     0x8
#define PCIL0_PMM0PCIHA     0xc
#define PCIL0_PMM1LA        0x10
#define PCIL0_PMM1MA        0x14
#define PCIL0_PMM1PCILA     0x18
#define PCIL0_PMM1PCIHA     0x1c
#define PCIL0_PMM2LA        0x20
#define PCIL0_PMM2MA        0x24
#define PCIL0_PMM2PCILA     0x28
#define PCIL0_PMM2PCIHA     0x2c

/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
 * PLB accesses. */
#define PCIL0_PTM1MS        0x30
#define PCIL0_PTM1LA        0x34
#define PCIL0_PTM2MS        0x38
#define PCIL0_PTM2LA        0x3c
#define PCI_REG_BASE        0x800000
#define PCI_REG_SIZE        0x40

#define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)

static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
                                  uint64_t value, unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;

    /* We ignore all target attempts at PCI configuration, effectively
     * assuming a bidirectional 1:1 mapping of PLB and PCI space. */

    switch (offset) {
    case PCIL0_PMM0LA:
        pci->pmm[0].la = value;
        break;
    case PCIL0_PMM0MA:
        pci->pmm[0].ma = value;
        break;
    case PCIL0_PMM0PCIHA:
        pci->pmm[0].pciha = value;
        break;
    case PCIL0_PMM0PCILA:
        pci->pmm[0].pcila = value;
        break;

    case PCIL0_PMM1LA:
        pci->pmm[1].la = value;
        break;
    case PCIL0_PMM1MA:
        pci->pmm[1].ma = value;
        break;
    case PCIL0_PMM1PCIHA:
        pci->pmm[1].pciha = value;
        break;
    case PCIL0_PMM1PCILA:
        pci->pmm[1].pcila = value;
        break;

    case PCIL0_PMM2LA:
        pci->pmm[2].la = value;
        break;
    case PCIL0_PMM2MA:
        pci->pmm[2].ma = value;
        break;
    case PCIL0_PMM2PCIHA:
        pci->pmm[2].pciha = value;
        break;
    case PCIL0_PMM2PCILA:
        pci->pmm[2].pcila = value;
        break;

    case PCIL0_PTM1MS:
        pci->ptm[0].ms = value;
        break;
    case PCIL0_PTM1LA:
        pci->ptm[0].la = value;
        break;
    case PCIL0_PTM2MS:
        pci->ptm[1].ms = value;
        break;
    case PCIL0_PTM2LA:
        pci->ptm[1].la = value;
        break;

    default:
        printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        break;
    }
}

static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
                                     unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;
    uint32_t value;

    switch (offset) {
    case PCIL0_PMM0LA:
        value = pci->pmm[0].la;
        break;
    case PCIL0_PMM0MA:
        value = pci->pmm[0].ma;
        break;
    case PCIL0_PMM0PCIHA:
        value = pci->pmm[0].pciha;
        break;
    case PCIL0_PMM0PCILA:
        value = pci->pmm[0].pcila;
        break;

    case PCIL0_PMM1LA:
        value = pci->pmm[1].la;
        break;
    case PCIL0_PMM1MA:
        value = pci->pmm[1].ma;
        break;
    case PCIL0_PMM1PCIHA:
        value = pci->pmm[1].pciha;
        break;
    case PCIL0_PMM1PCILA:
        value = pci->pmm[1].pcila;
        break;

    case PCIL0_PMM2LA:
        value = pci->pmm[2].la;
        break;
    case PCIL0_PMM2MA:
        value = pci->pmm[2].ma;
        break;
    case PCIL0_PMM2PCIHA:
        value = pci->pmm[2].pciha;
        break;
    case PCIL0_PMM2PCILA:
        value = pci->pmm[2].pcila;
        break;

    case PCIL0_PTM1MS:
        value = pci->ptm[0].ms;
        break;
    case PCIL0_PTM1LA:
        value = pci->ptm[0].la;
        break;
    case PCIL0_PTM2MS:
        value = pci->ptm[1].ms;
        break;
    case PCIL0_PTM2LA:
        value = pci->ptm[1].la;
        break;

    default:
        printf("%s: invalid PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        value = 0;
    }

    return value;
}

static const MemoryRegionOps pci_reg_ops = {
    .read = ppc4xx_pci_reg_read4,
    .write = ppc4xx_pci_reg_write4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc4xx_pci_reset(void *opaque)
{
    struct PPC4xxPCIState *pci = opaque;

    memset(pci->pmm, 0, sizeof(pci->pmm));
    memset(pci->ptm, 0, sizeof(pci->ptm));
}

/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 * may need further refactoring for other boards. */
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot = pci_dev->devfn >> 3;

    DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
            pci_dev->devfn, irq_num, slot);

    return slot - 1;
}

static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irqs = opaque;

    DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
    if (irq_num < 0) {
        fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
        return;
    }
    qemu_set_irq(pci_irqs[irq_num], level);
}

static const VMStateDescription vmstate_pci_master_map = {
    .name = "pci_master_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(la, struct PCIMasterMap),
        VMSTATE_UINT32(ma, struct PCIMasterMap),
        VMSTATE_UINT32(pcila, struct PCIMasterMap),
        VMSTATE_UINT32(pciha, struct PCIMasterMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_target_map = {
    .name = "pci_target_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(ms, struct PCITargetMap),
        VMSTATE_UINT32(la, struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppc4xx_pci = {
    .name = "ppc4xx_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
                             vmstate_pci_master_map,
                             struct PCIMasterMap),
        VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
                             vmstate_pci_target_map,
                             struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

/* XXX Interrupt acknowledge cycles not supported. */
static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
{
    PPC4xxPCIState *s;
    PCIHostState *h;
    PCIBus *b;
    int i;

    h = PCI_HOST_BRIDGE(dev);
    s = PPC4xx_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
                         ppc4xx_pci_map_irq, s->irq, get_system_memory(),
                         get_system_io(), 0, 4, TYPE_PCI_BUS);
    h->bus = b;

    pci_create_simple(b, 0, "ppc4xx-host-bridge");

    /* XXX split into 2 memory regions, one for config space, one for regs */
    memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
                          "pci.reg", PCI_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);
    qemu_register_reset(ppc4xx_pci_reset, s);

    return 0;
}

static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc        = "Host bridge";
    k->vendor_id    = PCI_VENDOR_ID_IBM;
    k->device_id    = PCI_DEVICE_ID_IBM_440GX;
    k->class_id     = PCI_CLASS_BRIDGE_OTHER;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo ppc4xx_host_bridge_info = {
    .name          = "ppc4xx-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = ppc4xx_host_bridge_class_init,
};

static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->init = ppc4xx_pcihost_initfn;
    dc->vmsd = &vmstate_ppc4xx_pci;
}

static const TypeInfo ppc4xx_pcihost_info = {
    .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPC4xxPCIState),
    .class_init    = ppc4xx_pcihost_class_init,
};

static void ppc4xx_pci_register_types(void)
{
    type_register_static(&ppc4xx_pcihost_info);
    type_register_static(&ppc4xx_host_bridge_info);
}

type_init(ppc4xx_pci_register_types)
Commit	Line	Data
825bb581 AJ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
8167ee88	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
825bb581 AJ	13	*
	14	* Copyright IBM Corp. 2008
	15	*
	16	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	17	*/
	18
	19	/* This file implements emulation of the 32-bit PCI controller found in some
	20	* 4xx SoCs, such as the 440EP. */
	21
0d75590d	22	#include "qemu/osdep.h"
83c9f4ca	23	#include "hw/hw.h"
0d09e41a PB	24	#include "hw/ppc/ppc.h"
0d09e41a PB	25	#include "hw/ppc/ppc4xx.h"
83c9f4ca PB	26	#include "hw/pci/pci.h"
83c9f4ca PB	27	#include "hw/pci/pci_host.h"
022c62cb	28	#include "exec/address-spaces.h"
825bb581 AJ	29
	30	#undef DEBUG
	31	#ifdef DEBUG
	32	#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
	33	#else
001faf32	34	#define DPRINTF(fmt, ...)
825bb581 AJ	35	#endif /* DEBUG */
	36
	37	struct PCIMasterMap {
	38	uint32_t la;
	39	uint32_t ma;
	40	uint32_t pcila;
	41	uint32_t pciha;
	42	};
	43
	44	struct PCITargetMap {
	45	uint32_t ms;
	46	uint32_t la;
	47	};
	48
42c281a2 AF	49	#define PPC4xx_PCI_HOST_BRIDGE(obj) \
	50	OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
	51
825bb581 AJ	52	#define PPC4xx_PCI_NR_PMMS 3
	53	#define PPC4xx_PCI_NR_PTMS 2
	54
	55	struct PPC4xxPCIState {
67c332fd	56	PCIHostState parent_obj;
623f7c21	57
825bb581 AJ	58	struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
825bb581 AJ	59	struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
623f7c21	60	qemu_irq irq[4];
825bb581	61
623f7c21 AG	62	MemoryRegion container;
623f7c21 AG	63	MemoryRegion iomem;
825bb581 AJ	64	};
	65	typedef struct PPC4xxPCIState PPC4xxPCIState;
	66
	67	#define PCIC0_CFGADDR 0x0
	68	#define PCIC0_CFGDATA 0x4
	69
	70	/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
	71	* PCI accesses. */
	72	#define PCIL0_PMM0LA 0x0
	73	#define PCIL0_PMM0MA 0x4
	74	#define PCIL0_PMM0PCILA 0x8
	75	#define PCIL0_PMM0PCIHA 0xc
	76	#define PCIL0_PMM1LA 0x10
	77	#define PCIL0_PMM1MA 0x14
	78	#define PCIL0_PMM1PCILA 0x18
	79	#define PCIL0_PMM1PCIHA 0x1c
	80	#define PCIL0_PMM2LA 0x20
	81	#define PCIL0_PMM2MA 0x24
	82	#define PCIL0_PMM2PCILA 0x28
	83	#define PCIL0_PMM2PCIHA 0x2c
	84
	85	/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
	86	* PLB accesses. */
	87	#define PCIL0_PTM1MS 0x30
	88	#define PCIL0_PTM1LA 0x34
	89	#define PCIL0_PTM2MS 0x38
	90	#define PCIL0_PTM2LA 0x3c
623f7c21	91	#define PCI_REG_BASE 0x800000
825bb581 AJ	92	#define PCI_REG_SIZE 0x40
825bb581 AJ	93
623f7c21	94	#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
825bb581	95
a8170e5e	96	static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
da726e5e	97	uint64_t value, unsigned size)
825bb581 AJ	98	{
	99	struct PPC4xxPCIState *pci = opaque;
	100
825bb581 AJ	101	/* We ignore all target attempts at PCI configuration, effectively
	102	* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
	103
	104	switch (offset) {
	105	case PCIL0_PMM0LA:
	106	pci->pmm[0].la = value;
	107	break;
	108	case PCIL0_PMM0MA:
	109	pci->pmm[0].ma = value;
	110	break;
	111	case PCIL0_PMM0PCIHA:
	112	pci->pmm[0].pciha = value;
	113	break;
	114	case PCIL0_PMM0PCILA:
	115	pci->pmm[0].pcila = value;
	116	break;
	117
	118	case PCIL0_PMM1LA:
	119	pci->pmm[1].la = value;
	120	break;
	121	case PCIL0_PMM1MA:
	122	pci->pmm[1].ma = value;
	123	break;
	124	case PCIL0_PMM1PCIHA:
	125	pci->pmm[1].pciha = value;
	126	break;
	127	case PCIL0_PMM1PCILA:
	128	pci->pmm[1].pcila = value;
	129	break;
	130
	131	case PCIL0_PMM2LA:
	132	pci->pmm[2].la = value;
	133	break;
	134	case PCIL0_PMM2MA:
	135	pci->pmm[2].ma = value;
	136	break;
	137	case PCIL0_PMM2PCIHA:
	138	pci->pmm[2].pciha = value;
	139	break;
	140	case PCIL0_PMM2PCILA:
	141	pci->pmm[2].pcila = value;
	142	break;
	143
	144	case PCIL0_PTM1MS:
	145	pci->ptm[0].ms = value;
	146	break;
	147	case PCIL0_PTM1LA:
	148	pci->ptm[0].la = value;
	149	break;
	150	case PCIL0_PTM2MS:
	151	pci->ptm[1].ms = value;
	152	break;
	153	case PCIL0_PTM2LA:
	154	pci->ptm[1].la = value;
	155	break;
	156
	157	default:
	158	printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
	159	(unsigned long)offset);
	160	break;
	161	}
	162	}
	163
a8170e5e	164	static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
da726e5e	165	unsigned size)
825bb581 AJ	166	{
	167	struct PPC4xxPCIState *pci = opaque;
	168	uint32_t value;
	169
	170	switch (offset) {
	171	case PCIL0_PMM0LA:
	172	value = pci->pmm[0].la;
	173	break;
	174	case PCIL0_PMM0MA:
	175	value = pci->pmm[0].ma;
	176	break;
	177	case PCIL0_PMM0PCIHA:
	178	value = pci->pmm[0].pciha;
	179	break;
	180	case PCIL0_PMM0PCILA:
	181	value = pci->pmm[0].pcila;
	182	break;
	183
	184	case PCIL0_PMM1LA:
	185	value = pci->pmm[1].la;
	186	break;
	187	case PCIL0_PMM1MA:
	188	value = pci->pmm[1].ma;
	189	break;
	190	case PCIL0_PMM1PCIHA:
	191	value = pci->pmm[1].pciha;
	192	break;
	193	case PCIL0_PMM1PCILA:
	194	value = pci->pmm[1].pcila;
	195	break;
	196
	197	case PCIL0_PMM2LA:
	198	value = pci->pmm[2].la;
	199	break;
	200	case PCIL0_PMM2MA:
	201	value = pci->pmm[2].ma;
	202	break;
	203	case PCIL0_PMM2PCIHA:
	204	value = pci->pmm[2].pciha;
	205	break;
	206	case PCIL0_PMM2PCILA:
	207	value = pci->pmm[2].pcila;
	208	break;
	209
	210	case PCIL0_PTM1MS:
	211	value = pci->ptm[0].ms;
	212	break;
	213	case PCIL0_PTM1LA:
	214	value = pci->ptm[0].la;
	215	break;
	216	case PCIL0_PTM2MS:
	217	value = pci->ptm[1].ms;
	218	break;
	219	case PCIL0_PTM2LA:
	220	value = pci->ptm[1].la;
	221	break;
	222
	223	default:
	224	printf("%s: invalid PCI internal register 0x%lx\n", __func__,
	225	(unsigned long)offset);
	226	value = 0;
	227	}
	228
825bb581 AJ	229	return value;
	230	}
	231
da726e5e AK	232	static const MemoryRegionOps pci_reg_ops = {
	233	.read = ppc4xx_pci_reg_read4,
	234	.write = ppc4xx_pci_reg_write4,
	235	.endianness = DEVICE_LITTLE_ENDIAN,
825bb581 AJ	236	};
	237
	238	static void ppc4xx_pci_reset(void *opaque)
	239	{
	240	struct PPC4xxPCIState *pci = opaque;
	241
	242	memset(pci->pmm, 0, sizeof(pci->pmm));
	243	memset(pci->ptm, 0, sizeof(pci->ptm));
	244	}
	245
	246	/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
	247	* may need further refactoring for other boards. */
	248	static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	249	{
	250	int slot = pci_dev->devfn >> 3;
	251
	252	DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
	253	pci_dev->devfn, irq_num, slot);
	254
	255	return slot - 1;
	256	}
	257
5d4e84c8	258	static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
825bb581	259	{
5d4e84c8 JQ	260	qemu_irq *pci_irqs = opaque;
5d4e84c8 JQ	261
825bb581	262	DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
d49bc1fb AG	263	if (irq_num < 0) {
	264	fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
	265	return;
	266	}
825bb581 AJ	267	qemu_set_irq(pci_irqs[irq_num], level);
	268	}
	269
b605f222 JQ	270	static const VMStateDescription vmstate_pci_master_map = {
	271	.name = "pci_master_map",
	272	.version_id = 0,
	273	.minimum_version_id = 0,
3aff6c2f	274	.fields = (VMStateField[]) {
b605f222 JQ	275	VMSTATE_UINT32(la, struct PCIMasterMap),
	276	VMSTATE_UINT32(ma, struct PCIMasterMap),
	277	VMSTATE_UINT32(pcila, struct PCIMasterMap),
	278	VMSTATE_UINT32(pciha, struct PCIMasterMap),
	279	VMSTATE_END_OF_LIST()
825bb581	280	}
b605f222	281	};
825bb581	282
b605f222 JQ	283	static const VMStateDescription vmstate_pci_target_map = {
	284	.name = "pci_target_map",
	285	.version_id = 0,
	286	.minimum_version_id = 0,
3aff6c2f	287	.fields = (VMStateField[]) {
b605f222 JQ	288	VMSTATE_UINT32(ms, struct PCITargetMap),
	289	VMSTATE_UINT32(la, struct PCITargetMap),
	290	VMSTATE_END_OF_LIST()
825bb581	291	}
b605f222	292	};
825bb581	293
b605f222 JQ	294	static const VMStateDescription vmstate_ppc4xx_pci = {
	295	.name = "ppc4xx_pci",
	296	.version_id = 1,
	297	.minimum_version_id = 1,
3aff6c2f	298	.fields = (VMStateField[]) {
b605f222 JQ	299	VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
	300	vmstate_pci_master_map,
	301	struct PCIMasterMap),
	302	VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
	303	vmstate_pci_target_map,
	304	struct PCITargetMap),
	305	VMSTATE_END_OF_LIST()
825bb581	306	}
b605f222	307	};
825bb581 AJ	308
825bb581 AJ	309	/* XXX Interrupt acknowledge cycles not supported. */
623f7c21 AG	310	static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
	311	{
	312	PPC4xxPCIState *s;
	313	PCIHostState *h;
	314	PCIBus *b;
	315	int i;
	316
8558d942	317	h = PCI_HOST_BRIDGE(dev);
42c281a2	318	s = PPC4xx_PCI_HOST_BRIDGE(dev);
623f7c21 AG	319
	320	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	321	sysbus_init_irq(dev, &s->irq[i]);
	322	}
	323
42c281a2	324	b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
623f7c21	325	ppc4xx_pci_map_irq, s->irq, get_system_memory(),
60a0e443	326	get_system_io(), 0, 4, TYPE_PCI_BUS);
42c281a2	327	h->bus = b;
623f7c21 AG	328
	329	pci_create_simple(b, 0, "ppc4xx-host-bridge");
	330
	331	/* XXX split into 2 memory regions, one for config space, one for regs */
40c5dce9 PB	332	memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
40c5dce9 PB	333	memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
623f7c21	334	"pci-conf-idx", 4);
40c5dce9	335	memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
623f7c21	336	"pci-conf-data", 4);
40c5dce9	337	memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
623f7c21 AG	338	"pci.reg", PCI_REG_SIZE);
	339	memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
	340	memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
	341	memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
	342	sysbus_init_mmio(dev, &s->container);
	343	qemu_register_reset(ppc4xx_pci_reset, s);
	344
	345	return 0;
	346	}
	347
40021f08 AL	348	static void ppc4xx_host_bridge_class_init(ObjectClass klass, void data)
	349	{
	350	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2	351	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	352
39bffca2	353	dc->desc = "Host bridge";
40021f08 AL	354	k->vendor_id = PCI_VENDOR_ID_IBM;
	355	k->device_id = PCI_DEVICE_ID_IBM_440GX;
	356	k->class_id = PCI_CLASS_BRIDGE_OTHER;
08c58f92 MA	357	/*
	358	* PCI-facing part of the host bridge, not usable without the
	359	* host-facing part, which can't be device_add'ed, yet.
	360	*/
	361	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	362	}
40021f08 AL	363
4240abff	364	static const TypeInfo ppc4xx_host_bridge_info = {
39bffca2 AL	365	.name = "ppc4xx-host-bridge",
	366	.parent = TYPE_PCI_DEVICE,
	367	.instance_size = sizeof(PCIDevice),
	368	.class_init = ppc4xx_host_bridge_class_init,
623f7c21 AG	369	};
623f7c21 AG	370
999e12bb AL	371	static void ppc4xx_pcihost_class_init(ObjectClass klass, void data)
	372	{
	373	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	374	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	375
999e12bb AL	376	k->init = ppc4xx_pcihost_initfn;
39bffca2	377	dc->vmsd = &vmstate_ppc4xx_pci;
999e12bb AL	378	}
999e12bb AL	379
4240abff	380	static const TypeInfo ppc4xx_pcihost_info = {
42c281a2	381	.name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
8558d942	382	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	383	.instance_size = sizeof(PPC4xxPCIState),
39bffca2 AL	384	.class_init = ppc4xx_pcihost_class_init,
623f7c21 AG	385	};
623f7c21 AG	386
83f7d43a	387	static void ppc4xx_pci_register_types(void)
825bb581	388	{
39bffca2 AL	389	type_register_static(&ppc4xx_pcihost_info);
39bffca2 AL	390	type_register_static(&ppc4xx_host_bridge_info);
825bb581	391	}
83f7d43a AF	392
83f7d43a AF	393	type_init(ppc4xx_pci_register_types)