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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
34b9b557 | 5 | * Copyright (c) 2017 Hervé Poussineau |
5fafdf24 | 6 | * |
a541f297 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
9a64fbe4 | 24 | */ |
71e8a915 | 25 | |
0d75590d | 26 | #include "qemu/osdep.h" |
33c11879 | 27 | #include "cpu.h" |
819ce6b2 | 28 | #include "hw/rtc/m48t59.h" |
0d09e41a PB |
29 | #include "hw/char/serial.h" |
30 | #include "hw/block/fdc.h" | |
1422e32d | 31 | #include "net/net.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
0d09e41a | 33 | #include "hw/isa/isa.h" |
75610155 AF |
34 | #include "hw/pci/pci.h" |
35 | #include "hw/pci/pci_host.h" | |
0d09e41a | 36 | #include "hw/ppc/ppc.h" |
75610155 | 37 | #include "hw/boards.h" |
3e80f690 | 38 | #include "qapi/error.h" |
c525436e | 39 | #include "qemu/error-report.h" |
1de7afc9 | 40 | #include "qemu/log.h" |
64552b6b | 41 | #include "hw/irq.h" |
75610155 | 42 | #include "hw/loader.h" |
bcdb9064 | 43 | #include "hw/rtc/mc146818rtc.h" |
0d09e41a | 44 | #include "hw/isa/pc87312.h" |
b2ce76a0 | 45 | #include "hw/qdev-properties.h" |
9c17d615 | 46 | #include "sysemu/arch_init.h" |
34b9b557 | 47 | #include "sysemu/kvm.h" |
97c42c3c | 48 | #include "sysemu/qtest.h" |
71e8a915 | 49 | #include "sysemu/reset.h" |
022c62cb | 50 | #include "exec/address-spaces.h" |
659f7f65 | 51 | #include "trace.h" |
97c42c3c | 52 | #include "elf.h" |
ab3dd749 | 53 | #include "qemu/units.h" |
34b9b557 | 54 | #include "kvm_ppc.h" |
9fddaa0c | 55 | |
fe33cc71 JM |
56 | /* SMP is not enabled, for now */ |
57 | #define MAX_CPUS 1 | |
58 | ||
e4bcb14c TS |
59 | #define MAX_IDE_BUS 2 |
60 | ||
34b9b557 HP |
61 | #define CFG_ADDR 0xf0000510 |
62 | ||
b6b8bd18 FB |
63 | #define KERNEL_LOAD_ADDR 0x01000000 |
64 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 65 | |
64201201 | 66 | #define NVRAM_SIZE 0x2000 |
a541f297 | 67 | |
34b9b557 HP |
68 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
69 | Error **errp) | |
70 | { | |
71 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
72 | } | |
73 | ||
1bba0dc9 AF |
74 | static void ppc_prep_reset(void *opaque) |
75 | { | |
5c3e735f | 76 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 77 | |
5c3e735f | 78 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
79 | } |
80 | ||
848696bf | 81 | |
31688246 HP |
82 | /*****************************************************************************/ |
83 | /* NVRAM helpers */ | |
84 | static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) | |
85 | { | |
5904bca8 | 86 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
87 | return (k->read)(nvram, addr); |
88 | } | |
89 | ||
90 | static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) | |
91 | { | |
5904bca8 | 92 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
93 | (k->write)(nvram, addr, val); |
94 | } | |
95 | ||
96 | static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) | |
97 | { | |
98 | nvram_write(nvram, addr, value); | |
99 | } | |
100 | ||
101 | static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) | |
102 | { | |
103 | return nvram_read(nvram, addr); | |
104 | } | |
105 | ||
106 | static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) | |
107 | { | |
108 | nvram_write(nvram, addr, value >> 8); | |
109 | nvram_write(nvram, addr + 1, value & 0xFF); | |
110 | } | |
111 | ||
112 | static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) | |
113 | { | |
114 | uint16_t tmp; | |
115 | ||
116 | tmp = nvram_read(nvram, addr) << 8; | |
117 | tmp |= nvram_read(nvram, addr + 1); | |
118 | ||
119 | return tmp; | |
120 | } | |
121 | ||
122 | static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) | |
123 | { | |
124 | nvram_write(nvram, addr, value >> 24); | |
125 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
126 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
127 | nvram_write(nvram, addr + 3, value & 0xFF); | |
128 | } | |
129 | ||
130 | static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, | |
131 | uint32_t max) | |
132 | { | |
133 | int i; | |
134 | ||
135 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
136 | nvram_write(nvram, addr + i, str[i]); | |
137 | } | |
138 | nvram_write(nvram, addr + i, str[i]); | |
139 | nvram_write(nvram, addr + max - 1, '\0'); | |
140 | } | |
141 | ||
142 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
143 | { | |
144 | uint16_t tmp; | |
145 | uint16_t pd, pd1, pd2; | |
146 | ||
147 | tmp = prev >> 8; | |
148 | pd = prev ^ value; | |
149 | pd1 = pd & 0x000F; | |
150 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
151 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
152 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
153 | ||
154 | return tmp; | |
155 | } | |
156 | ||
157 | static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) | |
158 | { | |
159 | uint32_t i; | |
160 | uint16_t crc = 0xFFFF; | |
161 | int odd; | |
162 | ||
163 | odd = count & 1; | |
164 | count &= ~1; | |
165 | for (i = 0; i != count; i++) { | |
166 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
167 | } | |
168 | if (odd) { | |
169 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
170 | } | |
171 | ||
172 | return crc; | |
173 | } | |
174 | ||
175 | #define CMDLINE_ADDR 0x017ff000 | |
176 | ||
177 | static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, | |
178 | const char *arch, | |
179 | uint32_t RAM_size, int boot_device, | |
180 | uint32_t kernel_image, uint32_t kernel_size, | |
181 | const char *cmdline, | |
182 | uint32_t initrd_image, uint32_t initrd_size, | |
183 | uint32_t NVRAM_image, | |
184 | int width, int height, int depth) | |
185 | { | |
186 | uint16_t crc; | |
187 | ||
188 | /* Set parameters for Open Hack'Ware BIOS */ | |
189 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
190 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
191 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
192 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
193 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
194 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
195 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
196 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
197 | if (cmdline) { | |
198 | /* XXX: put the cmdline in NVRAM too ? */ | |
199 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, | |
200 | cmdline); | |
201 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
202 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
203 | } else { | |
204 | NVRAM_set_lword(nvram, 0x40, 0); | |
205 | NVRAM_set_lword(nvram, 0x44, 0); | |
206 | } | |
207 | NVRAM_set_lword(nvram, 0x48, initrd_image); | |
208 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
209 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
210 | ||
211 | NVRAM_set_word(nvram, 0x54, width); | |
212 | NVRAM_set_word(nvram, 0x56, height); | |
213 | NVRAM_set_word(nvram, 0x58, depth); | |
214 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
215 | NVRAM_set_word(nvram, 0xFC, crc); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
34b9b557 HP |
220 | static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) |
221 | { | |
222 | uint16_t checksum = *(uint16_t *)opaque; | |
223 | ISADevice *rtc; | |
224 | ||
c50be9e1 | 225 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { |
34b9b557 HP |
226 | rtc = ISA_DEVICE(dev); |
227 | rtc_set_memory(rtc, 0x2e, checksum & 0xff); | |
228 | rtc_set_memory(rtc, 0x3e, checksum & 0xff); | |
229 | rtc_set_memory(rtc, 0x2f, checksum >> 8); | |
230 | rtc_set_memory(rtc, 0x3f, checksum >> 8); | |
29551fdc TH |
231 | |
232 | object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), | |
d2623129 | 233 | "date"); |
34b9b557 HP |
234 | } |
235 | return 0; | |
236 | } | |
237 | ||
238 | static void ibm_40p_init(MachineState *machine) | |
239 | { | |
cd7b9498 | 240 | const char *bios_name = machine->firmware ?: "openbios-ppc"; |
34b9b557 HP |
241 | CPUPPCState *env = NULL; |
242 | uint16_t cmos_checksum; | |
243 | PowerPCCPU *cpu; | |
0358687b | 244 | DeviceState *dev, *i82378_dev; |
0f080859 | 245 | SysBusDevice *pcihost, *s; |
34b9b557 HP |
246 | Nvram *m48t59 = NULL; |
247 | PCIBus *pci_bus; | |
96927c74 | 248 | ISADevice *isa_dev; |
34b9b557 HP |
249 | ISABus *isa_bus; |
250 | void *fw_cfg; | |
251 | int i; | |
252 | uint32_t kernel_base = 0, initrd_base = 0; | |
253 | long kernel_size = 0, initrd_size = 0; | |
254 | char boot_device; | |
255 | ||
256 | /* init CPU */ | |
23ec69ec | 257 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
34b9b557 HP |
258 | env = &cpu->env; |
259 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
260 | error_report("only 6xx bus is supported on this machine"); | |
261 | exit(1); | |
262 | } | |
263 | ||
264 | if (env->flags & POWERPC_FLAG_RTC_CLK) { | |
265 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
266 | cpu_ppc_tb_init(env, 7812500UL); | |
267 | } else { | |
268 | /* Set time-base frequency to 100 Mhz */ | |
269 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
270 | } | |
271 | qemu_register_reset(ppc_prep_reset, cpu); | |
272 | ||
273 | /* PCI host */ | |
3e80f690 | 274 | dev = qdev_new("raven-pcihost"); |
34b9b557 HP |
275 | qdev_prop_set_string(dev, "bios-name", bios_name); |
276 | qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); | |
277 | pcihost = SYS_BUS_DEVICE(dev); | |
d2623129 | 278 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); |
3c6ef471 | 279 | sysbus_realize_and_unref(pcihost, &error_fatal); |
34b9b557 HP |
280 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
281 | if (!pci_bus) { | |
282 | error_report("could not create PCI host controller"); | |
283 | exit(1); | |
284 | } | |
285 | ||
286 | /* PCI -> ISA bridge */ | |
0358687b MCA |
287 | i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); |
288 | qdev_connect_gpio_out(i82378_dev, 0, | |
34b9b557 | 289 | cpu->env.irq_inputs[PPC6xx_INPUT_INT]); |
0358687b MCA |
290 | sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); |
291 | isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); | |
34b9b557 HP |
292 | |
293 | /* Memory controller */ | |
96927c74 MA |
294 | isa_dev = isa_new("rs6000-mc"); |
295 | dev = DEVICE(isa_dev); | |
34b9b557 | 296 | qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); |
96927c74 | 297 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 298 | |
2e8f8518 | 299 | /* RTC */ |
96927c74 MA |
300 | isa_dev = isa_new(TYPE_MC146818_RTC); |
301 | dev = DEVICE(isa_dev); | |
1dbe3d19 | 302 | qdev_prop_set_int32(dev, "base_year", 1900); |
96927c74 | 303 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
2e8f8518 | 304 | |
34b9b557 HP |
305 | /* initialize CMOS checksums */ |
306 | cmos_checksum = 0x6aa9; | |
307 | qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, | |
308 | &cmos_checksum); | |
309 | ||
34b9b557 HP |
310 | /* add some more devices */ |
311 | if (defaults_enabled()) { | |
34b9b557 HP |
312 | m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); |
313 | ||
96927c74 MA |
314 | isa_dev = isa_new("cs4231a"); |
315 | dev = DEVICE(isa_dev); | |
34b9b557 HP |
316 | qdev_prop_set_uint32(dev, "iobase", 0x830); |
317 | qdev_prop_set_uint32(dev, "irq", 10); | |
96927c74 | 318 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 319 | |
96927c74 MA |
320 | isa_dev = isa_new("pc87312"); |
321 | dev = DEVICE(isa_dev); | |
34b9b557 | 322 | qdev_prop_set_uint32(dev, "config", 12); |
96927c74 | 323 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 324 | |
96927c74 MA |
325 | isa_dev = isa_new("prep-systemio"); |
326 | dev = DEVICE(isa_dev); | |
34b9b557 HP |
327 | qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); |
328 | qdev_prop_set_uint32(dev, "equipment", 0xc0); | |
96927c74 | 329 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 330 | |
877eb21d MCA |
331 | dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), |
332 | "lsi53c810")); | |
333 | lsi53c8xx_handle_legacy_cmdline(dev); | |
0358687b | 334 | qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); |
34b9b557 HP |
335 | |
336 | /* XXX: s3-trio at PCI_DEVFN(2, 0) */ | |
337 | pci_vga_init(pci_bus); | |
338 | ||
339 | for (i = 0; i < nb_nics; i++) { | |
340 | pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", | |
341 | i == 0 ? "3" : NULL); | |
342 | } | |
343 | } | |
344 | ||
345 | /* Prepare firmware configuration for OpenBIOS */ | |
3e80f690 | 346 | dev = qdev_new(TYPE_FW_CFG_MEM); |
0f080859 MCA |
347 | fw_cfg = FW_CFG(dev); |
348 | qdev_prop_set_uint32(dev, "data_width", 1); | |
349 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
350 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, | |
d2623129 | 351 | OBJECT(fw_cfg)); |
0f080859 | 352 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 353 | sysbus_realize_and_unref(s, &error_fatal); |
0f080859 MCA |
354 | sysbus_mmio_map(s, 0, CFG_ADDR); |
355 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); | |
34b9b557 HP |
356 | |
357 | if (machine->kernel_filename) { | |
358 | /* load kernel */ | |
359 | kernel_base = KERNEL_LOAD_ADDR; | |
360 | kernel_size = load_image_targphys(machine->kernel_filename, | |
361 | kernel_base, | |
362 | machine->ram_size - kernel_base); | |
363 | if (kernel_size < 0) { | |
364 | error_report("could not load kernel '%s'", | |
365 | machine->kernel_filename); | |
366 | exit(1); | |
367 | } | |
368 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); | |
369 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
370 | /* load initrd */ | |
371 | if (machine->initrd_filename) { | |
372 | initrd_base = INITRD_LOAD_ADDR; | |
373 | initrd_size = load_image_targphys(machine->initrd_filename, | |
374 | initrd_base, | |
375 | machine->ram_size - initrd_base); | |
376 | if (initrd_size < 0) { | |
377 | error_report("could not load initial ram disk '%s'", | |
378 | machine->initrd_filename); | |
379 | exit(1); | |
380 | } | |
381 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
382 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
383 | } | |
384 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | |
385 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
386 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, | |
387 | machine->kernel_cmdline); | |
388 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
389 | machine->kernel_cmdline); | |
390 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
391 | strlen(machine->kernel_cmdline) + 1); | |
392 | } | |
393 | boot_device = 'm'; | |
394 | } else { | |
395 | boot_device = machine->boot_order[0]; | |
396 | } | |
397 | ||
fe6b6346 | 398 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
34b9b557 HP |
399 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
400 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); | |
401 | ||
402 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); | |
403 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); | |
404 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); | |
405 | ||
406 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); | |
407 | if (kvm_enabled()) { | |
34b9b557 HP |
408 | uint8_t *hypercall; |
409 | ||
410 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); | |
411 | hypercall = g_malloc(16); | |
412 | kvmppc_get_hypercall(env, hypercall, 16); | |
413 | fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); | |
414 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); | |
34b9b557 HP |
415 | } else { |
416 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); | |
417 | } | |
418 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); | |
419 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
420 | ||
421 | /* Prepare firmware configuration for Open Hack'Ware */ | |
422 | if (m48t59) { | |
ead2b283 | 423 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, |
34b9b557 HP |
424 | boot_device, |
425 | kernel_base, kernel_size, | |
426 | machine->kernel_cmdline, | |
427 | initrd_base, initrd_size, | |
428 | /* XXX: need an option to load a NVRAM image */ | |
429 | 0, | |
430 | graphic_width, graphic_height, graphic_depth); | |
431 | } | |
432 | } | |
433 | ||
434 | static void ibm_40p_machine_init(MachineClass *mc) | |
435 | { | |
436 | mc->desc = "IBM RS/6000 7020 (40p)", | |
437 | mc->init = ibm_40p_init; | |
438 | mc->max_cpus = 1; | |
d23b6caa | 439 | mc->default_ram_size = 128 * MiB; |
34b9b557 HP |
440 | mc->block_default_type = IF_SCSI; |
441 | mc->default_boot_order = "c"; | |
23ec69ec | 442 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); |
4cb25fbb | 443 | mc->default_display = "std"; |
34b9b557 HP |
444 | } |
445 | ||
446 | DEFINE_MACHINE("40p", ibm_40p_machine_init) |