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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
34b9b557 | 5 | * Copyright (c) 2017 Hervé Poussineau |
5fafdf24 | 6 | * |
a541f297 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
9a64fbe4 | 24 | */ |
0d75590d | 25 | #include "qemu/osdep.h" |
33c11879 | 26 | #include "cpu.h" |
75610155 | 27 | #include "hw/hw.h" |
0d09e41a PB |
28 | #include "hw/timer/m48t59.h" |
29 | #include "hw/i386/pc.h" | |
30 | #include "hw/char/serial.h" | |
31 | #include "hw/block/fdc.h" | |
1422e32d | 32 | #include "net/net.h" |
9c17d615 | 33 | #include "sysemu/sysemu.h" |
0d09e41a | 34 | #include "hw/isa/isa.h" |
75610155 AF |
35 | #include "hw/pci/pci.h" |
36 | #include "hw/pci/pci_host.h" | |
0d09e41a | 37 | #include "hw/ppc/ppc.h" |
75610155 | 38 | #include "hw/boards.h" |
c525436e | 39 | #include "qemu/error-report.h" |
1de7afc9 | 40 | #include "qemu/log.h" |
75610155 AF |
41 | #include "hw/ide.h" |
42 | #include "hw/loader.h" | |
0d09e41a PB |
43 | #include "hw/timer/mc146818rtc.h" |
44 | #include "hw/isa/pc87312.h" | |
4be74634 | 45 | #include "sysemu/block-backend.h" |
9c17d615 | 46 | #include "sysemu/arch_init.h" |
34b9b557 | 47 | #include "sysemu/kvm.h" |
97c42c3c | 48 | #include "sysemu/qtest.h" |
022c62cb | 49 | #include "exec/address-spaces.h" |
659f7f65 | 50 | #include "trace.h" |
97c42c3c | 51 | #include "elf.h" |
f348b6d1 | 52 | #include "qemu/cutils.h" |
34b9b557 | 53 | #include "kvm_ppc.h" |
9fddaa0c | 54 | |
fe33cc71 JM |
55 | /* SMP is not enabled, for now */ |
56 | #define MAX_CPUS 1 | |
57 | ||
e4bcb14c TS |
58 | #define MAX_IDE_BUS 2 |
59 | ||
34b9b557 HP |
60 | #define CFG_ADDR 0xf0000510 |
61 | ||
bba831e8 | 62 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
63 | #define BIOS_FILENAME "ppc_rom.bin" |
64 | #define KERNEL_LOAD_ADDR 0x01000000 | |
65 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 66 | |
64201201 | 67 | /* Constants for devices init */ |
a541f297 FB |
68 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
69 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
70 | static const int ide_irq[2] = { 13, 13 }; | |
71 | ||
72 | #define NE2000_NB_MAX 6 | |
73 | ||
74 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
75 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 76 | |
64201201 | 77 | /* ISA IO ports bridge */ |
9a64fbe4 FB |
78 | #define PPC_IO_BASE 0x80000000 |
79 | ||
64201201 FB |
80 | /* PowerPC control and status registers */ |
81 | #if 0 // Not used | |
82 | static struct { | |
83 | /* IDs */ | |
84 | uint32_t veni_devi; | |
85 | uint32_t revi; | |
86 | /* Control and status */ | |
87 | uint32_t gcsr; | |
88 | uint32_t xcfr; | |
89 | uint32_t ct32; | |
90 | uint32_t mcsr; | |
91 | /* General purpose registers */ | |
92 | uint32_t gprg[6]; | |
93 | /* Exceptions */ | |
94 | uint32_t feen; | |
95 | uint32_t fest; | |
96 | uint32_t fema; | |
97 | uint32_t fecl; | |
98 | uint32_t eeen; | |
99 | uint32_t eest; | |
100 | uint32_t eecl; | |
101 | uint32_t eeint; | |
102 | uint32_t eemck0; | |
103 | uint32_t eemck1; | |
104 | /* Error diagnostic */ | |
105 | } XCSR; | |
64201201 | 106 | |
36081602 | 107 | static void PPC_XCSR_writeb (void *opaque, |
a8170e5e | 108 | hwaddr addr, uint32_t value) |
64201201 | 109 | { |
90e189ec BS |
110 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
111 | value); | |
64201201 FB |
112 | } |
113 | ||
36081602 | 114 | static void PPC_XCSR_writew (void *opaque, |
a8170e5e | 115 | hwaddr addr, uint32_t value) |
9a64fbe4 | 116 | { |
90e189ec BS |
117 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
118 | value); | |
9a64fbe4 FB |
119 | } |
120 | ||
36081602 | 121 | static void PPC_XCSR_writel (void *opaque, |
a8170e5e | 122 | hwaddr addr, uint32_t value) |
9a64fbe4 | 123 | { |
90e189ec BS |
124 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
125 | value); | |
9a64fbe4 FB |
126 | } |
127 | ||
a8170e5e | 128 | static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) |
64201201 FB |
129 | { |
130 | uint32_t retval = 0; | |
9a64fbe4 | 131 | |
90e189ec BS |
132 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
133 | retval); | |
9a64fbe4 | 134 | |
64201201 FB |
135 | return retval; |
136 | } | |
137 | ||
a8170e5e | 138 | static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) |
9a64fbe4 | 139 | { |
64201201 FB |
140 | uint32_t retval = 0; |
141 | ||
90e189ec BS |
142 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
143 | retval); | |
64201201 FB |
144 | |
145 | return retval; | |
9a64fbe4 FB |
146 | } |
147 | ||
a8170e5e | 148 | static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) |
9a64fbe4 FB |
149 | { |
150 | uint32_t retval = 0; | |
151 | ||
90e189ec BS |
152 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
153 | retval); | |
9a64fbe4 FB |
154 | |
155 | return retval; | |
156 | } | |
157 | ||
0c90c52f AK |
158 | static const MemoryRegionOps PPC_XCSR_ops = { |
159 | .old_mmio = { | |
160 | .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, | |
161 | .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, | |
162 | }, | |
163 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9a64fbe4 FB |
164 | }; |
165 | ||
b6b8bd18 | 166 | #endif |
9a64fbe4 | 167 | |
64201201 | 168 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 169 | typedef struct sysctrl_t { |
c4781a51 | 170 | qemu_irq reset_irq; |
31688246 | 171 | Nvram *nvram; |
64201201 FB |
172 | uint8_t state; |
173 | uint8_t syscontrol; | |
da9b266b | 174 | int contiguous_map; |
9a183916 | 175 | qemu_irq contiguous_map_irq; |
fb3444b8 | 176 | int endian; |
c227f099 | 177 | } sysctrl_t; |
9a64fbe4 | 178 | |
64201201 FB |
179 | enum { |
180 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 181 | }; |
9a64fbe4 | 182 | |
c227f099 | 183 | static sysctrl_t *sysctrl; |
9a64fbe4 | 184 | |
a541f297 | 185 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 186 | { |
c227f099 | 187 | sysctrl_t *sysctrl = opaque; |
64201201 | 188 | |
659f7f65 | 189 | trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); |
9a64fbe4 FB |
190 | switch (addr) { |
191 | case 0x0092: | |
192 | /* Special port 92 */ | |
193 | /* Check soft reset asked */ | |
64201201 | 194 | if (val & 0x01) { |
c4781a51 JM |
195 | qemu_irq_raise(sysctrl->reset_irq); |
196 | } else { | |
197 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
198 | } |
199 | /* Check LE mode */ | |
64201201 | 200 | if (val & 0x02) { |
fb3444b8 FB |
201 | sysctrl->endian = 1; |
202 | } else { | |
203 | sysctrl->endian = 0; | |
9a64fbe4 FB |
204 | } |
205 | break; | |
64201201 FB |
206 | case 0x0800: |
207 | /* Motorola CPU configuration register : read-only */ | |
208 | break; | |
209 | case 0x0802: | |
210 | /* Motorola base module feature register : read-only */ | |
211 | break; | |
212 | case 0x0803: | |
213 | /* Motorola base module status register : read-only */ | |
214 | break; | |
9a64fbe4 | 215 | case 0x0808: |
64201201 FB |
216 | /* Hardfile light register */ |
217 | if (val & 1) | |
218 | sysctrl->state |= STATE_HARDFILE; | |
219 | else | |
220 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
221 | break; |
222 | case 0x0810: | |
223 | /* Password protect 1 register */ | |
31688246 HP |
224 | if (sysctrl->nvram != NULL) { |
225 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
226 | (k->toggle_lock)(sysctrl->nvram, 1); | |
227 | } | |
9a64fbe4 FB |
228 | break; |
229 | case 0x0812: | |
230 | /* Password protect 2 register */ | |
31688246 HP |
231 | if (sysctrl->nvram != NULL) { |
232 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
233 | (k->toggle_lock)(sysctrl->nvram, 2); | |
234 | } | |
9a64fbe4 FB |
235 | break; |
236 | case 0x0814: | |
64201201 | 237 | /* L2 invalidate register */ |
c68ea704 | 238 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
239 | break; |
240 | case 0x081C: | |
241 | /* system control register */ | |
64201201 | 242 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
243 | break; |
244 | case 0x0850: | |
245 | /* I/O map type register */ | |
da9b266b | 246 | sysctrl->contiguous_map = val & 0x01; |
9a183916 | 247 | qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); |
9a64fbe4 FB |
248 | break; |
249 | default: | |
aae9366a JM |
250 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
251 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
252 | break; |
253 | } | |
254 | } | |
255 | ||
a541f297 | 256 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 257 | { |
c227f099 | 258 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
259 | uint32_t retval = 0xFF; |
260 | ||
261 | switch (addr) { | |
262 | case 0x0092: | |
263 | /* Special port 92 */ | |
b6f54b31 | 264 | retval = sysctrl->endian << 1; |
64201201 FB |
265 | break; |
266 | case 0x0800: | |
267 | /* Motorola CPU configuration register */ | |
268 | retval = 0xEF; /* MPC750 */ | |
269 | break; | |
270 | case 0x0802: | |
271 | /* Motorola Base module feature register */ | |
272 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
273 | break; | |
274 | case 0x0803: | |
275 | /* Motorola base module status register */ | |
276 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
277 | break; |
278 | case 0x080C: | |
279 | /* Equipment present register: | |
280 | * no L2 cache | |
281 | * no upgrade processor | |
282 | * no cards in PCI slots | |
283 | * SCSI fuse is bad | |
284 | */ | |
64201201 FB |
285 | retval = 0x3C; |
286 | break; | |
287 | case 0x0810: | |
288 | /* Motorola base module extended feature register */ | |
289 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 290 | break; |
da9b266b FB |
291 | case 0x0814: |
292 | /* L2 invalidate: don't care */ | |
293 | break; | |
9a64fbe4 FB |
294 | case 0x0818: |
295 | /* Keylock */ | |
296 | retval = 0x00; | |
297 | break; | |
298 | case 0x081C: | |
299 | /* system control register | |
300 | * 7 - 6 / 1 - 0: L2 cache enable | |
301 | */ | |
64201201 | 302 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
303 | break; |
304 | case 0x0823: | |
305 | /* */ | |
306 | retval = 0x03; /* no L2 cache */ | |
307 | break; | |
308 | case 0x0850: | |
309 | /* I/O map type register */ | |
da9b266b | 310 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
311 | break; |
312 | default: | |
aae9366a | 313 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
314 | break; |
315 | } | |
659f7f65 | 316 | trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); |
9a64fbe4 FB |
317 | |
318 | return retval; | |
319 | } | |
320 | ||
da9b266b | 321 | |
64201201 | 322 | #define NVRAM_SIZE 0x2000 |
a541f297 | 323 | |
34b9b557 HP |
324 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
325 | Error **errp) | |
326 | { | |
327 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
328 | } | |
329 | ||
1bba0dc9 AF |
330 | static void ppc_prep_reset(void *opaque) |
331 | { | |
5c3e735f | 332 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 333 | |
5c3e735f | 334 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
335 | } |
336 | ||
fd533eb5 JK |
337 | static const MemoryRegionPortio prep_portio_list[] = { |
338 | /* System control ports */ | |
339 | { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, | |
340 | { 0x0800, 0x52, 1, | |
341 | .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, | |
342 | /* Special port to get debug messages from Open-Firmware */ | |
343 | { 0x0F00, 4, 1, .write = PPC_debug_write, }, | |
344 | PORTIO_END_OF_LIST(), | |
345 | }; | |
346 | ||
848696bf KB |
347 | static PortioList prep_port_list; |
348 | ||
31688246 HP |
349 | /*****************************************************************************/ |
350 | /* NVRAM helpers */ | |
351 | static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) | |
352 | { | |
5904bca8 | 353 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
354 | return (k->read)(nvram, addr); |
355 | } | |
356 | ||
357 | static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) | |
358 | { | |
5904bca8 | 359 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
360 | (k->write)(nvram, addr, val); |
361 | } | |
362 | ||
363 | static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) | |
364 | { | |
365 | nvram_write(nvram, addr, value); | |
366 | } | |
367 | ||
368 | static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) | |
369 | { | |
370 | return nvram_read(nvram, addr); | |
371 | } | |
372 | ||
373 | static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) | |
374 | { | |
375 | nvram_write(nvram, addr, value >> 8); | |
376 | nvram_write(nvram, addr + 1, value & 0xFF); | |
377 | } | |
378 | ||
379 | static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) | |
380 | { | |
381 | uint16_t tmp; | |
382 | ||
383 | tmp = nvram_read(nvram, addr) << 8; | |
384 | tmp |= nvram_read(nvram, addr + 1); | |
385 | ||
386 | return tmp; | |
387 | } | |
388 | ||
389 | static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) | |
390 | { | |
391 | nvram_write(nvram, addr, value >> 24); | |
392 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
393 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
394 | nvram_write(nvram, addr + 3, value & 0xFF); | |
395 | } | |
396 | ||
397 | static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, | |
398 | uint32_t max) | |
399 | { | |
400 | int i; | |
401 | ||
402 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
403 | nvram_write(nvram, addr + i, str[i]); | |
404 | } | |
405 | nvram_write(nvram, addr + i, str[i]); | |
406 | nvram_write(nvram, addr + max - 1, '\0'); | |
407 | } | |
408 | ||
409 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
410 | { | |
411 | uint16_t tmp; | |
412 | uint16_t pd, pd1, pd2; | |
413 | ||
414 | tmp = prev >> 8; | |
415 | pd = prev ^ value; | |
416 | pd1 = pd & 0x000F; | |
417 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
418 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
419 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
420 | ||
421 | return tmp; | |
422 | } | |
423 | ||
424 | static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) | |
425 | { | |
426 | uint32_t i; | |
427 | uint16_t crc = 0xFFFF; | |
428 | int odd; | |
429 | ||
430 | odd = count & 1; | |
431 | count &= ~1; | |
432 | for (i = 0; i != count; i++) { | |
433 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
434 | } | |
435 | if (odd) { | |
436 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
437 | } | |
438 | ||
439 | return crc; | |
440 | } | |
441 | ||
442 | #define CMDLINE_ADDR 0x017ff000 | |
443 | ||
444 | static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, | |
445 | const char *arch, | |
446 | uint32_t RAM_size, int boot_device, | |
447 | uint32_t kernel_image, uint32_t kernel_size, | |
448 | const char *cmdline, | |
449 | uint32_t initrd_image, uint32_t initrd_size, | |
450 | uint32_t NVRAM_image, | |
451 | int width, int height, int depth) | |
452 | { | |
453 | uint16_t crc; | |
454 | ||
455 | /* Set parameters for Open Hack'Ware BIOS */ | |
456 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
457 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
458 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
459 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
460 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
461 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
462 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
463 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
464 | if (cmdline) { | |
465 | /* XXX: put the cmdline in NVRAM too ? */ | |
466 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, | |
467 | cmdline); | |
468 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
469 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
470 | } else { | |
471 | NVRAM_set_lword(nvram, 0x40, 0); | |
472 | NVRAM_set_lword(nvram, 0x44, 0); | |
473 | } | |
474 | NVRAM_set_lword(nvram, 0x48, initrd_image); | |
475 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
476 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
477 | ||
478 | NVRAM_set_word(nvram, 0x54, width); | |
479 | NVRAM_set_word(nvram, 0x56, height); | |
480 | NVRAM_set_word(nvram, 0x58, depth); | |
481 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
482 | NVRAM_set_word(nvram, 0xFC, crc); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
26aa7d72 | 487 | /* PowerPC PREP hardware initialisation */ |
3ef96221 | 488 | static void ppc_prep_init(MachineState *machine) |
a541f297 | 489 | { |
3ef96221 | 490 | ram_addr_t ram_size = machine->ram_size; |
3ef96221 MA |
491 | const char *kernel_filename = machine->kernel_filename; |
492 | const char *kernel_cmdline = machine->kernel_cmdline; | |
493 | const char *initrd_filename = machine->initrd_filename; | |
494 | const char *boot_device = machine->boot_order; | |
0c90c52f | 495 | MemoryRegion *sysmem = get_system_memory(); |
a9bf3df0 | 496 | PowerPCCPU *cpu = NULL; |
e2684c0b | 497 | CPUPPCState *env = NULL; |
31688246 | 498 | Nvram *m48t59; |
0c90c52f AK |
499 | #if 0 |
500 | MemoryRegion *xcsr = g_new(MemoryRegion, 1); | |
501 | #endif | |
d0b25425 | 502 | int linux_boot, i, nb_nics1; |
0c90c52f | 503 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
093209cd BS |
504 | uint32_t kernel_base, initrd_base; |
505 | long kernel_size, initrd_size; | |
8ca8c7bc | 506 | DeviceState *dev; |
8ca8c7bc | 507 | PCIHostState *pcihost; |
46e50e9d | 508 | PCIBus *pci_bus; |
506b7ddf | 509 | PCIDevice *pci; |
48a18b3c | 510 | ISABus *isa_bus; |
52a71bff | 511 | ISADevice *isa; |
28c5af54 | 512 | int ppc_boot_device; |
f455e98c | 513 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
64201201 | 514 | |
7267c094 | 515 | sysctrl = g_malloc0(sizeof(sysctrl_t)); |
a541f297 FB |
516 | |
517 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 518 | |
c68ea704 | 519 | /* init CPUs */ |
19fb2c36 BR |
520 | if (machine->cpu_model == NULL) |
521 | machine->cpu_model = "602"; | |
fe33cc71 | 522 | for (i = 0; i < smp_cpus; i++) { |
19fb2c36 | 523 | cpu = cpu_ppc_init(machine->cpu_model); |
a9bf3df0 | 524 | if (cpu == NULL) { |
aaed909a FB |
525 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
526 | exit(1); | |
527 | } | |
a9bf3df0 AF |
528 | env = &cpu->env; |
529 | ||
4018bae9 JM |
530 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
531 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
532 | cpu_ppc_tb_init(env, 7812500UL); | |
533 | } else { | |
534 | /* Set time-base frequency to 100 Mhz */ | |
535 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
536 | } | |
5c3e735f | 537 | qemu_register_reset(ppc_prep_reset, cpu); |
fe33cc71 | 538 | } |
a541f297 FB |
539 | |
540 | /* allocate RAM */ | |
e938ba0c | 541 | memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); |
0c90c52f | 542 | memory_region_add_subregion(sysmem, 0, ram); |
cf9c147c | 543 | |
a541f297 | 544 | if (linux_boot) { |
64201201 | 545 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 546 | /* now we can load the kernel */ |
dcac9679 PB |
547 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
548 | ram_size - kernel_base); | |
64201201 | 549 | if (kernel_size < 0) { |
c525436e | 550 | error_report("could not load kernel '%s'", kernel_filename); |
a541f297 FB |
551 | exit(1); |
552 | } | |
553 | /* load initrd */ | |
a541f297 | 554 | if (initrd_filename) { |
64201201 | 555 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
556 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
557 | ram_size - initrd_base); | |
a541f297 | 558 | if (initrd_size < 0) { |
c525436e MA |
559 | error_report("could not load initial ram disk '%s'", |
560 | initrd_filename); | |
561 | exit(1); | |
a541f297 | 562 | } |
64201201 FB |
563 | } else { |
564 | initrd_base = 0; | |
565 | initrd_size = 0; | |
a541f297 | 566 | } |
6ac0e82d | 567 | ppc_boot_device = 'm'; |
a541f297 | 568 | } else { |
64201201 FB |
569 | kernel_base = 0; |
570 | kernel_size = 0; | |
571 | initrd_base = 0; | |
572 | initrd_size = 0; | |
28c5af54 JM |
573 | ppc_boot_device = '\0'; |
574 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
575 | for (i = 0; boot_device[i] != '\0'; i++) { |
576 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
577 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 578 | break; |
0d913fdb | 579 | } |
28c5af54 JM |
580 | } |
581 | if (ppc_boot_device == '\0') { | |
582 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
583 | exit(1); | |
584 | } | |
a541f297 FB |
585 | } |
586 | ||
dd37a5e4 | 587 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
c525436e MA |
588 | error_report("Only 6xx bus is supported on PREP machine"); |
589 | exit(1); | |
dd37a5e4 | 590 | } |
8ca8c7bc AF |
591 | |
592 | dev = qdev_create(NULL, "raven-pcihost"); | |
d0b25425 HP |
593 | if (bios_name == NULL) { |
594 | bios_name = BIOS_FILENAME; | |
595 | } | |
596 | qdev_prop_set_string(dev, "bios-name", bios_name); | |
4ecd4d16 | 597 | qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); |
8558d942 | 598 | pcihost = PCI_HOST_BRIDGE(dev); |
f05f6b4a | 599 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); |
f424d5c4 | 600 | qdev_init_nofail(dev); |
8ca8c7bc AF |
601 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
602 | if (pci_bus == NULL) { | |
603 | fprintf(stderr, "Couldn't create PCI host controller.\n"); | |
604 | exit(1); | |
605 | } | |
9a183916 | 606 | sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); |
8ca8c7bc | 607 | |
506b7ddf AF |
608 | /* PCI -> ISA bridge */ |
609 | pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); | |
182735ef | 610 | cpu = POWERPC_CPU(first_cpu); |
506b7ddf | 611 | qdev_connect_gpio_out(&pci->qdev, 0, |
182735ef | 612 | cpu->env.irq_inputs[PPC6xx_INPUT_INT]); |
506b7ddf AF |
613 | sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); |
614 | sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); | |
615 | sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); | |
616 | sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); | |
2ae0e48d | 617 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); |
506b7ddf | 618 | |
52a71bff HP |
619 | /* Super I/O (parallel + serial ports) */ |
620 | isa = isa_create(isa_bus, TYPE_PC87312); | |
4a17cc4f AF |
621 | dev = DEVICE(isa); |
622 | qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ | |
623 | qdev_init_nofail(dev); | |
52a71bff | 624 | |
a541f297 | 625 | /* init basic PC hardware */ |
78895427 | 626 | pci_vga_init(pci_bus); |
a541f297 | 627 | |
a541f297 FB |
628 | nb_nics1 = nb_nics; |
629 | if (nb_nics1 > NE2000_NB_MAX) | |
630 | nb_nics1 = NE2000_NB_MAX; | |
631 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 632 | if (nd_table[i].model == NULL) { |
7267c094 | 633 | nd_table[i].model = g_strdup("ne2k_isa"); |
5652ef78 AJ |
634 | } |
635 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
48a18b3c HP |
636 | isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], |
637 | &nd_table[i]); | |
a41b2ff2 | 638 | } else { |
29b358f9 | 639 | pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); |
a41b2ff2 | 640 | } |
a541f297 | 641 | } |
a541f297 | 642 | |
d8f94e1b | 643 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
81aa0647 | 644 | for(i = 0; i < MAX_IDE_BUS; i++) { |
48a18b3c | 645 | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
646 | hd[2 * i], |
647 | hd[2 * i + 1]); | |
a541f297 | 648 | } |
48a18b3c | 649 | isa_create_simple(isa_bus, "i8042"); |
4556bd8b | 650 | |
182735ef AF |
651 | cpu = POWERPC_CPU(first_cpu); |
652 | sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; | |
fd533eb5 | 653 | |
848696bf KB |
654 | portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); |
655 | portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); | |
fd533eb5 | 656 | |
64201201 | 657 | /* PowerPC control and status register group */ |
b6b8bd18 | 658 | #if 0 |
2c9b15ca | 659 | memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); |
0c90c52f | 660 | memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); |
b6b8bd18 | 661 | #endif |
a541f297 | 662 | |
4bcbe0b6 | 663 | if (machine_usb(machine)) { |
afb9a60e | 664 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0d92ed30 PB |
665 | } |
666 | ||
6de04973 | 667 | m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); |
3cbee15b | 668 | if (m48t59 == NULL) |
64201201 | 669 | return; |
3cbee15b | 670 | sysctrl->nvram = m48t59; |
64201201 FB |
671 | |
672 | /* Initialise NVRAM */ | |
31688246 HP |
673 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, |
674 | ppc_boot_device, | |
64201201 | 675 | kernel_base, kernel_size, |
b6b8bd18 | 676 | kernel_cmdline, |
64201201 FB |
677 | initrd_base, initrd_size, |
678 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
679 | 0, |
680 | graphic_width, graphic_height, graphic_depth); | |
a541f297 | 681 | } |
c0e564d5 | 682 | |
e264d29d | 683 | static void prep_machine_init(MachineClass *mc) |
f80f9ec9 | 684 | { |
e264d29d EH |
685 | mc->desc = "PowerPC PREP platform"; |
686 | mc->init = ppc_prep_init; | |
2059839b | 687 | mc->block_default_type = IF_IDE; |
e264d29d EH |
688 | mc->max_cpus = MAX_CPUS; |
689 | mc->default_boot_order = "cad"; | |
f80f9ec9 AL |
690 | } |
691 | ||
34b9b557 HP |
692 | static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) |
693 | { | |
694 | uint16_t checksum = *(uint16_t *)opaque; | |
695 | ISADevice *rtc; | |
696 | ||
697 | if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) { | |
698 | rtc = ISA_DEVICE(dev); | |
699 | rtc_set_memory(rtc, 0x2e, checksum & 0xff); | |
700 | rtc_set_memory(rtc, 0x3e, checksum & 0xff); | |
701 | rtc_set_memory(rtc, 0x2f, checksum >> 8); | |
702 | rtc_set_memory(rtc, 0x3f, checksum >> 8); | |
703 | } | |
704 | return 0; | |
705 | } | |
706 | ||
707 | static void ibm_40p_init(MachineState *machine) | |
708 | { | |
709 | CPUPPCState *env = NULL; | |
710 | uint16_t cmos_checksum; | |
711 | PowerPCCPU *cpu; | |
712 | DeviceState *dev; | |
713 | SysBusDevice *pcihost; | |
714 | Nvram *m48t59 = NULL; | |
715 | PCIBus *pci_bus; | |
716 | ISABus *isa_bus; | |
717 | void *fw_cfg; | |
718 | int i; | |
719 | uint32_t kernel_base = 0, initrd_base = 0; | |
720 | long kernel_size = 0, initrd_size = 0; | |
721 | char boot_device; | |
722 | ||
723 | /* init CPU */ | |
724 | if (!machine->cpu_model) { | |
725 | machine->cpu_model = "604"; | |
726 | } | |
727 | cpu = cpu_ppc_init(machine->cpu_model); | |
728 | if (!cpu) { | |
729 | error_report("could not initialize CPU '%s'", | |
730 | machine->cpu_model); | |
731 | exit(1); | |
732 | } | |
733 | env = &cpu->env; | |
734 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
735 | error_report("only 6xx bus is supported on this machine"); | |
736 | exit(1); | |
737 | } | |
738 | ||
739 | if (env->flags & POWERPC_FLAG_RTC_CLK) { | |
740 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
741 | cpu_ppc_tb_init(env, 7812500UL); | |
742 | } else { | |
743 | /* Set time-base frequency to 100 Mhz */ | |
744 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
745 | } | |
746 | qemu_register_reset(ppc_prep_reset, cpu); | |
747 | ||
748 | /* PCI host */ | |
749 | dev = qdev_create(NULL, "raven-pcihost"); | |
750 | if (!bios_name) { | |
751 | bios_name = BIOS_FILENAME; | |
752 | } | |
753 | qdev_prop_set_string(dev, "bios-name", bios_name); | |
754 | qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); | |
755 | pcihost = SYS_BUS_DEVICE(dev); | |
756 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); | |
757 | qdev_init_nofail(dev); | |
758 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); | |
759 | if (!pci_bus) { | |
760 | error_report("could not create PCI host controller"); | |
761 | exit(1); | |
762 | } | |
763 | ||
764 | /* PCI -> ISA bridge */ | |
765 | dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); | |
766 | qdev_connect_gpio_out(dev, 0, | |
767 | cpu->env.irq_inputs[PPC6xx_INPUT_INT]); | |
768 | sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15)); | |
769 | sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13)); | |
770 | sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15)); | |
771 | sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13)); | |
772 | isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); | |
773 | ||
774 | /* Memory controller */ | |
775 | dev = DEVICE(isa_create(isa_bus, "rs6000-mc")); | |
776 | qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); | |
777 | qdev_init_nofail(dev); | |
778 | ||
779 | /* initialize CMOS checksums */ | |
780 | cmos_checksum = 0x6aa9; | |
781 | qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, | |
782 | &cmos_checksum); | |
783 | ||
784 | /* initialize audio subsystem */ | |
785 | audio_init(); | |
786 | ||
787 | /* add some more devices */ | |
788 | if (defaults_enabled()) { | |
789 | isa_create_simple(isa_bus, "i8042"); | |
790 | m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); | |
791 | ||
792 | dev = DEVICE(isa_create(isa_bus, "cs4231a")); | |
793 | qdev_prop_set_uint32(dev, "iobase", 0x830); | |
794 | qdev_prop_set_uint32(dev, "irq", 10); | |
795 | qdev_init_nofail(dev); | |
796 | ||
797 | dev = DEVICE(isa_create(isa_bus, "pc87312")); | |
798 | qdev_prop_set_uint32(dev, "config", 12); | |
799 | qdev_init_nofail(dev); | |
800 | ||
801 | dev = DEVICE(isa_create(isa_bus, "prep-systemio")); | |
802 | qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); | |
803 | qdev_prop_set_uint32(dev, "equipment", 0xc0); | |
804 | qdev_init_nofail(dev); | |
805 | ||
806 | pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810"); | |
807 | ||
808 | /* XXX: s3-trio at PCI_DEVFN(2, 0) */ | |
809 | pci_vga_init(pci_bus); | |
810 | ||
811 | for (i = 0; i < nb_nics; i++) { | |
812 | pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", | |
813 | i == 0 ? "3" : NULL); | |
814 | } | |
815 | } | |
816 | ||
817 | /* Prepare firmware configuration for OpenBIOS */ | |
818 | fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); | |
819 | ||
820 | if (machine->kernel_filename) { | |
821 | /* load kernel */ | |
822 | kernel_base = KERNEL_LOAD_ADDR; | |
823 | kernel_size = load_image_targphys(machine->kernel_filename, | |
824 | kernel_base, | |
825 | machine->ram_size - kernel_base); | |
826 | if (kernel_size < 0) { | |
827 | error_report("could not load kernel '%s'", | |
828 | machine->kernel_filename); | |
829 | exit(1); | |
830 | } | |
831 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); | |
832 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
833 | /* load initrd */ | |
834 | if (machine->initrd_filename) { | |
835 | initrd_base = INITRD_LOAD_ADDR; | |
836 | initrd_size = load_image_targphys(machine->initrd_filename, | |
837 | initrd_base, | |
838 | machine->ram_size - initrd_base); | |
839 | if (initrd_size < 0) { | |
840 | error_report("could not load initial ram disk '%s'", | |
841 | machine->initrd_filename); | |
842 | exit(1); | |
843 | } | |
844 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
845 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
846 | } | |
847 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | |
848 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
849 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, | |
850 | machine->kernel_cmdline); | |
851 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
852 | machine->kernel_cmdline); | |
853 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
854 | strlen(machine->kernel_cmdline) + 1); | |
855 | } | |
856 | boot_device = 'm'; | |
857 | } else { | |
858 | boot_device = machine->boot_order[0]; | |
859 | } | |
860 | ||
861 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); | |
862 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); | |
863 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); | |
864 | ||
865 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); | |
866 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); | |
867 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); | |
868 | ||
869 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); | |
870 | if (kvm_enabled()) { | |
871 | #ifdef CONFIG_KVM | |
872 | uint8_t *hypercall; | |
873 | ||
874 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); | |
875 | hypercall = g_malloc(16); | |
876 | kvmppc_get_hypercall(env, hypercall, 16); | |
877 | fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); | |
878 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); | |
879 | #endif | |
880 | } else { | |
881 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); | |
882 | } | |
883 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); | |
884 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
885 | ||
886 | /* Prepare firmware configuration for Open Hack'Ware */ | |
887 | if (m48t59) { | |
888 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, | |
889 | boot_device, | |
890 | kernel_base, kernel_size, | |
891 | machine->kernel_cmdline, | |
892 | initrd_base, initrd_size, | |
893 | /* XXX: need an option to load a NVRAM image */ | |
894 | 0, | |
895 | graphic_width, graphic_height, graphic_depth); | |
896 | } | |
897 | } | |
898 | ||
899 | static void ibm_40p_machine_init(MachineClass *mc) | |
900 | { | |
901 | mc->desc = "IBM RS/6000 7020 (40p)", | |
902 | mc->init = ibm_40p_init; | |
903 | mc->max_cpus = 1; | |
904 | mc->pci_allow_0_address = true; | |
905 | mc->default_ram_size = 128 * M_BYTE; | |
906 | mc->block_default_type = IF_SCSI; | |
907 | mc->default_boot_order = "c"; | |
908 | } | |
909 | ||
910 | DEFINE_MACHINE("40p", ibm_40p_machine_init) | |
e264d29d | 911 | DEFINE_MACHINE("prep", prep_machine_init) |