]>
Commit | Line | Data |
---|---|---|
9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
34b9b557 | 5 | * Copyright (c) 2017 Hervé Poussineau |
5fafdf24 | 6 | * |
a541f297 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
9a64fbe4 | 24 | */ |
71e8a915 | 25 | |
0d75590d | 26 | #include "qemu/osdep.h" |
819ce6b2 | 27 | #include "hw/rtc/m48t59.h" |
0d09e41a PB |
28 | #include "hw/char/serial.h" |
29 | #include "hw/block/fdc.h" | |
1422e32d | 30 | #include "net/net.h" |
0d09e41a | 31 | #include "hw/isa/isa.h" |
75610155 AF |
32 | #include "hw/pci/pci.h" |
33 | #include "hw/pci/pci_host.h" | |
0d09e41a | 34 | #include "hw/ppc/ppc.h" |
75610155 | 35 | #include "hw/boards.h" |
3e80f690 | 36 | #include "qapi/error.h" |
c525436e | 37 | #include "qemu/error-report.h" |
1de7afc9 | 38 | #include "qemu/log.h" |
75610155 | 39 | #include "hw/loader.h" |
bcdb9064 | 40 | #include "hw/rtc/mc146818rtc.h" |
0d09e41a | 41 | #include "hw/isa/pc87312.h" |
b2ce76a0 | 42 | #include "hw/qdev-properties.h" |
34b9b557 | 43 | #include "sysemu/kvm.h" |
71e8a915 | 44 | #include "sysemu/reset.h" |
659f7f65 | 45 | #include "trace.h" |
97c42c3c | 46 | #include "elf.h" |
ab3dd749 | 47 | #include "qemu/units.h" |
9fddaa0c | 48 | |
fe33cc71 JM |
49 | /* SMP is not enabled, for now */ |
50 | #define MAX_CPUS 1 | |
51 | ||
34b9b557 HP |
52 | #define CFG_ADDR 0xf0000510 |
53 | ||
b6b8bd18 FB |
54 | #define KERNEL_LOAD_ADDR 0x01000000 |
55 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 56 | |
64201201 | 57 | #define NVRAM_SIZE 0x2000 |
a541f297 | 58 | |
34b9b557 HP |
59 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
60 | Error **errp) | |
61 | { | |
62 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
63 | } | |
64 | ||
1bba0dc9 AF |
65 | static void ppc_prep_reset(void *opaque) |
66 | { | |
5c3e735f | 67 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 68 | |
5c3e735f | 69 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
70 | } |
71 | ||
848696bf | 72 | |
31688246 HP |
73 | /*****************************************************************************/ |
74 | /* NVRAM helpers */ | |
75 | static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) | |
76 | { | |
5904bca8 | 77 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
78 | return (k->read)(nvram, addr); |
79 | } | |
80 | ||
81 | static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) | |
82 | { | |
5904bca8 | 83 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
31688246 HP |
84 | (k->write)(nvram, addr, val); |
85 | } | |
86 | ||
87 | static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) | |
88 | { | |
89 | nvram_write(nvram, addr, value); | |
90 | } | |
91 | ||
92 | static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) | |
93 | { | |
94 | return nvram_read(nvram, addr); | |
95 | } | |
96 | ||
97 | static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) | |
98 | { | |
99 | nvram_write(nvram, addr, value >> 8); | |
100 | nvram_write(nvram, addr + 1, value & 0xFF); | |
101 | } | |
102 | ||
103 | static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) | |
104 | { | |
105 | uint16_t tmp; | |
106 | ||
107 | tmp = nvram_read(nvram, addr) << 8; | |
108 | tmp |= nvram_read(nvram, addr + 1); | |
109 | ||
110 | return tmp; | |
111 | } | |
112 | ||
113 | static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) | |
114 | { | |
115 | nvram_write(nvram, addr, value >> 24); | |
116 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
117 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
118 | nvram_write(nvram, addr + 3, value & 0xFF); | |
119 | } | |
120 | ||
121 | static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, | |
122 | uint32_t max) | |
123 | { | |
124 | int i; | |
125 | ||
126 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
127 | nvram_write(nvram, addr + i, str[i]); | |
128 | } | |
129 | nvram_write(nvram, addr + i, str[i]); | |
130 | nvram_write(nvram, addr + max - 1, '\0'); | |
131 | } | |
132 | ||
133 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
134 | { | |
135 | uint16_t tmp; | |
136 | uint16_t pd, pd1, pd2; | |
137 | ||
138 | tmp = prev >> 8; | |
139 | pd = prev ^ value; | |
140 | pd1 = pd & 0x000F; | |
141 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
142 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
143 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
144 | ||
145 | return tmp; | |
146 | } | |
147 | ||
148 | static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) | |
149 | { | |
150 | uint32_t i; | |
151 | uint16_t crc = 0xFFFF; | |
152 | int odd; | |
153 | ||
154 | odd = count & 1; | |
155 | count &= ~1; | |
156 | for (i = 0; i != count; i++) { | |
157 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
158 | } | |
159 | if (odd) { | |
160 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
161 | } | |
162 | ||
163 | return crc; | |
164 | } | |
165 | ||
166 | #define CMDLINE_ADDR 0x017ff000 | |
167 | ||
168 | static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, | |
169 | const char *arch, | |
170 | uint32_t RAM_size, int boot_device, | |
171 | uint32_t kernel_image, uint32_t kernel_size, | |
172 | const char *cmdline, | |
173 | uint32_t initrd_image, uint32_t initrd_size, | |
174 | uint32_t NVRAM_image, | |
175 | int width, int height, int depth) | |
176 | { | |
177 | uint16_t crc; | |
178 | ||
179 | /* Set parameters for Open Hack'Ware BIOS */ | |
180 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
181 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
182 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
183 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
184 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
185 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
186 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
187 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
188 | if (cmdline) { | |
189 | /* XXX: put the cmdline in NVRAM too ? */ | |
190 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, | |
191 | cmdline); | |
192 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
193 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
194 | } else { | |
195 | NVRAM_set_lword(nvram, 0x40, 0); | |
196 | NVRAM_set_lword(nvram, 0x44, 0); | |
197 | } | |
198 | NVRAM_set_lword(nvram, 0x48, initrd_image); | |
199 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
200 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
201 | ||
202 | NVRAM_set_word(nvram, 0x54, width); | |
203 | NVRAM_set_word(nvram, 0x56, height); | |
204 | NVRAM_set_word(nvram, 0x58, depth); | |
205 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
206 | NVRAM_set_word(nvram, 0xFC, crc); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
34b9b557 HP |
211 | static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) |
212 | { | |
213 | uint16_t checksum = *(uint16_t *)opaque; | |
34b9b557 | 214 | |
c50be9e1 | 215 | if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { |
55c86cb8 | 216 | MC146818RtcState *rtc = MC146818_RTC(dev); |
2d4bd81e PMD |
217 | mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff); |
218 | mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff); | |
219 | mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8); | |
220 | mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8); | |
29551fdc TH |
221 | |
222 | object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc), | |
d2623129 | 223 | "date"); |
34b9b557 HP |
224 | } |
225 | return 0; | |
226 | } | |
227 | ||
228 | static void ibm_40p_init(MachineState *machine) | |
229 | { | |
cd7b9498 | 230 | const char *bios_name = machine->firmware ?: "openbios-ppc"; |
053b7086 | 231 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
34b9b557 HP |
232 | CPUPPCState *env = NULL; |
233 | uint16_t cmos_checksum; | |
234 | PowerPCCPU *cpu; | |
0358687b | 235 | DeviceState *dev, *i82378_dev; |
0f080859 | 236 | SysBusDevice *pcihost, *s; |
34b9b557 HP |
237 | Nvram *m48t59 = NULL; |
238 | PCIBus *pci_bus; | |
96927c74 | 239 | ISADevice *isa_dev; |
34b9b557 HP |
240 | ISABus *isa_bus; |
241 | void *fw_cfg; | |
242 | int i; | |
243 | uint32_t kernel_base = 0, initrd_base = 0; | |
244 | long kernel_size = 0, initrd_size = 0; | |
245 | char boot_device; | |
246 | ||
9df480db CLG |
247 | if (kvm_enabled()) { |
248 | error_report("machine %s does not support the KVM accelerator", | |
249 | MACHINE_GET_CLASS(machine)->name); | |
250 | exit(EXIT_FAILURE); | |
251 | } | |
252 | ||
34b9b557 | 253 | /* init CPU */ |
23ec69ec | 254 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); |
34b9b557 HP |
255 | env = &cpu->env; |
256 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
257 | error_report("only 6xx bus is supported on this machine"); | |
258 | exit(1); | |
259 | } | |
260 | ||
005b69fd CLG |
261 | /* Set time-base frequency to 100 Mhz */ |
262 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
34b9b557 HP |
263 | qemu_register_reset(ppc_prep_reset, cpu); |
264 | ||
265 | /* PCI host */ | |
3e80f690 | 266 | dev = qdev_new("raven-pcihost"); |
34b9b557 HP |
267 | qdev_prop_set_string(dev, "bios-name", bios_name); |
268 | qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); | |
269 | pcihost = SYS_BUS_DEVICE(dev); | |
d2623129 | 270 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); |
3c6ef471 | 271 | sysbus_realize_and_unref(pcihost, &error_fatal); |
34b9b557 HP |
272 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); |
273 | if (!pci_bus) { | |
274 | error_report("could not create PCI host controller"); | |
275 | exit(1); | |
276 | } | |
277 | ||
278 | /* PCI -> ISA bridge */ | |
2237af5e | 279 | i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378")); |
0358687b | 280 | qdev_connect_gpio_out(i82378_dev, 0, |
0f3e0c6f | 281 | qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); |
2237af5e BB |
282 | qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); |
283 | ||
0358687b MCA |
284 | sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); |
285 | isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); | |
34b9b557 HP |
286 | |
287 | /* Memory controller */ | |
96927c74 MA |
288 | isa_dev = isa_new("rs6000-mc"); |
289 | dev = DEVICE(isa_dev); | |
34b9b557 | 290 | qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); |
96927c74 | 291 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 292 | |
2e8f8518 | 293 | /* RTC */ |
96927c74 MA |
294 | isa_dev = isa_new(TYPE_MC146818_RTC); |
295 | dev = DEVICE(isa_dev); | |
1dbe3d19 | 296 | qdev_prop_set_int32(dev, "base_year", 1900); |
96927c74 | 297 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
2e8f8518 | 298 | |
34b9b557 HP |
299 | /* initialize CMOS checksums */ |
300 | cmos_checksum = 0x6aa9; | |
301 | qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, | |
302 | &cmos_checksum); | |
303 | ||
34b9b557 HP |
304 | /* add some more devices */ |
305 | if (defaults_enabled()) { | |
34b9b557 HP |
306 | m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); |
307 | ||
96927c74 MA |
308 | isa_dev = isa_new("cs4231a"); |
309 | dev = DEVICE(isa_dev); | |
34b9b557 HP |
310 | qdev_prop_set_uint32(dev, "iobase", 0x830); |
311 | qdev_prop_set_uint32(dev, "irq", 10); | |
96927c74 | 312 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 313 | |
96927c74 MA |
314 | isa_dev = isa_new("pc87312"); |
315 | dev = DEVICE(isa_dev); | |
34b9b557 | 316 | qdev_prop_set_uint32(dev, "config", 12); |
96927c74 | 317 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 318 | |
96927c74 MA |
319 | isa_dev = isa_new("prep-systemio"); |
320 | dev = DEVICE(isa_dev); | |
34b9b557 HP |
321 | qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); |
322 | qdev_prop_set_uint32(dev, "equipment", 0xc0); | |
96927c74 | 323 | isa_realize_and_unref(isa_dev, isa_bus, &error_fatal); |
34b9b557 | 324 | |
877eb21d MCA |
325 | dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0), |
326 | "lsi53c810")); | |
327 | lsi53c8xx_handle_legacy_cmdline(dev); | |
0358687b | 328 | qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13)); |
34b9b557 HP |
329 | |
330 | /* XXX: s3-trio at PCI_DEVFN(2, 0) */ | |
331 | pci_vga_init(pci_bus); | |
332 | ||
333 | for (i = 0; i < nb_nics; i++) { | |
053b7086 | 334 | pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, |
34b9b557 HP |
335 | i == 0 ? "3" : NULL); |
336 | } | |
337 | } | |
338 | ||
339 | /* Prepare firmware configuration for OpenBIOS */ | |
3e80f690 | 340 | dev = qdev_new(TYPE_FW_CFG_MEM); |
0f080859 MCA |
341 | fw_cfg = FW_CFG(dev); |
342 | qdev_prop_set_uint32(dev, "data_width", 1); | |
343 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
344 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, | |
d2623129 | 345 | OBJECT(fw_cfg)); |
0f080859 | 346 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 347 | sysbus_realize_and_unref(s, &error_fatal); |
0f080859 MCA |
348 | sysbus_mmio_map(s, 0, CFG_ADDR); |
349 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); | |
34b9b557 HP |
350 | |
351 | if (machine->kernel_filename) { | |
352 | /* load kernel */ | |
353 | kernel_base = KERNEL_LOAD_ADDR; | |
354 | kernel_size = load_image_targphys(machine->kernel_filename, | |
355 | kernel_base, | |
356 | machine->ram_size - kernel_base); | |
357 | if (kernel_size < 0) { | |
358 | error_report("could not load kernel '%s'", | |
359 | machine->kernel_filename); | |
360 | exit(1); | |
361 | } | |
362 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); | |
363 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
364 | /* load initrd */ | |
365 | if (machine->initrd_filename) { | |
366 | initrd_base = INITRD_LOAD_ADDR; | |
367 | initrd_size = load_image_targphys(machine->initrd_filename, | |
368 | initrd_base, | |
369 | machine->ram_size - initrd_base); | |
370 | if (initrd_size < 0) { | |
371 | error_report("could not load initial ram disk '%s'", | |
372 | machine->initrd_filename); | |
373 | exit(1); | |
374 | } | |
375 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); | |
376 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
377 | } | |
378 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | |
379 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
380 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, | |
381 | machine->kernel_cmdline); | |
382 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
383 | machine->kernel_cmdline); | |
384 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
385 | strlen(machine->kernel_cmdline) + 1); | |
386 | } | |
387 | boot_device = 'm'; | |
388 | } else { | |
97ec4d21 | 389 | boot_device = machine->boot_config.order[0]; |
34b9b557 HP |
390 | } |
391 | ||
fe6b6346 | 392 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
34b9b557 HP |
393 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
394 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); | |
395 | ||
396 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); | |
397 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); | |
398 | fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); | |
399 | ||
9df480db | 400 | fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); |
34b9b557 HP |
401 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); |
402 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
403 | ||
404 | /* Prepare firmware configuration for Open Hack'Ware */ | |
405 | if (m48t59) { | |
ead2b283 | 406 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size, |
34b9b557 HP |
407 | boot_device, |
408 | kernel_base, kernel_size, | |
409 | machine->kernel_cmdline, | |
410 | initrd_base, initrd_size, | |
411 | /* XXX: need an option to load a NVRAM image */ | |
412 | 0, | |
413 | graphic_width, graphic_height, graphic_depth); | |
414 | } | |
415 | } | |
416 | ||
417 | static void ibm_40p_machine_init(MachineClass *mc) | |
418 | { | |
419 | mc->desc = "IBM RS/6000 7020 (40p)", | |
420 | mc->init = ibm_40p_init; | |
421 | mc->max_cpus = 1; | |
d23b6caa | 422 | mc->default_ram_size = 128 * MiB; |
34b9b557 HP |
423 | mc->block_default_type = IF_SCSI; |
424 | mc->default_boot_order = "c"; | |
23ec69ec | 425 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); |
4cb25fbb | 426 | mc->default_display = "std"; |
053b7086 | 427 | mc->default_nic = "pcnet"; |
34b9b557 HP |
428 | } |
429 | ||
430 | DEFINE_MACHINE("40p", ibm_40p_machine_init) |