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Commit | Line | Data |
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4b387f9e BZ |
1 | /* |
2 | * QEMU aCube Sam460ex board emulation | |
3 | * | |
4 | * Copyright (c) 2012 François Revol | |
08fd9917 | 5 | * Copyright (c) 2016-2019 BALATON Zoltan |
4b387f9e BZ |
6 | * |
7 | * This file is derived from hw/ppc440_bamboo.c, | |
8 | * the copyright for that material belongs to the original owners. | |
9 | * | |
10 | * This work is licensed under the GNU GPL license version 2 or later. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "qemu/osdep.h" | |
ab3dd749 | 15 | #include "qemu/units.h" |
4b387f9e | 16 | #include "qemu-common.h" |
4b387f9e BZ |
17 | #include "qemu/error-report.h" |
18 | #include "qapi/error.h" | |
4b387f9e BZ |
19 | #include "hw/boards.h" |
20 | #include "sysemu/kvm.h" | |
21 | #include "kvm_ppc.h" | |
22 | #include "sysemu/device_tree.h" | |
23 | #include "sysemu/block-backend.h" | |
24 | #include "hw/loader.h" | |
25 | #include "elf.h" | |
26 | #include "exec/address-spaces.h" | |
27 | #include "exec/memory.h" | |
72a56a1f MT |
28 | #include "ppc440.h" |
29 | #include "ppc405.h" | |
4b387f9e BZ |
30 | #include "hw/block/flash.h" |
31 | #include "sysemu/sysemu.h" | |
32 | #include "sysemu/qtest.h" | |
71e8a915 | 33 | #include "sysemu/reset.h" |
4b387f9e BZ |
34 | #include "hw/sysbus.h" |
35 | #include "hw/char/serial.h" | |
36 | #include "hw/i2c/ppc4xx_i2c.h" | |
93198b6c | 37 | #include "hw/i2c/smbus_eeprom.h" |
4b387f9e | 38 | #include "hw/usb/hcd-ehci.h" |
ad633de6 | 39 | #include "hw/ppc/fdt.h" |
a27bd6c7 | 40 | #include "hw/qdev-properties.h" |
4b387f9e | 41 | |
43f7868d GR |
42 | #include <libfdt.h> |
43 | ||
4b387f9e BZ |
44 | #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" |
45 | #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" | |
46 | /* to extract the official U-Boot bin from the updater: */ | |
47 | /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ | |
48 | if=updater/updater-460 of=u-boot-sam460-20100605.bin */ | |
49 | ||
50 | /* from Sam460 U-Boot include/configs/Sam460ex.h */ | |
51 | #define FLASH_BASE 0xfff00000 | |
52 | #define FLASH_BASE_H 0x4 | |
ab3dd749 | 53 | #define FLASH_SIZE (1 * MiB) |
4b387f9e BZ |
54 | #define UBOOT_LOAD_BASE 0xfff80000 |
55 | #define UBOOT_SIZE 0x00080000 | |
56 | #define UBOOT_ENTRY 0xfffffffc | |
57 | ||
58 | /* from U-Boot */ | |
59 | #define EPAPR_MAGIC (0x45504150) | |
60 | #define KERNEL_ADDR 0x1000000 | |
61 | #define FDT_ADDR 0x1800000 | |
62 | #define RAMDISK_ADDR 0x1900000 | |
63 | ||
64 | /* Sam460ex IRQ MAP: | |
65 | IRQ0 = ETH_INT | |
66 | IRQ1 = FPGA_INT | |
67 | IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) | |
68 | IRQ3 = FPGA_INT2 | |
69 | IRQ11 = RTC_INT | |
70 | IRQ12 = SM502_INT | |
71 | */ | |
72 | ||
f8815532 | 73 | #define CPU_FREQ 1150000000 |
43f7868d GR |
74 | #define PLB_FREQ 230000000 |
75 | #define OPB_FREQ 115000000 | |
76 | #define EBC_FREQ 115000000 | |
77 | #define UART_FREQ 11059200 | |
4b387f9e BZ |
78 | #define SDRAM_NR_BANKS 4 |
79 | ||
6a9938a3 BZ |
80 | /* The SoC could also handle 4 GiB but firmware does not work with that. */ |
81 | /* Maybe it overflows a signed 32 bit number somewhere? */ | |
7d8ccf58 | 82 | static const ram_addr_t ppc460ex_sdram_bank_sizes[] = { |
6a9938a3 BZ |
83 | 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, |
84 | 32 * MiB, 0 | |
4b387f9e BZ |
85 | }; |
86 | ||
87 | struct boot_info { | |
88 | uint32_t dt_base; | |
89 | uint32_t dt_size; | |
90 | uint32_t entry; | |
91 | }; | |
92 | ||
4b387f9e BZ |
93 | static int sam460ex_load_uboot(void) |
94 | { | |
f30bc995 MA |
95 | /* |
96 | * This first creates 1MiB of flash memory mapped at the end of | |
97 | * the 32-bit address space (0xFFF00000..0xFFFFFFFF). | |
98 | * | |
99 | * If_PFLASH unit 0 is defined, the flash memory is initialized | |
100 | * from that block backend. | |
101 | * | |
102 | * Else, it's initialized to zero. And then 512KiB of ROM get | |
103 | * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), | |
104 | * initialized from u-boot-sam460-20100605.bin. | |
105 | * | |
106 | * This doesn't smell right. | |
107 | * | |
108 | * The physical hardware appears to have 512KiB flash memory. | |
109 | * | |
110 | * TODO Figure out what we really need here, and clean this up. | |
111 | */ | |
112 | ||
4b387f9e | 113 | DriveInfo *dinfo; |
4b387f9e BZ |
114 | |
115 | dinfo = drive_get(IF_PFLASH, 0, 0); | |
f30bc995 | 116 | if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), |
940d5b13 | 117 | "sam460ex.flash", FLASH_SIZE, |
f30bc995 | 118 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 119 | 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { |
371b74e2 | 120 | error_report("Error registering flash memory"); |
4b387f9e BZ |
121 | /* XXX: return an error instead? */ |
122 | exit(1); | |
123 | } | |
124 | ||
f30bc995 | 125 | if (!dinfo) { |
4b387f9e BZ |
126 | /*error_report("No flash image given with the 'pflash' parameter," |
127 | " using default u-boot image");*/ | |
f30bc995 MA |
128 | rom_add_file_fixed(UBOOT_FILENAME, |
129 | UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), | |
130 | -1); | |
4b387f9e BZ |
131 | } |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static int sam460ex_load_device_tree(hwaddr addr, | |
137 | uint32_t ramsize, | |
138 | hwaddr initrd_base, | |
139 | hwaddr initrd_size, | |
140 | const char *kernel_cmdline) | |
141 | { | |
4b387f9e BZ |
142 | uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; |
143 | char *filename; | |
144 | int fdt_size; | |
145 | void *fdt; | |
f8815532 BZ |
146 | uint32_t tb_freq = CPU_FREQ; |
147 | uint32_t clock_freq = CPU_FREQ; | |
43f7868d | 148 | int offset; |
4b387f9e BZ |
149 | |
150 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); | |
151 | if (!filename) { | |
51b0d834 DG |
152 | error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); |
153 | exit(1); | |
4b387f9e BZ |
154 | } |
155 | fdt = load_device_tree(filename, &fdt_size); | |
51b0d834 DG |
156 | if (!fdt) { |
157 | error_report("Couldn't load dtb file `%s'", filename); | |
3cc702d6 | 158 | g_free(filename); |
51b0d834 | 159 | exit(1); |
4b387f9e | 160 | } |
3cc702d6 | 161 | g_free(filename); |
4b387f9e BZ |
162 | |
163 | /* Manipulate device tree in memory. */ | |
164 | ||
e753f331 DG |
165 | qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, |
166 | sizeof(mem_reg_property)); | |
4b387f9e BZ |
167 | |
168 | /* default FDT doesn't have a /chosen node... */ | |
169 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
170 | ||
e753f331 | 171 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); |
4b387f9e | 172 | |
e753f331 DG |
173 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
174 | (initrd_base + initrd_size)); | |
4b387f9e | 175 | |
e753f331 | 176 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); |
4b387f9e BZ |
177 | |
178 | /* Copy data from the host device tree into the guest. Since the guest can | |
179 | * directly access the timebase without host involvement, we must expose | |
180 | * the correct frequencies. */ | |
181 | if (kvm_enabled()) { | |
182 | tb_freq = kvmppc_get_tbfreq(); | |
183 | clock_freq = kvmppc_get_clockfreq(); | |
184 | } | |
185 | ||
186 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", | |
187 | clock_freq); | |
188 | qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", | |
189 | tb_freq); | |
190 | ||
43f7868d GR |
191 | /* Remove cpm node if it exists (it is not emulated) */ |
192 | offset = fdt_path_offset(fdt, "/cpm"); | |
193 | if (offset >= 0) { | |
ad633de6 | 194 | _FDT(fdt_nop_node(fdt, offset)); |
43f7868d GR |
195 | } |
196 | ||
197 | /* set serial port clocks */ | |
198 | offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); | |
199 | while (offset >= 0) { | |
ad633de6 | 200 | _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); |
43f7868d GR |
201 | offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); |
202 | } | |
203 | ||
204 | /* some more clocks */ | |
205 | qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", | |
206 | PLB_FREQ); | |
207 | qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", | |
208 | OPB_FREQ); | |
209 | qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", | |
210 | EBC_FREQ); | |
211 | ||
4b387f9e BZ |
212 | rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
213 | g_free(fdt); | |
4b387f9e | 214 | |
51b0d834 | 215 | return fdt_size; |
4b387f9e BZ |
216 | } |
217 | ||
218 | /* Create reset TLB entries for BookE, mapping only the flash memory. */ | |
219 | static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) | |
220 | { | |
221 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; | |
222 | ||
223 | /* on reset the flash is mapped by a shadow TLB, | |
224 | * but since we don't implement them we need to use | |
225 | * the same values U-Boot will use to avoid a fault. | |
226 | */ | |
227 | tlb->attr = 0; | |
228 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
229 | tlb->size = 0x10000000; /* up to 0xffffffff */ | |
230 | tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; | |
231 | tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; | |
232 | tlb->PID = 0; | |
233 | } | |
234 | ||
235 | /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ | |
236 | static void mmubooke_create_initial_mapping(CPUPPCState *env, | |
237 | target_ulong va, | |
238 | hwaddr pa) | |
239 | { | |
240 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; | |
241 | ||
242 | tlb->attr = 0; | |
243 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
244 | tlb->size = 1 << 31; /* up to 0x80000000 */ | |
245 | tlb->EPN = va & TARGET_PAGE_MASK; | |
246 | tlb->RPN = pa & TARGET_PAGE_MASK; | |
247 | tlb->PID = 0; | |
248 | } | |
249 | ||
250 | static void main_cpu_reset(void *opaque) | |
251 | { | |
252 | PowerPCCPU *cpu = opaque; | |
253 | CPUPPCState *env = &cpu->env; | |
254 | struct boot_info *bi = env->load_info; | |
255 | ||
256 | cpu_reset(CPU(cpu)); | |
257 | ||
258 | /* either we have a kernel to boot or we jump to U-Boot */ | |
259 | if (bi->entry != UBOOT_ENTRY) { | |
ab3dd749 | 260 | env->gpr[1] = (16 * MiB) - 8; |
4b387f9e BZ |
261 | env->gpr[3] = FDT_ADDR; |
262 | env->nip = bi->entry; | |
263 | ||
264 | /* Create a mapping for the kernel. */ | |
265 | mmubooke_create_initial_mapping(env, 0, 0); | |
266 | env->gpr[6] = tswap32(EPAPR_MAGIC); | |
ab3dd749 | 267 | env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ |
4b387f9e BZ |
268 | |
269 | } else { | |
270 | env->nip = UBOOT_ENTRY; | |
271 | mmubooke_create_initial_mapping_uboot(env); | |
272 | } | |
273 | } | |
274 | ||
275 | static void sam460ex_init(MachineState *machine) | |
276 | { | |
277 | MemoryRegion *address_space_mem = get_system_memory(); | |
278 | MemoryRegion *isa = g_new(MemoryRegion, 1); | |
279 | MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS); | |
08fd9917 BZ |
280 | hwaddr ram_bases[SDRAM_NR_BANKS] = {0}; |
281 | hwaddr ram_sizes[SDRAM_NR_BANKS] = {0}; | |
4b387f9e BZ |
282 | MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); |
283 | qemu_irq *irqs, *uic[4]; | |
284 | PCIBus *pci_bus; | |
285 | PowerPCCPU *cpu; | |
286 | CPUPPCState *env; | |
08fd9917 | 287 | I2CBus *i2c; |
4b387f9e | 288 | hwaddr entry = UBOOT_ENTRY; |
f831f955 | 289 | hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; |
4b387f9e BZ |
290 | target_long initrd_size = 0; |
291 | DeviceState *dev; | |
292 | SysBusDevice *sbdev; | |
4b387f9e | 293 | struct boot_info *boot_info; |
08fd9917 | 294 | uint8_t *spd_data; |
08fd9917 | 295 | int success; |
4b387f9e BZ |
296 | |
297 | cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); | |
298 | env = &cpu->env; | |
299 | if (env->mmu_model != POWERPC_MMU_BOOKE) { | |
300 | error_report("Only MMU model BookE is supported by this machine."); | |
301 | exit(1); | |
302 | } | |
303 | ||
4b387f9e BZ |
304 | qemu_register_reset(main_cpu_reset, cpu); |
305 | boot_info = g_malloc0(sizeof(*boot_info)); | |
306 | env->load_info = boot_info; | |
307 | ||
f8815532 | 308 | ppc_booke_timers_init(cpu, CPU_FREQ, 0); |
4b387f9e BZ |
309 | ppc_dcr_init(env, NULL, NULL); |
310 | ||
311 | /* PLB arbitrer */ | |
312 | ppc4xx_plb_init(env); | |
313 | ||
314 | /* interrupt controllers */ | |
0989e6d1 | 315 | irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); |
4b387f9e BZ |
316 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
317 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; | |
318 | uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1); | |
319 | uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1); | |
320 | uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1); | |
321 | uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1); | |
322 | ||
323 | /* SDRAM controller */ | |
4b387f9e BZ |
324 | /* put all RAM on first bank because board has one slot |
325 | * and firmware only checks that */ | |
b28f0188 | 326 | ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, |
a0258e4a | 327 | ppc460ex_sdram_bank_sizes); |
4b387f9e BZ |
328 | |
329 | /* FIXME: does 460EX have ECC interrupts? */ | |
330 | ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, | |
331 | ram_bases, ram_sizes, 1); | |
332 | ||
08fd9917 | 333 | /* IIC controllers and devices */ |
4b387f9e | 334 | dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]); |
08fd9917 BZ |
335 | i2c = PPC4xx_I2C(dev)->bus; |
336 | /* SPD EEPROM on RAM module */ | |
fc0cfc1d | 337 | spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, |
f26740c6 MA |
338 | ram_sizes[0]); |
339 | spd_data[20] = 4; /* SO-DIMM module */ | |
340 | smbus_eeprom_init_one(i2c, 0x50, spd_data); | |
08fd9917 BZ |
341 | /* RTC */ |
342 | i2c_create_slave(i2c, "m41t80", 0x68); | |
4b387f9e BZ |
343 | |
344 | dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); | |
4b387f9e BZ |
345 | |
346 | /* External bus controller */ | |
347 | ppc405_ebc_init(env); | |
348 | ||
349 | /* CPR */ | |
350 | ppc4xx_cpr_init(env); | |
351 | ||
352 | /* PLB to AHB bridge */ | |
353 | ppc4xx_ahb_init(env); | |
354 | ||
355 | /* System DCRs */ | |
356 | ppc4xx_sdr_init(env); | |
357 | ||
358 | /* MAL */ | |
359 | ppc4xx_mal_init(env, 4, 16, &uic[2][3]); | |
360 | ||
3c409c19 BZ |
361 | /* DMA */ |
362 | ppc4xx_dma_init(env, 0x200); | |
363 | ||
4b387f9e BZ |
364 | /* 256K of L2 cache as memory */ |
365 | ppc4xx_l2sram_init(env); | |
366 | /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ | |
ab3dd749 | 367 | memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, |
4b387f9e BZ |
368 | &error_abort); |
369 | memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); | |
370 | ||
371 | /* USB */ | |
372 | sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); | |
3e80f690 | 373 | dev = qdev_new("sysbus-ohci"); |
4b387f9e BZ |
374 | qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); |
375 | qdev_prop_set_uint32(dev, "num-ports", 6); | |
3e80f690 | 376 | qdev_realize_and_unref(dev, NULL, &error_fatal); |
4b387f9e BZ |
377 | sbdev = SYS_BUS_DEVICE(dev); |
378 | sysbus_mmio_map(sbdev, 0, 0x4bffd0000); | |
379 | sysbus_connect_irq(sbdev, 0, uic[2][30]); | |
380 | usb_create_simple(usb_bus_find(-1), "usb-kbd"); | |
381 | usb_create_simple(usb_bus_find(-1), "usb-mouse"); | |
382 | ||
383 | /* PCI bus */ | |
384 | ppc460ex_pcie_init(env); | |
6484ab3d BZ |
385 | /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ |
386 | dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]); | |
4b387f9e BZ |
387 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
388 | if (!pci_bus) { | |
389 | error_report("couldn't create PCI controller!"); | |
390 | exit(1); | |
391 | } | |
392 | memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), | |
393 | 0, 0x10000); | |
394 | memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); | |
395 | ||
396 | /* PCI devices */ | |
397 | pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); | |
398 | /* SoC has a single SATA port but we don't emulate that yet | |
399 | * However, firmware and usual clients have driver for SiI311x | |
400 | * so add one for convenience by default */ | |
401 | if (defaults_enabled()) { | |
402 | pci_create_simple(pci_bus, -1, "sii3112"); | |
403 | } | |
404 | ||
405 | /* SoC has 4 UARTs | |
406 | * but board has only one wired and two are present in fdt */ | |
9bca0edb | 407 | if (serial_hd(0) != NULL) { |
4b387f9e | 408 | serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], |
9bca0edb | 409 | PPC_SERIAL_MM_BAUDBASE, serial_hd(0), |
4b387f9e BZ |
410 | DEVICE_BIG_ENDIAN); |
411 | } | |
9bca0edb | 412 | if (serial_hd(1) != NULL) { |
4b387f9e | 413 | serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], |
9bca0edb | 414 | PPC_SERIAL_MM_BAUDBASE, serial_hd(1), |
4b387f9e BZ |
415 | DEVICE_BIG_ENDIAN); |
416 | } | |
417 | ||
418 | /* Load U-Boot image. */ | |
419 | if (!machine->kernel_filename) { | |
420 | success = sam460ex_load_uboot(); | |
421 | if (success < 0) { | |
371b74e2 | 422 | error_report("could not load firmware"); |
4b387f9e BZ |
423 | exit(1); |
424 | } | |
425 | } | |
426 | ||
427 | /* Load kernel. */ | |
428 | if (machine->kernel_filename) { | |
429 | success = load_uimage(machine->kernel_filename, &entry, &loadaddr, | |
430 | NULL, NULL, NULL); | |
431 | if (success < 0) { | |
432 | uint64_t elf_entry, elf_lowaddr; | |
433 | ||
4366e1db LM |
434 | success = load_elf(machine->kernel_filename, NULL, |
435 | NULL, NULL, &elf_entry, | |
6cdda0ff AM |
436 | &elf_lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE, 0, |
437 | 0); | |
4b387f9e BZ |
438 | entry = elf_entry; |
439 | loadaddr = elf_lowaddr; | |
440 | } | |
441 | /* XXX try again as binary */ | |
442 | if (success < 0) { | |
371b74e2 | 443 | error_report("could not load kernel '%s'", |
4b387f9e BZ |
444 | machine->kernel_filename); |
445 | exit(1); | |
446 | } | |
447 | } | |
448 | ||
449 | /* Load initrd. */ | |
450 | if (machine->initrd_filename) { | |
451 | initrd_size = load_image_targphys(machine->initrd_filename, | |
452 | RAMDISK_ADDR, | |
453 | machine->ram_size - RAMDISK_ADDR); | |
454 | if (initrd_size < 0) { | |
371b74e2 | 455 | error_report("could not load ram disk '%s' at %x", |
4b387f9e BZ |
456 | machine->initrd_filename, RAMDISK_ADDR); |
457 | exit(1); | |
458 | } | |
459 | } | |
460 | ||
461 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
462 | if (machine->kernel_filename) { | |
463 | int dt_size; | |
464 | ||
465 | dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size, | |
466 | RAMDISK_ADDR, initrd_size, | |
467 | machine->kernel_cmdline); | |
4b387f9e BZ |
468 | |
469 | boot_info->dt_base = FDT_ADDR; | |
470 | boot_info->dt_size = dt_size; | |
471 | } | |
472 | ||
473 | boot_info->entry = entry; | |
474 | } | |
475 | ||
476 | static void sam460ex_machine_init(MachineClass *mc) | |
477 | { | |
478 | mc->desc = "aCube Sam460ex"; | |
479 | mc->init = sam460ex_init; | |
480 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); | |
d23b6caa | 481 | mc->default_ram_size = 512 * MiB; |
b28f0188 | 482 | mc->default_ram_id = "ppc4xx.sdram"; |
4b387f9e BZ |
483 | } |
484 | ||
485 | DEFINE_MACHINE("sam460ex", sam460ex_machine_init) |