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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
fa98fbfc | 29 | #include "qapi/visitor.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
e35704ba | 31 | #include "sysemu/numa.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
03dd024f | 33 | #include "qemu/log.h" |
71461b0f | 34 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 35 | #include "elf.h" |
1422e32d | 36 | #include "net/net.h" |
ad440b4a | 37 | #include "sysemu/device_tree.h" |
fa1d36df | 38 | #include "sysemu/block-backend.h" |
9c17d615 | 39 | #include "sysemu/cpus.h" |
b3946626 | 40 | #include "sysemu/hw_accel.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
c4b63b7c | 42 | #include "migration/misc.h" |
84a899de | 43 | #include "migration/global_state.h" |
f2a8f0a6 | 44 | #include "migration/register.h" |
4be21d56 | 45 | #include "mmu-hash64.h" |
b4db5413 | 46 | #include "mmu-book3s-v3.h" |
7abd43ba | 47 | #include "cpu-models.h" |
3794d548 | 48 | #include "qom/cpu.h" |
9fdf0c29 DG |
49 | |
50 | #include "hw/boards.h" | |
0d09e41a | 51 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
52 | #include "hw/loader.h" |
53 | ||
7804c353 | 54 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
55 | #include "hw/ppc/spapr.h" |
56 | #include "hw/ppc/spapr_vio.h" | |
57 | #include "hw/pci-host/spapr.h" | |
58 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 59 | #include "hw/pci/msi.h" |
9fdf0c29 | 60 | |
83c9f4ca | 61 | #include "hw/pci/pci.h" |
71461b0f AK |
62 | #include "hw/scsi/scsi.h" |
63 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 64 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 65 | |
022c62cb | 66 | #include "exec/address-spaces.h" |
35139a59 | 67 | #include "hw/usb.h" |
1de7afc9 | 68 | #include "qemu/config-file.h" |
135a129a | 69 | #include "qemu/error-report.h" |
2a6593cb | 70 | #include "trace.h" |
34316482 | 71 | #include "hw/nmi.h" |
6449da45 | 72 | #include "hw/intc/intc.h" |
890c2b77 | 73 | |
68a27b20 | 74 | #include "hw/compat.h" |
f348b6d1 | 75 | #include "qemu/cutils.h" |
94a94e4c | 76 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 77 | #include "qmp-commands.h" |
68a27b20 | 78 | |
9fdf0c29 DG |
79 | #include <libfdt.h> |
80 | ||
4d8d5467 BH |
81 | /* SLOF memory layout: |
82 | * | |
83 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
84 | * device-tree, then position SLOF itself 31M below that | |
85 | * | |
86 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
87 | * and more | |
88 | * | |
89 | * We load our kernel at 4M, leaving space for SLOF initial image | |
90 | */ | |
38b02bd8 | 91 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 92 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 93 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
94 | #define FW_MAX_SIZE 0x400000 |
95 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
96 | #define FW_OVERHEAD 0x2800000 |
97 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 98 | |
4d8d5467 | 99 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 100 | |
0c103f8e DG |
101 | #define PHANDLE_XICP 0x00001111 |
102 | ||
71cd4dac CLG |
103 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
104 | const char *type_ics, | |
105 | int nr_irqs, Error **errp) | |
c04d6cfa | 106 | { |
175d2aa0 | 107 | Error *local_err = NULL; |
71cd4dac | 108 | Object *obj; |
4e4169f7 | 109 | |
71cd4dac | 110 | obj = object_new(type_ics); |
175d2aa0 | 111 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
ad265631 GK |
112 | object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
113 | &error_abort); | |
175d2aa0 GK |
114 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
115 | if (local_err) { | |
116 | goto error; | |
117 | } | |
71cd4dac | 118 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
119 | if (local_err) { |
120 | goto error; | |
4e4169f7 | 121 | } |
4e4169f7 | 122 | |
71cd4dac | 123 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
124 | |
125 | error: | |
126 | error_propagate(errp, local_err); | |
127 | return NULL; | |
c04d6cfa AL |
128 | } |
129 | ||
46f7afa3 GK |
130 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
131 | { | |
132 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
133 | * and newer QEMUs don't even have them. In both cases, we don't want | |
134 | * to send anything on the wire. | |
135 | */ | |
136 | return false; | |
137 | } | |
138 | ||
139 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
140 | .name = "icp/server", | |
141 | .version_id = 1, | |
142 | .minimum_version_id = 1, | |
143 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
144 | .fields = (VMStateField[]) { | |
145 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
146 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
147 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
148 | VMSTATE_END_OF_LIST() | |
149 | }, | |
150 | }; | |
151 | ||
152 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
153 | { | |
154 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
155 | (void *)(uintptr_t) i); | |
156 | } | |
157 | ||
158 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
159 | { | |
160 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
161 | (void *)(uintptr_t) i); | |
162 | } | |
163 | ||
164 | static inline int xics_max_server_number(void) | |
165 | { | |
166 | return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); | |
167 | } | |
168 | ||
71cd4dac | 169 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 170 | { |
71cd4dac | 171 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
46f7afa3 | 172 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
c04d6cfa | 173 | |
11ad93f6 | 174 | if (kvm_enabled()) { |
2192a930 | 175 | if (machine_kernel_irqchip_allowed(machine) && |
71cd4dac CLG |
176 | !xics_kvm_init(spapr, errp)) { |
177 | spapr->icp_type = TYPE_KVM_ICP; | |
3d85885a | 178 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); |
11ad93f6 | 179 | } |
71cd4dac | 180 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
3d85885a GK |
181 | error_prepend(errp, "kernel_irqchip requested but unavailable: "); |
182 | return; | |
11ad93f6 DG |
183 | } |
184 | } | |
185 | ||
71cd4dac | 186 | if (!spapr->ics) { |
f63ebfe0 | 187 | xics_spapr_init(spapr); |
71cd4dac CLG |
188 | spapr->icp_type = TYPE_ICP; |
189 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); | |
3d85885a GK |
190 | if (!spapr->ics) { |
191 | return; | |
192 | } | |
c04d6cfa | 193 | } |
46f7afa3 GK |
194 | |
195 | if (smc->pre_2_10_has_unused_icps) { | |
196 | int i; | |
197 | ||
198 | for (i = 0; i < xics_max_server_number(); i++) { | |
199 | /* Dummy entries get deregistered when real ICPState objects | |
200 | * are registered during CPU core hotplug. | |
201 | */ | |
202 | pre_2_10_vmstate_register_dummy_icp(i); | |
203 | } | |
204 | } | |
c04d6cfa AL |
205 | } |
206 | ||
833d4668 AK |
207 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
208 | int smt_threads) | |
209 | { | |
210 | int i, ret = 0; | |
211 | uint32_t servers_prop[smt_threads]; | |
212 | uint32_t gservers_prop[smt_threads * 2]; | |
2e886fb3 | 213 | int index = spapr_vcpu_id(cpu); |
833d4668 | 214 | |
d6e166c0 DG |
215 | if (cpu->compat_pvr) { |
216 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
217 | if (ret < 0) { |
218 | return ret; | |
219 | } | |
220 | } | |
221 | ||
833d4668 AK |
222 | /* Build interrupt servers and gservers properties */ |
223 | for (i = 0; i < smt_threads; i++) { | |
224 | servers_prop[i] = cpu_to_be32(index + i); | |
225 | /* Hack, direct the group queues back to cpu 0 */ | |
226 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
227 | gservers_prop[i*2 + 1] = 0; | |
228 | } | |
229 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
230 | servers_prop, sizeof(servers_prop)); | |
231 | if (ret < 0) { | |
232 | return ret; | |
233 | } | |
234 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
235 | gservers_prop, sizeof(gservers_prop)); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
99861ecb | 240 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 241 | { |
2e886fb3 | 242 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
243 | uint32_t associativity[] = {cpu_to_be32(0x5), |
244 | cpu_to_be32(0x0), | |
245 | cpu_to_be32(0x0), | |
246 | cpu_to_be32(0x0), | |
15f8b142 | 247 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
248 | cpu_to_be32(index)}; |
249 | ||
250 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 251 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 252 | sizeof(associativity)); |
0da6f3fe BR |
253 | } |
254 | ||
86d5771a | 255 | /* Populate the "ibm,pa-features" property */ |
ee76a09f DG |
256 | static void spapr_populate_pa_features(sPAPRMachineState *spapr, |
257 | PowerPCCPU *cpu, | |
258 | void *fdt, int offset, | |
7abd43ba | 259 | bool legacy_guest) |
86d5771a | 260 | { |
7abd43ba | 261 | CPUPPCState *env = &cpu->env; |
86d5771a SB |
262 | uint8_t pa_features_206[] = { 6, 0, |
263 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
264 | uint8_t pa_features_207[] = { 24, 0, | |
265 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
266 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
267 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
268 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
269 | uint8_t pa_features_300[] = { 66, 0, |
270 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
271 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
272 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
273 | /* 6: DS207 */ | |
274 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
275 | /* 16: Vector */ | |
86d5771a | 276 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 277 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 278 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
279 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
280 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
281 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
282 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
283 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
284 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
285 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
286 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
287 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
288 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
289 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
290 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
291 | /* 60: NM atomic, 62: RNG */ | |
292 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
293 | }; | |
7abd43ba | 294 | uint8_t *pa_features = NULL; |
86d5771a SB |
295 | size_t pa_size; |
296 | ||
7abd43ba | 297 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
298 | pa_features = pa_features_206; |
299 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
300 | } |
301 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
302 | pa_features = pa_features_207; |
303 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
304 | } |
305 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
306 | pa_features = pa_features_300; |
307 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
308 | } |
309 | if (!pa_features) { | |
86d5771a SB |
310 | return; |
311 | } | |
312 | ||
313 | if (env->ci_large_pages) { | |
314 | /* | |
315 | * Note: we keep CI large pages off by default because a 64K capable | |
316 | * guest provisioned with large pages might otherwise try to map a qemu | |
317 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
318 | * even if that qemu runs on a 4k host. | |
319 | * We dd this bit back here if we are confident this is not an issue | |
320 | */ | |
321 | pa_features[3] |= 0x20; | |
322 | } | |
4e5fe368 | 323 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
86d5771a SB |
324 | pa_features[24] |= 0x80; /* Transactional memory support */ |
325 | } | |
e957f6a9 SB |
326 | if (legacy_guest && pa_size > 40) { |
327 | /* Workaround for broken kernels that attempt (guest) radix | |
328 | * mode when they can't handle it, if they see the radix bit set | |
329 | * in pa-features. So hide it from them. */ | |
330 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
331 | } | |
86d5771a SB |
332 | |
333 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
334 | } | |
335 | ||
28e02042 | 336 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 337 | { |
82677ed2 AK |
338 | int ret = 0, offset, cpus_offset; |
339 | CPUState *cs; | |
6e806cc3 BR |
340 | char cpu_model[32]; |
341 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 342 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 343 | |
82677ed2 AK |
344 | CPU_FOREACH(cs) { |
345 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
346 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2e886fb3 | 347 | int index = spapr_vcpu_id(cpu); |
12dbeb16 | 348 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
6e806cc3 | 349 | |
0f20ba62 | 350 | if ((index % smt) != 0) { |
6e806cc3 BR |
351 | continue; |
352 | } | |
353 | ||
82677ed2 | 354 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 355 | |
82677ed2 AK |
356 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
357 | if (cpus_offset < 0) { | |
a4f3885c | 358 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
82677ed2 AK |
359 | if (cpus_offset < 0) { |
360 | return cpus_offset; | |
361 | } | |
362 | } | |
363 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 364 | if (offset < 0) { |
82677ed2 AK |
365 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
366 | if (offset < 0) { | |
367 | return offset; | |
368 | } | |
6e806cc3 BR |
369 | } |
370 | ||
7f763a5d DG |
371 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
372 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
373 | if (ret < 0) { |
374 | return ret; | |
375 | } | |
833d4668 | 376 | |
99861ecb IM |
377 | if (nb_numa_nodes > 1) { |
378 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
379 | if (ret < 0) { | |
380 | return ret; | |
381 | } | |
0da6f3fe BR |
382 | } |
383 | ||
12dbeb16 | 384 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
385 | if (ret < 0) { |
386 | return ret; | |
387 | } | |
e957f6a9 | 388 | |
ee76a09f DG |
389 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
390 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
391 | } |
392 | return ret; | |
393 | } | |
394 | ||
c86c1aff | 395 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a AK |
396 | { |
397 | if (nb_numa_nodes) { | |
398 | int i; | |
399 | for (i = 0; i < nb_numa_nodes; ++i) { | |
400 | if (numa_info[i].node_mem) { | |
fb164994 DG |
401 | return MIN(pow2floor(numa_info[i].node_mem), |
402 | machine->ram_size); | |
b082d65a AK |
403 | } |
404 | } | |
405 | } | |
fb164994 | 406 | return machine->ram_size; |
b082d65a AK |
407 | } |
408 | ||
a1d59c0f AK |
409 | static void add_str(GString *s, const gchar *s1) |
410 | { | |
411 | g_string_append_len(s, s1, strlen(s1) + 1); | |
412 | } | |
7f763a5d | 413 | |
03d196b7 | 414 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
415 | hwaddr size) |
416 | { | |
417 | uint32_t associativity[] = { | |
418 | cpu_to_be32(0x4), /* length */ | |
419 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 420 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
421 | }; |
422 | char mem_name[32]; | |
423 | uint64_t mem_reg_property[2]; | |
424 | int off; | |
425 | ||
426 | mem_reg_property[0] = cpu_to_be64(start); | |
427 | mem_reg_property[1] = cpu_to_be64(size); | |
428 | ||
429 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
430 | off = fdt_add_subnode(fdt, 0, mem_name); | |
431 | _FDT(off); | |
432 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
433 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
434 | sizeof(mem_reg_property)))); | |
435 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
436 | sizeof(associativity)))); | |
03d196b7 | 437 | return off; |
26a8c353 AK |
438 | } |
439 | ||
28e02042 | 440 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 441 | { |
fb164994 | 442 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
443 | hwaddr mem_start, node_size; |
444 | int i, nb_nodes = nb_numa_nodes; | |
445 | NodeInfo *nodes = numa_info; | |
446 | NodeInfo ramnode; | |
447 | ||
448 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
449 | if (!nb_numa_nodes) { | |
450 | nb_nodes = 1; | |
fb164994 | 451 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 452 | nodes = &ramnode; |
5fe269b1 | 453 | } |
7f763a5d | 454 | |
7db8a127 AK |
455 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
456 | if (!nodes[i].node_mem) { | |
457 | continue; | |
458 | } | |
fb164994 | 459 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
460 | node_size = 0; |
461 | } else { | |
7db8a127 | 462 | node_size = nodes[i].node_mem; |
fb164994 DG |
463 | if (node_size > machine->ram_size - mem_start) { |
464 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
465 | } |
466 | } | |
7db8a127 AK |
467 | if (!mem_start) { |
468 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 469 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
470 | mem_start += spapr->rma_size; |
471 | node_size -= spapr->rma_size; | |
472 | } | |
6010818c AK |
473 | for ( ; node_size; ) { |
474 | hwaddr sizetmp = pow2floor(node_size); | |
475 | ||
476 | /* mem_start != 0 here */ | |
477 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
478 | sizetmp = 1ULL << ctzl(mem_start); | |
479 | } | |
480 | ||
481 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
482 | node_size -= sizetmp; | |
483 | mem_start += sizetmp; | |
484 | } | |
7f763a5d DG |
485 | } |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
0da6f3fe BR |
490 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
491 | sPAPRMachineState *spapr) | |
492 | { | |
493 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
494 | CPUPPCState *env = &cpu->env; | |
495 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
2e886fb3 | 496 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
497 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
498 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
499 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
500 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
501 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
502 | uint32_t page_sizes_prop[64]; | |
503 | size_t page_sizes_prop_size; | |
22419c2a | 504 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 505 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
12dbeb16 | 506 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
af81cf32 | 507 | sPAPRDRConnector *drc; |
af81cf32 | 508 | int drc_index; |
c64abd1f SB |
509 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
510 | int i; | |
af81cf32 | 511 | |
fbf55397 | 512 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 513 | if (drc) { |
0b55aa91 | 514 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
515 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
516 | } | |
0da6f3fe BR |
517 | |
518 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
519 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
520 | ||
521 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
522 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
523 | env->dcache_line_size))); | |
524 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
525 | env->dcache_line_size))); | |
526 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
527 | env->icache_line_size))); | |
528 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
529 | env->icache_line_size))); | |
530 | ||
531 | if (pcc->l1_dcache_size) { | |
532 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
533 | pcc->l1_dcache_size))); | |
534 | } else { | |
3dc6f869 | 535 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
536 | } |
537 | if (pcc->l1_icache_size) { | |
538 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
539 | pcc->l1_icache_size))); | |
540 | } else { | |
3dc6f869 | 541 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
542 | } |
543 | ||
544 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
545 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 546 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
547 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
548 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
549 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
550 | ||
551 | if (env->spr_cb[SPR_PURR].oea_read) { | |
552 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
553 | } | |
554 | ||
555 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
556 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
557 | segs, sizeof(segs)))); | |
558 | } | |
559 | ||
29386642 | 560 | /* Advertise VSX (vector extensions) if available |
0da6f3fe | 561 | * 1 == VMX / Altivec available |
29386642 DG |
562 | * 2 == VSX available |
563 | * | |
564 | * Only CPUs for which we create core types in spapr_cpu_core.c | |
565 | * are possible, and all of those have VMX */ | |
4e5fe368 | 566 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { |
29386642 DG |
567 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); |
568 | } else { | |
569 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); | |
0da6f3fe BR |
570 | } |
571 | ||
572 | /* Advertise DFP (Decimal Floating Point) if available | |
573 | * 0 / no property == no DFP | |
574 | * 1 == DFP available */ | |
4e5fe368 | 575 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { |
0da6f3fe BR |
576 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); |
577 | } | |
578 | ||
3654fa95 | 579 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
580 | sizeof(page_sizes_prop)); |
581 | if (page_sizes_prop_size) { | |
582 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
583 | page_sizes_prop, page_sizes_prop_size))); | |
584 | } | |
585 | ||
ee76a09f | 586 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
90da0d5a | 587 | |
0da6f3fe | 588 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 589 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
590 | |
591 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
592 | pft_size_prop, sizeof(pft_size_prop)))); | |
593 | ||
99861ecb IM |
594 | if (nb_numa_nodes > 1) { |
595 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
596 | } | |
0da6f3fe | 597 | |
12dbeb16 | 598 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
599 | |
600 | if (pcc->radix_page_info) { | |
601 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
602 | radix_AP_encodings[i] = | |
603 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
604 | } | |
605 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
606 | radix_AP_encodings, | |
607 | pcc->radix_page_info->count * | |
608 | sizeof(radix_AP_encodings[0])))); | |
609 | } | |
0da6f3fe BR |
610 | } |
611 | ||
612 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
613 | { | |
614 | CPUState *cs; | |
615 | int cpus_offset; | |
616 | char *nodename; | |
617 | int smt = kvmppc_smt_threads(); | |
618 | ||
619 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
620 | _FDT(cpus_offset); | |
621 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
622 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
623 | ||
624 | /* | |
625 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
626 | * created by fdt_add_subnode() end up in the right order in FDT | |
627 | * for the guest kernel the enumerate the CPUs correctly. | |
628 | */ | |
629 | CPU_FOREACH_REVERSE(cs) { | |
630 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2e886fb3 | 631 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
632 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
633 | int offset; | |
634 | ||
635 | if ((index % smt) != 0) { | |
636 | continue; | |
637 | } | |
638 | ||
639 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
640 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
641 | g_free(nodename); | |
642 | _FDT(offset); | |
643 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
644 | } | |
645 | ||
646 | } | |
647 | ||
f47bd1c8 IM |
648 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
649 | { | |
650 | MemoryDeviceInfoList *info; | |
651 | ||
652 | for (info = list; info; info = info->next) { | |
653 | MemoryDeviceInfo *value = info->value; | |
654 | ||
655 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
656 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
657 | ||
658 | if (pcdimm_info->addr >= addr && | |
659 | addr < (pcdimm_info->addr + pcdimm_info->size)) { | |
660 | return pcdimm_info->node; | |
661 | } | |
662 | } | |
663 | } | |
664 | ||
665 | return -1; | |
666 | } | |
667 | ||
03d196b7 BR |
668 | /* |
669 | * Adds ibm,dynamic-reconfiguration-memory node. | |
670 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
671 | * of this device tree node. | |
672 | */ | |
673 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
674 | { | |
675 | MachineState *machine = MACHINE(spapr); | |
676 | int ret, i, offset; | |
677 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
678 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
679 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
680 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
681 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
682 | lmb_size; | |
03d196b7 | 683 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 684 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
f47bd1c8 | 685 | MemoryDeviceInfoList *dimms = NULL; |
03d196b7 | 686 | |
16c25aef | 687 | /* |
d0e5a8f2 | 688 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 689 | */ |
d0e5a8f2 | 690 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
691 | return 0; |
692 | } | |
693 | ||
ef001f06 TH |
694 | /* |
695 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
696 | * or ibm,associativity-lookup-arrays | |
697 | */ | |
698 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
699 | * sizeof(uint32_t); | |
03d196b7 BR |
700 | cur_index = int_buf = g_malloc0(buf_len); |
701 | ||
702 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
703 | ||
704 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
705 | sizeof(prop_lmb_size)); | |
706 | if (ret < 0) { | |
707 | goto out; | |
708 | } | |
709 | ||
710 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
711 | if (ret < 0) { | |
712 | goto out; | |
713 | } | |
714 | ||
715 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
716 | if (ret < 0) { | |
717 | goto out; | |
718 | } | |
719 | ||
f47bd1c8 IM |
720 | if (hotplug_lmb_start) { |
721 | MemoryDeviceInfoList **prev = &dimms; | |
722 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
723 | } | |
724 | ||
03d196b7 BR |
725 | /* ibm,dynamic-memory */ |
726 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
727 | cur_index++; | |
728 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 729 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
730 | uint32_t *dynamic_memory = cur_index; |
731 | ||
d0e5a8f2 BR |
732 | if (i >= hotplug_lmb_start) { |
733 | sPAPRDRConnector *drc; | |
d0e5a8f2 | 734 | |
fbf55397 | 735 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 736 | g_assert(drc); |
d0e5a8f2 BR |
737 | |
738 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
739 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 740 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 741 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 742 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
743 | if (memory_region_present(get_system_memory(), addr)) { |
744 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
745 | } else { | |
746 | dynamic_memory[5] = cpu_to_be32(0); | |
747 | } | |
03d196b7 | 748 | } else { |
d0e5a8f2 BR |
749 | /* |
750 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
751 | * hotplug memory region -- all these are marked as reserved | |
752 | * and as having no valid DRC. | |
753 | */ | |
754 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
755 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
756 | dynamic_memory[2] = cpu_to_be32(0); | |
757 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
758 | dynamic_memory[4] = cpu_to_be32(-1); | |
759 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
760 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
761 | } |
762 | ||
763 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
764 | } | |
f47bd1c8 | 765 | qapi_free_MemoryDeviceInfoList(dimms); |
03d196b7 BR |
766 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); |
767 | if (ret < 0) { | |
768 | goto out; | |
769 | } | |
770 | ||
771 | /* ibm,associativity-lookup-arrays */ | |
772 | cur_index = int_buf; | |
6663864e | 773 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
774 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
775 | cur_index += 2; | |
6663864e | 776 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
777 | uint32_t associativity[] = { |
778 | cpu_to_be32(0x0), | |
779 | cpu_to_be32(0x0), | |
780 | cpu_to_be32(0x0), | |
781 | cpu_to_be32(i) | |
782 | }; | |
783 | memcpy(cur_index, associativity, sizeof(associativity)); | |
784 | cur_index += 4; | |
785 | } | |
786 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
787 | (cur_index - int_buf) * sizeof(uint32_t)); | |
788 | out: | |
789 | g_free(int_buf); | |
790 | return ret; | |
791 | } | |
792 | ||
6787d27b MR |
793 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
794 | sPAPROptionVector *ov5_updates) | |
795 | { | |
796 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 797 | int ret = 0, offset; |
6787d27b MR |
798 | |
799 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
800 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
801 | g_assert(smc->dr_lmb_enabled); | |
802 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
803 | if (ret) { |
804 | goto out; | |
805 | } | |
6787d27b MR |
806 | } |
807 | ||
417ece33 MR |
808 | offset = fdt_path_offset(fdt, "/chosen"); |
809 | if (offset < 0) { | |
810 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
811 | if (offset < 0) { | |
812 | return offset; | |
813 | } | |
814 | } | |
815 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
816 | "ibm,architecture-vec-5"); | |
817 | ||
818 | out: | |
6787d27b MR |
819 | return ret; |
820 | } | |
821 | ||
10f12e64 DHB |
822 | static bool spapr_hotplugged_dev_before_cas(void) |
823 | { | |
824 | Object *drc_container, *obj; | |
825 | ObjectProperty *prop; | |
826 | ObjectPropertyIterator iter; | |
827 | ||
828 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
829 | object_property_iter_init(&iter, drc_container); | |
830 | while ((prop = object_property_iter_next(&iter))) { | |
831 | if (!strstart(prop->type, "link<", NULL)) { | |
832 | continue; | |
833 | } | |
834 | obj = object_property_get_link(drc_container, prop->name, NULL); | |
835 | if (spapr_drc_needed(obj)) { | |
836 | return true; | |
837 | } | |
838 | } | |
839 | return false; | |
840 | } | |
841 | ||
03d196b7 BR |
842 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
843 | target_ulong addr, target_ulong size, | |
6787d27b | 844 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
845 | { |
846 | void *fdt, *fdt_skel; | |
847 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 | 848 | |
10f12e64 DHB |
849 | if (spapr_hotplugged_dev_before_cas()) { |
850 | return 1; | |
851 | } | |
852 | ||
827b17c4 GK |
853 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
854 | error_report("SLOF provided an unexpected CAS buffer size " | |
855 | TARGET_FMT_lu " (min: %zu, max: %u)", | |
856 | size, sizeof(hdr), FW_MAX_SIZE); | |
857 | exit(EXIT_FAILURE); | |
858 | } | |
859 | ||
03d196b7 BR |
860 | size -= sizeof(hdr); |
861 | ||
10f12e64 | 862 | /* Create skeleton */ |
03d196b7 BR |
863 | fdt_skel = g_malloc0(size); |
864 | _FDT((fdt_create(fdt_skel, size))); | |
865 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
866 | _FDT((fdt_end_node(fdt_skel))); | |
867 | _FDT((fdt_finish(fdt_skel))); | |
868 | fdt = g_malloc0(size); | |
869 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
870 | g_free(fdt_skel); | |
871 | ||
872 | /* Fixup cpu nodes */ | |
5b120785 | 873 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 874 | |
6787d27b MR |
875 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
876 | return -1; | |
03d196b7 BR |
877 | } |
878 | ||
879 | /* Pack resulting tree */ | |
880 | _FDT((fdt_pack(fdt))); | |
881 | ||
882 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
883 | trace_spapr_cas_failed(size); | |
884 | return -1; | |
885 | } | |
886 | ||
887 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
888 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
889 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
890 | g_free(fdt); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
3f5dabce DG |
895 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
896 | { | |
897 | int rtas; | |
898 | GString *hypertas = g_string_sized_new(256); | |
899 | GString *qemu_hypertas = g_string_sized_new(256); | |
900 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
901 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
902 | memory_region_size(&spapr->hotplug_memory.mr); | |
903 | uint32_t lrdr_capacity[] = { | |
904 | cpu_to_be32(max_hotplug_addr >> 32), | |
905 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
906 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
907 | cpu_to_be32(max_cpus / smp_threads), | |
908 | }; | |
909 | ||
910 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
911 | ||
912 | /* hypertas */ | |
913 | add_str(hypertas, "hcall-pft"); | |
914 | add_str(hypertas, "hcall-term"); | |
915 | add_str(hypertas, "hcall-dabr"); | |
916 | add_str(hypertas, "hcall-interrupt"); | |
917 | add_str(hypertas, "hcall-tce"); | |
918 | add_str(hypertas, "hcall-vio"); | |
919 | add_str(hypertas, "hcall-splpar"); | |
920 | add_str(hypertas, "hcall-bulk"); | |
921 | add_str(hypertas, "hcall-set-mode"); | |
922 | add_str(hypertas, "hcall-sprg0"); | |
923 | add_str(hypertas, "hcall-copy"); | |
924 | add_str(hypertas, "hcall-debug"); | |
925 | add_str(qemu_hypertas, "hcall-memop1"); | |
926 | ||
927 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
928 | add_str(hypertas, "hcall-multi-tce"); | |
929 | } | |
30f4b05b DG |
930 | |
931 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
932 | add_str(hypertas, "hcall-hpt-resize"); | |
933 | } | |
934 | ||
3f5dabce DG |
935 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
936 | hypertas->str, hypertas->len)); | |
937 | g_string_free(hypertas, TRUE); | |
938 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
939 | qemu_hypertas->str, qemu_hypertas->len)); | |
940 | g_string_free(qemu_hypertas, TRUE); | |
941 | ||
942 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
943 | refpoints, sizeof(refpoints))); | |
944 | ||
945 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
946 | RTAS_ERROR_LOG_MAX)); | |
947 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
948 | RTAS_EVENT_SCAN_RATE)); | |
949 | ||
4f441474 DG |
950 | g_assert(msi_nonbroken); |
951 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
952 | |
953 | /* | |
954 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
955 | * back to the guest cpu. | |
956 | * | |
957 | * While an additional ibm,extended-os-term property indicates | |
958 | * that rtas call return will always occur. Set this property. | |
959 | */ | |
960 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
961 | ||
962 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
963 | lrdr_capacity, sizeof(lrdr_capacity))); | |
964 | ||
965 | spapr_dt_rtas_tokens(fdt, rtas); | |
966 | } | |
967 | ||
9fb4541f SB |
968 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
969 | * that the guest may request and thus the valid values for bytes 24..26 of | |
970 | * option vector 5: */ | |
971 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
972 | { | |
545d6e2b SJS |
973 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
974 | ||
f2b14e3a | 975 | char val[2 * 4] = { |
21f3f8db | 976 | 23, 0x00, /* Xive mode, filled in below. */ |
9fb4541f SB |
977 | 24, 0x00, /* Hash/Radix, filled in below. */ |
978 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
979 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
980 | }; | |
981 | ||
7abd43ba SJS |
982 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
983 | first_ppc_cpu->compat_pvr)) { | |
984 | /* If we're in a pre POWER9 compat mode then the guest should do hash */ | |
985 | val[3] = 0x00; /* Hash */ | |
986 | } else if (kvm_enabled()) { | |
9fb4541f | 987 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 988 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 989 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 990 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 991 | } else { |
f2b14e3a | 992 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
993 | } |
994 | } else { | |
7abd43ba SJS |
995 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
996 | val[3] = 0xC0; | |
9fb4541f SB |
997 | } |
998 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
999 | val, sizeof(val))); | |
1000 | } | |
1001 | ||
7c866c6a DG |
1002 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
1003 | { | |
1004 | MachineState *machine = MACHINE(spapr); | |
1005 | int chosen; | |
1006 | const char *boot_device = machine->boot_order; | |
1007 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1008 | size_t cb = 0; | |
1009 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
1010 | |
1011 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1012 | ||
7c866c6a DG |
1013 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
1014 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1015 | spapr->initrd_base)); | |
1016 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1017 | spapr->initrd_base + spapr->initrd_size)); | |
1018 | ||
1019 | if (spapr->kernel_size) { | |
1020 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
1021 | cpu_to_be64(spapr->kernel_size) }; | |
1022 | ||
1023 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
1024 | &kprop, sizeof(kprop))); | |
1025 | if (spapr->kernel_le) { | |
1026 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1027 | } | |
1028 | } | |
1029 | if (boot_menu) { | |
1030 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1031 | } | |
1032 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1033 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1034 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
1035 | ||
1036 | if (cb && bootlist) { | |
1037 | int i; | |
1038 | ||
1039 | for (i = 0; i < cb; i++) { | |
1040 | if (bootlist[i] == '\n') { | |
1041 | bootlist[i] = ' '; | |
1042 | } | |
1043 | } | |
1044 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
1045 | } | |
1046 | ||
1047 | if (boot_device && strlen(boot_device)) { | |
1048 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1049 | } | |
1050 | ||
1051 | if (!spapr->has_graphics && stdout_path) { | |
1052 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
1053 | } | |
1054 | ||
9fb4541f SB |
1055 | spapr_dt_ov5_platform_support(fdt, chosen); |
1056 | ||
7c866c6a DG |
1057 | g_free(stdout_path); |
1058 | g_free(bootlist); | |
1059 | } | |
1060 | ||
fca5f2dc DG |
1061 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1062 | { | |
1063 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1064 | * KVM to work under pHyp with some guest co-operation */ | |
1065 | int hypervisor; | |
1066 | uint8_t hypercall[16]; | |
1067 | ||
1068 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1069 | /* indicate KVM hypercall interface */ | |
1070 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1071 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1072 | /* | |
1073 | * Older KVM versions with older guest kernels were broken | |
1074 | * with the magic page, don't allow the guest to map it. | |
1075 | */ | |
1076 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1077 | sizeof(hypercall))) { | |
1078 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1079 | hypercall, sizeof(hypercall))); | |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | ||
997b6cfc DG |
1084 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1085 | hwaddr rtas_addr, | |
1086 | hwaddr rtas_size) | |
a3467baa | 1087 | { |
c86c1aff | 1088 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1089 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1090 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1091 | int ret; |
a3467baa | 1092 | void *fdt; |
3384f95c | 1093 | sPAPRPHBState *phb; |
398a0bd5 | 1094 | char *buf; |
a3467baa | 1095 | |
398a0bd5 DG |
1096 | fdt = g_malloc0(FDT_MAX_SIZE); |
1097 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1098 | |
398a0bd5 DG |
1099 | /* Root node */ |
1100 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1101 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1102 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1103 | ||
1104 | /* | |
1105 | * Add info to guest to indentify which host is it being run on | |
1106 | * and what is the uuid of the guest | |
1107 | */ | |
1108 | if (kvmppc_get_host_model(&buf)) { | |
1109 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1110 | g_free(buf); | |
1111 | } | |
1112 | if (kvmppc_get_host_serial(&buf)) { | |
1113 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1114 | g_free(buf); | |
1115 | } | |
1116 | ||
1117 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1118 | ||
1119 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1120 | if (qemu_uuid_set) { | |
1121 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1122 | } | |
1123 | g_free(buf); | |
1124 | ||
1125 | if (qemu_get_vm_name()) { | |
1126 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1127 | qemu_get_vm_name())); | |
1128 | } | |
1129 | ||
1130 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1131 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1132 | |
fc7e0765 DG |
1133 | /* /interrupt controller */ |
1134 | spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); | |
1135 | ||
e8f986fc BR |
1136 | ret = spapr_populate_memory(spapr, fdt); |
1137 | if (ret < 0) { | |
ce9863b7 | 1138 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1139 | exit(1); |
7f763a5d DG |
1140 | } |
1141 | ||
bf5a6696 DG |
1142 | /* /vdevice */ |
1143 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1144 | |
4d9392be TH |
1145 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1146 | ret = spapr_rng_populate_dt(fdt); | |
1147 | if (ret < 0) { | |
ce9863b7 | 1148 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1149 | exit(1); |
1150 | } | |
1151 | } | |
1152 | ||
3384f95c | 1153 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1154 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1155 | if (ret < 0) { |
1156 | error_report("couldn't setup PCI devices in fdt"); | |
1157 | exit(1); | |
1158 | } | |
3384f95c DG |
1159 | } |
1160 | ||
0da6f3fe BR |
1161 | /* cpus */ |
1162 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1163 | |
c20d332a BR |
1164 | if (smc->dr_lmb_enabled) { |
1165 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1166 | } | |
1167 | ||
c5514d0e | 1168 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1169 | int offset = fdt_path_offset(fdt, "/cpus"); |
1170 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1171 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1172 | if (ret < 0) { | |
1173 | error_report("Couldn't set up CPU DR device tree properties"); | |
1174 | exit(1); | |
1175 | } | |
1176 | } | |
1177 | ||
ffb1e275 | 1178 | /* /event-sources */ |
ffbb1705 | 1179 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1180 | |
3f5dabce DG |
1181 | /* /rtas */ |
1182 | spapr_dt_rtas(spapr, fdt); | |
1183 | ||
7c866c6a DG |
1184 | /* /chosen */ |
1185 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1186 | |
fca5f2dc DG |
1187 | /* /hypervisor */ |
1188 | if (kvm_enabled()) { | |
1189 | spapr_dt_hypervisor(spapr, fdt); | |
1190 | } | |
1191 | ||
cf6e5223 DG |
1192 | /* Build memory reserve map */ |
1193 | if (spapr->kernel_size) { | |
1194 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1195 | } | |
1196 | if (spapr->initrd_size) { | |
1197 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1198 | } | |
1199 | ||
6787d27b MR |
1200 | /* ibm,client-architecture-support updates */ |
1201 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1202 | if (ret < 0) { | |
1203 | error_report("couldn't setup CAS properties fdt"); | |
1204 | exit(1); | |
1205 | } | |
1206 | ||
997b6cfc | 1207 | return fdt; |
9fdf0c29 DG |
1208 | } |
1209 | ||
1210 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1211 | { | |
1212 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1213 | } | |
1214 | ||
1d1be34d DG |
1215 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1216 | PowerPCCPU *cpu) | |
9fdf0c29 | 1217 | { |
1b14670a AF |
1218 | CPUPPCState *env = &cpu->env; |
1219 | ||
8d04fb55 JK |
1220 | /* The TCG path should also be holding the BQL at this point */ |
1221 | g_assert(qemu_mutex_iothread_locked()); | |
1222 | ||
efcb9383 DG |
1223 | if (msr_pr) { |
1224 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1225 | env->gpr[3] = H_PRIVILEGE; | |
1226 | } else { | |
aa100fa4 | 1227 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1228 | } |
9fdf0c29 DG |
1229 | } |
1230 | ||
9861bb3e SJS |
1231 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1232 | { | |
1233 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1234 | ||
1235 | return spapr->patb_entry; | |
1236 | } | |
1237 | ||
e6b8fd24 SMJ |
1238 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1239 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1240 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1241 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1242 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1243 | ||
715c5407 DG |
1244 | /* |
1245 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1246 | */ | |
1247 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1248 | { | |
14b0d748 GK |
1249 | Error *local_err = NULL; |
1250 | ||
715c5407 DG |
1251 | if (spapr->htab_fd >= 0) { |
1252 | return spapr->htab_fd; | |
1253 | } | |
1254 | ||
14b0d748 | 1255 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1256 | if (spapr->htab_fd < 0) { |
14b0d748 | 1257 | error_report_err(local_err); |
715c5407 DG |
1258 | } |
1259 | ||
1260 | return spapr->htab_fd; | |
1261 | } | |
1262 | ||
b4db5413 | 1263 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1264 | { |
1265 | if (spapr->htab_fd >= 0) { | |
1266 | close(spapr->htab_fd); | |
1267 | } | |
1268 | spapr->htab_fd = -1; | |
1269 | } | |
1270 | ||
e57ca75c DG |
1271 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1272 | { | |
1273 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1274 | ||
1275 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1276 | } | |
1277 | ||
1ec26c75 GK |
1278 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1279 | { | |
1280 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1281 | ||
1282 | assert(kvm_enabled()); | |
1283 | ||
1284 | if (!spapr->htab) { | |
1285 | return 0; | |
1286 | } | |
1287 | ||
1288 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1289 | } | |
1290 | ||
e57ca75c DG |
1291 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1292 | hwaddr ptex, int n) | |
1293 | { | |
1294 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1295 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1296 | ||
1297 | if (!spapr->htab) { | |
1298 | /* | |
1299 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1300 | */ | |
1301 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1302 | kvmppc_read_hptes(hptes, ptex, n); | |
1303 | return hptes; | |
1304 | } | |
1305 | ||
1306 | /* | |
1307 | * HTAB is controlled by QEMU. Just point to the internally | |
1308 | * accessible PTEG. | |
1309 | */ | |
1310 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1311 | } | |
1312 | ||
1313 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1314 | const ppc_hash_pte64_t *hptes, | |
1315 | hwaddr ptex, int n) | |
1316 | { | |
1317 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1318 | ||
1319 | if (!spapr->htab) { | |
1320 | g_free((void *)hptes); | |
1321 | } | |
1322 | ||
1323 | /* Nothing to do for qemu managed HPT */ | |
1324 | } | |
1325 | ||
1326 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1327 | uint64_t pte0, uint64_t pte1) | |
1328 | { | |
1329 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1330 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1331 | ||
1332 | if (!spapr->htab) { | |
1333 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1334 | } else { | |
1335 | stq_p(spapr->htab + offset, pte0); | |
1336 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1337 | } | |
1338 | } | |
1339 | ||
0b0b8310 | 1340 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1341 | { |
1342 | int shift; | |
1343 | ||
1344 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1345 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1346 | * that's much more than is needed for Linux guests */ | |
1347 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1348 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1349 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1350 | return shift; | |
1351 | } | |
1352 | ||
06ec79e8 BR |
1353 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1354 | { | |
1355 | g_free(spapr->htab); | |
1356 | spapr->htab = NULL; | |
1357 | spapr->htab_shift = 0; | |
1358 | close_htab_fd(spapr); | |
1359 | } | |
1360 | ||
2772cf6b DG |
1361 | void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1362 | Error **errp) | |
7f763a5d | 1363 | { |
c5f54f3e DG |
1364 | long rc; |
1365 | ||
1366 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1367 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1368 | |
1369 | rc = kvmppc_reset_htab(shift); | |
1370 | if (rc < 0) { | |
1371 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1372 | error_setg_errno(errp, errno, | |
1373 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1374 | shift); | |
1375 | /* This is almost certainly fatal, but if the caller really | |
1376 | * wants to carry on with shift == 0, it's welcome to try */ | |
1377 | } else if (rc > 0) { | |
1378 | /* kernel-side HPT allocated */ | |
1379 | if (rc != shift) { | |
1380 | error_setg(errp, | |
1381 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1382 | shift, rc); | |
7735feda BR |
1383 | } |
1384 | ||
7f763a5d | 1385 | spapr->htab_shift = shift; |
c18ad9a5 | 1386 | spapr->htab = NULL; |
b817772a | 1387 | } else { |
c5f54f3e DG |
1388 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1389 | size_t size = 1ULL << shift; | |
1390 | int i; | |
b817772a | 1391 | |
c5f54f3e DG |
1392 | spapr->htab = qemu_memalign(size, size); |
1393 | if (!spapr->htab) { | |
1394 | error_setg_errno(errp, errno, | |
1395 | "Could not allocate HPT of order %d", shift); | |
1396 | return; | |
7735feda BR |
1397 | } |
1398 | ||
c5f54f3e DG |
1399 | memset(spapr->htab, 0, size); |
1400 | spapr->htab_shift = shift; | |
e6b8fd24 | 1401 | |
c5f54f3e DG |
1402 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1403 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1404 | } |
7f763a5d | 1405 | } |
ee4d9ecc SJS |
1406 | /* We're setting up a hash table, so that means we're not radix */ |
1407 | spapr->patb_entry = 0; | |
9fdf0c29 DG |
1408 | } |
1409 | ||
b4db5413 SJS |
1410 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1411 | { | |
2772cf6b DG |
1412 | int hpt_shift; |
1413 | ||
1414 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) | |
1415 | || (spapr->cas_reboot | |
1416 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { | |
1417 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1418 | } else { | |
768a20f3 DG |
1419 | uint64_t current_ram_size; |
1420 | ||
1421 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1422 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1423 | } |
1424 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1425 | ||
b4db5413 | 1426 | if (spapr->vrma_adjust) { |
c86c1aff | 1427 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
b4db5413 SJS |
1428 | spapr->htab_shift); |
1429 | } | |
b4db5413 SJS |
1430 | } |
1431 | ||
4f01a637 | 1432 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1433 | { |
1434 | bool matched = false; | |
1435 | ||
1436 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1437 | matched = true; | |
1438 | } | |
1439 | ||
1440 | if (!matched) { | |
1441 | error_report("Device %s is not supported by this machine yet.", | |
1442 | qdev_fw_name(DEVICE(sbdev))); | |
1443 | exit(1); | |
1444 | } | |
9e3f9733 AG |
1445 | } |
1446 | ||
82512483 GK |
1447 | static int spapr_reset_drcs(Object *child, void *opaque) |
1448 | { | |
1449 | sPAPRDRConnector *drc = | |
1450 | (sPAPRDRConnector *) object_dynamic_cast(child, | |
1451 | TYPE_SPAPR_DR_CONNECTOR); | |
1452 | ||
1453 | if (drc) { | |
1454 | spapr_drc_reset(drc); | |
1455 | } | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
bcb5ce08 | 1460 | static void spapr_machine_reset(void) |
a3467baa | 1461 | { |
c5f54f3e DG |
1462 | MachineState *machine = MACHINE(qdev_get_machine()); |
1463 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1464 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1465 | uint32_t rtas_limit; |
cae172ab | 1466 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1467 | void *fdt; |
1468 | int rc; | |
259186a7 | 1469 | |
9e3f9733 AG |
1470 | /* Check for unknown sysbus devices */ |
1471 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1472 | ||
33face6b DG |
1473 | spapr_caps_reset(spapr); |
1474 | ||
1481fe5f LV |
1475 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1476 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
1477 | ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, | |
1478 | spapr->max_compat_pvr)) { | |
b4db5413 SJS |
1479 | /* If using KVM with radix mode available, VCPUs can be started |
1480 | * without a HPT because KVM will start them in radix mode. | |
1481 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1482 | spapr->patb_entry = PATBE1_GR; | |
1483 | } else { | |
b4db5413 | 1484 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1485 | } |
a3467baa | 1486 | |
c8787ad4 | 1487 | qemu_devices_reset(); |
82512483 GK |
1488 | |
1489 | /* DRC reset may cause a device to be unplugged. This will cause troubles | |
1490 | * if this device is used by another device (eg, a running vhost backend | |
1491 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1492 | * situations, we reset DRCs after all devices have been reset. | |
1493 | */ | |
1494 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1495 | ||
56258174 | 1496 | spapr_clear_pending_events(spapr); |
a3467baa | 1497 | |
b7d1f77a BH |
1498 | /* |
1499 | * We place the device tree and RTAS just below either the top of the RMA, | |
1500 | * or just below 2GB, whichever is lowere, so that it can be | |
1501 | * processed with 32-bit real mode code if necessary | |
1502 | */ | |
1503 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1504 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1505 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1506 | |
6787d27b MR |
1507 | /* if this reset wasn't generated by CAS, we should reset our |
1508 | * negotiated options and start from scratch */ | |
1509 | if (!spapr->cas_reboot) { | |
1510 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1511 | spapr->ov5_cas = spapr_ovec_new(); | |
66d5c492 | 1512 | |
51f84465 | 1513 | ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); |
6787d27b MR |
1514 | } |
1515 | ||
cae172ab | 1516 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1517 | |
2cac78c1 | 1518 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1519 | |
997b6cfc DG |
1520 | rc = fdt_pack(fdt); |
1521 | ||
1522 | /* Should only fail if we've built a corrupted tree */ | |
1523 | assert(rc == 0); | |
1524 | ||
1525 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1526 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1527 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1528 | exit(1); | |
1529 | } | |
1530 | ||
1531 | /* Load the fdt */ | |
1532 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1533 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1534 | g_free(fdt); |
1535 | ||
a3467baa | 1536 | /* Set up the entry state */ |
cae172ab | 1537 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1538 | first_ppc_cpu->env.gpr[5] = 0; |
1539 | first_cpu->halted = 0; | |
1b718907 | 1540 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1541 | |
6787d27b | 1542 | spapr->cas_reboot = false; |
a3467baa DG |
1543 | } |
1544 | ||
28e02042 | 1545 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1546 | { |
2ff3de68 | 1547 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1548 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1549 | |
3978b863 | 1550 | if (dinfo) { |
6231a6da MA |
1551 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1552 | &error_fatal); | |
639e8102 DG |
1553 | } |
1554 | ||
1555 | qdev_init_nofail(dev); | |
1556 | ||
1557 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1558 | } | |
1559 | ||
28e02042 | 1560 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1561 | { |
147ff807 CLG |
1562 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1563 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1564 | &error_fatal); | |
1565 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1566 | &error_fatal); | |
1567 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1568 | "date", &error_fatal); | |
28df36a1 DG |
1569 | } |
1570 | ||
8c57b867 | 1571 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1572 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1573 | { |
8c57b867 | 1574 | switch (vga_interface_type) { |
8c57b867 | 1575 | case VGA_NONE: |
7effdaa3 MW |
1576 | return false; |
1577 | case VGA_DEVICE: | |
1578 | return true; | |
1ddcae82 | 1579 | case VGA_STD: |
b798c190 | 1580 | case VGA_VIRTIO: |
1ddcae82 | 1581 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1582 | default: |
14c6a894 DG |
1583 | error_setg(errp, |
1584 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1585 | return false; | |
f28359d8 | 1586 | } |
f28359d8 LZ |
1587 | } |
1588 | ||
4e5fe368 SJS |
1589 | static int spapr_pre_load(void *opaque) |
1590 | { | |
1591 | int rc; | |
1592 | ||
1593 | rc = spapr_caps_pre_load(opaque); | |
1594 | if (rc) { | |
1595 | return rc; | |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
880ae7de DG |
1601 | static int spapr_post_load(void *opaque, int version_id) |
1602 | { | |
28e02042 | 1603 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1604 | int err = 0; |
1605 | ||
be85537d DG |
1606 | err = spapr_caps_post_migration(spapr); |
1607 | if (err) { | |
1608 | return err; | |
1609 | } | |
1610 | ||
a7ff1212 | 1611 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1612 | CPUState *cs; |
1613 | CPU_FOREACH(cs) { | |
1614 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1615 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1616 | } |
1617 | } | |
1618 | ||
631b22ea | 1619 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1620 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1621 | * So when migrating from those versions, poke the incoming offset | |
1622 | * value into the RTC device */ | |
1623 | if (version_id < 3) { | |
147ff807 | 1624 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1625 | } |
1626 | ||
0c86b2df | 1627 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 BR |
1628 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1629 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1630 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1631 | ||
1632 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1633 | if (err) { | |
1634 | error_report("Process table config unsupported by the host"); | |
1635 | return -EINVAL; | |
1636 | } | |
1637 | } | |
1638 | ||
880ae7de DG |
1639 | return err; |
1640 | } | |
1641 | ||
4e5fe368 SJS |
1642 | static int spapr_pre_save(void *opaque) |
1643 | { | |
1644 | int rc; | |
1645 | ||
1646 | rc = spapr_caps_pre_save(opaque); | |
1647 | if (rc) { | |
1648 | return rc; | |
1649 | } | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
880ae7de DG |
1654 | static bool version_before_3(void *opaque, int version_id) |
1655 | { | |
1656 | return version_id < 3; | |
1657 | } | |
1658 | ||
fd38804b DHB |
1659 | static bool spapr_pending_events_needed(void *opaque) |
1660 | { | |
1661 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1662 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1663 | } | |
1664 | ||
1665 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1666 | .name = "spapr_event_log_entry", | |
1667 | .version_id = 1, | |
1668 | .minimum_version_id = 1, | |
1669 | .fields = (VMStateField[]) { | |
5341258e DG |
1670 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1671 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1672 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1673 | NULL, extended_length), |
fd38804b DHB |
1674 | VMSTATE_END_OF_LIST() |
1675 | }, | |
1676 | }; | |
1677 | ||
1678 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1679 | .name = "spapr_pending_events", | |
1680 | .version_id = 1, | |
1681 | .minimum_version_id = 1, | |
1682 | .needed = spapr_pending_events_needed, | |
1683 | .fields = (VMStateField[]) { | |
1684 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1685 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1686 | VMSTATE_END_OF_LIST() | |
1687 | }, | |
1688 | }; | |
1689 | ||
62ef3760 MR |
1690 | static bool spapr_ov5_cas_needed(void *opaque) |
1691 | { | |
1692 | sPAPRMachineState *spapr = opaque; | |
1693 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1694 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1695 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1696 | bool cas_needed; | |
1697 | ||
1698 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1699 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1700 | * Both of these options encode machine topology into the device-tree | |
1701 | * in such a way that the now-booted OS should still be able to interact | |
1702 | * appropriately with QEMU regardless of what options were actually | |
1703 | * negotiatied on the source side. | |
1704 | * | |
1705 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1706 | * are the only options available on the current machine/platform. | |
1707 | * Since these are the only options available for pseries-2.7 and | |
1708 | * earlier, this allows us to maintain old->new/new->old migration | |
1709 | * compatibility. | |
1710 | * | |
1711 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1712 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1713 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1714 | * of the actual CAS-negotiated values to continue working properly. For | |
1715 | * example, availability of memory unplug depends on knowing whether | |
1716 | * OV5_HP_EVT was negotiated via CAS. | |
1717 | * | |
1718 | * Thus, for any cases where the set of available CAS-negotiatable | |
1719 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
1720 | * include the CAS-negotiated options in the migration stream. | |
1721 | */ | |
1722 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1723 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
1724 | ||
1725 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1726 | * the mask itself since in the future it's possible "legacy" bits may be | |
1727 | * removed via machine options, which could generate a false positive | |
1728 | * that breaks migration. | |
1729 | */ | |
1730 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1731 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1732 | ||
1733 | spapr_ovec_cleanup(ov5_mask); | |
1734 | spapr_ovec_cleanup(ov5_legacy); | |
1735 | spapr_ovec_cleanup(ov5_removed); | |
1736 | ||
1737 | return cas_needed; | |
1738 | } | |
1739 | ||
1740 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1741 | .name = "spapr_option_vector_ov5_cas", | |
1742 | .version_id = 1, | |
1743 | .minimum_version_id = 1, | |
1744 | .needed = spapr_ov5_cas_needed, | |
1745 | .fields = (VMStateField[]) { | |
1746 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1747 | vmstate_spapr_ovec, sPAPROptionVector), | |
1748 | VMSTATE_END_OF_LIST() | |
1749 | }, | |
1750 | }; | |
1751 | ||
9861bb3e SJS |
1752 | static bool spapr_patb_entry_needed(void *opaque) |
1753 | { | |
1754 | sPAPRMachineState *spapr = opaque; | |
1755 | ||
1756 | return !!spapr->patb_entry; | |
1757 | } | |
1758 | ||
1759 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1760 | .name = "spapr_patb_entry", | |
1761 | .version_id = 1, | |
1762 | .minimum_version_id = 1, | |
1763 | .needed = spapr_patb_entry_needed, | |
1764 | .fields = (VMStateField[]) { | |
1765 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1766 | VMSTATE_END_OF_LIST() | |
1767 | }, | |
1768 | }; | |
1769 | ||
4be21d56 DG |
1770 | static const VMStateDescription vmstate_spapr = { |
1771 | .name = "spapr", | |
880ae7de | 1772 | .version_id = 3, |
4be21d56 | 1773 | .minimum_version_id = 1, |
4e5fe368 | 1774 | .pre_load = spapr_pre_load, |
880ae7de | 1775 | .post_load = spapr_post_load, |
4e5fe368 | 1776 | .pre_save = spapr_pre_save, |
3aff6c2f | 1777 | .fields = (VMStateField[]) { |
880ae7de DG |
1778 | /* used to be @next_irq */ |
1779 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1780 | |
1781 | /* RTC offset */ | |
28e02042 | 1782 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1783 | |
28e02042 | 1784 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1785 | VMSTATE_END_OF_LIST() |
1786 | }, | |
62ef3760 MR |
1787 | .subsections = (const VMStateDescription*[]) { |
1788 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1789 | &vmstate_spapr_patb_entry, |
fd38804b | 1790 | &vmstate_spapr_pending_events, |
4e5fe368 SJS |
1791 | &vmstate_spapr_cap_htm, |
1792 | &vmstate_spapr_cap_vsx, | |
1793 | &vmstate_spapr_cap_dfp, | |
62ef3760 MR |
1794 | NULL |
1795 | } | |
4be21d56 DG |
1796 | }; |
1797 | ||
4be21d56 DG |
1798 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1799 | { | |
28e02042 | 1800 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1801 | |
4be21d56 | 1802 | /* "Iteration" header */ |
3a384297 BR |
1803 | if (!spapr->htab_shift) { |
1804 | qemu_put_be32(f, -1); | |
1805 | } else { | |
1806 | qemu_put_be32(f, spapr->htab_shift); | |
1807 | } | |
4be21d56 | 1808 | |
e68cb8b4 AK |
1809 | if (spapr->htab) { |
1810 | spapr->htab_save_index = 0; | |
1811 | spapr->htab_first_pass = true; | |
1812 | } else { | |
3a384297 BR |
1813 | if (spapr->htab_shift) { |
1814 | assert(kvm_enabled()); | |
1815 | } | |
e68cb8b4 AK |
1816 | } |
1817 | ||
1818 | ||
4be21d56 DG |
1819 | return 0; |
1820 | } | |
1821 | ||
332f7721 GK |
1822 | static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, |
1823 | int chunkstart, int n_valid, int n_invalid) | |
1824 | { | |
1825 | qemu_put_be32(f, chunkstart); | |
1826 | qemu_put_be16(f, n_valid); | |
1827 | qemu_put_be16(f, n_invalid); | |
1828 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1829 | HASH_PTE_SIZE_64 * n_valid); | |
1830 | } | |
1831 | ||
1832 | static void htab_save_end_marker(QEMUFile *f) | |
1833 | { | |
1834 | qemu_put_be32(f, 0); | |
1835 | qemu_put_be16(f, 0); | |
1836 | qemu_put_be16(f, 0); | |
1837 | } | |
1838 | ||
28e02042 | 1839 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1840 | int64_t max_ns) |
1841 | { | |
378bc217 | 1842 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1843 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1844 | int index = spapr->htab_save_index; | |
bc72ad67 | 1845 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1846 | |
1847 | assert(spapr->htab_first_pass); | |
1848 | ||
1849 | do { | |
1850 | int chunkstart; | |
1851 | ||
1852 | /* Consume invalid HPTEs */ | |
1853 | while ((index < htabslots) | |
1854 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 1855 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1856 | index++; |
4be21d56 DG |
1857 | } |
1858 | ||
1859 | /* Consume valid HPTEs */ | |
1860 | chunkstart = index; | |
338c25b6 | 1861 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 1862 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 1863 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1864 | index++; |
4be21d56 DG |
1865 | } |
1866 | ||
1867 | if (index > chunkstart) { | |
1868 | int n_valid = index - chunkstart; | |
1869 | ||
332f7721 | 1870 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 1871 | |
378bc217 DG |
1872 | if (has_timeout && |
1873 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1874 | break; |
1875 | } | |
1876 | } | |
1877 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1878 | ||
1879 | if (index >= htabslots) { | |
1880 | assert(index == htabslots); | |
1881 | index = 0; | |
1882 | spapr->htab_first_pass = false; | |
1883 | } | |
1884 | spapr->htab_save_index = index; | |
1885 | } | |
1886 | ||
28e02042 | 1887 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1888 | int64_t max_ns) |
4be21d56 DG |
1889 | { |
1890 | bool final = max_ns < 0; | |
1891 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1892 | int examined = 0, sent = 0; | |
1893 | int index = spapr->htab_save_index; | |
bc72ad67 | 1894 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1895 | |
1896 | assert(!spapr->htab_first_pass); | |
1897 | ||
1898 | do { | |
1899 | int chunkstart, invalidstart; | |
1900 | ||
1901 | /* Consume non-dirty HPTEs */ | |
1902 | while ((index < htabslots) | |
1903 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1904 | index++; | |
1905 | examined++; | |
1906 | } | |
1907 | ||
1908 | chunkstart = index; | |
1909 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1910 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1911 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1912 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1913 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1914 | index++; | |
1915 | examined++; | |
1916 | } | |
1917 | ||
1918 | invalidstart = index; | |
1919 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1920 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1921 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1922 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1923 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1924 | index++; | |
1925 | examined++; | |
1926 | } | |
1927 | ||
1928 | if (index > chunkstart) { | |
1929 | int n_valid = invalidstart - chunkstart; | |
1930 | int n_invalid = index - invalidstart; | |
1931 | ||
332f7721 | 1932 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
1933 | sent += index - chunkstart; |
1934 | ||
bc72ad67 | 1935 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1936 | break; |
1937 | } | |
1938 | } | |
1939 | ||
1940 | if (examined >= htabslots) { | |
1941 | break; | |
1942 | } | |
1943 | ||
1944 | if (index >= htabslots) { | |
1945 | assert(index == htabslots); | |
1946 | index = 0; | |
1947 | } | |
1948 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1949 | ||
1950 | if (index >= htabslots) { | |
1951 | assert(index == htabslots); | |
1952 | index = 0; | |
1953 | } | |
1954 | ||
1955 | spapr->htab_save_index = index; | |
1956 | ||
e68cb8b4 | 1957 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1958 | } |
1959 | ||
e68cb8b4 AK |
1960 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1961 | #define MAX_KVM_BUF_SIZE 2048 | |
1962 | ||
4be21d56 DG |
1963 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1964 | { | |
28e02042 | 1965 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1966 | int fd; |
e68cb8b4 | 1967 | int rc = 0; |
4be21d56 DG |
1968 | |
1969 | /* Iteration header */ | |
3a384297 BR |
1970 | if (!spapr->htab_shift) { |
1971 | qemu_put_be32(f, -1); | |
e8cd4247 | 1972 | return 1; |
3a384297 BR |
1973 | } else { |
1974 | qemu_put_be32(f, 0); | |
1975 | } | |
4be21d56 | 1976 | |
e68cb8b4 AK |
1977 | if (!spapr->htab) { |
1978 | assert(kvm_enabled()); | |
1979 | ||
715c5407 DG |
1980 | fd = get_htab_fd(spapr); |
1981 | if (fd < 0) { | |
1982 | return fd; | |
01a57972 SMJ |
1983 | } |
1984 | ||
715c5407 | 1985 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1986 | if (rc < 0) { |
1987 | return rc; | |
1988 | } | |
1989 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1990 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1991 | } else { | |
e68cb8b4 | 1992 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1993 | } |
1994 | ||
332f7721 | 1995 | htab_save_end_marker(f); |
4be21d56 | 1996 | |
e68cb8b4 | 1997 | return rc; |
4be21d56 DG |
1998 | } |
1999 | ||
2000 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
2001 | { | |
28e02042 | 2002 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2003 | int fd; |
4be21d56 DG |
2004 | |
2005 | /* Iteration header */ | |
3a384297 BR |
2006 | if (!spapr->htab_shift) { |
2007 | qemu_put_be32(f, -1); | |
2008 | return 0; | |
2009 | } else { | |
2010 | qemu_put_be32(f, 0); | |
2011 | } | |
4be21d56 | 2012 | |
e68cb8b4 AK |
2013 | if (!spapr->htab) { |
2014 | int rc; | |
2015 | ||
2016 | assert(kvm_enabled()); | |
2017 | ||
715c5407 DG |
2018 | fd = get_htab_fd(spapr); |
2019 | if (fd < 0) { | |
2020 | return fd; | |
01a57972 SMJ |
2021 | } |
2022 | ||
715c5407 | 2023 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
2024 | if (rc < 0) { |
2025 | return rc; | |
2026 | } | |
e68cb8b4 | 2027 | } else { |
378bc217 DG |
2028 | if (spapr->htab_first_pass) { |
2029 | htab_save_first_pass(f, spapr, -1); | |
2030 | } | |
e68cb8b4 AK |
2031 | htab_save_later_pass(f, spapr, -1); |
2032 | } | |
4be21d56 DG |
2033 | |
2034 | /* End marker */ | |
332f7721 | 2035 | htab_save_end_marker(f); |
4be21d56 DG |
2036 | |
2037 | return 0; | |
2038 | } | |
2039 | ||
2040 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2041 | { | |
28e02042 | 2042 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 2043 | uint32_t section_hdr; |
e68cb8b4 | 2044 | int fd = -1; |
14b0d748 | 2045 | Error *local_err = NULL; |
4be21d56 DG |
2046 | |
2047 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2048 | error_report("htab_load() bad version"); |
4be21d56 DG |
2049 | return -EINVAL; |
2050 | } | |
2051 | ||
2052 | section_hdr = qemu_get_be32(f); | |
2053 | ||
3a384297 BR |
2054 | if (section_hdr == -1) { |
2055 | spapr_free_hpt(spapr); | |
2056 | return 0; | |
2057 | } | |
2058 | ||
4be21d56 | 2059 | if (section_hdr) { |
c5f54f3e DG |
2060 | /* First section gives the htab size */ |
2061 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2062 | if (local_err) { | |
2063 | error_report_err(local_err); | |
4be21d56 DG |
2064 | return -EINVAL; |
2065 | } | |
2066 | return 0; | |
2067 | } | |
2068 | ||
e68cb8b4 AK |
2069 | if (!spapr->htab) { |
2070 | assert(kvm_enabled()); | |
2071 | ||
14b0d748 | 2072 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2073 | if (fd < 0) { |
14b0d748 | 2074 | error_report_err(local_err); |
82be8e73 | 2075 | return fd; |
e68cb8b4 AK |
2076 | } |
2077 | } | |
2078 | ||
4be21d56 DG |
2079 | while (true) { |
2080 | uint32_t index; | |
2081 | uint16_t n_valid, n_invalid; | |
2082 | ||
2083 | index = qemu_get_be32(f); | |
2084 | n_valid = qemu_get_be16(f); | |
2085 | n_invalid = qemu_get_be16(f); | |
2086 | ||
2087 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2088 | /* End of Stream */ | |
2089 | break; | |
2090 | } | |
2091 | ||
e68cb8b4 | 2092 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2093 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2094 | /* Bad index in stream */ | |
98a5d100 DG |
2095 | error_report( |
2096 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2097 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2098 | return -EINVAL; |
2099 | } | |
2100 | ||
e68cb8b4 AK |
2101 | if (spapr->htab) { |
2102 | if (n_valid) { | |
2103 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2104 | HASH_PTE_SIZE_64 * n_valid); | |
2105 | } | |
2106 | if (n_invalid) { | |
2107 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2108 | HASH_PTE_SIZE_64 * n_invalid); | |
2109 | } | |
2110 | } else { | |
2111 | int rc; | |
2112 | ||
2113 | assert(fd >= 0); | |
2114 | ||
2115 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2116 | if (rc < 0) { | |
2117 | return rc; | |
2118 | } | |
4be21d56 DG |
2119 | } |
2120 | } | |
2121 | ||
e68cb8b4 AK |
2122 | if (!spapr->htab) { |
2123 | assert(fd >= 0); | |
2124 | close(fd); | |
2125 | } | |
2126 | ||
4be21d56 DG |
2127 | return 0; |
2128 | } | |
2129 | ||
70f794fc | 2130 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
2131 | { |
2132 | sPAPRMachineState *spapr = opaque; | |
2133 | ||
2134 | close_htab_fd(spapr); | |
2135 | } | |
2136 | ||
4be21d56 | 2137 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2138 | .save_setup = htab_save_setup, |
4be21d56 | 2139 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2140 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2141 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2142 | .load_state = htab_load, |
2143 | }; | |
2144 | ||
5b2128d2 AG |
2145 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2146 | Error **errp) | |
2147 | { | |
c86c1aff | 2148 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2149 | machine->boot_order = g_strdup(boot_device); |
2150 | } | |
2151 | ||
224245bf DG |
2152 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2153 | { | |
2154 | MachineState *machine = MACHINE(spapr); | |
2155 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2156 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2157 | int i; |
2158 | ||
2159 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2160 | uint64_t addr; |
2161 | ||
e8f986fc | 2162 | addr = i * lmb_size + spapr->hotplug_memory.base; |
6caf3ac6 DG |
2163 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2164 | addr / lmb_size); | |
224245bf DG |
2165 | } |
2166 | } | |
2167 | ||
2168 | /* | |
2169 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2170 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2171 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2172 | */ | |
7c150d6f | 2173 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2174 | { |
2175 | int i; | |
2176 | ||
7c150d6f DG |
2177 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2178 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
2179 | " is not aligned to %llu MiB", | |
2180 | machine->ram_size, | |
2181 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2182 | return; | |
2183 | } | |
2184 | ||
2185 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2186 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
2187 | " is not aligned to %llu MiB", | |
2188 | machine->ram_size, | |
2189 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2190 | return; | |
224245bf DG |
2191 | } |
2192 | ||
2193 | for (i = 0; i < nb_numa_nodes; i++) { | |
2194 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2195 | error_setg(errp, |
2196 | "Node %d memory size 0x%" PRIx64 | |
2197 | " is not aligned to %llu MiB", | |
2198 | i, numa_info[i].node_mem, | |
2199 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2200 | return; | |
224245bf DG |
2201 | } |
2202 | } | |
2203 | } | |
2204 | ||
535455fd IM |
2205 | /* find cpu slot in machine->possible_cpus by core_id */ |
2206 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2207 | { | |
2208 | int index = id / smp_threads; | |
2209 | ||
2210 | if (index >= ms->possible_cpus->len) { | |
2211 | return NULL; | |
2212 | } | |
2213 | if (idx) { | |
2214 | *idx = index; | |
2215 | } | |
2216 | return &ms->possible_cpus->cpus[index]; | |
2217 | } | |
2218 | ||
0c86d0fd DG |
2219 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2220 | { | |
2221 | MachineState *machine = MACHINE(spapr); | |
2222 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2e9c10eb | 2223 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); |
0c86d0fd | 2224 | int smt = kvmppc_smt_threads(); |
535455fd IM |
2225 | const CPUArchIdList *possible_cpus; |
2226 | int boot_cores_nr = smp_cpus / smp_threads; | |
0c86d0fd DG |
2227 | int i; |
2228 | ||
2229 | if (!type) { | |
2230 | error_report("Unable to find sPAPR CPU Core definition"); | |
2231 | exit(1); | |
2232 | } | |
2233 | ||
535455fd | 2234 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
c5514d0e | 2235 | if (mc->has_hotpluggable_cpus) { |
0c86d0fd DG |
2236 | if (smp_cpus % smp_threads) { |
2237 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2238 | smp_cpus, smp_threads); | |
2239 | exit(1); | |
2240 | } | |
2241 | if (max_cpus % smp_threads) { | |
2242 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2243 | max_cpus, smp_threads); | |
2244 | exit(1); | |
2245 | } | |
0c86d0fd DG |
2246 | } else { |
2247 | if (max_cpus != smp_cpus) { | |
2248 | error_report("This machine version does not support CPU hotplug"); | |
2249 | exit(1); | |
2250 | } | |
535455fd | 2251 | boot_cores_nr = possible_cpus->len; |
0c86d0fd DG |
2252 | } |
2253 | ||
535455fd | 2254 | for (i = 0; i < possible_cpus->len; i++) { |
0c86d0fd DG |
2255 | int core_id = i * smp_threads; |
2256 | ||
c5514d0e | 2257 | if (mc->has_hotpluggable_cpus) { |
6caf3ac6 DG |
2258 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, |
2259 | (core_id / smp_threads) * smt); | |
0c86d0fd DG |
2260 | } |
2261 | ||
535455fd | 2262 | if (i < boot_cores_nr) { |
0c86d0fd DG |
2263 | Object *core = object_new(type); |
2264 | int nr_threads = smp_threads; | |
2265 | ||
2266 | /* Handle the partially filled core for older machine types */ | |
2267 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2268 | nr_threads = smp_cpus - i * smp_threads; | |
2269 | } | |
2270 | ||
2271 | object_property_set_int(core, nr_threads, "nr-threads", | |
2272 | &error_fatal); | |
2273 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2274 | &error_fatal); | |
2275 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2276 | } | |
2277 | } | |
0c86d0fd DG |
2278 | } |
2279 | ||
fa98fbfc SB |
2280 | static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) |
2281 | { | |
2282 | Error *local_err = NULL; | |
2283 | bool vsmt_user = !!spapr->vsmt; | |
2284 | int kvm_smt = kvmppc_smt_threads(); | |
2285 | int ret; | |
2286 | ||
2287 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2288 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2289 | "on a pseries machine"); | |
2290 | goto out; | |
2291 | } | |
2292 | if (!is_power_of_2(smp_threads)) { | |
2293 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2294 | "machine because it must be a power of 2", smp_threads); | |
2295 | goto out; | |
2296 | } | |
2297 | ||
2298 | /* Detemine the VSMT mode to use: */ | |
2299 | if (vsmt_user) { | |
2300 | if (spapr->vsmt < smp_threads) { | |
2301 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2302 | " because it must be >= threads/core (%d)", | |
2303 | spapr->vsmt, smp_threads); | |
2304 | goto out; | |
2305 | } | |
2306 | /* In this case, spapr->vsmt has been set by the command line */ | |
2307 | } else { | |
2308 | /* Choose a VSMT mode that may be higher than necessary but is | |
2309 | * likely to be compatible with hosts that don't have VSMT. */ | |
2310 | spapr->vsmt = MAX(kvm_smt, smp_threads); | |
2311 | } | |
2312 | ||
2313 | /* KVM: If necessary, set the SMT mode: */ | |
2314 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2315 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2316 | if (ret) { | |
2317 | error_setg(&local_err, | |
2318 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2319 | spapr->vsmt, ret); | |
2320 | if (!vsmt_user) { | |
2321 | error_append_hint(&local_err, "On PPC, a VM with %d threads/" | |
2322 | "core on a host with %d threads/core requires " | |
2323 | " the use of VSMT mode %d.\n", | |
2324 | smp_threads, kvm_smt, spapr->vsmt); | |
2325 | } | |
2326 | kvmppc_hint_smt_possible(&local_err); | |
2327 | goto out; | |
2328 | } | |
2329 | } | |
2330 | /* else TCG: nothing to do currently */ | |
2331 | out: | |
2332 | error_propagate(errp, local_err); | |
2333 | } | |
2334 | ||
9fdf0c29 | 2335 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2336 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2337 | { |
28e02042 | 2338 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2339 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2340 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2341 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2342 | PCIHostState *phb; |
9fdf0c29 | 2343 | int i; |
890c2b77 AK |
2344 | MemoryRegion *sysmem = get_system_memory(); |
2345 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
2346 | MemoryRegion *rma_region; |
2347 | void *rma = NULL; | |
a8170e5e | 2348 | hwaddr rma_alloc_size; |
c86c1aff | 2349 | hwaddr node0_size = spapr_node0_size(machine); |
b7d1f77a | 2350 | long load_limit, fw_size; |
39ac8455 | 2351 | char *filename; |
30f4b05b | 2352 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2353 | |
226419d6 | 2354 | msi_nonbroken = true; |
0ee2c058 | 2355 | |
d43b45e2 | 2356 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2357 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2358 | |
30f4b05b DG |
2359 | /* Check HPT resizing availability */ |
2360 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); | |
2361 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2362 | /* | |
2363 | * If the user explicitly requested a mode we should either | |
2364 | * supply it, or fail completely (which we do below). But if | |
2365 | * it's not set explicitly, we reset our mode to something | |
2366 | * that works | |
2367 | */ | |
2368 | if (resize_hpt_err) { | |
2369 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2370 | error_free(resize_hpt_err); | |
2371 | resize_hpt_err = NULL; | |
2372 | } else { | |
2373 | spapr->resize_hpt = smc->resize_hpt_default; | |
2374 | } | |
2375 | } | |
2376 | ||
2377 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2378 | ||
2379 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2380 | /* | |
2381 | * User requested HPT resize, but this host can't supply it. Bail out | |
2382 | */ | |
2383 | error_report_err(resize_hpt_err); | |
2384 | exit(1); | |
2385 | } | |
2386 | ||
354ac20a | 2387 | /* Allocate RMA if necessary */ |
658fa66b | 2388 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
2389 | |
2390 | if (rma_alloc_size == -1) { | |
730fce59 | 2391 | error_report("Unable to create RMA"); |
354ac20a DG |
2392 | exit(1); |
2393 | } | |
7f763a5d | 2394 | |
c4177479 | 2395 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 2396 | spapr->rma_size = rma_alloc_size; |
354ac20a | 2397 | } else { |
c4177479 | 2398 | spapr->rma_size = node0_size; |
7f763a5d DG |
2399 | |
2400 | /* With KVM, we don't actually know whether KVM supports an | |
2401 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2402 | * (HV KVM using VRMA), so we always assume the latter | |
2403 | * | |
2404 | * In that case, we also limit the initial allocations for RTAS | |
2405 | * etc... to 256M since we have no way to know what the VRMA size | |
2406 | * is going to be as it depends on the size of the hash table | |
2407 | * isn't determined yet. | |
2408 | */ | |
2409 | if (kvm_enabled()) { | |
2410 | spapr->vrma_adjust = 1; | |
2411 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
2412 | } | |
912acdf4 BH |
2413 | |
2414 | /* Actually we don't support unbounded RMA anymore since we | |
2415 | * added proper emulation of HV mode. The max we can get is | |
2416 | * 16G which also happens to be what we configure for PAPR | |
2417 | * mode so make sure we don't do anything bigger than that | |
2418 | */ | |
2419 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
2420 | } |
2421 | ||
c4177479 | 2422 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2423 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2424 | spapr->rma_size); | |
c4177479 AK |
2425 | exit(1); |
2426 | } | |
2427 | ||
b7d1f77a BH |
2428 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2429 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2430 | |
7b565160 | 2431 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2432 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2433 | |
dc1b5eee GK |
2434 | /* Set up containers for ibm,client-architecture-support negotiated options |
2435 | */ | |
facdb8b6 MR |
2436 | spapr->ov5 = spapr_ovec_new(); |
2437 | spapr->ov5_cas = spapr_ovec_new(); | |
2438 | ||
224245bf | 2439 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2440 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2441 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2442 | } |
2443 | ||
417ece33 | 2444 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
545d6e2b SJS |
2445 | if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { |
2446 | /* KVM and TCG always allow GTSE with radix... */ | |
9fb4541f SB |
2447 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2448 | } | |
2449 | /* ... but not with hash (currently). */ | |
417ece33 | 2450 | |
ffbb1705 MR |
2451 | /* advertise support for dedicated HP event source to guests */ |
2452 | if (spapr->use_hotplug_event_source) { | |
2453 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2454 | } | |
2455 | ||
2772cf6b DG |
2456 | /* advertise support for HPT resizing */ |
2457 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2458 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2459 | } | |
2460 | ||
9fdf0c29 | 2461 | /* init CPUs */ |
fa98fbfc SB |
2462 | spapr_set_vsmt_mode(spapr, &error_fatal); |
2463 | ||
0c86d0fd | 2464 | spapr_init_cpus(spapr); |
9fdf0c29 | 2465 | |
026bfd89 DG |
2466 | if (kvm_enabled()) { |
2467 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2468 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2469 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2470 | |
2471 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2472 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2473 | } |
2474 | ||
9fdf0c29 | 2475 | /* allocate RAM */ |
f92f5da1 | 2476 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2477 | machine->ram_size); |
f92f5da1 | 2478 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2479 | |
658fa66b AK |
2480 | if (rma_alloc_size && rma) { |
2481 | rma_region = g_new(MemoryRegion, 1); | |
2482 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
2483 | rma_alloc_size, rma); | |
2484 | vmstate_register_ram_global(rma_region); | |
2485 | memory_region_add_subregion(sysmem, 0, rma_region); | |
2486 | } | |
2487 | ||
4a1c9cf0 BR |
2488 | /* initialize hotplug memory address space */ |
2489 | if (machine->ram_size < machine->maxram_size) { | |
2490 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
2491 | /* |
2492 | * Limit the number of hotpluggable memory slots to half the number | |
2493 | * slots that KVM supports, leaving the other half for PCI and other | |
2494 | * devices. However ensure that number of slots doesn't drop below 32. | |
2495 | */ | |
2496 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2497 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2498 | |
71c9a3dd BR |
2499 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2500 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2501 | } | |
2502 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2503 | error_report("Specified number of memory slots %" |
2504 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2505 | machine->ram_slots, max_memslots); |
d54e4d76 | 2506 | exit(1); |
4a1c9cf0 BR |
2507 | } |
2508 | ||
2509 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
2510 | SPAPR_HOTPLUG_MEM_ALIGN); | |
2511 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
2512 | "hotplug-memory", hotplug_mem_size); | |
2513 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
2514 | &spapr->hotplug_memory.mr); | |
2515 | } | |
2516 | ||
224245bf DG |
2517 | if (smc->dr_lmb_enabled) { |
2518 | spapr_create_lmb_dr_connectors(spapr); | |
2519 | } | |
2520 | ||
39ac8455 | 2521 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2522 | if (!filename) { |
730fce59 | 2523 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2524 | exit(1); |
2525 | } | |
b7d1f77a | 2526 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2527 | if (spapr->rtas_size < 0) { |
2528 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2529 | exit(1); | |
2530 | } | |
b7d1f77a BH |
2531 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2532 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2533 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2534 | exit(1); |
2535 | } | |
4d8d5467 | 2536 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2537 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2538 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2539 | exit(1); |
2540 | } | |
7267c094 | 2541 | g_free(filename); |
39ac8455 | 2542 | |
ffbb1705 | 2543 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2544 | spapr_events_init(spapr); |
2545 | ||
12f42174 | 2546 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2547 | spapr_rtc_create(spapr); |
12f42174 | 2548 | |
b5cec4c5 | 2549 | /* Set up VIO bus */ |
4040ab72 DG |
2550 | spapr->vio_bus = spapr_vio_bus_init(); |
2551 | ||
277f9acf | 2552 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 2553 | if (serial_hds[i]) { |
d601fac4 | 2554 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
2555 | } |
2556 | } | |
9fdf0c29 | 2557 | |
639e8102 DG |
2558 | /* We always have at least the nvram device on VIO */ |
2559 | spapr_create_nvram(spapr); | |
2560 | ||
3384f95c | 2561 | /* Set up PCI */ |
fa28f71b AK |
2562 | spapr_pci_rtas_init(); |
2563 | ||
89dfd6e1 | 2564 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2565 | |
277f9acf | 2566 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2567 | NICInfo *nd = &nd_table[i]; |
2568 | ||
2569 | if (!nd->model) { | |
7267c094 | 2570 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
2571 | } |
2572 | ||
2573 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 2574 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2575 | } else { |
29b358f9 | 2576 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2577 | } |
2578 | } | |
2579 | ||
6e270446 | 2580 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2581 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2582 | } |
2583 | ||
f28359d8 | 2584 | /* Graphics */ |
14c6a894 | 2585 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2586 | spapr->has_graphics = true; |
c6e76503 | 2587 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2588 | } |
2589 | ||
4ee9ced9 | 2590 | if (machine->usb) { |
57040d45 TH |
2591 | if (smc->use_ohci_by_default) { |
2592 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2593 | } else { | |
2594 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2595 | } | |
c86580b8 | 2596 | |
35139a59 | 2597 | if (spapr->has_graphics) { |
c86580b8 MA |
2598 | USBBus *usb_bus = usb_bus_find(-1); |
2599 | ||
2600 | usb_create_simple(usb_bus, "usb-kbd"); | |
2601 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2602 | } |
2603 | } | |
2604 | ||
7f763a5d | 2605 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2606 | error_report( |
2607 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2608 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2609 | exit(1); |
2610 | } | |
2611 | ||
9fdf0c29 DG |
2612 | if (kernel_filename) { |
2613 | uint64_t lowaddr = 0; | |
2614 | ||
a19f7fb0 DG |
2615 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2616 | NULL, NULL, &lowaddr, NULL, 1, | |
2617 | PPC_ELF_MACHINE, 0, 0); | |
2618 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2619 | spapr->kernel_size = load_elf(kernel_filename, | |
2620 | translate_kernel_address, NULL, NULL, | |
2621 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2622 | 0, 0); | |
2623 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2624 | } |
a19f7fb0 DG |
2625 | if (spapr->kernel_size < 0) { |
2626 | error_report("error loading %s: %s", kernel_filename, | |
2627 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2628 | exit(1); |
2629 | } | |
2630 | ||
2631 | /* load initrd */ | |
2632 | if (initrd_filename) { | |
4d8d5467 BH |
2633 | /* Try to locate the initrd in the gap between the kernel |
2634 | * and the firmware. Add a bit of space just in case | |
2635 | */ | |
a19f7fb0 DG |
2636 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2637 | + 0x1ffff) & ~0xffff; | |
2638 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2639 | spapr->initrd_base, | |
2640 | load_limit | |
2641 | - spapr->initrd_base); | |
2642 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2643 | error_report("could not load initial ram disk '%s'", |
2644 | initrd_filename); | |
9fdf0c29 DG |
2645 | exit(1); |
2646 | } | |
9fdf0c29 | 2647 | } |
4d8d5467 | 2648 | } |
a3467baa | 2649 | |
8e7ea787 AF |
2650 | if (bios_name == NULL) { |
2651 | bios_name = FW_FILE_NAME; | |
2652 | } | |
2653 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2654 | if (!filename) { |
68fea5a0 | 2655 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2656 | exit(1); |
2657 | } | |
4d8d5467 | 2658 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2659 | if (fw_size <= 0) { |
2660 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2661 | exit(1); |
2662 | } | |
2663 | g_free(filename); | |
4d8d5467 | 2664 | |
28e02042 DG |
2665 | /* FIXME: Should register things through the MachineState's qdev |
2666 | * interface, this is a legacy from the sPAPREnvironment structure | |
2667 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2668 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2669 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2670 | &savevm_htab_handlers, spapr); | |
2671 | ||
5b2128d2 | 2672 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2673 | |
42043e4f | 2674 | if (kvm_enabled()) { |
3dc410ae | 2675 | /* to stop and start vmclock */ |
42043e4f LV |
2676 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2677 | &spapr->tb); | |
3dc410ae AK |
2678 | |
2679 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2680 | } |
9fdf0c29 DG |
2681 | } |
2682 | ||
135a129a AK |
2683 | static int spapr_kvm_type(const char *vm_type) |
2684 | { | |
2685 | if (!vm_type) { | |
2686 | return 0; | |
2687 | } | |
2688 | ||
2689 | if (!strcmp(vm_type, "HV")) { | |
2690 | return 1; | |
2691 | } | |
2692 | ||
2693 | if (!strcmp(vm_type, "PR")) { | |
2694 | return 2; | |
2695 | } | |
2696 | ||
2697 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2698 | exit(1); | |
2699 | } | |
2700 | ||
71461b0f | 2701 | /* |
627b84f4 | 2702 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2703 | * for the bootindex property handling. |
2704 | */ | |
2705 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2706 | DeviceState *dev) | |
2707 | { | |
2708 | #define CAST(type, obj, name) \ | |
2709 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2710 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2711 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2712 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2713 | |
2714 | if (d) { | |
2715 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2716 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2717 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2718 | ||
2719 | if (spapr) { | |
2720 | /* | |
2721 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2722 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2723 | * in the top 16 bits of the 64-bit LUN | |
2724 | */ | |
2725 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2726 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2727 | (uint64_t)id << 48); | |
2728 | } else if (virtio) { | |
2729 | /* | |
2730 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2731 | * in the top 32 bits of the 64-bit LUN | |
2732 | * Note: the quote above is from SLOF and it is wrong, | |
2733 | * the actual binding is: | |
2734 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2735 | */ | |
2736 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
2737 | if (d->lun >= 256) { |
2738 | /* Use the LUN "flat space addressing method" */ | |
2739 | id |= 0x4000; | |
2740 | } | |
71461b0f AK |
2741 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
2742 | (uint64_t)id << 32); | |
2743 | } else if (usb) { | |
2744 | /* | |
2745 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2746 | * in the top 32 bits of the 64-bit LUN | |
2747 | */ | |
2748 | unsigned usb_port = atoi(usb->port->path); | |
2749 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2750 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2751 | (uint64_t)id << 32); | |
2752 | } | |
2753 | } | |
2754 | ||
b99260eb TH |
2755 | /* |
2756 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2757 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2758 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2759 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2760 | */ | |
2761 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2762 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2763 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2764 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2765 | } | |
2766 | } | |
2767 | ||
71461b0f AK |
2768 | if (phb) { |
2769 | /* Replace "pci" with "pci@800000020000000" */ | |
2770 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2771 | } | |
2772 | ||
c4e13492 FF |
2773 | if (vsc) { |
2774 | /* Same logic as virtio above */ | |
2775 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2776 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2777 | } | |
2778 | ||
4871dd4c TH |
2779 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2780 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2781 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2782 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2783 | } | |
2784 | ||
71461b0f AK |
2785 | return NULL; |
2786 | } | |
2787 | ||
23825581 EH |
2788 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2789 | { | |
28e02042 | 2790 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2791 | |
28e02042 | 2792 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2793 | } |
2794 | ||
2795 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2796 | { | |
28e02042 | 2797 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2798 | |
28e02042 DG |
2799 | g_free(spapr->kvm_type); |
2800 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2801 | } |
2802 | ||
f6229214 MR |
2803 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2804 | { | |
2805 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2806 | ||
2807 | return spapr->use_hotplug_event_source; | |
2808 | } | |
2809 | ||
2810 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2811 | Error **errp) | |
2812 | { | |
2813 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2814 | ||
2815 | spapr->use_hotplug_event_source = value; | |
2816 | } | |
2817 | ||
30f4b05b DG |
2818 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2819 | { | |
2820 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2821 | ||
2822 | switch (spapr->resize_hpt) { | |
2823 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2824 | return g_strdup("default"); | |
2825 | case SPAPR_RESIZE_HPT_DISABLED: | |
2826 | return g_strdup("disabled"); | |
2827 | case SPAPR_RESIZE_HPT_ENABLED: | |
2828 | return g_strdup("enabled"); | |
2829 | case SPAPR_RESIZE_HPT_REQUIRED: | |
2830 | return g_strdup("required"); | |
2831 | } | |
2832 | g_assert_not_reached(); | |
2833 | } | |
2834 | ||
2835 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
2836 | { | |
2837 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2838 | ||
2839 | if (strcmp(value, "default") == 0) { | |
2840 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
2841 | } else if (strcmp(value, "disabled") == 0) { | |
2842 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2843 | } else if (strcmp(value, "enabled") == 0) { | |
2844 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
2845 | } else if (strcmp(value, "required") == 0) { | |
2846 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
2847 | } else { | |
2848 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
2849 | } | |
2850 | } | |
2851 | ||
fa98fbfc SB |
2852 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
2853 | void *opaque, Error **errp) | |
2854 | { | |
2855 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2856 | } | |
2857 | ||
2858 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, | |
2859 | void *opaque, Error **errp) | |
2860 | { | |
2861 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2862 | } | |
2863 | ||
bcb5ce08 | 2864 | static void spapr_instance_init(Object *obj) |
23825581 | 2865 | { |
715c5407 DG |
2866 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2867 | ||
2868 | spapr->htab_fd = -1; | |
f6229214 | 2869 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2870 | object_property_add_str(obj, "kvm-type", |
2871 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2872 | object_property_set_description(obj, "kvm-type", |
2873 | "Specifies the KVM virtualization mode (HV, PR)", | |
2874 | NULL); | |
f6229214 MR |
2875 | object_property_add_bool(obj, "modern-hotplug-events", |
2876 | spapr_get_modern_hotplug_events, | |
2877 | spapr_set_modern_hotplug_events, | |
2878 | NULL); | |
2879 | object_property_set_description(obj, "modern-hotplug-events", | |
2880 | "Use dedicated hotplug event mechanism in" | |
2881 | " place of standard EPOW events when possible" | |
2882 | " (required for memory hot-unplug support)", | |
2883 | NULL); | |
7843c0d6 DG |
2884 | |
2885 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, | |
2886 | "Maximum permitted CPU compatibility mode", | |
2887 | &error_fatal); | |
30f4b05b DG |
2888 | |
2889 | object_property_add_str(obj, "resize-hpt", | |
2890 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
2891 | object_property_set_description(obj, "resize-hpt", | |
2892 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
2893 | NULL); | |
fa98fbfc SB |
2894 | object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, |
2895 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); | |
2896 | object_property_set_description(obj, "vsmt", | |
2897 | "Virtual SMT: KVM behaves as if this were" | |
2898 | " the host's SMT mode", &error_abort); | |
23825581 EH |
2899 | } |
2900 | ||
87bbdd9c DG |
2901 | static void spapr_machine_finalizefn(Object *obj) |
2902 | { | |
2903 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2904 | ||
2905 | g_free(spapr->kvm_type); | |
2906 | } | |
2907 | ||
1c7ad77e | 2908 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 2909 | { |
34316482 AK |
2910 | cpu_synchronize_state(cs); |
2911 | ppc_cpu_do_system_reset(cs); | |
2912 | } | |
2913 | ||
2914 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2915 | { | |
2916 | CPUState *cs; | |
2917 | ||
2918 | CPU_FOREACH(cs) { | |
1c7ad77e | 2919 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
2920 | } |
2921 | } | |
2922 | ||
79b78a6b MR |
2923 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2924 | uint32_t node, bool dedicated_hp_event_source, | |
2925 | Error **errp) | |
c20d332a BR |
2926 | { |
2927 | sPAPRDRConnector *drc; | |
c20d332a BR |
2928 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
2929 | int i, fdt_offset, fdt_size; | |
2930 | void *fdt; | |
79b78a6b | 2931 | uint64_t addr = addr_start; |
94fd9cba | 2932 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 2933 | Error *local_err = NULL; |
c20d332a | 2934 | |
c20d332a | 2935 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
2936 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2937 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
2938 | g_assert(drc); |
2939 | ||
2940 | fdt = create_device_tree(&fdt_size); | |
2941 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2942 | SPAPR_MEMORY_BLOCK_SIZE); | |
2943 | ||
160bb678 GK |
2944 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
2945 | if (local_err) { | |
2946 | while (addr > addr_start) { | |
2947 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
2948 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
2949 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 2950 | spapr_drc_detach(drc); |
160bb678 GK |
2951 | } |
2952 | g_free(fdt); | |
2953 | error_propagate(errp, local_err); | |
2954 | return; | |
2955 | } | |
94fd9cba LV |
2956 | if (!hotplugged) { |
2957 | spapr_drc_reset(drc); | |
2958 | } | |
c20d332a BR |
2959 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2960 | } | |
5dd5238c JD |
2961 | /* send hotplug notification to the |
2962 | * guest only in case of hotplugged memory | |
2963 | */ | |
94fd9cba | 2964 | if (hotplugged) { |
79b78a6b | 2965 | if (dedicated_hp_event_source) { |
fbf55397 DG |
2966 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2967 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
2968 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
2969 | nr_lmbs, | |
0b55aa91 | 2970 | spapr_drc_index(drc)); |
79b78a6b MR |
2971 | } else { |
2972 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2973 | nr_lmbs); | |
2974 | } | |
5dd5238c | 2975 | } |
c20d332a BR |
2976 | } |
2977 | ||
2978 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2979 | uint32_t node, Error **errp) | |
2980 | { | |
2981 | Error *local_err = NULL; | |
2982 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2983 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2984 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
2985 | MemoryRegion *mr; |
2986 | uint64_t align, size, addr; | |
2987 | ||
2988 | mr = ddc->get_memory_region(dimm, &local_err); | |
2989 | if (local_err) { | |
2990 | goto out; | |
2991 | } | |
2992 | align = memory_region_get_alignment(mr); | |
2993 | size = memory_region_size(mr); | |
df587133 | 2994 | |
d6a9b0b8 | 2995 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2996 | if (local_err) { |
2997 | goto out; | |
2998 | } | |
2999 | ||
9ed442b8 MAL |
3000 | addr = object_property_get_uint(OBJECT(dimm), |
3001 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 3002 | if (local_err) { |
160bb678 | 3003 | goto out_unplug; |
c20d332a BR |
3004 | } |
3005 | ||
79b78a6b MR |
3006 | spapr_add_lmbs(dev, addr, size, node, |
3007 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
3008 | &local_err); |
3009 | if (local_err) { | |
3010 | goto out_unplug; | |
3011 | } | |
3012 | ||
3013 | return; | |
c20d332a | 3014 | |
160bb678 GK |
3015 | out_unplug: |
3016 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
c20d332a BR |
3017 | out: |
3018 | error_propagate(errp, local_err); | |
3019 | } | |
3020 | ||
c871bc70 LV |
3021 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3022 | Error **errp) | |
3023 | { | |
3024 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3025 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3026 | MemoryRegion *mr; |
3027 | uint64_t size; | |
c871bc70 LV |
3028 | char *mem_dev; |
3029 | ||
04790978 TH |
3030 | mr = ddc->get_memory_region(dimm, errp); |
3031 | if (!mr) { | |
3032 | return; | |
3033 | } | |
3034 | size = memory_region_size(mr); | |
3035 | ||
c871bc70 LV |
3036 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3037 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
3038 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
3039 | return; | |
3040 | } | |
3041 | ||
3042 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
3043 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
3044 | error_setg(errp, "Memory backend has bad page size. " | |
3045 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 3046 | goto out; |
c871bc70 | 3047 | } |
8a9e0e7b GK |
3048 | |
3049 | out: | |
3050 | g_free(mem_dev); | |
c871bc70 LV |
3051 | } |
3052 | ||
0cffce56 DG |
3053 | struct sPAPRDIMMState { |
3054 | PCDIMMDevice *dimm; | |
cf632463 | 3055 | uint32_t nr_lmbs; |
0cffce56 DG |
3056 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
3057 | }; | |
3058 | ||
3059 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
3060 | PCDIMMDevice *dimm) | |
3061 | { | |
3062 | sPAPRDIMMState *dimm_state = NULL; | |
3063 | ||
3064 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3065 | if (dimm_state->dimm == dimm) { | |
3066 | break; | |
3067 | } | |
3068 | } | |
3069 | return dimm_state; | |
3070 | } | |
3071 | ||
8d5981c4 BR |
3072 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, |
3073 | uint32_t nr_lmbs, | |
3074 | PCDIMMDevice *dimm) | |
0cffce56 | 3075 | { |
8d5981c4 BR |
3076 | sPAPRDIMMState *ds = NULL; |
3077 | ||
3078 | /* | |
3079 | * If this request is for a DIMM whose removal had failed earlier | |
3080 | * (due to guest's refusal to remove the LMBs), we would have this | |
3081 | * dimm already in the pending_dimm_unplugs list. In that | |
3082 | * case don't add again. | |
3083 | */ | |
3084 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3085 | if (!ds) { | |
3086 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
3087 | ds->nr_lmbs = nr_lmbs; | |
3088 | ds->dimm = dimm; | |
3089 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3090 | } | |
3091 | return ds; | |
0cffce56 DG |
3092 | } |
3093 | ||
3094 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
3095 | sPAPRDIMMState *dimm_state) | |
3096 | { | |
3097 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3098 | g_free(dimm_state); | |
3099 | } | |
cf632463 | 3100 | |
16ee9980 DHB |
3101 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
3102 | PCDIMMDevice *dimm) | |
3103 | { | |
3104 | sPAPRDRConnector *drc; | |
3105 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3106 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
16ee9980 DHB |
3107 | uint64_t size = memory_region_size(mr); |
3108 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3109 | uint32_t avail_lmbs = 0; | |
3110 | uint64_t addr_start, addr; | |
3111 | int i; | |
16ee9980 DHB |
3112 | |
3113 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3114 | &error_abort); | |
3115 | ||
3116 | addr = addr_start; | |
3117 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3118 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3119 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3120 | g_assert(drc); |
454b580a | 3121 | if (drc->dev) { |
16ee9980 DHB |
3122 | avail_lmbs++; |
3123 | } | |
3124 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3125 | } | |
3126 | ||
8d5981c4 | 3127 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3128 | } |
3129 | ||
31834723 DHB |
3130 | /* Callback to be called during DRC release. */ |
3131 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3132 | { |
765d1bdd DG |
3133 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); |
3134 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3135 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3136 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
0cffce56 | 3137 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 3138 | |
16ee9980 DHB |
3139 | /* This information will get lost if a migration occurs |
3140 | * during the unplug process. In this case recover it. */ | |
3141 | if (ds == NULL) { | |
3142 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3143 | g_assert(ds); |
454b580a DG |
3144 | /* The DRC being examined by the caller at least must be counted */ |
3145 | g_assert(ds->nr_lmbs); | |
3146 | } | |
3147 | ||
3148 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3149 | return; |
3150 | } | |
3151 | ||
cf632463 BR |
3152 | /* |
3153 | * Now that all the LMBs have been removed by the guest, call the | |
3154 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
3155 | */ | |
765d1bdd | 3156 | pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); |
cf632463 | 3157 | object_unparent(OBJECT(dev)); |
2a129767 | 3158 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3159 | } |
3160 | ||
3161 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3162 | DeviceState *dev, Error **errp) | |
3163 | { | |
0cffce56 | 3164 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3165 | Error *local_err = NULL; |
3166 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3167 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3168 | MemoryRegion *mr; |
3169 | uint32_t nr_lmbs; | |
3170 | uint64_t size, addr_start, addr; | |
0cffce56 DG |
3171 | int i; |
3172 | sPAPRDRConnector *drc; | |
04790978 TH |
3173 | |
3174 | mr = ddc->get_memory_region(dimm, &local_err); | |
3175 | if (local_err) { | |
3176 | goto out; | |
3177 | } | |
3178 | size = memory_region_size(mr); | |
3179 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3180 | ||
9ed442b8 | 3181 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3182 | &local_err); |
cf632463 BR |
3183 | if (local_err) { |
3184 | goto out; | |
3185 | } | |
3186 | ||
2a129767 DHB |
3187 | /* |
3188 | * An existing pending dimm state for this DIMM means that there is an | |
3189 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3190 | * callback to complete the job (BQL can't cover that far). In this case, | |
3191 | * bail out to avoid detaching DRCs that were already released. | |
3192 | */ | |
3193 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3194 | error_setg(&local_err, | |
3195 | "Memory unplug already in progress for device %s", | |
3196 | dev->id); | |
3197 | goto out; | |
3198 | } | |
3199 | ||
8d5981c4 | 3200 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3201 | |
3202 | addr = addr_start; | |
3203 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3204 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3205 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3206 | g_assert(drc); |
3207 | ||
a8dc47fd | 3208 | spapr_drc_detach(drc); |
0cffce56 DG |
3209 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3210 | } | |
3211 | ||
fbf55397 DG |
3212 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3213 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3214 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3215 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3216 | out: |
3217 | error_propagate(errp, local_err); | |
3218 | } | |
3219 | ||
04d0ffbd GK |
3220 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
3221 | sPAPRMachineState *spapr) | |
af81cf32 BR |
3222 | { |
3223 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3224 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2e886fb3 | 3225 | int id = spapr_vcpu_id(cpu); |
af81cf32 BR |
3226 | void *fdt; |
3227 | int offset, fdt_size; | |
3228 | char *nodename; | |
3229 | ||
3230 | fdt = create_device_tree(&fdt_size); | |
3231 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3232 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3233 | ||
3234 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
3235 | g_free(nodename); | |
3236 | ||
3237 | *fdt_offset = offset; | |
3238 | return fdt; | |
3239 | } | |
3240 | ||
765d1bdd DG |
3241 | /* Callback to be called during DRC release. */ |
3242 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3243 | { |
765d1bdd | 3244 | MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); |
46f7afa3 | 3245 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3246 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3247 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3248 | |
46f7afa3 GK |
3249 | if (smc->pre_2_10_has_unused_icps) { |
3250 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
46f7afa3 GK |
3251 | int i; |
3252 | ||
3253 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3254 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3255 | |
3256 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3257 | } | |
3258 | } | |
3259 | ||
07572c06 | 3260 | assert(core_slot); |
535455fd | 3261 | core_slot->cpu = NULL; |
ff9006dd IM |
3262 | object_unparent(OBJECT(dev)); |
3263 | } | |
3264 | ||
115debf2 IM |
3265 | static |
3266 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3267 | Error **errp) | |
ff9006dd | 3268 | { |
535455fd IM |
3269 | int index; |
3270 | sPAPRDRConnector *drc; | |
535455fd IM |
3271 | CPUCore *cc = CPU_CORE(dev); |
3272 | int smt = kvmppc_smt_threads(); | |
ff9006dd | 3273 | |
535455fd IM |
3274 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3275 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3276 | cc->core_id); | |
3277 | return; | |
3278 | } | |
ff9006dd IM |
3279 | if (index == 0) { |
3280 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3281 | return; | |
3282 | } | |
3283 | ||
fbf55397 | 3284 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd IM |
3285 | g_assert(drc); |
3286 | ||
a8dc47fd | 3287 | spapr_drc_detach(drc); |
ff9006dd IM |
3288 | |
3289 | spapr_hotplug_req_remove_by_index(drc); | |
3290 | } | |
3291 | ||
3292 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3293 | Error **errp) | |
3294 | { | |
3295 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3296 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3297 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3298 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3299 | CPUCore *cc = CPU_CORE(dev); | |
94ad93bd | 3300 | CPUState *cs = CPU(core->threads[0]); |
ff9006dd IM |
3301 | sPAPRDRConnector *drc; |
3302 | Error *local_err = NULL; | |
ff9006dd | 3303 | int smt = kvmppc_smt_threads(); |
535455fd IM |
3304 | CPUArchId *core_slot; |
3305 | int index; | |
94fd9cba | 3306 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3307 | |
535455fd IM |
3308 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3309 | if (!core_slot) { | |
3310 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3311 | cc->core_id); | |
3312 | return; | |
3313 | } | |
fbf55397 | 3314 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd | 3315 | |
c5514d0e | 3316 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3317 | |
ff9006dd | 3318 | if (drc) { |
e49c63d5 GK |
3319 | void *fdt; |
3320 | int fdt_offset; | |
3321 | ||
3322 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3323 | ||
5c1da812 | 3324 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3325 | if (local_err) { |
3326 | g_free(fdt); | |
ff9006dd IM |
3327 | error_propagate(errp, local_err); |
3328 | return; | |
3329 | } | |
ff9006dd | 3330 | |
94fd9cba LV |
3331 | if (hotplugged) { |
3332 | /* | |
3333 | * Send hotplug notification interrupt to the guest only | |
3334 | * in case of hotplugged CPUs. | |
3335 | */ | |
3336 | spapr_hotplug_req_add_by_index(drc); | |
3337 | } else { | |
3338 | spapr_drc_reset(drc); | |
3339 | } | |
ff9006dd | 3340 | } |
94fd9cba | 3341 | |
535455fd | 3342 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3343 | |
3344 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 GK |
3345 | int i; |
3346 | ||
3347 | for (i = 0; i < cc->nr_threads; i++) { | |
3348 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); | |
46f7afa3 | 3349 | |
94ad93bd | 3350 | cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3351 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3352 | } | |
3353 | } | |
ff9006dd IM |
3354 | } |
3355 | ||
3356 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3357 | Error **errp) | |
3358 | { | |
3359 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3360 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3361 | Error *local_err = NULL; |
3362 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3363 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3364 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3365 | CPUArchId *core_slot; |
3366 | int index; | |
ff9006dd | 3367 | |
c5514d0e | 3368 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3369 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3370 | goto out; | |
3371 | } | |
3372 | ||
3373 | if (strcmp(base_core_type, type)) { | |
3374 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3375 | goto out; | |
3376 | } | |
3377 | ||
3378 | if (cc->core_id % smp_threads) { | |
3379 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3380 | goto out; | |
3381 | } | |
3382 | ||
459264ef DG |
3383 | /* |
3384 | * In general we should have homogeneous threads-per-core, but old | |
3385 | * (pre hotplug support) machine types allow the last core to have | |
3386 | * reduced threads as a compatibility hack for when we allowed | |
3387 | * total vcpus not a multiple of threads-per-core. | |
3388 | */ | |
3389 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3390 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3391 | cc->nr_threads, smp_threads); |
df8658de | 3392 | goto out; |
8149e299 DG |
3393 | } |
3394 | ||
535455fd IM |
3395 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3396 | if (!core_slot) { | |
ff9006dd IM |
3397 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3398 | goto out; | |
3399 | } | |
3400 | ||
535455fd | 3401 | if (core_slot->cpu) { |
ff9006dd IM |
3402 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3403 | goto out; | |
3404 | } | |
3405 | ||
a0ceb640 | 3406 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3407 | |
ff9006dd | 3408 | out: |
ff9006dd IM |
3409 | error_propagate(errp, local_err); |
3410 | } | |
3411 | ||
c20d332a BR |
3412 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3413 | DeviceState *dev, Error **errp) | |
3414 | { | |
c86c1aff DHB |
3415 | MachineState *ms = MACHINE(hotplug_dev); |
3416 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); | |
c20d332a BR |
3417 | |
3418 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 3419 | int node; |
c20d332a BR |
3420 | |
3421 | if (!smc->dr_lmb_enabled) { | |
3422 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3423 | return; | |
3424 | } | |
9ed442b8 | 3425 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); |
c20d332a BR |
3426 | if (*errp) { |
3427 | return; | |
3428 | } | |
1a5512bb GA |
3429 | if (node < 0 || node >= MAX_NODES) { |
3430 | error_setg(errp, "Invaild node %d", node); | |
3431 | return; | |
3432 | } | |
c20d332a | 3433 | |
b556854b BR |
3434 | /* |
3435 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
3436 | * memory-less node, but instead will silently add the memory | |
3437 | * to the first node that has some memory. This causes two | |
3438 | * unexpected behaviours for the user. | |
3439 | * | |
3440 | * - Memory gets hotplugged to a different node than what the user | |
3441 | * specified. | |
3442 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
3443 | * to memory-less node, a reboot will set things accordingly | |
3444 | * and the previously hotplugged memory now ends in the right node. | |
3445 | * This appears as if some memory moved from one node to another. | |
3446 | * | |
3447 | * So until kernel starts supporting memory hotplug to memory-less | |
3448 | * nodes, just prevent such attempts upfront in QEMU. | |
3449 | */ | |
3450 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
3451 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
3452 | node); | |
3453 | return; | |
3454 | } | |
3455 | ||
c20d332a | 3456 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
3457 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3458 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3459 | } |
3460 | } | |
3461 | ||
cf632463 BR |
3462 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3463 | DeviceState *dev, Error **errp) | |
3464 | { | |
c86c1aff DHB |
3465 | sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3466 | MachineClass *mc = MACHINE_GET_CLASS(sms); | |
cf632463 BR |
3467 | |
3468 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3469 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3470 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3471 | } else { | |
3472 | /* NOTE: this means there is a window after guest reset, prior to | |
3473 | * CAS negotiation, where unplug requests will fail due to the | |
3474 | * capability not being detected yet. This is a bit different than | |
3475 | * the case with PCI unplug, where the events will be queued and | |
3476 | * eventually handled by the guest after boot | |
3477 | */ | |
3478 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3479 | } | |
6f4b5c3e | 3480 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3481 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3482 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3483 | return; | |
3484 | } | |
115debf2 | 3485 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3486 | } |
3487 | } | |
3488 | ||
94a94e4c BR |
3489 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3490 | DeviceState *dev, Error **errp) | |
3491 | { | |
c871bc70 LV |
3492 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3493 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3494 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3495 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3496 | } | |
3497 | } | |
3498 | ||
7ebaf795 BR |
3499 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3500 | DeviceState *dev) | |
c20d332a | 3501 | { |
94a94e4c BR |
3502 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3503 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3504 | return HOTPLUG_HANDLER(machine); |
3505 | } | |
3506 | return NULL; | |
3507 | } | |
3508 | ||
ea089eeb IM |
3509 | static CpuInstanceProperties |
3510 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3511 | { |
ea089eeb IM |
3512 | CPUArchId *core_slot; |
3513 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3514 | ||
3515 | /* make sure possible_cpu are intialized */ | |
3516 | mc->possible_cpu_arch_ids(machine); | |
3517 | /* get CPU core slot containing thread that matches cpu_index */ | |
3518 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3519 | assert(core_slot); | |
3520 | return core_slot->props; | |
20bb648d DG |
3521 | } |
3522 | ||
79e07936 IM |
3523 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
3524 | { | |
3525 | return idx / smp_cores % nb_numa_nodes; | |
3526 | } | |
3527 | ||
535455fd IM |
3528 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3529 | { | |
3530 | int i; | |
3531 | int spapr_max_cores = max_cpus / smp_threads; | |
3532 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3533 | ||
c5514d0e | 3534 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3535 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3536 | } | |
3537 | if (machine->possible_cpus) { | |
3538 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3539 | return machine->possible_cpus; | |
3540 | } | |
3541 | ||
3542 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
3543 | sizeof(CPUArchId) * spapr_max_cores); | |
3544 | machine->possible_cpus->len = spapr_max_cores; | |
3545 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3546 | int core_id = i * smp_threads; | |
3547 | ||
f2d672c2 | 3548 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3549 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3550 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3551 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
3552 | } |
3553 | return machine->possible_cpus; | |
3554 | } | |
3555 | ||
6737d9ad | 3556 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3557 | uint64_t *buid, hwaddr *pio, |
3558 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3559 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3560 | { | |
357d1e3b DG |
3561 | /* |
3562 | * New-style PHB window placement. | |
3563 | * | |
3564 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3565 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3566 | * windows. | |
3567 | * | |
3568 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3569 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3570 | * | |
3571 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3572 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3573 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3574 | * 1TiB 64-bit MMIO windows for each PHB. | |
3575 | */ | |
6737d9ad | 3576 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3577 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3578 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3579 | int i; |
3580 | ||
357d1e3b DG |
3581 | /* Sanity check natural alignments */ |
3582 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3583 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3584 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3585 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3586 | /* Sanity check bounds */ | |
25e6a118 MT |
3587 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3588 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3589 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3590 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3591 | ||
3592 | if (index >= SPAPR_MAX_PHBS) { | |
3593 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3594 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3595 | return; |
3596 | } | |
3597 | ||
3598 | *buid = base_buid + index; | |
3599 | for (i = 0; i < n_dma; ++i) { | |
3600 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3601 | } | |
3602 | ||
357d1e3b DG |
3603 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3604 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3605 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3606 | } |
3607 | ||
7844e12b CLG |
3608 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3609 | { | |
3610 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3611 | ||
3612 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3613 | } | |
3614 | ||
3615 | static void spapr_ics_resend(XICSFabric *dev) | |
3616 | { | |
3617 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3618 | ||
3619 | ics_resend(spapr->ics); | |
3620 | } | |
3621 | ||
81210c20 | 3622 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 3623 | { |
2e886fb3 | 3624 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 3625 | |
5bc8d26d | 3626 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3627 | } |
3628 | ||
60c6823b CLG |
3629 | #define ICS_IRQ_FREE(ics, srcno) \ |
3630 | (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) | |
3631 | ||
3632 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) | |
3633 | { | |
3634 | int first, i; | |
3635 | ||
3636 | for (first = 0; first < ics->nr_irqs; first += alignnum) { | |
3637 | if (num > (ics->nr_irqs - first)) { | |
3638 | return -1; | |
3639 | } | |
3640 | for (i = first; i < first + num; ++i) { | |
3641 | if (!ICS_IRQ_FREE(ics, i)) { | |
3642 | break; | |
3643 | } | |
3644 | } | |
3645 | if (i == (first + num)) { | |
3646 | return first; | |
3647 | } | |
3648 | } | |
3649 | ||
3650 | return -1; | |
3651 | } | |
3652 | ||
9e7dc5fc CLG |
3653 | /* |
3654 | * Allocate the IRQ number and set the IRQ type, LSI or MSI | |
3655 | */ | |
3656 | static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) | |
3657 | { | |
3658 | ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); | |
3659 | } | |
3660 | ||
60c6823b CLG |
3661 | int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, |
3662 | Error **errp) | |
3663 | { | |
3664 | ICSState *ics = spapr->ics; | |
3665 | int irq; | |
3666 | ||
3667 | if (!ics) { | |
3668 | return -1; | |
3669 | } | |
3670 | if (irq_hint) { | |
3671 | if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { | |
3672 | error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); | |
3673 | return -1; | |
3674 | } | |
3675 | irq = irq_hint; | |
3676 | } else { | |
3677 | irq = ics_find_free_block(ics, 1, 1); | |
3678 | if (irq < 0) { | |
3679 | error_setg(errp, "can't allocate IRQ: no IRQ left"); | |
3680 | return -1; | |
3681 | } | |
3682 | irq += ics->offset; | |
3683 | } | |
3684 | ||
9e7dc5fc | 3685 | spapr_irq_set_lsi(spapr, irq, lsi); |
60c6823b CLG |
3686 | trace_spapr_irq_alloc(irq); |
3687 | ||
3688 | return irq; | |
3689 | } | |
3690 | ||
3691 | /* | |
3692 | * Allocate block of consecutive IRQs, and return the number of the first IRQ in | |
3693 | * the block. If align==true, aligns the first IRQ number to num. | |
3694 | */ | |
3695 | int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, | |
3696 | bool align, Error **errp) | |
3697 | { | |
3698 | ICSState *ics = spapr->ics; | |
3699 | int i, first = -1; | |
3700 | ||
3701 | if (!ics) { | |
3702 | return -1; | |
3703 | } | |
3704 | ||
3705 | /* | |
3706 | * MSIMesage::data is used for storing VIRQ so | |
3707 | * it has to be aligned to num to support multiple | |
3708 | * MSI vectors. MSI-X is not affected by this. | |
3709 | * The hint is used for the first IRQ, the rest should | |
3710 | * be allocated continuously. | |
3711 | */ | |
3712 | if (align) { | |
3713 | assert((num == 1) || (num == 2) || (num == 4) || | |
3714 | (num == 8) || (num == 16) || (num == 32)); | |
3715 | first = ics_find_free_block(ics, num, num); | |
3716 | } else { | |
3717 | first = ics_find_free_block(ics, num, 1); | |
3718 | } | |
3719 | if (first < 0) { | |
3720 | error_setg(errp, "can't find a free %d-IRQ block", num); | |
3721 | return -1; | |
3722 | } | |
3723 | ||
9e7dc5fc | 3724 | first += ics->offset; |
60c6823b | 3725 | for (i = first; i < first + num; ++i) { |
9e7dc5fc | 3726 | spapr_irq_set_lsi(spapr, i, lsi); |
60c6823b | 3727 | } |
60c6823b CLG |
3728 | |
3729 | trace_spapr_irq_alloc_block(first, num, lsi, align); | |
3730 | ||
3731 | return first; | |
3732 | } | |
3733 | ||
3734 | void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) | |
3735 | { | |
3736 | ICSState *ics = spapr->ics; | |
3737 | int srcno = irq - ics->offset; | |
3738 | int i; | |
3739 | ||
3740 | if (ics_valid_irq(ics, irq)) { | |
3741 | trace_spapr_irq_free(0, irq, num); | |
3742 | for (i = srcno; i < srcno + num; ++i) { | |
3743 | if (ICS_IRQ_FREE(ics, i)) { | |
3744 | trace_spapr_irq_free_warn(0, i + ics->offset); | |
3745 | } | |
3746 | memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); | |
3747 | } | |
3748 | } | |
3749 | } | |
3750 | ||
77183755 CLG |
3751 | qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) |
3752 | { | |
3753 | ICSState *ics = spapr->ics; | |
3754 | ||
3755 | if (ics_valid_irq(ics, irq)) { | |
3756 | return ics->qirqs[irq - ics->offset]; | |
3757 | } | |
3758 | ||
3759 | return NULL; | |
3760 | } | |
3761 | ||
6449da45 CLG |
3762 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3763 | Monitor *mon) | |
3764 | { | |
3765 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3766 | CPUState *cs; |
3767 | ||
3768 | CPU_FOREACH(cs) { | |
3769 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3770 | |
5bc8d26d | 3771 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3772 | } |
3773 | ||
3774 | ics_pic_print_info(spapr->ics, mon); | |
3775 | } | |
3776 | ||
2e886fb3 SB |
3777 | int spapr_vcpu_id(PowerPCCPU *cpu) |
3778 | { | |
3779 | CPUState *cs = CPU(cpu); | |
3780 | ||
3781 | if (kvm_enabled()) { | |
3782 | return kvm_arch_vcpu_id(cs); | |
3783 | } else { | |
3784 | return cs->cpu_index; | |
3785 | } | |
3786 | } | |
3787 | ||
3788 | PowerPCCPU *spapr_find_cpu(int vcpu_id) | |
3789 | { | |
3790 | CPUState *cs; | |
3791 | ||
3792 | CPU_FOREACH(cs) { | |
3793 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3794 | ||
3795 | if (spapr_vcpu_id(cpu) == vcpu_id) { | |
3796 | return cpu; | |
3797 | } | |
3798 | } | |
3799 | ||
3800 | return NULL; | |
3801 | } | |
3802 | ||
29ee3247 AK |
3803 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3804 | { | |
3805 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3806 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3807 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3808 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3809 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3810 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3811 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3812 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3813 | |
0eb9054c | 3814 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3815 | |
3816 | /* | |
3817 | * We set up the default / latest behaviour here. The class_init | |
3818 | * functions for the specific versioned machine types can override | |
3819 | * these details for backwards compatibility | |
3820 | */ | |
bcb5ce08 DG |
3821 | mc->init = spapr_machine_init; |
3822 | mc->reset = spapr_machine_reset; | |
958db90c | 3823 | mc->block_default_type = IF_SCSI; |
6244bb7e | 3824 | mc->max_cpus = 1024; |
958db90c | 3825 | mc->no_parallel = 1; |
5b2128d2 | 3826 | mc->default_boot_order = ""; |
a34944fe | 3827 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 3828 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 3829 | mc->has_dynamic_sysbus = true; |
e4024630 | 3830 | mc->pci_allow_0_address = true; |
7ebaf795 | 3831 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3832 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 3833 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 3834 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 3835 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 3836 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3837 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 3838 | |
fc9f38c3 | 3839 | smc->dr_lmb_enabled = true; |
2e9c10eb | 3840 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
c5514d0e | 3841 | mc->has_hotpluggable_cpus = true; |
52b81ab5 | 3842 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 3843 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3844 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3845 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3846 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3847 | vhc->hpt_mask = spapr_hpt_mask; |
3848 | vhc->map_hptes = spapr_map_hptes; | |
3849 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3850 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3851 | vhc->get_patbe = spapr_get_patbe; |
1ec26c75 | 3852 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
7844e12b CLG |
3853 | xic->ics_get = spapr_ics_get; |
3854 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3855 | xic->icp_get = spapr_icp_get; |
6449da45 | 3856 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3857 | /* Force NUMA node memory size to be a multiple of |
3858 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3859 | * in which LMBs are represented and hot-added | |
3860 | */ | |
3861 | mc->numa_mem_align_shift = 28; | |
33face6b | 3862 | |
4e5fe368 SJS |
3863 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
3864 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; | |
3865 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; | |
33face6b | 3866 | spapr_caps_add_properties(smc, &error_abort); |
29ee3247 AK |
3867 | } |
3868 | ||
3869 | static const TypeInfo spapr_machine_info = { | |
3870 | .name = TYPE_SPAPR_MACHINE, | |
3871 | .parent = TYPE_MACHINE, | |
4aee7362 | 3872 | .abstract = true, |
6ca1502e | 3873 | .instance_size = sizeof(sPAPRMachineState), |
bcb5ce08 | 3874 | .instance_init = spapr_instance_init, |
87bbdd9c | 3875 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3876 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3877 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3878 | .interfaces = (InterfaceInfo[]) { |
3879 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3880 | { TYPE_NMI }, |
c20d332a | 3881 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3882 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3883 | { TYPE_XICS_FABRIC }, |
6449da45 | 3884 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3885 | { } |
3886 | }, | |
29ee3247 AK |
3887 | }; |
3888 | ||
fccbc785 | 3889 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3890 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3891 | void *data) \ | |
3892 | { \ | |
3893 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3894 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3895 | if (latest) { \ |
3896 | mc->alias = "pseries"; \ | |
3897 | mc->is_default = 1; \ | |
3898 | } \ | |
5013c547 DG |
3899 | } \ |
3900 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
3901 | { \ | |
3902 | MachineState *machine = MACHINE(obj); \ | |
3903 | spapr_machine_##suffix##_instance_options(machine); \ | |
3904 | } \ | |
3905 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
3906 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3907 | .parent = TYPE_SPAPR_MACHINE, \ | |
3908 | .class_init = spapr_machine_##suffix##_class_init, \ | |
3909 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
3910 | }; \ | |
3911 | static void spapr_machine_register_##suffix(void) \ | |
3912 | { \ | |
3913 | type_register(&spapr_machine_##suffix##_info); \ | |
3914 | } \ | |
0e6aac87 | 3915 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3916 | |
2b615412 DG |
3917 | /* |
3918 | * pseries-2.12 | |
3919 | */ | |
3920 | static void spapr_machine_2_12_instance_options(MachineState *machine) | |
3921 | { | |
3922 | } | |
3923 | ||
3924 | static void spapr_machine_2_12_class_options(MachineClass *mc) | |
3925 | { | |
3926 | /* Defaults for the latest behaviour inherited from the base class */ | |
3927 | } | |
3928 | ||
3929 | DEFINE_SPAPR_MACHINE(2_12, "2.12", true); | |
3930 | ||
e2676b16 GK |
3931 | /* |
3932 | * pseries-2.11 | |
3933 | */ | |
2b615412 DG |
3934 | #define SPAPR_COMPAT_2_11 \ |
3935 | HW_COMPAT_2_11 | |
3936 | ||
e2676b16 GK |
3937 | static void spapr_machine_2_11_instance_options(MachineState *machine) |
3938 | { | |
2b615412 | 3939 | spapr_machine_2_12_instance_options(machine); |
e2676b16 GK |
3940 | } |
3941 | ||
3942 | static void spapr_machine_2_11_class_options(MachineClass *mc) | |
3943 | { | |
ee76a09f DG |
3944 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3945 | ||
2b615412 | 3946 | spapr_machine_2_12_class_options(mc); |
4e5fe368 | 3947 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
2b615412 | 3948 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); |
e2676b16 GK |
3949 | } |
3950 | ||
2b615412 | 3951 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 3952 | |
3fa14fbe DG |
3953 | /* |
3954 | * pseries-2.10 | |
3955 | */ | |
e2676b16 | 3956 | #define SPAPR_COMPAT_2_10 \ |
2b615412 | 3957 | HW_COMPAT_2_10 |
e2676b16 | 3958 | |
3fa14fbe DG |
3959 | static void spapr_machine_2_10_instance_options(MachineState *machine) |
3960 | { | |
2b615412 | 3961 | spapr_machine_2_11_instance_options(machine); |
3fa14fbe DG |
3962 | } |
3963 | ||
3964 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
3965 | { | |
e2676b16 GK |
3966 | spapr_machine_2_11_class_options(mc); |
3967 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); | |
3fa14fbe DG |
3968 | } |
3969 | ||
e2676b16 | 3970 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 3971 | |
fa325e6c DG |
3972 | /* |
3973 | * pseries-2.9 | |
3974 | */ | |
3fa14fbe | 3975 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
3976 | HW_COMPAT_2_9 \ |
3977 | { \ | |
3978 | .driver = TYPE_POWERPC_CPU, \ | |
3979 | .property = "pre-2.10-migration", \ | |
3980 | .value = "on", \ | |
3981 | }, \ | |
3fa14fbe | 3982 | |
fa325e6c DG |
3983 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
3984 | { | |
3fa14fbe | 3985 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
3986 | } |
3987 | ||
3988 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
3989 | { | |
46f7afa3 GK |
3990 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3991 | ||
3fa14fbe DG |
3992 | spapr_machine_2_10_class_options(mc); |
3993 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 3994 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 3995 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 3996 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
3997 | } |
3998 | ||
3fa14fbe | 3999 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 4000 | |
db800b21 DG |
4001 | /* |
4002 | * pseries-2.8 | |
4003 | */ | |
82516263 DG |
4004 | #define SPAPR_COMPAT_2_8 \ |
4005 | HW_COMPAT_2_8 \ | |
4006 | { \ | |
4007 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4008 | .property = "pcie-extended-configuration-space", \ | |
4009 | .value = "off", \ | |
4010 | }, | |
fa325e6c | 4011 | |
db800b21 DG |
4012 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
4013 | { | |
fa325e6c | 4014 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
4015 | } |
4016 | ||
4017 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
4018 | { | |
fa325e6c DG |
4019 | spapr_machine_2_9_class_options(mc); |
4020 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 4021 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
4022 | } |
4023 | ||
fa325e6c | 4024 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 4025 | |
1ea1eefc BR |
4026 | /* |
4027 | * pseries-2.7 | |
4028 | */ | |
357d1e3b DG |
4029 | #define SPAPR_COMPAT_2_7 \ |
4030 | HW_COMPAT_2_7 \ | |
4031 | { \ | |
4032 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4033 | .property = "mem_win_size", \ | |
4034 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
4035 | }, \ | |
4036 | { \ | |
4037 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4038 | .property = "mem64_win_size", \ | |
4039 | .value = "0", \ | |
146c11f1 DG |
4040 | }, \ |
4041 | { \ | |
4042 | .driver = TYPE_POWERPC_CPU, \ | |
4043 | .property = "pre-2.8-migration", \ | |
4044 | .value = "on", \ | |
5c4537bd DG |
4045 | }, \ |
4046 | { \ | |
4047 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4048 | .property = "pre-2.8-migration", \ | |
4049 | .value = "on", \ | |
357d1e3b DG |
4050 | }, |
4051 | ||
4052 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
4053 | uint64_t *buid, hwaddr *pio, | |
4054 | hwaddr *mmio32, hwaddr *mmio64, | |
4055 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
4056 | { | |
4057 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4058 | const uint64_t base_buid = 0x800000020000000ULL; | |
4059 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4060 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4061 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4062 | const uint32_t max_index = 255; | |
4063 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4064 | ||
4065 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4066 | hwaddr phb0_base, phb_base; | |
4067 | int i; | |
4068 | ||
4069 | /* Do we have hotpluggable memory? */ | |
4070 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
4071 | /* Can't just use maxram_size, because there may be an | |
4072 | * alignment gap between normal and hotpluggable memory | |
4073 | * regions */ | |
4074 | ram_top = spapr->hotplug_memory.base + | |
4075 | memory_region_size(&spapr->hotplug_memory.mr); | |
4076 | } | |
4077 | ||
4078 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4079 | ||
4080 | if (index > max_index) { | |
4081 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4082 | max_index); | |
4083 | return; | |
4084 | } | |
4085 | ||
4086 | *buid = base_buid + index; | |
4087 | for (i = 0; i < n_dma; ++i) { | |
4088 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4089 | } | |
4090 | ||
4091 | phb_base = phb0_base + index * phb_spacing; | |
4092 | *pio = phb_base + pio_offset; | |
4093 | *mmio32 = phb_base + mmio_offset; | |
4094 | /* | |
4095 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4096 | * fallback behaviour of automatically splitting a large "32-bit" | |
4097 | * window into contiguous 32-bit and 64-bit windows | |
4098 | */ | |
4099 | } | |
db800b21 | 4100 | |
1ea1eefc BR |
4101 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
4102 | { | |
f6229214 MR |
4103 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
4104 | ||
672de881 | 4105 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 4106 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
4107 | } |
4108 | ||
4109 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
4110 | { | |
3daa4a9f TH |
4111 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4112 | ||
db800b21 | 4113 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4114 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
db800b21 | 4115 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 4116 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4117 | } |
4118 | ||
db800b21 | 4119 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4120 | |
4b23699c DG |
4121 | /* |
4122 | * pseries-2.6 | |
4123 | */ | |
1ea1eefc | 4124 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
4125 | HW_COMPAT_2_6 \ |
4126 | { \ | |
4127 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4128 | .property = "ddw",\ | |
4129 | .value = stringify(off),\ | |
4130 | }, | |
1ea1eefc | 4131 | |
4b23699c DG |
4132 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
4133 | { | |
672de881 | 4134 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
4135 | } |
4136 | ||
4137 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
4138 | { | |
1ea1eefc | 4139 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4140 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 4141 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
4142 | } |
4143 | ||
1ea1eefc | 4144 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4145 | |
1c5f29bb DG |
4146 | /* |
4147 | * pseries-2.5 | |
4148 | */ | |
4b23699c | 4149 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
4150 | HW_COMPAT_2_5 \ |
4151 | { \ | |
4152 | .driver = "spapr-vlan", \ | |
4153 | .property = "use-rx-buffer-pools", \ | |
4154 | .value = "off", \ | |
4155 | }, | |
4b23699c | 4156 | |
5013c547 | 4157 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 4158 | { |
672de881 | 4159 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
4160 | } |
4161 | ||
4162 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
4163 | { | |
57040d45 TH |
4164 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4165 | ||
4b23699c | 4166 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4167 | smc->use_ohci_by_default = true; |
4b23699c | 4168 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
4169 | } |
4170 | ||
4b23699c | 4171 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4172 | |
4173 | /* | |
4174 | * pseries-2.4 | |
4175 | */ | |
80fd50f9 CH |
4176 | #define SPAPR_COMPAT_2_4 \ |
4177 | HW_COMPAT_2_4 | |
4178 | ||
5013c547 | 4179 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 4180 | { |
5013c547 DG |
4181 | spapr_machine_2_5_instance_options(machine); |
4182 | } | |
1c5f29bb | 4183 | |
5013c547 DG |
4184 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4185 | { | |
fc9f38c3 DG |
4186 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4187 | ||
4188 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4189 | smc->dr_lmb_enabled = false; |
f949b4e5 | 4190 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
4191 | } |
4192 | ||
fccbc785 | 4193 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4194 | |
4195 | /* | |
4196 | * pseries-2.3 | |
4197 | */ | |
38ff32c6 | 4198 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
4199 | HW_COMPAT_2_3 \ |
4200 | {\ | |
4201 | .driver = "spapr-pci-host-bridge",\ | |
4202 | .property = "dynamic-reconfiguration",\ | |
4203 | .value = "off",\ | |
4204 | }, | |
38ff32c6 | 4205 | |
5013c547 | 4206 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 4207 | { |
5013c547 | 4208 | spapr_machine_2_4_instance_options(machine); |
d25228e7 JW |
4209 | } |
4210 | ||
5013c547 | 4211 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4212 | { |
fc9f38c3 | 4213 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 4214 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 4215 | } |
fccbc785 | 4216 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4217 | |
1c5f29bb DG |
4218 | /* |
4219 | * pseries-2.2 | |
4220 | */ | |
4221 | ||
4222 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
4223 | HW_COMPAT_2_2 \ |
4224 | {\ | |
4225 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4226 | .property = "mem_win_size",\ | |
4227 | .value = "0x20000000",\ | |
4228 | }, | |
4229 | ||
5013c547 | 4230 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 4231 | { |
5013c547 | 4232 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 4233 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
4234 | } |
4235 | ||
5013c547 | 4236 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4237 | { |
fc9f38c3 | 4238 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 4239 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 4240 | } |
fccbc785 | 4241 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4242 | |
1c5f29bb DG |
4243 | /* |
4244 | * pseries-2.1 | |
4245 | */ | |
4246 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 4247 | HW_COMPAT_2_1 |
3dab0244 | 4248 | |
5013c547 | 4249 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 4250 | { |
5013c547 | 4251 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 4252 | } |
d25228e7 | 4253 | |
5013c547 | 4254 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4255 | { |
fc9f38c3 | 4256 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 4257 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 4258 | } |
fccbc785 | 4259 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4260 | |
29ee3247 | 4261 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4262 | { |
29ee3247 | 4263 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4264 | } |
4265 | ||
29ee3247 | 4266 | type_init(spapr_machine_register_types) |