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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
e35704ba | 28 | #include "sysemu/numa.h" |
83c9f4ca | 29 | #include "hw/hw.h" |
71461b0f | 30 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 31 | #include "elf.h" |
1422e32d | 32 | #include "net/net.h" |
ad440b4a | 33 | #include "sysemu/device_tree.h" |
fa1d36df | 34 | #include "sysemu/block-backend.h" |
9c17d615 PB |
35 | #include "sysemu/cpus.h" |
36 | #include "sysemu/kvm.h" | |
e97c3636 | 37 | #include "kvm_ppc.h" |
ff14e817 | 38 | #include "migration/migration.h" |
4be21d56 | 39 | #include "mmu-hash64.h" |
3794d548 | 40 | #include "qom/cpu.h" |
9fdf0c29 DG |
41 | |
42 | #include "hw/boards.h" | |
0d09e41a | 43 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
44 | #include "hw/loader.h" |
45 | ||
0d09e41a PB |
46 | #include "hw/ppc/spapr.h" |
47 | #include "hw/ppc/spapr_vio.h" | |
48 | #include "hw/pci-host/spapr.h" | |
49 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 50 | #include "hw/pci/msi.h" |
9fdf0c29 | 51 | |
83c9f4ca | 52 | #include "hw/pci/pci.h" |
71461b0f AK |
53 | #include "hw/scsi/scsi.h" |
54 | #include "hw/virtio/virtio-scsi.h" | |
f61b4bed | 55 | |
022c62cb | 56 | #include "exec/address-spaces.h" |
35139a59 | 57 | #include "hw/usb.h" |
1de7afc9 | 58 | #include "qemu/config-file.h" |
135a129a | 59 | #include "qemu/error-report.h" |
2a6593cb | 60 | #include "trace.h" |
34316482 | 61 | #include "hw/nmi.h" |
890c2b77 | 62 | |
68a27b20 MT |
63 | #include "hw/compat.h" |
64 | ||
9fdf0c29 DG |
65 | #include <libfdt.h> |
66 | ||
4d8d5467 BH |
67 | /* SLOF memory layout: |
68 | * | |
69 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
70 | * device-tree, then position SLOF itself 31M below that | |
71 | * | |
72 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
73 | * and more | |
74 | * | |
75 | * We load our kernel at 4M, leaving space for SLOF initial image | |
76 | */ | |
3bf6eedd | 77 | #define FDT_MAX_SIZE 0x40000 |
39ac8455 | 78 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 79 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
80 | #define FW_MAX_SIZE 0x400000 |
81 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
82 | #define FW_OVERHEAD 0x2800000 |
83 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 84 | |
4d8d5467 | 85 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 DG |
86 | |
87 | #define TIMEBASE_FREQ 512000000ULL | |
88 | ||
9674a356 | 89 | #define MAX_CPUS 255 |
9fdf0c29 | 90 | |
0c103f8e DG |
91 | #define PHANDLE_XICP 0x00001111 |
92 | ||
7f763a5d DG |
93 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
94 | ||
c04d6cfa | 95 | static XICSState *try_create_xics(const char *type, int nr_servers, |
34f2af3d | 96 | int nr_irqs, Error **errp) |
c04d6cfa | 97 | { |
34f2af3d | 98 | Error *err = NULL; |
c04d6cfa AL |
99 | DeviceState *dev; |
100 | ||
101 | dev = qdev_create(NULL, type); | |
102 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
103 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
34f2af3d MA |
104 | object_property_set_bool(OBJECT(dev), true, "realized", &err); |
105 | if (err) { | |
106 | error_propagate(errp, err); | |
107 | object_unparent(OBJECT(dev)); | |
c04d6cfa AL |
108 | return NULL; |
109 | } | |
5a3d7b23 | 110 | return XICS_COMMON(dev); |
c04d6cfa AL |
111 | } |
112 | ||
446f16a6 MA |
113 | static XICSState *xics_system_init(MachineState *machine, |
114 | int nr_servers, int nr_irqs) | |
c04d6cfa AL |
115 | { |
116 | XICSState *icp = NULL; | |
117 | ||
11ad93f6 | 118 | if (kvm_enabled()) { |
34f2af3d MA |
119 | Error *err = NULL; |
120 | ||
446f16a6 | 121 | if (machine_kernel_irqchip_allowed(machine)) { |
34f2af3d | 122 | icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); |
11ad93f6 | 123 | } |
446f16a6 | 124 | if (machine_kernel_irqchip_required(machine) && !icp) { |
34f2af3d MA |
125 | error_report("kernel_irqchip requested but unavailable: %s", |
126 | error_get_pretty(err)); | |
11ad93f6 DG |
127 | } |
128 | } | |
129 | ||
130 | if (!icp) { | |
34f2af3d | 131 | icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); |
c04d6cfa AL |
132 | } |
133 | ||
134 | return icp; | |
135 | } | |
136 | ||
833d4668 AK |
137 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
138 | int smt_threads) | |
139 | { | |
140 | int i, ret = 0; | |
141 | uint32_t servers_prop[smt_threads]; | |
142 | uint32_t gservers_prop[smt_threads * 2]; | |
143 | int index = ppc_get_vcpu_dt_id(cpu); | |
144 | ||
6d9412ea | 145 | if (cpu->cpu_version) { |
4bce526e | 146 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); |
6d9412ea AK |
147 | if (ret < 0) { |
148 | return ret; | |
149 | } | |
150 | } | |
151 | ||
833d4668 AK |
152 | /* Build interrupt servers and gservers properties */ |
153 | for (i = 0; i < smt_threads; i++) { | |
154 | servers_prop[i] = cpu_to_be32(index + i); | |
155 | /* Hack, direct the group queues back to cpu 0 */ | |
156 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
157 | gservers_prop[i*2 + 1] = 0; | |
158 | } | |
159 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
160 | servers_prop, sizeof(servers_prop)); | |
161 | if (ret < 0) { | |
162 | return ret; | |
163 | } | |
164 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
165 | gservers_prop, sizeof(gservers_prop)); | |
166 | ||
167 | return ret; | |
168 | } | |
169 | ||
0da6f3fe BR |
170 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) |
171 | { | |
172 | int ret = 0; | |
173 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
174 | int index = ppc_get_vcpu_dt_id(cpu); | |
175 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
176 | cpu_to_be32(0x0), | |
177 | cpu_to_be32(0x0), | |
178 | cpu_to_be32(0x0), | |
179 | cpu_to_be32(cs->numa_node), | |
180 | cpu_to_be32(index)}; | |
181 | ||
182 | /* Advertise NUMA via ibm,associativity */ | |
183 | if (nb_numa_nodes > 1) { | |
184 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
185 | sizeof(associativity)); | |
186 | } | |
187 | ||
188 | return ret; | |
189 | } | |
190 | ||
28e02042 | 191 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 192 | { |
82677ed2 AK |
193 | int ret = 0, offset, cpus_offset; |
194 | CPUState *cs; | |
6e806cc3 BR |
195 | char cpu_model[32]; |
196 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 197 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 198 | |
82677ed2 AK |
199 | CPU_FOREACH(cs) { |
200 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
201 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
202 | int index = ppc_get_vcpu_dt_id(cpu); | |
6e806cc3 | 203 | |
0f20ba62 | 204 | if ((index % smt) != 0) { |
6e806cc3 BR |
205 | continue; |
206 | } | |
207 | ||
82677ed2 | 208 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 209 | |
82677ed2 AK |
210 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
211 | if (cpus_offset < 0) { | |
212 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
213 | "cpus"); | |
214 | if (cpus_offset < 0) { | |
215 | return cpus_offset; | |
216 | } | |
217 | } | |
218 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 219 | if (offset < 0) { |
82677ed2 AK |
220 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
221 | if (offset < 0) { | |
222 | return offset; | |
223 | } | |
6e806cc3 BR |
224 | } |
225 | ||
7f763a5d DG |
226 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
227 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
228 | if (ret < 0) { |
229 | return ret; | |
230 | } | |
833d4668 | 231 | |
0da6f3fe BR |
232 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); |
233 | if (ret < 0) { | |
234 | return ret; | |
235 | } | |
236 | ||
82677ed2 | 237 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, |
2a48d993 | 238 | ppc_get_compat_smt_threads(cpu)); |
833d4668 AK |
239 | if (ret < 0) { |
240 | return ret; | |
241 | } | |
6e806cc3 BR |
242 | } |
243 | return ret; | |
244 | } | |
245 | ||
5af9873d BH |
246 | |
247 | static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, | |
248 | size_t maxsize) | |
249 | { | |
250 | size_t maxcells = maxsize / sizeof(uint32_t); | |
251 | int i, j, count; | |
252 | uint32_t *p = prop; | |
253 | ||
254 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
255 | struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
256 | ||
257 | if (!sps->page_shift) { | |
258 | break; | |
259 | } | |
260 | for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { | |
261 | if (sps->enc[count].page_shift == 0) { | |
262 | break; | |
263 | } | |
264 | } | |
265 | if ((p - prop) >= (maxcells - 3 - count * 2)) { | |
266 | break; | |
267 | } | |
268 | *(p++) = cpu_to_be32(sps->page_shift); | |
269 | *(p++) = cpu_to_be32(sps->slb_enc); | |
270 | *(p++) = cpu_to_be32(count); | |
271 | for (j = 0; j < count; j++) { | |
272 | *(p++) = cpu_to_be32(sps->enc[j].page_shift); | |
273 | *(p++) = cpu_to_be32(sps->enc[j].pte_enc); | |
274 | } | |
275 | } | |
276 | ||
277 | return (p - prop) * sizeof(uint32_t); | |
278 | } | |
279 | ||
b082d65a AK |
280 | static hwaddr spapr_node0_size(void) |
281 | { | |
fb164994 DG |
282 | MachineState *machine = MACHINE(qdev_get_machine()); |
283 | ||
b082d65a AK |
284 | if (nb_numa_nodes) { |
285 | int i; | |
286 | for (i = 0; i < nb_numa_nodes; ++i) { | |
287 | if (numa_info[i].node_mem) { | |
fb164994 DG |
288 | return MIN(pow2floor(numa_info[i].node_mem), |
289 | machine->ram_size); | |
b082d65a AK |
290 | } |
291 | } | |
292 | } | |
fb164994 | 293 | return machine->ram_size; |
b082d65a AK |
294 | } |
295 | ||
7f763a5d DG |
296 | #define _FDT(exp) \ |
297 | do { \ | |
298 | int ret = (exp); \ | |
299 | if (ret < 0) { \ | |
300 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
301 | #exp, fdt_strerror(ret)); \ | |
302 | exit(1); \ | |
303 | } \ | |
304 | } while (0) | |
305 | ||
a1d59c0f AK |
306 | static void add_str(GString *s, const gchar *s1) |
307 | { | |
308 | g_string_append_len(s, s1, strlen(s1) + 1); | |
309 | } | |
7f763a5d | 310 | |
3bbf37f2 | 311 | static void *spapr_create_fdt_skel(hwaddr initrd_base, |
a8170e5e AK |
312 | hwaddr initrd_size, |
313 | hwaddr kernel_size, | |
16457e7f | 314 | bool little_endian, |
74d042e5 DG |
315 | const char *kernel_cmdline, |
316 | uint32_t epow_irq) | |
9fdf0c29 DG |
317 | { |
318 | void *fdt; | |
9fdf0c29 DG |
319 | uint32_t start_prop = cpu_to_be32(initrd_base); |
320 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
a1d59c0f AK |
321 | GString *hypertas = g_string_sized_new(256); |
322 | GString *qemu_hypertas = g_string_sized_new(256); | |
7f763a5d | 323 | uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
9e734e3d | 324 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; |
6e806cc3 | 325 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
ef951443 | 326 | char *buf; |
9fdf0c29 | 327 | |
a1d59c0f AK |
328 | add_str(hypertas, "hcall-pft"); |
329 | add_str(hypertas, "hcall-term"); | |
330 | add_str(hypertas, "hcall-dabr"); | |
331 | add_str(hypertas, "hcall-interrupt"); | |
332 | add_str(hypertas, "hcall-tce"); | |
333 | add_str(hypertas, "hcall-vio"); | |
334 | add_str(hypertas, "hcall-splpar"); | |
335 | add_str(hypertas, "hcall-bulk"); | |
336 | add_str(hypertas, "hcall-set-mode"); | |
337 | add_str(qemu_hypertas, "hcall-memop1"); | |
338 | ||
7267c094 | 339 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
340 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
341 | ||
4d8d5467 BH |
342 | if (kernel_size) { |
343 | _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); | |
344 | } | |
345 | if (initrd_size) { | |
346 | _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); | |
347 | } | |
9fdf0c29 DG |
348 | _FDT((fdt_finish_reservemap(fdt))); |
349 | ||
350 | /* Root node */ | |
351 | _FDT((fdt_begin_node(fdt, ""))); | |
352 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 353 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 354 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 | 355 | |
ef951443 ND |
356 | /* |
357 | * Add info to guest to indentify which host is it being run on | |
358 | * and what is the uuid of the guest | |
359 | */ | |
360 | if (kvmppc_get_host_model(&buf)) { | |
361 | _FDT((fdt_property_string(fdt, "host-model", buf))); | |
362 | g_free(buf); | |
363 | } | |
364 | if (kvmppc_get_host_serial(&buf)) { | |
365 | _FDT((fdt_property_string(fdt, "host-serial", buf))); | |
366 | g_free(buf); | |
367 | } | |
368 | ||
369 | buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], | |
370 | qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], | |
371 | qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], | |
372 | qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], | |
373 | qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], | |
374 | qemu_uuid[14], qemu_uuid[15]); | |
375 | ||
376 | _FDT((fdt_property_string(fdt, "vm,uuid", buf))); | |
377 | g_free(buf); | |
378 | ||
2c1aaa81 SB |
379 | if (qemu_get_vm_name()) { |
380 | _FDT((fdt_property_string(fdt, "ibm,partition-name", | |
381 | qemu_get_vm_name()))); | |
382 | } | |
383 | ||
9fdf0c29 DG |
384 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
385 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
386 | ||
387 | /* /chosen */ | |
388 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
389 | ||
6e806cc3 BR |
390 | /* Set Form1_affinity */ |
391 | _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); | |
392 | ||
9fdf0c29 DG |
393 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); |
394 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
395 | &start_prop, sizeof(start_prop)))); | |
396 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
397 | &end_prop, sizeof(end_prop)))); | |
4d8d5467 BH |
398 | if (kernel_size) { |
399 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
400 | cpu_to_be64(kernel_size) }; | |
9fdf0c29 | 401 | |
4d8d5467 | 402 | _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
16457e7f BH |
403 | if (little_endian) { |
404 | _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); | |
405 | } | |
4d8d5467 | 406 | } |
cc84c0f3 AS |
407 | if (boot_menu) { |
408 | _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); | |
409 | } | |
f28359d8 LZ |
410 | _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); |
411 | _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); | |
412 | _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); | |
3384f95c | 413 | |
9fdf0c29 DG |
414 | _FDT((fdt_end_node(fdt))); |
415 | ||
f43e3525 DG |
416 | /* RTAS */ |
417 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
418 | ||
da95324e AK |
419 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { |
420 | add_str(hypertas, "hcall-multi-tce"); | |
421 | } | |
a1d59c0f AK |
422 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, |
423 | hypertas->len))); | |
424 | g_string_free(hypertas, TRUE); | |
425 | _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, | |
426 | qemu_hypertas->len))); | |
427 | g_string_free(qemu_hypertas, TRUE); | |
f43e3525 | 428 | |
6e806cc3 BR |
429 | _FDT((fdt_property(fdt, "ibm,associativity-reference-points", |
430 | refpoints, sizeof(refpoints)))); | |
431 | ||
74d042e5 | 432 | _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); |
79853e18 TD |
433 | _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", |
434 | RTAS_EVENT_SCAN_RATE))); | |
74d042e5 | 435 | |
a95f9922 SB |
436 | if (msi_supported) { |
437 | _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); | |
438 | } | |
439 | ||
2e14072f | 440 | /* |
9d632f5f | 441 | * According to PAPR, rtas ibm,os-term does not guarantee a return |
2e14072f ND |
442 | * back to the guest cpu. |
443 | * | |
444 | * While an additional ibm,extended-os-term property indicates that | |
445 | * rtas call return will always occur. Set this property. | |
446 | */ | |
447 | _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); | |
448 | ||
f43e3525 DG |
449 | _FDT((fdt_end_node(fdt))); |
450 | ||
b5cec4c5 | 451 | /* interrupt controller */ |
9dfef5aa | 452 | _FDT((fdt_begin_node(fdt, "interrupt-controller"))); |
b5cec4c5 DG |
453 | |
454 | _FDT((fdt_property_string(fdt, "device_type", | |
455 | "PowerPC-External-Interrupt-Presentation"))); | |
456 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
b5cec4c5 DG |
457 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
458 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
459 | interrupt_server_ranges_prop, | |
460 | sizeof(interrupt_server_ranges_prop)))); | |
0c103f8e DG |
461 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
462 | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); | |
463 | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); | |
b5cec4c5 DG |
464 | |
465 | _FDT((fdt_end_node(fdt))); | |
466 | ||
4040ab72 DG |
467 | /* vdevice */ |
468 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
469 | ||
470 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
471 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
472 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
473 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
474 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
475 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
476 | |
477 | _FDT((fdt_end_node(fdt))); | |
478 | ||
74d042e5 DG |
479 | /* event-sources */ |
480 | spapr_events_fdt_skel(fdt, epow_irq); | |
481 | ||
f7d69146 AG |
482 | /* /hypervisor node */ |
483 | if (kvm_enabled()) { | |
484 | uint8_t hypercall[16]; | |
485 | ||
486 | /* indicate KVM hypercall interface */ | |
487 | _FDT((fdt_begin_node(fdt, "hypervisor"))); | |
488 | _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); | |
489 | if (kvmppc_has_cap_fixup_hcalls()) { | |
490 | /* | |
491 | * Older KVM versions with older guest kernels were broken with the | |
492 | * magic page, don't allow the guest to map it. | |
493 | */ | |
494 | kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
495 | sizeof(hypercall)); | |
496 | _FDT((fdt_property(fdt, "hcall-instructions", hypercall, | |
497 | sizeof(hypercall)))); | |
498 | } | |
499 | _FDT((fdt_end_node(fdt))); | |
500 | } | |
501 | ||
9fdf0c29 DG |
502 | _FDT((fdt_end_node(fdt))); /* close root node */ |
503 | _FDT((fdt_finish(fdt))); | |
504 | ||
a3467baa DG |
505 | return fdt; |
506 | } | |
507 | ||
28e02042 DG |
508 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
509 | target_ulong addr, target_ulong size) | |
2a6593cb AK |
510 | { |
511 | void *fdt, *fdt_skel; | |
512 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
513 | ||
514 | size -= sizeof(hdr); | |
515 | ||
516 | /* Create sceleton */ | |
517 | fdt_skel = g_malloc0(size); | |
518 | _FDT((fdt_create(fdt_skel, size))); | |
519 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
520 | _FDT((fdt_end_node(fdt_skel))); | |
521 | _FDT((fdt_finish(fdt_skel))); | |
522 | fdt = g_malloc0(size); | |
523 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
524 | g_free(fdt_skel); | |
525 | ||
3794d548 AK |
526 | /* Fix skeleton up */ |
527 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); | |
2a6593cb AK |
528 | |
529 | /* Pack resulting tree */ | |
530 | _FDT((fdt_pack(fdt))); | |
531 | ||
532 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
533 | trace_spapr_cas_failed(size); | |
534 | return -1; | |
535 | } | |
536 | ||
537 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
538 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
539 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
540 | g_free(fdt); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
26a8c353 AK |
545 | static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
546 | hwaddr size) | |
547 | { | |
548 | uint32_t associativity[] = { | |
549 | cpu_to_be32(0x4), /* length */ | |
550 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 551 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
552 | }; |
553 | char mem_name[32]; | |
554 | uint64_t mem_reg_property[2]; | |
555 | int off; | |
556 | ||
557 | mem_reg_property[0] = cpu_to_be64(start); | |
558 | mem_reg_property[1] = cpu_to_be64(size); | |
559 | ||
560 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
561 | off = fdt_add_subnode(fdt, 0, mem_name); | |
562 | _FDT(off); | |
563 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
564 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
565 | sizeof(mem_reg_property)))); | |
566 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
567 | sizeof(associativity)))); | |
568 | } | |
569 | ||
28e02042 | 570 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 571 | { |
fb164994 | 572 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
573 | hwaddr mem_start, node_size; |
574 | int i, nb_nodes = nb_numa_nodes; | |
575 | NodeInfo *nodes = numa_info; | |
576 | NodeInfo ramnode; | |
577 | ||
578 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
579 | if (!nb_numa_nodes) { | |
580 | nb_nodes = 1; | |
fb164994 | 581 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 582 | nodes = &ramnode; |
5fe269b1 | 583 | } |
7f763a5d | 584 | |
7db8a127 AK |
585 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
586 | if (!nodes[i].node_mem) { | |
587 | continue; | |
588 | } | |
fb164994 | 589 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
590 | node_size = 0; |
591 | } else { | |
7db8a127 | 592 | node_size = nodes[i].node_mem; |
fb164994 DG |
593 | if (node_size > machine->ram_size - mem_start) { |
594 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
595 | } |
596 | } | |
7db8a127 AK |
597 | if (!mem_start) { |
598 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
599 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); | |
600 | mem_start += spapr->rma_size; | |
601 | node_size -= spapr->rma_size; | |
602 | } | |
6010818c AK |
603 | for ( ; node_size; ) { |
604 | hwaddr sizetmp = pow2floor(node_size); | |
605 | ||
606 | /* mem_start != 0 here */ | |
607 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
608 | sizetmp = 1ULL << ctzl(mem_start); | |
609 | } | |
610 | ||
611 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
612 | node_size -= sizetmp; | |
613 | mem_start += sizetmp; | |
614 | } | |
7f763a5d DG |
615 | } |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
0da6f3fe BR |
620 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
621 | sPAPRMachineState *spapr) | |
622 | { | |
623 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
624 | CPUPPCState *env = &cpu->env; | |
625 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
626 | int index = ppc_get_vcpu_dt_id(cpu); | |
627 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
628 | 0xffffffff, 0xffffffff}; | |
629 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; | |
630 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; | |
631 | uint32_t page_sizes_prop[64]; | |
632 | size_t page_sizes_prop_size; | |
22419c2a | 633 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe BR |
634 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
635 | ||
636 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
637 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
638 | ||
639 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
640 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
641 | env->dcache_line_size))); | |
642 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
643 | env->dcache_line_size))); | |
644 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
645 | env->icache_line_size))); | |
646 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
647 | env->icache_line_size))); | |
648 | ||
649 | if (pcc->l1_dcache_size) { | |
650 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
651 | pcc->l1_dcache_size))); | |
652 | } else { | |
653 | fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); | |
654 | } | |
655 | if (pcc->l1_icache_size) { | |
656 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
657 | pcc->l1_icache_size))); | |
658 | } else { | |
659 | fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); | |
660 | } | |
661 | ||
662 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
663 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
664 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); | |
665 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
666 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
667 | ||
668 | if (env->spr_cb[SPR_PURR].oea_read) { | |
669 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
670 | } | |
671 | ||
672 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
673 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
674 | segs, sizeof(segs)))); | |
675 | } | |
676 | ||
677 | /* Advertise VMX/VSX (vector extensions) if available | |
678 | * 0 / no property == no vector extensions | |
679 | * 1 == VMX / Altivec available | |
680 | * 2 == VSX available */ | |
681 | if (env->insns_flags & PPC_ALTIVEC) { | |
682 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
683 | ||
684 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
685 | } | |
686 | ||
687 | /* Advertise DFP (Decimal Floating Point) if available | |
688 | * 0 / no property == no DFP | |
689 | * 1 == DFP available */ | |
690 | if (env->insns_flags2 & PPC2_DFP) { | |
691 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
692 | } | |
693 | ||
694 | page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, | |
695 | sizeof(page_sizes_prop)); | |
696 | if (page_sizes_prop_size) { | |
697 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
698 | page_sizes_prop, page_sizes_prop_size))); | |
699 | } | |
700 | ||
701 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", | |
22419c2a | 702 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
703 | |
704 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
705 | pft_size_prop, sizeof(pft_size_prop)))); | |
706 | ||
707 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); | |
708 | ||
709 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, | |
710 | ppc_get_compat_smt_threads(cpu))); | |
711 | } | |
712 | ||
713 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
714 | { | |
715 | CPUState *cs; | |
716 | int cpus_offset; | |
717 | char *nodename; | |
718 | int smt = kvmppc_smt_threads(); | |
719 | ||
720 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
721 | _FDT(cpus_offset); | |
722 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
723 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
724 | ||
725 | /* | |
726 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
727 | * created by fdt_add_subnode() end up in the right order in FDT | |
728 | * for the guest kernel the enumerate the CPUs correctly. | |
729 | */ | |
730 | CPU_FOREACH_REVERSE(cs) { | |
731 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
732 | int index = ppc_get_vcpu_dt_id(cpu); | |
733 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
734 | int offset; | |
735 | ||
736 | if ((index % smt) != 0) { | |
737 | continue; | |
738 | } | |
739 | ||
740 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
741 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
742 | g_free(nodename); | |
743 | _FDT(offset); | |
744 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
745 | } | |
746 | ||
747 | } | |
748 | ||
28e02042 | 749 | static void spapr_finalize_fdt(sPAPRMachineState *spapr, |
a8170e5e AK |
750 | hwaddr fdt_addr, |
751 | hwaddr rtas_addr, | |
752 | hwaddr rtas_size) | |
a3467baa | 753 | { |
5b2128d2 AG |
754 | MachineState *machine = MACHINE(qdev_get_machine()); |
755 | const char *boot_device = machine->boot_order; | |
71461b0f AK |
756 | int ret, i; |
757 | size_t cb = 0; | |
758 | char *bootlist; | |
a3467baa | 759 | void *fdt; |
3384f95c | 760 | sPAPRPHBState *phb; |
a3467baa | 761 | |
7267c094 | 762 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
763 | |
764 | /* open out the base tree into a temp buffer for the final tweaks */ | |
765 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 766 | |
7f763a5d DG |
767 | ret = spapr_populate_memory(spapr, fdt); |
768 | if (ret < 0) { | |
769 | fprintf(stderr, "couldn't setup memory nodes in fdt\n"); | |
770 | exit(1); | |
771 | } | |
772 | ||
4040ab72 DG |
773 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
774 | if (ret < 0) { | |
775 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
776 | exit(1); | |
777 | } | |
778 | ||
3384f95c | 779 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 780 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
3384f95c DG |
781 | } |
782 | ||
783 | if (ret < 0) { | |
784 | fprintf(stderr, "couldn't setup PCI devices in fdt\n"); | |
785 | exit(1); | |
786 | } | |
787 | ||
39ac8455 DG |
788 | /* RTAS */ |
789 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
790 | if (ret < 0) { | |
791 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
792 | } | |
793 | ||
0da6f3fe BR |
794 | /* cpus */ |
795 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 796 | |
71461b0f AK |
797 | bootlist = get_boot_devices_list(&cb, true); |
798 | if (cb && bootlist) { | |
799 | int offset = fdt_path_offset(fdt, "/chosen"); | |
800 | if (offset < 0) { | |
801 | exit(1); | |
802 | } | |
803 | for (i = 0; i < cb; i++) { | |
804 | if (bootlist[i] == '\n') { | |
805 | bootlist[i] = ' '; | |
806 | } | |
807 | ||
808 | } | |
809 | ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); | |
810 | } | |
811 | ||
5b2128d2 AG |
812 | if (boot_device && strlen(boot_device)) { |
813 | int offset = fdt_path_offset(fdt, "/chosen"); | |
814 | ||
815 | if (offset < 0) { | |
816 | exit(1); | |
817 | } | |
818 | fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); | |
819 | } | |
820 | ||
3fc5acde | 821 | if (!spapr->has_graphics) { |
f28359d8 LZ |
822 | spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
823 | } | |
68f3a94c | 824 | |
4040ab72 DG |
825 | _FDT((fdt_pack(fdt))); |
826 | ||
4d8d5467 | 827 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
730fce59 TH |
828 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", |
829 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
4d8d5467 BH |
830 | exit(1); |
831 | } | |
832 | ||
ad440b4a | 833 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); |
a3467baa | 834 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 835 | |
a21a7a70 | 836 | g_free(bootlist); |
7267c094 | 837 | g_free(fdt); |
9fdf0c29 DG |
838 | } |
839 | ||
840 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
841 | { | |
842 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
843 | } | |
844 | ||
1b14670a | 845 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 846 | { |
1b14670a AF |
847 | CPUPPCState *env = &cpu->env; |
848 | ||
efcb9383 DG |
849 | if (msr_pr) { |
850 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
851 | env->gpr[3] = H_PRIVILEGE; | |
852 | } else { | |
aa100fa4 | 853 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 854 | } |
9fdf0c29 DG |
855 | } |
856 | ||
e6b8fd24 SMJ |
857 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
858 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
859 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
860 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
861 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
862 | ||
28e02042 | 863 | static void spapr_reset_htab(sPAPRMachineState *spapr) |
7f763a5d DG |
864 | { |
865 | long shift; | |
e6b8fd24 | 866 | int index; |
7f763a5d DG |
867 | |
868 | /* allocate hash page table. For now we always make this 16mb, | |
869 | * later we should probably make it scale to the size of guest | |
870 | * RAM */ | |
871 | ||
872 | shift = kvmppc_reset_htab(spapr->htab_shift); | |
873 | ||
874 | if (shift > 0) { | |
875 | /* Kernel handles htab, we don't need to allocate one */ | |
876 | spapr->htab_shift = shift; | |
7c43bca0 | 877 | kvmppc_kern_htab = true; |
01a57972 SMJ |
878 | |
879 | /* Tell readers to update their file descriptor */ | |
880 | if (spapr->htab_fd >= 0) { | |
881 | spapr->htab_fd_stale = true; | |
882 | } | |
7f763a5d DG |
883 | } else { |
884 | if (!spapr->htab) { | |
885 | /* Allocate an htab if we don't yet have one */ | |
886 | spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); | |
887 | } | |
888 | ||
889 | /* And clear it */ | |
890 | memset(spapr->htab, 0, HTAB_SIZE(spapr)); | |
e6b8fd24 SMJ |
891 | |
892 | for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { | |
893 | DIRTY_HPTE(HPTE(spapr->htab, index)); | |
894 | } | |
7f763a5d DG |
895 | } |
896 | ||
897 | /* Update the RMA size if necessary */ | |
898 | if (spapr->vrma_adjust) { | |
b082d65a AK |
899 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), |
900 | spapr->htab_shift); | |
7f763a5d | 901 | } |
9fdf0c29 DG |
902 | } |
903 | ||
9e3f9733 AG |
904 | static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
905 | { | |
906 | bool matched = false; | |
907 | ||
908 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
909 | matched = true; | |
910 | } | |
911 | ||
912 | if (!matched) { | |
913 | error_report("Device %s is not supported by this machine yet.", | |
914 | qdev_fw_name(DEVICE(sbdev))); | |
915 | exit(1); | |
916 | } | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
01a57972 SMJ |
921 | /* |
922 | * A guest reset will cause spapr->htab_fd to become stale if being used. | |
923 | * Reopen the file descriptor to make sure the whole HTAB is properly read. | |
924 | */ | |
28e02042 | 925 | static int spapr_check_htab_fd(sPAPRMachineState *spapr) |
01a57972 SMJ |
926 | { |
927 | int rc = 0; | |
928 | ||
929 | if (spapr->htab_fd_stale) { | |
930 | close(spapr->htab_fd); | |
931 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
932 | if (spapr->htab_fd < 0) { | |
933 | error_report("Unable to open fd for reading hash table from KVM: " | |
730fce59 | 934 | "%s", strerror(errno)); |
01a57972 SMJ |
935 | rc = -1; |
936 | } | |
937 | spapr->htab_fd_stale = false; | |
938 | } | |
939 | ||
940 | return rc; | |
941 | } | |
942 | ||
c8787ad4 | 943 | static void ppc_spapr_reset(void) |
a3467baa | 944 | { |
28e02042 | 945 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
182735ef | 946 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 947 | uint32_t rtas_limit; |
259186a7 | 948 | |
9e3f9733 AG |
949 | /* Check for unknown sysbus devices */ |
950 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
951 | ||
7f763a5d DG |
952 | /* Reset the hash table & recalc the RMA */ |
953 | spapr_reset_htab(spapr); | |
a3467baa | 954 | |
c8787ad4 | 955 | qemu_devices_reset(); |
a3467baa | 956 | |
b7d1f77a BH |
957 | /* |
958 | * We place the device tree and RTAS just below either the top of the RMA, | |
959 | * or just below 2GB, whichever is lowere, so that it can be | |
960 | * processed with 32-bit real mode code if necessary | |
961 | */ | |
962 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
963 | spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; | |
964 | spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; | |
965 | ||
a3467baa DG |
966 | /* Load the fdt */ |
967 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
968 | spapr->rtas_size); | |
969 | ||
b7d1f77a BH |
970 | /* Copy RTAS over */ |
971 | cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, | |
972 | spapr->rtas_size); | |
973 | ||
a3467baa | 974 | /* Set up the entry state */ |
182735ef AF |
975 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
976 | first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; | |
977 | first_ppc_cpu->env.gpr[5] = 0; | |
978 | first_cpu->halted = 0; | |
1b718907 | 979 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa DG |
980 | |
981 | } | |
982 | ||
1bba0dc9 AF |
983 | static void spapr_cpu_reset(void *opaque) |
984 | { | |
28e02042 | 985 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
5b2038e0 | 986 | PowerPCCPU *cpu = opaque; |
259186a7 | 987 | CPUState *cs = CPU(cpu); |
048706d9 | 988 | CPUPPCState *env = &cpu->env; |
1bba0dc9 | 989 | |
259186a7 | 990 | cpu_reset(cs); |
048706d9 DG |
991 | |
992 | /* All CPUs start halted. CPU0 is unhalted from the machine level | |
993 | * reset code and the rest are explicitly started up by the guest | |
994 | * using an RTAS call */ | |
259186a7 | 995 | cs->halted = 1; |
048706d9 DG |
996 | |
997 | env->spr[SPR_HIOR] = 0; | |
7f763a5d | 998 | |
4be21d56 | 999 | env->external_htab = (uint8_t *)spapr->htab; |
5736245c AK |
1000 | if (kvm_enabled() && !env->external_htab) { |
1001 | /* | |
1002 | * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* | |
1003 | * functions do the right thing. | |
1004 | */ | |
1005 | env->external_htab = (void *)1; | |
1006 | } | |
7f763a5d | 1007 | env->htab_base = -1; |
f3c75d42 AK |
1008 | /* |
1009 | * htab_mask is the mask used to normalize hash value to PTEG index. | |
1010 | * htab_shift is log2 of hash table size. | |
1011 | * We have 8 hpte per group, and each hpte is 16 bytes. | |
1012 | * ie have 128 bytes per hpte entry. | |
1013 | */ | |
28e02042 | 1014 | env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; |
ec4936e1 | 1015 | env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | |
7f763a5d | 1016 | (spapr->htab_shift - 18); |
1bba0dc9 AF |
1017 | } |
1018 | ||
28e02042 | 1019 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1020 | { |
2ff3de68 | 1021 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1022 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1023 | |
3978b863 | 1024 | if (dinfo) { |
4be74634 | 1025 | qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
639e8102 DG |
1026 | } |
1027 | ||
1028 | qdev_init_nofail(dev); | |
1029 | ||
1030 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1031 | } | |
1032 | ||
28e02042 | 1033 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 DG |
1034 | { |
1035 | DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); | |
1036 | ||
1037 | qdev_init_nofail(dev); | |
1038 | spapr->rtc = dev; | |
74e5ae28 DG |
1039 | |
1040 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
1041 | OBJECT(spapr->rtc), "date", NULL); | |
28df36a1 DG |
1042 | } |
1043 | ||
8c57b867 | 1044 | /* Returns whether we want to use VGA or not */ |
f28359d8 LZ |
1045 | static int spapr_vga_init(PCIBus *pci_bus) |
1046 | { | |
8c57b867 | 1047 | switch (vga_interface_type) { |
8c57b867 | 1048 | case VGA_NONE: |
7effdaa3 MW |
1049 | return false; |
1050 | case VGA_DEVICE: | |
1051 | return true; | |
1ddcae82 AJ |
1052 | case VGA_STD: |
1053 | return pci_vga_init(pci_bus) != NULL; | |
8c57b867 | 1054 | default: |
f28359d8 LZ |
1055 | fprintf(stderr, "This vga model is not supported," |
1056 | "currently it only supports -vga std\n"); | |
8c57b867 | 1057 | exit(0); |
f28359d8 | 1058 | } |
f28359d8 LZ |
1059 | } |
1060 | ||
880ae7de DG |
1061 | static int spapr_post_load(void *opaque, int version_id) |
1062 | { | |
28e02042 | 1063 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1064 | int err = 0; |
1065 | ||
631b22ea | 1066 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1067 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1068 | * So when migrating from those versions, poke the incoming offset | |
1069 | * value into the RTC device */ | |
1070 | if (version_id < 3) { | |
1071 | err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); | |
1072 | } | |
1073 | ||
1074 | return err; | |
1075 | } | |
1076 | ||
1077 | static bool version_before_3(void *opaque, int version_id) | |
1078 | { | |
1079 | return version_id < 3; | |
1080 | } | |
1081 | ||
4be21d56 DG |
1082 | static const VMStateDescription vmstate_spapr = { |
1083 | .name = "spapr", | |
880ae7de | 1084 | .version_id = 3, |
4be21d56 | 1085 | .minimum_version_id = 1, |
880ae7de | 1086 | .post_load = spapr_post_load, |
3aff6c2f | 1087 | .fields = (VMStateField[]) { |
880ae7de DG |
1088 | /* used to be @next_irq */ |
1089 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1090 | |
1091 | /* RTC offset */ | |
28e02042 | 1092 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1093 | |
28e02042 | 1094 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1095 | VMSTATE_END_OF_LIST() |
1096 | }, | |
1097 | }; | |
1098 | ||
4be21d56 DG |
1099 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1100 | { | |
28e02042 | 1101 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1102 | |
4be21d56 DG |
1103 | /* "Iteration" header */ |
1104 | qemu_put_be32(f, spapr->htab_shift); | |
1105 | ||
e68cb8b4 AK |
1106 | if (spapr->htab) { |
1107 | spapr->htab_save_index = 0; | |
1108 | spapr->htab_first_pass = true; | |
1109 | } else { | |
1110 | assert(kvm_enabled()); | |
1111 | ||
1112 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
01a57972 | 1113 | spapr->htab_fd_stale = false; |
e68cb8b4 AK |
1114 | if (spapr->htab_fd < 0) { |
1115 | fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", | |
1116 | strerror(errno)); | |
1117 | return -1; | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | ||
4be21d56 DG |
1122 | return 0; |
1123 | } | |
1124 | ||
28e02042 | 1125 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1126 | int64_t max_ns) |
1127 | { | |
1128 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1129 | int index = spapr->htab_save_index; | |
bc72ad67 | 1130 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1131 | |
1132 | assert(spapr->htab_first_pass); | |
1133 | ||
1134 | do { | |
1135 | int chunkstart; | |
1136 | ||
1137 | /* Consume invalid HPTEs */ | |
1138 | while ((index < htabslots) | |
1139 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1140 | index++; | |
1141 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1142 | } | |
1143 | ||
1144 | /* Consume valid HPTEs */ | |
1145 | chunkstart = index; | |
338c25b6 | 1146 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1147 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
1148 | index++; | |
1149 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1150 | } | |
1151 | ||
1152 | if (index > chunkstart) { | |
1153 | int n_valid = index - chunkstart; | |
1154 | ||
1155 | qemu_put_be32(f, chunkstart); | |
1156 | qemu_put_be16(f, n_valid); | |
1157 | qemu_put_be16(f, 0); | |
1158 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1159 | HASH_PTE_SIZE_64 * n_valid); | |
1160 | ||
bc72ad67 | 1161 | if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1162 | break; |
1163 | } | |
1164 | } | |
1165 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1166 | ||
1167 | if (index >= htabslots) { | |
1168 | assert(index == htabslots); | |
1169 | index = 0; | |
1170 | spapr->htab_first_pass = false; | |
1171 | } | |
1172 | spapr->htab_save_index = index; | |
1173 | } | |
1174 | ||
28e02042 | 1175 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1176 | int64_t max_ns) |
4be21d56 DG |
1177 | { |
1178 | bool final = max_ns < 0; | |
1179 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1180 | int examined = 0, sent = 0; | |
1181 | int index = spapr->htab_save_index; | |
bc72ad67 | 1182 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1183 | |
1184 | assert(!spapr->htab_first_pass); | |
1185 | ||
1186 | do { | |
1187 | int chunkstart, invalidstart; | |
1188 | ||
1189 | /* Consume non-dirty HPTEs */ | |
1190 | while ((index < htabslots) | |
1191 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1192 | index++; | |
1193 | examined++; | |
1194 | } | |
1195 | ||
1196 | chunkstart = index; | |
1197 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1198 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1199 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1200 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1201 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1202 | index++; | |
1203 | examined++; | |
1204 | } | |
1205 | ||
1206 | invalidstart = index; | |
1207 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1208 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1209 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1210 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1211 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1212 | index++; | |
1213 | examined++; | |
1214 | } | |
1215 | ||
1216 | if (index > chunkstart) { | |
1217 | int n_valid = invalidstart - chunkstart; | |
1218 | int n_invalid = index - invalidstart; | |
1219 | ||
1220 | qemu_put_be32(f, chunkstart); | |
1221 | qemu_put_be16(f, n_valid); | |
1222 | qemu_put_be16(f, n_invalid); | |
1223 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1224 | HASH_PTE_SIZE_64 * n_valid); | |
1225 | sent += index - chunkstart; | |
1226 | ||
bc72ad67 | 1227 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1228 | break; |
1229 | } | |
1230 | } | |
1231 | ||
1232 | if (examined >= htabslots) { | |
1233 | break; | |
1234 | } | |
1235 | ||
1236 | if (index >= htabslots) { | |
1237 | assert(index == htabslots); | |
1238 | index = 0; | |
1239 | } | |
1240 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1241 | ||
1242 | if (index >= htabslots) { | |
1243 | assert(index == htabslots); | |
1244 | index = 0; | |
1245 | } | |
1246 | ||
1247 | spapr->htab_save_index = index; | |
1248 | ||
e68cb8b4 | 1249 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1250 | } |
1251 | ||
e68cb8b4 AK |
1252 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1253 | #define MAX_KVM_BUF_SIZE 2048 | |
1254 | ||
4be21d56 DG |
1255 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1256 | { | |
28e02042 | 1257 | sPAPRMachineState *spapr = opaque; |
e68cb8b4 | 1258 | int rc = 0; |
4be21d56 DG |
1259 | |
1260 | /* Iteration header */ | |
1261 | qemu_put_be32(f, 0); | |
1262 | ||
e68cb8b4 AK |
1263 | if (!spapr->htab) { |
1264 | assert(kvm_enabled()); | |
1265 | ||
01a57972 SMJ |
1266 | rc = spapr_check_htab_fd(spapr); |
1267 | if (rc < 0) { | |
1268 | return rc; | |
1269 | } | |
1270 | ||
e68cb8b4 AK |
1271 | rc = kvmppc_save_htab(f, spapr->htab_fd, |
1272 | MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); | |
1273 | if (rc < 0) { | |
1274 | return rc; | |
1275 | } | |
1276 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1277 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1278 | } else { | |
e68cb8b4 | 1279 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1280 | } |
1281 | ||
1282 | /* End marker */ | |
1283 | qemu_put_be32(f, 0); | |
1284 | qemu_put_be16(f, 0); | |
1285 | qemu_put_be16(f, 0); | |
1286 | ||
e68cb8b4 | 1287 | return rc; |
4be21d56 DG |
1288 | } |
1289 | ||
1290 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1291 | { | |
28e02042 | 1292 | sPAPRMachineState *spapr = opaque; |
4be21d56 DG |
1293 | |
1294 | /* Iteration header */ | |
1295 | qemu_put_be32(f, 0); | |
1296 | ||
e68cb8b4 AK |
1297 | if (!spapr->htab) { |
1298 | int rc; | |
1299 | ||
1300 | assert(kvm_enabled()); | |
1301 | ||
01a57972 SMJ |
1302 | rc = spapr_check_htab_fd(spapr); |
1303 | if (rc < 0) { | |
1304 | return rc; | |
1305 | } | |
1306 | ||
e68cb8b4 AK |
1307 | rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); |
1308 | if (rc < 0) { | |
1309 | return rc; | |
1310 | } | |
1311 | close(spapr->htab_fd); | |
1312 | spapr->htab_fd = -1; | |
1313 | } else { | |
1314 | htab_save_later_pass(f, spapr, -1); | |
1315 | } | |
4be21d56 DG |
1316 | |
1317 | /* End marker */ | |
1318 | qemu_put_be32(f, 0); | |
1319 | qemu_put_be16(f, 0); | |
1320 | qemu_put_be16(f, 0); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1326 | { | |
28e02042 | 1327 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1328 | uint32_t section_hdr; |
e68cb8b4 | 1329 | int fd = -1; |
4be21d56 DG |
1330 | |
1331 | if (version_id < 1 || version_id > 1) { | |
1332 | fprintf(stderr, "htab_load() bad version\n"); | |
1333 | return -EINVAL; | |
1334 | } | |
1335 | ||
1336 | section_hdr = qemu_get_be32(f); | |
1337 | ||
1338 | if (section_hdr) { | |
1339 | /* First section, just the hash shift */ | |
1340 | if (spapr->htab_shift != section_hdr) { | |
613e7a76 BR |
1341 | error_report("htab_shift mismatch: source %d target %d", |
1342 | section_hdr, spapr->htab_shift); | |
4be21d56 DG |
1343 | return -EINVAL; |
1344 | } | |
1345 | return 0; | |
1346 | } | |
1347 | ||
e68cb8b4 AK |
1348 | if (!spapr->htab) { |
1349 | assert(kvm_enabled()); | |
1350 | ||
1351 | fd = kvmppc_get_htab_fd(true); | |
1352 | if (fd < 0) { | |
1353 | fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", | |
1354 | strerror(errno)); | |
1355 | } | |
1356 | } | |
1357 | ||
4be21d56 DG |
1358 | while (true) { |
1359 | uint32_t index; | |
1360 | uint16_t n_valid, n_invalid; | |
1361 | ||
1362 | index = qemu_get_be32(f); | |
1363 | n_valid = qemu_get_be16(f); | |
1364 | n_invalid = qemu_get_be16(f); | |
1365 | ||
1366 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1367 | /* End of Stream */ | |
1368 | break; | |
1369 | } | |
1370 | ||
e68cb8b4 | 1371 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1372 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1373 | /* Bad index in stream */ | |
1374 | fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " | |
e68cb8b4 AK |
1375 | "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, |
1376 | spapr->htab_shift); | |
4be21d56 DG |
1377 | return -EINVAL; |
1378 | } | |
1379 | ||
e68cb8b4 AK |
1380 | if (spapr->htab) { |
1381 | if (n_valid) { | |
1382 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1383 | HASH_PTE_SIZE_64 * n_valid); | |
1384 | } | |
1385 | if (n_invalid) { | |
1386 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1387 | HASH_PTE_SIZE_64 * n_invalid); | |
1388 | } | |
1389 | } else { | |
1390 | int rc; | |
1391 | ||
1392 | assert(fd >= 0); | |
1393 | ||
1394 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1395 | if (rc < 0) { | |
1396 | return rc; | |
1397 | } | |
4be21d56 DG |
1398 | } |
1399 | } | |
1400 | ||
e68cb8b4 AK |
1401 | if (!spapr->htab) { |
1402 | assert(fd >= 0); | |
1403 | close(fd); | |
1404 | } | |
1405 | ||
4be21d56 DG |
1406 | return 0; |
1407 | } | |
1408 | ||
1409 | static SaveVMHandlers savevm_htab_handlers = { | |
1410 | .save_live_setup = htab_save_setup, | |
1411 | .save_live_iterate = htab_save_iterate, | |
1412 | .save_live_complete = htab_save_complete, | |
1413 | .load_state = htab_load, | |
1414 | }; | |
1415 | ||
5b2128d2 AG |
1416 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1417 | Error **errp) | |
1418 | { | |
1419 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1420 | machine->boot_order = g_strdup(boot_device); | |
1421 | } | |
1422 | ||
bab99ea0 BR |
1423 | static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) |
1424 | { | |
1425 | CPUPPCState *env = &cpu->env; | |
1426 | ||
1427 | /* Set time-base frequency to 512 MHz */ | |
1428 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
1429 | ||
1430 | /* PAPR always has exception vectors in RAM not ROM. To ensure this, | |
1431 | * MSR[IP] should never be set. | |
1432 | */ | |
1433 | env->msr_mask &= ~(1 << 6); | |
1434 | ||
1435 | /* Tell KVM that we're in PAPR mode */ | |
1436 | if (kvm_enabled()) { | |
1437 | kvmppc_set_papr(cpu); | |
1438 | } | |
1439 | ||
1440 | if (cpu->max_compat) { | |
1441 | if (ppc_set_compat(cpu, cpu->max_compat) < 0) { | |
1442 | exit(1); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | xics_cpu_setup(spapr->icp, cpu); | |
1447 | ||
1448 | qemu_register_reset(spapr_cpu_reset, cpu); | |
1449 | } | |
1450 | ||
9fdf0c29 | 1451 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 1452 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 1453 | { |
28e02042 | 1454 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3ef96221 MA |
1455 | const char *kernel_filename = machine->kernel_filename; |
1456 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1457 | const char *initrd_filename = machine->initrd_filename; | |
05769733 | 1458 | PowerPCCPU *cpu; |
8c9f64df | 1459 | PCIHostState *phb; |
9fdf0c29 | 1460 | int i; |
890c2b77 AK |
1461 | MemoryRegion *sysmem = get_system_memory(); |
1462 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
1463 | MemoryRegion *rma_region; |
1464 | void *rma = NULL; | |
a8170e5e | 1465 | hwaddr rma_alloc_size; |
b082d65a | 1466 | hwaddr node0_size = spapr_node0_size(); |
4d8d5467 BH |
1467 | uint32_t initrd_base = 0; |
1468 | long kernel_size = 0, initrd_size = 0; | |
b7d1f77a | 1469 | long load_limit, fw_size; |
16457e7f | 1470 | bool kernel_le = false; |
39ac8455 | 1471 | char *filename; |
9fdf0c29 | 1472 | |
0ee2c058 AK |
1473 | msi_supported = true; |
1474 | ||
d43b45e2 DG |
1475 | QLIST_INIT(&spapr->phbs); |
1476 | ||
9fdf0c29 DG |
1477 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1478 | ||
354ac20a | 1479 | /* Allocate RMA if necessary */ |
658fa66b | 1480 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
1481 | |
1482 | if (rma_alloc_size == -1) { | |
730fce59 | 1483 | error_report("Unable to create RMA"); |
354ac20a DG |
1484 | exit(1); |
1485 | } | |
7f763a5d | 1486 | |
c4177479 | 1487 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1488 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1489 | } else { |
c4177479 | 1490 | spapr->rma_size = node0_size; |
7f763a5d DG |
1491 | |
1492 | /* With KVM, we don't actually know whether KVM supports an | |
1493 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1494 | * (HV KVM using VRMA), so we always assume the latter | |
1495 | * | |
1496 | * In that case, we also limit the initial allocations for RTAS | |
1497 | * etc... to 256M since we have no way to know what the VRMA size | |
1498 | * is going to be as it depends on the size of the hash table | |
1499 | * isn't determined yet. | |
1500 | */ | |
1501 | if (kvm_enabled()) { | |
1502 | spapr->vrma_adjust = 1; | |
1503 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1504 | } | |
354ac20a DG |
1505 | } |
1506 | ||
c4177479 AK |
1507 | if (spapr->rma_size > node0_size) { |
1508 | fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", | |
1509 | spapr->rma_size); | |
1510 | exit(1); | |
1511 | } | |
1512 | ||
b7d1f77a BH |
1513 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
1514 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 1515 | |
382be75d DG |
1516 | /* We aim for a hash table of size 1/128 the size of RAM. The |
1517 | * normal rule of thumb is 1/64 the size of RAM, but that's much | |
1518 | * more than needed for the Linux guests we support. */ | |
1519 | spapr->htab_shift = 18; /* Minimum architected size */ | |
1520 | while (spapr->htab_shift <= 46) { | |
fb164994 | 1521 | if ((1ULL << (spapr->htab_shift + 7)) >= machine->ram_size) { |
382be75d DG |
1522 | break; |
1523 | } | |
1524 | spapr->htab_shift++; | |
1525 | } | |
7f763a5d | 1526 | |
7b565160 | 1527 | /* Set up Interrupt Controller before we create the VCPUs */ |
446f16a6 | 1528 | spapr->icp = xics_system_init(machine, |
9e734e3d | 1529 | DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), |
f303f117 | 1530 | smp_threads), |
7b565160 | 1531 | XICS_IRQS); |
7b565160 | 1532 | |
9fdf0c29 | 1533 | /* init CPUs */ |
19fb2c36 BR |
1534 | if (machine->cpu_model == NULL) { |
1535 | machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; | |
9fdf0c29 DG |
1536 | } |
1537 | for (i = 0; i < smp_cpus; i++) { | |
19fb2c36 | 1538 | cpu = cpu_ppc_init(machine->cpu_model); |
05769733 | 1539 | if (cpu == NULL) { |
9fdf0c29 DG |
1540 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
1541 | exit(1); | |
1542 | } | |
bab99ea0 | 1543 | spapr_cpu_init(spapr, cpu); |
9fdf0c29 DG |
1544 | } |
1545 | ||
026bfd89 DG |
1546 | if (kvm_enabled()) { |
1547 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
1548 | kvmppc_enable_logical_ci_hcalls(); | |
1549 | } | |
1550 | ||
9fdf0c29 | 1551 | /* allocate RAM */ |
f92f5da1 | 1552 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 1553 | machine->ram_size); |
f92f5da1 | 1554 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 1555 | |
658fa66b AK |
1556 | if (rma_alloc_size && rma) { |
1557 | rma_region = g_new(MemoryRegion, 1); | |
1558 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
1559 | rma_alloc_size, rma); | |
1560 | vmstate_register_ram_global(rma_region); | |
1561 | memory_region_add_subregion(sysmem, 0, rma_region); | |
1562 | } | |
1563 | ||
39ac8455 | 1564 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 1565 | if (!filename) { |
730fce59 | 1566 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
1567 | exit(1); |
1568 | } | |
b7d1f77a BH |
1569 | spapr->rtas_size = get_image_size(filename); |
1570 | spapr->rtas_blob = g_malloc(spapr->rtas_size); | |
1571 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 1572 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
1573 | exit(1); |
1574 | } | |
4d8d5467 | 1575 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
1576 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
1577 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
1578 | exit(1); |
1579 | } | |
7267c094 | 1580 | g_free(filename); |
39ac8455 | 1581 | |
74d042e5 DG |
1582 | /* Set up EPOW events infrastructure */ |
1583 | spapr_events_init(spapr); | |
1584 | ||
12f42174 | 1585 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 1586 | spapr_rtc_create(spapr); |
12f42174 | 1587 | |
b5cec4c5 | 1588 | /* Set up VIO bus */ |
4040ab72 DG |
1589 | spapr->vio_bus = spapr_vio_bus_init(); |
1590 | ||
277f9acf | 1591 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1592 | if (serial_hds[i]) { |
d601fac4 | 1593 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1594 | } |
1595 | } | |
9fdf0c29 | 1596 | |
639e8102 DG |
1597 | /* We always have at least the nvram device on VIO */ |
1598 | spapr_create_nvram(spapr); | |
1599 | ||
3384f95c | 1600 | /* Set up PCI */ |
fa28f71b AK |
1601 | spapr_pci_rtas_init(); |
1602 | ||
89dfd6e1 | 1603 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1604 | |
277f9acf | 1605 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1606 | NICInfo *nd = &nd_table[i]; |
1607 | ||
1608 | if (!nd->model) { | |
7267c094 | 1609 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1610 | } |
1611 | ||
1612 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1613 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1614 | } else { |
29b358f9 | 1615 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1616 | } |
1617 | } | |
1618 | ||
6e270446 | 1619 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1620 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1621 | } |
1622 | ||
f28359d8 | 1623 | /* Graphics */ |
8c9f64df | 1624 | if (spapr_vga_init(phb->bus)) { |
3fc5acde | 1625 | spapr->has_graphics = true; |
c6e76503 | 1626 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
1627 | } |
1628 | ||
4ee9ced9 | 1629 | if (machine->usb) { |
8c9f64df | 1630 | pci_create_simple(phb->bus, -1, "pci-ohci"); |
c86580b8 | 1631 | |
35139a59 | 1632 | if (spapr->has_graphics) { |
c86580b8 MA |
1633 | USBBus *usb_bus = usb_bus_find(-1); |
1634 | ||
1635 | usb_create_simple(usb_bus, "usb-kbd"); | |
1636 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
1637 | } |
1638 | } | |
1639 | ||
7f763a5d | 1640 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
4d8d5467 BH |
1641 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " |
1642 | "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); | |
1643 | exit(1); | |
1644 | } | |
1645 | ||
9fdf0c29 DG |
1646 | if (kernel_filename) { |
1647 | uint64_t lowaddr = 0; | |
1648 | ||
9fdf0c29 DG |
1649 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
1650 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
3b66da82 | 1651 | if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { |
16457e7f BH |
1652 | kernel_size = load_elf(kernel_filename, |
1653 | translate_kernel_address, NULL, | |
1654 | NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); | |
1655 | kernel_le = kernel_size > 0; | |
1656 | } | |
9fdf0c29 | 1657 | if (kernel_size < 0) { |
3b66da82 AK |
1658 | fprintf(stderr, "qemu: error loading %s: %s\n", |
1659 | kernel_filename, load_elf_strerror(kernel_size)); | |
9fdf0c29 DG |
1660 | exit(1); |
1661 | } | |
1662 | ||
1663 | /* load initrd */ | |
1664 | if (initrd_filename) { | |
4d8d5467 BH |
1665 | /* Try to locate the initrd in the gap between the kernel |
1666 | * and the firmware. Add a bit of space just in case | |
1667 | */ | |
1668 | initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; | |
9fdf0c29 | 1669 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
4d8d5467 | 1670 | load_limit - initrd_base); |
9fdf0c29 DG |
1671 | if (initrd_size < 0) { |
1672 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
1673 | initrd_filename); | |
1674 | exit(1); | |
1675 | } | |
1676 | } else { | |
1677 | initrd_base = 0; | |
1678 | initrd_size = 0; | |
1679 | } | |
4d8d5467 | 1680 | } |
a3467baa | 1681 | |
8e7ea787 AF |
1682 | if (bios_name == NULL) { |
1683 | bios_name = FW_FILE_NAME; | |
1684 | } | |
1685 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 1686 | if (!filename) { |
68fea5a0 | 1687 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
1688 | exit(1); |
1689 | } | |
4d8d5467 | 1690 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
1691 | if (fw_size <= 0) { |
1692 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
1693 | exit(1); |
1694 | } | |
1695 | g_free(filename); | |
4d8d5467 | 1696 | |
28e02042 DG |
1697 | /* FIXME: Should register things through the MachineState's qdev |
1698 | * interface, this is a legacy from the sPAPREnvironment structure | |
1699 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
1700 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
1701 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
1702 | &savevm_htab_handlers, spapr); | |
1703 | ||
9fdf0c29 | 1704 | /* Prepare the device tree */ |
3bbf37f2 | 1705 | spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, |
16457e7f | 1706 | kernel_size, kernel_le, |
31fe14d1 NF |
1707 | kernel_cmdline, |
1708 | spapr->check_exception_irq); | |
a3467baa | 1709 | assert(spapr->fdt_skel != NULL); |
5b2128d2 | 1710 | |
46503c2b MR |
1711 | /* used by RTAS */ |
1712 | QTAILQ_INIT(&spapr->ccs_list); | |
1713 | qemu_register_reset(spapr_ccs_reset_hook, spapr); | |
1714 | ||
5b2128d2 | 1715 | qemu_register_boot_set(spapr_boot_set, spapr); |
9fdf0c29 DG |
1716 | } |
1717 | ||
135a129a AK |
1718 | static int spapr_kvm_type(const char *vm_type) |
1719 | { | |
1720 | if (!vm_type) { | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | if (!strcmp(vm_type, "HV")) { | |
1725 | return 1; | |
1726 | } | |
1727 | ||
1728 | if (!strcmp(vm_type, "PR")) { | |
1729 | return 2; | |
1730 | } | |
1731 | ||
1732 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
1733 | exit(1); | |
1734 | } | |
1735 | ||
71461b0f | 1736 | /* |
627b84f4 | 1737 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
1738 | * for the bootindex property handling. |
1739 | */ | |
1740 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
1741 | DeviceState *dev) | |
1742 | { | |
1743 | #define CAST(type, obj, name) \ | |
1744 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
1745 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
1746 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
1747 | ||
1748 | if (d) { | |
1749 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
1750 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
1751 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
1752 | ||
1753 | if (spapr) { | |
1754 | /* | |
1755 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
1756 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
1757 | * in the top 16 bits of the 64-bit LUN | |
1758 | */ | |
1759 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
1760 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
1761 | (uint64_t)id << 48); | |
1762 | } else if (virtio) { | |
1763 | /* | |
1764 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
1765 | * in the top 32 bits of the 64-bit LUN | |
1766 | * Note: the quote above is from SLOF and it is wrong, | |
1767 | * the actual binding is: | |
1768 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
1769 | */ | |
1770 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
1771 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
1772 | (uint64_t)id << 32); | |
1773 | } else if (usb) { | |
1774 | /* | |
1775 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
1776 | * in the top 32 bits of the 64-bit LUN | |
1777 | */ | |
1778 | unsigned usb_port = atoi(usb->port->path); | |
1779 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
1780 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
1781 | (uint64_t)id << 32); | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | if (phb) { | |
1786 | /* Replace "pci" with "pci@800000020000000" */ | |
1787 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
1788 | } | |
1789 | ||
1790 | return NULL; | |
1791 | } | |
1792 | ||
23825581 EH |
1793 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
1794 | { | |
28e02042 | 1795 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 1796 | |
28e02042 | 1797 | return g_strdup(spapr->kvm_type); |
23825581 EH |
1798 | } |
1799 | ||
1800 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
1801 | { | |
28e02042 | 1802 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 1803 | |
28e02042 DG |
1804 | g_free(spapr->kvm_type); |
1805 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
1806 | } |
1807 | ||
1808 | static void spapr_machine_initfn(Object *obj) | |
1809 | { | |
1810 | object_property_add_str(obj, "kvm-type", | |
1811 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
1812 | object_property_set_description(obj, "kvm-type", |
1813 | "Specifies the KVM virtualization mode (HV, PR)", | |
1814 | NULL); | |
23825581 EH |
1815 | } |
1816 | ||
34316482 AK |
1817 | static void ppc_cpu_do_nmi_on_cpu(void *arg) |
1818 | { | |
1819 | CPUState *cs = arg; | |
1820 | ||
1821 | cpu_synchronize_state(cs); | |
1822 | ppc_cpu_do_system_reset(cs); | |
1823 | } | |
1824 | ||
1825 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
1826 | { | |
1827 | CPUState *cs; | |
1828 | ||
1829 | CPU_FOREACH(cs) { | |
1830 | async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); | |
1831 | } | |
1832 | } | |
1833 | ||
29ee3247 AK |
1834 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
1835 | { | |
1836 | MachineClass *mc = MACHINE_CLASS(oc); | |
71461b0f | 1837 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 1838 | NMIClass *nc = NMI_CLASS(oc); |
958db90c | 1839 | |
958db90c MA |
1840 | mc->init = ppc_spapr_init; |
1841 | mc->reset = ppc_spapr_reset; | |
1842 | mc->block_default_type = IF_SCSI; | |
1843 | mc->max_cpus = MAX_CPUS; | |
1844 | mc->no_parallel = 1; | |
5b2128d2 | 1845 | mc->default_boot_order = ""; |
a34944fe | 1846 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 1847 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 1848 | mc->has_dynamic_sysbus = true; |
e4024630 | 1849 | mc->pci_allow_0_address = true; |
00b4fbe2 | 1850 | |
71461b0f | 1851 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 1852 | nc->nmi_monitor_handler = spapr_nmi; |
29ee3247 AK |
1853 | } |
1854 | ||
1855 | static const TypeInfo spapr_machine_info = { | |
1856 | .name = TYPE_SPAPR_MACHINE, | |
1857 | .parent = TYPE_MACHINE, | |
4aee7362 | 1858 | .abstract = true, |
6ca1502e | 1859 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 1860 | .instance_init = spapr_machine_initfn, |
183930c0 | 1861 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 1862 | .class_init = spapr_machine_class_init, |
71461b0f AK |
1863 | .interfaces = (InterfaceInfo[]) { |
1864 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 1865 | { TYPE_NMI }, |
71461b0f AK |
1866 | { } |
1867 | }, | |
29ee3247 AK |
1868 | }; |
1869 | ||
38ff32c6 | 1870 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
1871 | HW_COMPAT_2_3 \ |
1872 | {\ | |
1873 | .driver = "spapr-pci-host-bridge",\ | |
1874 | .property = "dynamic-reconfiguration",\ | |
1875 | .value = "off",\ | |
1876 | }, | |
38ff32c6 | 1877 | |
b194df47 | 1878 | #define SPAPR_COMPAT_2_2 \ |
38ff32c6 | 1879 | SPAPR_COMPAT_2_3 \ |
4dfd8eaa | 1880 | HW_COMPAT_2_2 \ |
b194df47 AK |
1881 | {\ |
1882 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
1883 | .property = "mem_win_size",\ | |
1884 | .value = "0x20000000",\ | |
dd754baf | 1885 | }, |
b194df47 AK |
1886 | |
1887 | #define SPAPR_COMPAT_2_1 \ | |
4dfd8eaa EH |
1888 | SPAPR_COMPAT_2_2 \ |
1889 | HW_COMPAT_2_1 | |
b194df47 | 1890 | |
d25228e7 JW |
1891 | static void spapr_compat_2_3(Object *obj) |
1892 | { | |
ff14e817 | 1893 | savevm_skip_section_footers(); |
13d16814 | 1894 | global_state_set_optional(); |
d25228e7 JW |
1895 | } |
1896 | ||
b0e966d0 JW |
1897 | static void spapr_compat_2_2(Object *obj) |
1898 | { | |
d25228e7 | 1899 | spapr_compat_2_3(obj); |
b0e966d0 JW |
1900 | } |
1901 | ||
1902 | static void spapr_compat_2_1(Object *obj) | |
1903 | { | |
1904 | spapr_compat_2_2(obj); | |
1905 | } | |
1906 | ||
d25228e7 JW |
1907 | static void spapr_machine_2_3_instance_init(Object *obj) |
1908 | { | |
1909 | spapr_compat_2_3(obj); | |
1910 | spapr_machine_initfn(obj); | |
1911 | } | |
1912 | ||
b0e966d0 JW |
1913 | static void spapr_machine_2_2_instance_init(Object *obj) |
1914 | { | |
1915 | spapr_compat_2_2(obj); | |
1916 | spapr_machine_initfn(obj); | |
1917 | } | |
1918 | ||
1919 | static void spapr_machine_2_1_instance_init(Object *obj) | |
1920 | { | |
1921 | spapr_compat_2_1(obj); | |
1922 | spapr_machine_initfn(obj); | |
1923 | } | |
1924 | ||
6026db45 AK |
1925 | static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) |
1926 | { | |
1927 | MachineClass *mc = MACHINE_CLASS(oc); | |
68a27b20 | 1928 | static GlobalProperty compat_props[] = { |
dd754baf | 1929 | SPAPR_COMPAT_2_1 |
68a27b20 MT |
1930 | { /* end of list */ } |
1931 | }; | |
6026db45 | 1932 | |
6026db45 | 1933 | mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; |
68a27b20 | 1934 | mc->compat_props = compat_props; |
6026db45 AK |
1935 | } |
1936 | ||
1937 | static const TypeInfo spapr_machine_2_1_info = { | |
b9f072d0 | 1938 | .name = MACHINE_TYPE_NAME("pseries-2.1"), |
6026db45 AK |
1939 | .parent = TYPE_SPAPR_MACHINE, |
1940 | .class_init = spapr_machine_2_1_class_init, | |
b0e966d0 | 1941 | .instance_init = spapr_machine_2_1_instance_init, |
6026db45 AK |
1942 | }; |
1943 | ||
4aee7362 DG |
1944 | static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) |
1945 | { | |
b194df47 | 1946 | static GlobalProperty compat_props[] = { |
dd754baf | 1947 | SPAPR_COMPAT_2_2 |
b194df47 AK |
1948 | { /* end of list */ } |
1949 | }; | |
4aee7362 DG |
1950 | MachineClass *mc = MACHINE_CLASS(oc); |
1951 | ||
4aee7362 | 1952 | mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; |
b194df47 | 1953 | mc->compat_props = compat_props; |
4aee7362 DG |
1954 | } |
1955 | ||
1956 | static const TypeInfo spapr_machine_2_2_info = { | |
b9f072d0 | 1957 | .name = MACHINE_TYPE_NAME("pseries-2.2"), |
4aee7362 DG |
1958 | .parent = TYPE_SPAPR_MACHINE, |
1959 | .class_init = spapr_machine_2_2_class_init, | |
b0e966d0 | 1960 | .instance_init = spapr_machine_2_2_instance_init, |
4aee7362 DG |
1961 | }; |
1962 | ||
3dab0244 AK |
1963 | static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) |
1964 | { | |
a1a45612 | 1965 | static GlobalProperty compat_props[] = { |
7619c7b0 | 1966 | SPAPR_COMPAT_2_3 |
a1a45612 DG |
1967 | { /* end of list */ } |
1968 | }; | |
3dab0244 AK |
1969 | MachineClass *mc = MACHINE_CLASS(oc); |
1970 | ||
3dab0244 | 1971 | mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; |
a1a45612 | 1972 | mc->compat_props = compat_props; |
3dab0244 AK |
1973 | } |
1974 | ||
1975 | static const TypeInfo spapr_machine_2_3_info = { | |
b9f072d0 | 1976 | .name = MACHINE_TYPE_NAME("pseries-2.3"), |
3dab0244 AK |
1977 | .parent = TYPE_SPAPR_MACHINE, |
1978 | .class_init = spapr_machine_2_3_class_init, | |
d25228e7 JW |
1979 | .instance_init = spapr_machine_2_3_instance_init, |
1980 | }; | |
1981 | ||
1982 | static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) | |
1983 | { | |
1984 | MachineClass *mc = MACHINE_CLASS(oc); | |
1985 | ||
d25228e7 JW |
1986 | mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; |
1987 | mc->alias = "pseries"; | |
fb0fc8f6 | 1988 | mc->is_default = 0; |
d25228e7 JW |
1989 | } |
1990 | ||
1991 | static const TypeInfo spapr_machine_2_4_info = { | |
b9f072d0 | 1992 | .name = MACHINE_TYPE_NAME("pseries-2.4"), |
d25228e7 JW |
1993 | .parent = TYPE_SPAPR_MACHINE, |
1994 | .class_init = spapr_machine_2_4_class_init, | |
3dab0244 AK |
1995 | }; |
1996 | ||
fb0fc8f6 DG |
1997 | static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data) |
1998 | { | |
1999 | MachineClass *mc = MACHINE_CLASS(oc); | |
2000 | ||
2001 | mc->name = "pseries-2.5"; | |
2002 | mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5"; | |
2003 | mc->alias = "pseries"; | |
2004 | mc->is_default = 1; | |
2005 | } | |
2006 | ||
2007 | static const TypeInfo spapr_machine_2_5_info = { | |
2008 | .name = MACHINE_TYPE_NAME("pseries-2.5"), | |
2009 | .parent = TYPE_SPAPR_MACHINE, | |
2010 | .class_init = spapr_machine_2_5_class_init, | |
2011 | }; | |
2012 | ||
29ee3247 | 2013 | static void spapr_machine_register_types(void) |
9fdf0c29 | 2014 | { |
29ee3247 | 2015 | type_register_static(&spapr_machine_info); |
6026db45 | 2016 | type_register_static(&spapr_machine_2_1_info); |
4aee7362 | 2017 | type_register_static(&spapr_machine_2_2_info); |
3dab0244 | 2018 | type_register_static(&spapr_machine_2_3_info); |
d25228e7 | 2019 | type_register_static(&spapr_machine_2_4_info); |
fb0fc8f6 | 2020 | type_register_static(&spapr_machine_2_5_info); |
9fdf0c29 DG |
2021 | } |
2022 | ||
29ee3247 | 2023 | type_init(spapr_machine_register_types) |