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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
e35704ba | 29 | #include "sysemu/numa.h" |
83c9f4ca | 30 | #include "hw/hw.h" |
71461b0f | 31 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 32 | #include "elf.h" |
1422e32d | 33 | #include "net/net.h" |
ad440b4a | 34 | #include "sysemu/device_tree.h" |
fa1d36df | 35 | #include "sysemu/block-backend.h" |
9c17d615 PB |
36 | #include "sysemu/cpus.h" |
37 | #include "sysemu/kvm.h" | |
c20d332a | 38 | #include "sysemu/device_tree.h" |
e97c3636 | 39 | #include "kvm_ppc.h" |
ff14e817 | 40 | #include "migration/migration.h" |
4be21d56 | 41 | #include "mmu-hash64.h" |
3794d548 | 42 | #include "qom/cpu.h" |
9fdf0c29 DG |
43 | |
44 | #include "hw/boards.h" | |
0d09e41a | 45 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
46 | #include "hw/loader.h" |
47 | ||
0d09e41a PB |
48 | #include "hw/ppc/spapr.h" |
49 | #include "hw/ppc/spapr_vio.h" | |
50 | #include "hw/pci-host/spapr.h" | |
51 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 52 | #include "hw/pci/msi.h" |
9fdf0c29 | 53 | |
83c9f4ca | 54 | #include "hw/pci/pci.h" |
71461b0f AK |
55 | #include "hw/scsi/scsi.h" |
56 | #include "hw/virtio/virtio-scsi.h" | |
f61b4bed | 57 | |
022c62cb | 58 | #include "exec/address-spaces.h" |
35139a59 | 59 | #include "hw/usb.h" |
1de7afc9 | 60 | #include "qemu/config-file.h" |
135a129a | 61 | #include "qemu/error-report.h" |
2a6593cb | 62 | #include "trace.h" |
34316482 | 63 | #include "hw/nmi.h" |
890c2b77 | 64 | |
68a27b20 | 65 | #include "hw/compat.h" |
224245bf | 66 | #include "qemu-common.h" |
68a27b20 | 67 | |
9fdf0c29 DG |
68 | #include <libfdt.h> |
69 | ||
4d8d5467 BH |
70 | /* SLOF memory layout: |
71 | * | |
72 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
73 | * device-tree, then position SLOF itself 31M below that | |
74 | * | |
75 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
76 | * and more | |
77 | * | |
78 | * We load our kernel at 4M, leaving space for SLOF initial image | |
79 | */ | |
38b02bd8 | 80 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 81 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 82 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
83 | #define FW_MAX_SIZE 0x400000 |
84 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
85 | #define FW_OVERHEAD 0x2800000 |
86 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 87 | |
4d8d5467 | 88 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 DG |
89 | |
90 | #define TIMEBASE_FREQ 512000000ULL | |
91 | ||
0c103f8e DG |
92 | #define PHANDLE_XICP 0x00001111 |
93 | ||
7f763a5d DG |
94 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
95 | ||
c04d6cfa | 96 | static XICSState *try_create_xics(const char *type, int nr_servers, |
34f2af3d | 97 | int nr_irqs, Error **errp) |
c04d6cfa | 98 | { |
34f2af3d | 99 | Error *err = NULL; |
c04d6cfa AL |
100 | DeviceState *dev; |
101 | ||
102 | dev = qdev_create(NULL, type); | |
103 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
104 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
34f2af3d MA |
105 | object_property_set_bool(OBJECT(dev), true, "realized", &err); |
106 | if (err) { | |
107 | error_propagate(errp, err); | |
108 | object_unparent(OBJECT(dev)); | |
c04d6cfa AL |
109 | return NULL; |
110 | } | |
5a3d7b23 | 111 | return XICS_COMMON(dev); |
c04d6cfa AL |
112 | } |
113 | ||
446f16a6 MA |
114 | static XICSState *xics_system_init(MachineState *machine, |
115 | int nr_servers, int nr_irqs) | |
c04d6cfa AL |
116 | { |
117 | XICSState *icp = NULL; | |
118 | ||
11ad93f6 | 119 | if (kvm_enabled()) { |
34f2af3d MA |
120 | Error *err = NULL; |
121 | ||
446f16a6 | 122 | if (machine_kernel_irqchip_allowed(machine)) { |
34f2af3d | 123 | icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); |
11ad93f6 | 124 | } |
446f16a6 | 125 | if (machine_kernel_irqchip_required(machine) && !icp) { |
b83baa60 MA |
126 | error_reportf_err(err, |
127 | "kernel_irqchip requested but unavailable: "); | |
128 | } else { | |
129 | error_free(err); | |
11ad93f6 DG |
130 | } |
131 | } | |
132 | ||
133 | if (!icp) { | |
34f2af3d | 134 | icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort); |
c04d6cfa AL |
135 | } |
136 | ||
137 | return icp; | |
138 | } | |
139 | ||
833d4668 AK |
140 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
141 | int smt_threads) | |
142 | { | |
143 | int i, ret = 0; | |
144 | uint32_t servers_prop[smt_threads]; | |
145 | uint32_t gservers_prop[smt_threads * 2]; | |
146 | int index = ppc_get_vcpu_dt_id(cpu); | |
147 | ||
6d9412ea | 148 | if (cpu->cpu_version) { |
4bce526e | 149 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); |
6d9412ea AK |
150 | if (ret < 0) { |
151 | return ret; | |
152 | } | |
153 | } | |
154 | ||
833d4668 AK |
155 | /* Build interrupt servers and gservers properties */ |
156 | for (i = 0; i < smt_threads; i++) { | |
157 | servers_prop[i] = cpu_to_be32(index + i); | |
158 | /* Hack, direct the group queues back to cpu 0 */ | |
159 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
160 | gservers_prop[i*2 + 1] = 0; | |
161 | } | |
162 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
163 | servers_prop, sizeof(servers_prop)); | |
164 | if (ret < 0) { | |
165 | return ret; | |
166 | } | |
167 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
168 | gservers_prop, sizeof(gservers_prop)); | |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
0da6f3fe BR |
173 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) |
174 | { | |
175 | int ret = 0; | |
176 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
177 | int index = ppc_get_vcpu_dt_id(cpu); | |
178 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
179 | cpu_to_be32(0x0), | |
180 | cpu_to_be32(0x0), | |
181 | cpu_to_be32(0x0), | |
182 | cpu_to_be32(cs->numa_node), | |
183 | cpu_to_be32(index)}; | |
184 | ||
185 | /* Advertise NUMA via ibm,associativity */ | |
186 | if (nb_numa_nodes > 1) { | |
187 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
188 | sizeof(associativity)); | |
189 | } | |
190 | ||
191 | return ret; | |
192 | } | |
193 | ||
28e02042 | 194 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 195 | { |
82677ed2 AK |
196 | int ret = 0, offset, cpus_offset; |
197 | CPUState *cs; | |
6e806cc3 BR |
198 | char cpu_model[32]; |
199 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 200 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 201 | |
82677ed2 AK |
202 | CPU_FOREACH(cs) { |
203 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
204 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
205 | int index = ppc_get_vcpu_dt_id(cpu); | |
6e806cc3 | 206 | |
0f20ba62 | 207 | if ((index % smt) != 0) { |
6e806cc3 BR |
208 | continue; |
209 | } | |
210 | ||
82677ed2 | 211 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 212 | |
82677ed2 AK |
213 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
214 | if (cpus_offset < 0) { | |
215 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
216 | "cpus"); | |
217 | if (cpus_offset < 0) { | |
218 | return cpus_offset; | |
219 | } | |
220 | } | |
221 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 222 | if (offset < 0) { |
82677ed2 AK |
223 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
224 | if (offset < 0) { | |
225 | return offset; | |
226 | } | |
6e806cc3 BR |
227 | } |
228 | ||
7f763a5d DG |
229 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
230 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
231 | if (ret < 0) { |
232 | return ret; | |
233 | } | |
833d4668 | 234 | |
0da6f3fe BR |
235 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); |
236 | if (ret < 0) { | |
237 | return ret; | |
238 | } | |
239 | ||
82677ed2 | 240 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, |
2a48d993 | 241 | ppc_get_compat_smt_threads(cpu)); |
833d4668 AK |
242 | if (ret < 0) { |
243 | return ret; | |
244 | } | |
6e806cc3 BR |
245 | } |
246 | return ret; | |
247 | } | |
248 | ||
5af9873d BH |
249 | |
250 | static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, | |
251 | size_t maxsize) | |
252 | { | |
253 | size_t maxcells = maxsize / sizeof(uint32_t); | |
254 | int i, j, count; | |
255 | uint32_t *p = prop; | |
256 | ||
257 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
258 | struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
259 | ||
260 | if (!sps->page_shift) { | |
261 | break; | |
262 | } | |
263 | for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { | |
264 | if (sps->enc[count].page_shift == 0) { | |
265 | break; | |
266 | } | |
267 | } | |
268 | if ((p - prop) >= (maxcells - 3 - count * 2)) { | |
269 | break; | |
270 | } | |
271 | *(p++) = cpu_to_be32(sps->page_shift); | |
272 | *(p++) = cpu_to_be32(sps->slb_enc); | |
273 | *(p++) = cpu_to_be32(count); | |
274 | for (j = 0; j < count; j++) { | |
275 | *(p++) = cpu_to_be32(sps->enc[j].page_shift); | |
276 | *(p++) = cpu_to_be32(sps->enc[j].pte_enc); | |
277 | } | |
278 | } | |
279 | ||
280 | return (p - prop) * sizeof(uint32_t); | |
281 | } | |
282 | ||
b082d65a AK |
283 | static hwaddr spapr_node0_size(void) |
284 | { | |
fb164994 DG |
285 | MachineState *machine = MACHINE(qdev_get_machine()); |
286 | ||
b082d65a AK |
287 | if (nb_numa_nodes) { |
288 | int i; | |
289 | for (i = 0; i < nb_numa_nodes; ++i) { | |
290 | if (numa_info[i].node_mem) { | |
fb164994 DG |
291 | return MIN(pow2floor(numa_info[i].node_mem), |
292 | machine->ram_size); | |
b082d65a AK |
293 | } |
294 | } | |
295 | } | |
fb164994 | 296 | return machine->ram_size; |
b082d65a AK |
297 | } |
298 | ||
7f763a5d DG |
299 | #define _FDT(exp) \ |
300 | do { \ | |
301 | int ret = (exp); \ | |
302 | if (ret < 0) { \ | |
303 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
304 | #exp, fdt_strerror(ret)); \ | |
305 | exit(1); \ | |
306 | } \ | |
307 | } while (0) | |
308 | ||
a1d59c0f AK |
309 | static void add_str(GString *s, const gchar *s1) |
310 | { | |
311 | g_string_append_len(s, s1, strlen(s1) + 1); | |
312 | } | |
7f763a5d | 313 | |
3bbf37f2 | 314 | static void *spapr_create_fdt_skel(hwaddr initrd_base, |
a8170e5e AK |
315 | hwaddr initrd_size, |
316 | hwaddr kernel_size, | |
16457e7f | 317 | bool little_endian, |
74d042e5 DG |
318 | const char *kernel_cmdline, |
319 | uint32_t epow_irq) | |
9fdf0c29 DG |
320 | { |
321 | void *fdt; | |
9fdf0c29 DG |
322 | uint32_t start_prop = cpu_to_be32(initrd_base); |
323 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
a1d59c0f AK |
324 | GString *hypertas = g_string_sized_new(256); |
325 | GString *qemu_hypertas = g_string_sized_new(256); | |
7f763a5d | 326 | uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
9e734e3d | 327 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; |
6e806cc3 | 328 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
ef951443 | 329 | char *buf; |
9fdf0c29 | 330 | |
a1d59c0f AK |
331 | add_str(hypertas, "hcall-pft"); |
332 | add_str(hypertas, "hcall-term"); | |
333 | add_str(hypertas, "hcall-dabr"); | |
334 | add_str(hypertas, "hcall-interrupt"); | |
335 | add_str(hypertas, "hcall-tce"); | |
336 | add_str(hypertas, "hcall-vio"); | |
337 | add_str(hypertas, "hcall-splpar"); | |
338 | add_str(hypertas, "hcall-bulk"); | |
339 | add_str(hypertas, "hcall-set-mode"); | |
340 | add_str(qemu_hypertas, "hcall-memop1"); | |
341 | ||
7267c094 | 342 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
343 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
344 | ||
4d8d5467 BH |
345 | if (kernel_size) { |
346 | _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); | |
347 | } | |
348 | if (initrd_size) { | |
349 | _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); | |
350 | } | |
9fdf0c29 DG |
351 | _FDT((fdt_finish_reservemap(fdt))); |
352 | ||
353 | /* Root node */ | |
354 | _FDT((fdt_begin_node(fdt, ""))); | |
355 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 356 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 357 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 | 358 | |
ef951443 ND |
359 | /* |
360 | * Add info to guest to indentify which host is it being run on | |
361 | * and what is the uuid of the guest | |
362 | */ | |
363 | if (kvmppc_get_host_model(&buf)) { | |
364 | _FDT((fdt_property_string(fdt, "host-model", buf))); | |
365 | g_free(buf); | |
366 | } | |
367 | if (kvmppc_get_host_serial(&buf)) { | |
368 | _FDT((fdt_property_string(fdt, "host-serial", buf))); | |
369 | g_free(buf); | |
370 | } | |
371 | ||
372 | buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], | |
373 | qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], | |
374 | qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], | |
375 | qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], | |
376 | qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], | |
377 | qemu_uuid[14], qemu_uuid[15]); | |
378 | ||
379 | _FDT((fdt_property_string(fdt, "vm,uuid", buf))); | |
3dc0a66d AK |
380 | if (qemu_uuid_set) { |
381 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
382 | } | |
ef951443 ND |
383 | g_free(buf); |
384 | ||
2c1aaa81 SB |
385 | if (qemu_get_vm_name()) { |
386 | _FDT((fdt_property_string(fdt, "ibm,partition-name", | |
387 | qemu_get_vm_name()))); | |
388 | } | |
389 | ||
9fdf0c29 DG |
390 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
391 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
392 | ||
393 | /* /chosen */ | |
394 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
395 | ||
6e806cc3 BR |
396 | /* Set Form1_affinity */ |
397 | _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); | |
398 | ||
9fdf0c29 DG |
399 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); |
400 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
401 | &start_prop, sizeof(start_prop)))); | |
402 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
403 | &end_prop, sizeof(end_prop)))); | |
4d8d5467 BH |
404 | if (kernel_size) { |
405 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
406 | cpu_to_be64(kernel_size) }; | |
9fdf0c29 | 407 | |
4d8d5467 | 408 | _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
16457e7f BH |
409 | if (little_endian) { |
410 | _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); | |
411 | } | |
4d8d5467 | 412 | } |
cc84c0f3 AS |
413 | if (boot_menu) { |
414 | _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); | |
415 | } | |
f28359d8 LZ |
416 | _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); |
417 | _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); | |
418 | _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); | |
3384f95c | 419 | |
9fdf0c29 DG |
420 | _FDT((fdt_end_node(fdt))); |
421 | ||
f43e3525 DG |
422 | /* RTAS */ |
423 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
424 | ||
da95324e AK |
425 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { |
426 | add_str(hypertas, "hcall-multi-tce"); | |
427 | } | |
a1d59c0f AK |
428 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, |
429 | hypertas->len))); | |
430 | g_string_free(hypertas, TRUE); | |
431 | _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, | |
432 | qemu_hypertas->len))); | |
433 | g_string_free(qemu_hypertas, TRUE); | |
f43e3525 | 434 | |
6e806cc3 BR |
435 | _FDT((fdt_property(fdt, "ibm,associativity-reference-points", |
436 | refpoints, sizeof(refpoints)))); | |
437 | ||
74d042e5 | 438 | _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); |
79853e18 TD |
439 | _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", |
440 | RTAS_EVENT_SCAN_RATE))); | |
74d042e5 | 441 | |
a95f9922 SB |
442 | if (msi_supported) { |
443 | _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); | |
444 | } | |
445 | ||
2e14072f | 446 | /* |
9d632f5f | 447 | * According to PAPR, rtas ibm,os-term does not guarantee a return |
2e14072f ND |
448 | * back to the guest cpu. |
449 | * | |
450 | * While an additional ibm,extended-os-term property indicates that | |
451 | * rtas call return will always occur. Set this property. | |
452 | */ | |
453 | _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); | |
454 | ||
f43e3525 DG |
455 | _FDT((fdt_end_node(fdt))); |
456 | ||
b5cec4c5 | 457 | /* interrupt controller */ |
9dfef5aa | 458 | _FDT((fdt_begin_node(fdt, "interrupt-controller"))); |
b5cec4c5 DG |
459 | |
460 | _FDT((fdt_property_string(fdt, "device_type", | |
461 | "PowerPC-External-Interrupt-Presentation"))); | |
462 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
b5cec4c5 DG |
463 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
464 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
465 | interrupt_server_ranges_prop, | |
466 | sizeof(interrupt_server_ranges_prop)))); | |
0c103f8e DG |
467 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
468 | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); | |
469 | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); | |
b5cec4c5 DG |
470 | |
471 | _FDT((fdt_end_node(fdt))); | |
472 | ||
4040ab72 DG |
473 | /* vdevice */ |
474 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
475 | ||
476 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
477 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
478 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
479 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
480 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
481 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
482 | |
483 | _FDT((fdt_end_node(fdt))); | |
484 | ||
74d042e5 DG |
485 | /* event-sources */ |
486 | spapr_events_fdt_skel(fdt, epow_irq); | |
487 | ||
f7d69146 AG |
488 | /* /hypervisor node */ |
489 | if (kvm_enabled()) { | |
490 | uint8_t hypercall[16]; | |
491 | ||
492 | /* indicate KVM hypercall interface */ | |
493 | _FDT((fdt_begin_node(fdt, "hypervisor"))); | |
494 | _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); | |
495 | if (kvmppc_has_cap_fixup_hcalls()) { | |
496 | /* | |
497 | * Older KVM versions with older guest kernels were broken with the | |
498 | * magic page, don't allow the guest to map it. | |
499 | */ | |
500 | kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
501 | sizeof(hypercall)); | |
502 | _FDT((fdt_property(fdt, "hcall-instructions", hypercall, | |
503 | sizeof(hypercall)))); | |
504 | } | |
505 | _FDT((fdt_end_node(fdt))); | |
506 | } | |
507 | ||
9fdf0c29 DG |
508 | _FDT((fdt_end_node(fdt))); /* close root node */ |
509 | _FDT((fdt_finish(fdt))); | |
510 | ||
a3467baa DG |
511 | return fdt; |
512 | } | |
513 | ||
03d196b7 | 514 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
515 | hwaddr size) |
516 | { | |
517 | uint32_t associativity[] = { | |
518 | cpu_to_be32(0x4), /* length */ | |
519 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 520 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
521 | }; |
522 | char mem_name[32]; | |
523 | uint64_t mem_reg_property[2]; | |
524 | int off; | |
525 | ||
526 | mem_reg_property[0] = cpu_to_be64(start); | |
527 | mem_reg_property[1] = cpu_to_be64(size); | |
528 | ||
529 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
530 | off = fdt_add_subnode(fdt, 0, mem_name); | |
531 | _FDT(off); | |
532 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
533 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
534 | sizeof(mem_reg_property)))); | |
535 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
536 | sizeof(associativity)))); | |
03d196b7 | 537 | return off; |
26a8c353 AK |
538 | } |
539 | ||
28e02042 | 540 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 541 | { |
fb164994 | 542 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
543 | hwaddr mem_start, node_size; |
544 | int i, nb_nodes = nb_numa_nodes; | |
545 | NodeInfo *nodes = numa_info; | |
546 | NodeInfo ramnode; | |
547 | ||
548 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
549 | if (!nb_numa_nodes) { | |
550 | nb_nodes = 1; | |
fb164994 | 551 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 552 | nodes = &ramnode; |
5fe269b1 | 553 | } |
7f763a5d | 554 | |
7db8a127 AK |
555 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
556 | if (!nodes[i].node_mem) { | |
557 | continue; | |
558 | } | |
fb164994 | 559 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
560 | node_size = 0; |
561 | } else { | |
7db8a127 | 562 | node_size = nodes[i].node_mem; |
fb164994 DG |
563 | if (node_size > machine->ram_size - mem_start) { |
564 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
565 | } |
566 | } | |
7db8a127 AK |
567 | if (!mem_start) { |
568 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 569 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
570 | mem_start += spapr->rma_size; |
571 | node_size -= spapr->rma_size; | |
572 | } | |
6010818c AK |
573 | for ( ; node_size; ) { |
574 | hwaddr sizetmp = pow2floor(node_size); | |
575 | ||
576 | /* mem_start != 0 here */ | |
577 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
578 | sizetmp = 1ULL << ctzl(mem_start); | |
579 | } | |
580 | ||
581 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
582 | node_size -= sizetmp; | |
583 | mem_start += sizetmp; | |
584 | } | |
7f763a5d DG |
585 | } |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
0da6f3fe BR |
590 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
591 | sPAPRMachineState *spapr) | |
592 | { | |
593 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
594 | CPUPPCState *env = &cpu->env; | |
595 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
596 | int index = ppc_get_vcpu_dt_id(cpu); | |
597 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
598 | 0xffffffff, 0xffffffff}; | |
599 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; | |
600 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; | |
601 | uint32_t page_sizes_prop[64]; | |
602 | size_t page_sizes_prop_size; | |
22419c2a | 603 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe BR |
604 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
605 | ||
90da0d5a BH |
606 | /* Note: we keep CI large pages off for now because a 64K capable guest |
607 | * provisioned with large pages might otherwise try to map a qemu | |
608 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
609 | * even if that qemu runs on a 4k host. | |
610 | * | |
611 | * We can later add this bit back when we are confident this is not | |
612 | * an issue (!HV KVM or 64K host) | |
613 | */ | |
614 | uint8_t pa_features_206[] = { 6, 0, | |
615 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
616 | uint8_t pa_features_207[] = { 24, 0, | |
617 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
618 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
619 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
620 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
621 | uint8_t *pa_features; | |
622 | size_t pa_size; | |
623 | ||
0da6f3fe BR |
624 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); |
625 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
626 | ||
627 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
628 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
629 | env->dcache_line_size))); | |
630 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
631 | env->dcache_line_size))); | |
632 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
633 | env->icache_line_size))); | |
634 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
635 | env->icache_line_size))); | |
636 | ||
637 | if (pcc->l1_dcache_size) { | |
638 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
639 | pcc->l1_dcache_size))); | |
640 | } else { | |
641 | fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); | |
642 | } | |
643 | if (pcc->l1_icache_size) { | |
644 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
645 | pcc->l1_icache_size))); | |
646 | } else { | |
647 | fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); | |
648 | } | |
649 | ||
650 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
651 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 652 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
653 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
654 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
655 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
656 | ||
657 | if (env->spr_cb[SPR_PURR].oea_read) { | |
658 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
659 | } | |
660 | ||
661 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
662 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
663 | segs, sizeof(segs)))); | |
664 | } | |
665 | ||
666 | /* Advertise VMX/VSX (vector extensions) if available | |
667 | * 0 / no property == no vector extensions | |
668 | * 1 == VMX / Altivec available | |
669 | * 2 == VSX available */ | |
670 | if (env->insns_flags & PPC_ALTIVEC) { | |
671 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
672 | ||
673 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
674 | } | |
675 | ||
676 | /* Advertise DFP (Decimal Floating Point) if available | |
677 | * 0 / no property == no DFP | |
678 | * 1 == DFP available */ | |
679 | if (env->insns_flags2 & PPC2_DFP) { | |
680 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
681 | } | |
682 | ||
683 | page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, | |
684 | sizeof(page_sizes_prop)); | |
685 | if (page_sizes_prop_size) { | |
686 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
687 | page_sizes_prop, page_sizes_prop_size))); | |
688 | } | |
689 | ||
90da0d5a BH |
690 | /* Do the ibm,pa-features property, adjust it for ci-large-pages */ |
691 | if (env->mmu_model == POWERPC_MMU_2_06) { | |
692 | pa_features = pa_features_206; | |
693 | pa_size = sizeof(pa_features_206); | |
694 | } else /* env->mmu_model == POWERPC_MMU_2_07 */ { | |
695 | pa_features = pa_features_207; | |
696 | pa_size = sizeof(pa_features_207); | |
697 | } | |
698 | if (env->ci_large_pages) { | |
699 | pa_features[3] |= 0x20; | |
700 | } | |
701 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
702 | ||
0da6f3fe | 703 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 704 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
705 | |
706 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
707 | pft_size_prop, sizeof(pft_size_prop)))); | |
708 | ||
709 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); | |
710 | ||
711 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, | |
712 | ppc_get_compat_smt_threads(cpu))); | |
713 | } | |
714 | ||
715 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
716 | { | |
717 | CPUState *cs; | |
718 | int cpus_offset; | |
719 | char *nodename; | |
720 | int smt = kvmppc_smt_threads(); | |
721 | ||
722 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
723 | _FDT(cpus_offset); | |
724 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
725 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
726 | ||
727 | /* | |
728 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
729 | * created by fdt_add_subnode() end up in the right order in FDT | |
730 | * for the guest kernel the enumerate the CPUs correctly. | |
731 | */ | |
732 | CPU_FOREACH_REVERSE(cs) { | |
733 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
734 | int index = ppc_get_vcpu_dt_id(cpu); | |
735 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
736 | int offset; | |
737 | ||
738 | if ((index % smt) != 0) { | |
739 | continue; | |
740 | } | |
741 | ||
742 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
743 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
744 | g_free(nodename); | |
745 | _FDT(offset); | |
746 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
747 | } | |
748 | ||
749 | } | |
750 | ||
03d196b7 BR |
751 | /* |
752 | * Adds ibm,dynamic-reconfiguration-memory node. | |
753 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
754 | * of this device tree node. | |
755 | */ | |
756 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
757 | { | |
758 | MachineState *machine = MACHINE(spapr); | |
759 | int ret, i, offset; | |
760 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
761 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
e8f986fc | 762 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
03d196b7 | 763 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 764 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 765 | |
ef001f06 TH |
766 | /* |
767 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
768 | * or ibm,associativity-lookup-arrays | |
769 | */ | |
770 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
771 | * sizeof(uint32_t); | |
03d196b7 BR |
772 | cur_index = int_buf = g_malloc0(buf_len); |
773 | ||
774 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
775 | ||
776 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
777 | sizeof(prop_lmb_size)); | |
778 | if (ret < 0) { | |
779 | goto out; | |
780 | } | |
781 | ||
782 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
783 | if (ret < 0) { | |
784 | goto out; | |
785 | } | |
786 | ||
787 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
788 | if (ret < 0) { | |
789 | goto out; | |
790 | } | |
791 | ||
792 | /* ibm,dynamic-memory */ | |
793 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
794 | cur_index++; | |
795 | for (i = 0; i < nr_lmbs; i++) { | |
796 | sPAPRDRConnector *drc; | |
797 | sPAPRDRConnectorClass *drck; | |
e8f986fc | 798 | uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; |
03d196b7 BR |
799 | uint32_t *dynamic_memory = cur_index; |
800 | ||
03d196b7 BR |
801 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, |
802 | addr/lmb_size); | |
803 | g_assert(drc); | |
804 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
805 | ||
806 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
807 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
808 | dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); | |
809 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
810 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
811 | if (addr < machine->ram_size || | |
812 | memory_region_present(get_system_memory(), addr)) { | |
813 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
814 | } else { | |
815 | dynamic_memory[5] = cpu_to_be32(0); | |
816 | } | |
817 | ||
818 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
819 | } | |
820 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
821 | if (ret < 0) { | |
822 | goto out; | |
823 | } | |
824 | ||
825 | /* ibm,associativity-lookup-arrays */ | |
826 | cur_index = int_buf; | |
6663864e | 827 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
828 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
829 | cur_index += 2; | |
6663864e | 830 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
831 | uint32_t associativity[] = { |
832 | cpu_to_be32(0x0), | |
833 | cpu_to_be32(0x0), | |
834 | cpu_to_be32(0x0), | |
835 | cpu_to_be32(i) | |
836 | }; | |
837 | memcpy(cur_index, associativity, sizeof(associativity)); | |
838 | cur_index += 4; | |
839 | } | |
840 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
841 | (cur_index - int_buf) * sizeof(uint32_t)); | |
842 | out: | |
843 | g_free(int_buf); | |
844 | return ret; | |
845 | } | |
846 | ||
847 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, | |
848 | target_ulong addr, target_ulong size, | |
849 | bool cpu_update, bool memory_update) | |
850 | { | |
851 | void *fdt, *fdt_skel; | |
852 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
853 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
854 | ||
855 | size -= sizeof(hdr); | |
856 | ||
857 | /* Create sceleton */ | |
858 | fdt_skel = g_malloc0(size); | |
859 | _FDT((fdt_create(fdt_skel, size))); | |
860 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
861 | _FDT((fdt_end_node(fdt_skel))); | |
862 | _FDT((fdt_finish(fdt_skel))); | |
863 | fdt = g_malloc0(size); | |
864 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
865 | g_free(fdt_skel); | |
866 | ||
867 | /* Fixup cpu nodes */ | |
868 | if (cpu_update) { | |
869 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); | |
870 | } | |
871 | ||
872 | /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */ | |
873 | if (memory_update && smc->dr_lmb_enabled) { | |
874 | _FDT((spapr_populate_drconf_memory(spapr, fdt))); | |
03d196b7 BR |
875 | } |
876 | ||
877 | /* Pack resulting tree */ | |
878 | _FDT((fdt_pack(fdt))); | |
879 | ||
880 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
881 | trace_spapr_cas_failed(size); | |
882 | return -1; | |
883 | } | |
884 | ||
885 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
886 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
887 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
888 | g_free(fdt); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
28e02042 | 893 | static void spapr_finalize_fdt(sPAPRMachineState *spapr, |
a8170e5e AK |
894 | hwaddr fdt_addr, |
895 | hwaddr rtas_addr, | |
896 | hwaddr rtas_size) | |
a3467baa | 897 | { |
5b2128d2 | 898 | MachineState *machine = MACHINE(qdev_get_machine()); |
c20d332a | 899 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
5b2128d2 | 900 | const char *boot_device = machine->boot_order; |
71461b0f AK |
901 | int ret, i; |
902 | size_t cb = 0; | |
903 | char *bootlist; | |
a3467baa | 904 | void *fdt; |
3384f95c | 905 | sPAPRPHBState *phb; |
a3467baa | 906 | |
7267c094 | 907 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
908 | |
909 | /* open out the base tree into a temp buffer for the final tweaks */ | |
910 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 911 | |
e8f986fc BR |
912 | ret = spapr_populate_memory(spapr, fdt); |
913 | if (ret < 0) { | |
914 | fprintf(stderr, "couldn't setup memory nodes in fdt\n"); | |
915 | exit(1); | |
7f763a5d DG |
916 | } |
917 | ||
4040ab72 DG |
918 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
919 | if (ret < 0) { | |
920 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
921 | exit(1); | |
922 | } | |
923 | ||
4d9392be TH |
924 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
925 | ret = spapr_rng_populate_dt(fdt); | |
926 | if (ret < 0) { | |
927 | fprintf(stderr, "could not set up rng device in the fdt\n"); | |
928 | exit(1); | |
929 | } | |
930 | } | |
931 | ||
3384f95c | 932 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 933 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
3384f95c DG |
934 | } |
935 | ||
936 | if (ret < 0) { | |
937 | fprintf(stderr, "couldn't setup PCI devices in fdt\n"); | |
938 | exit(1); | |
939 | } | |
940 | ||
39ac8455 DG |
941 | /* RTAS */ |
942 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
943 | if (ret < 0) { | |
944 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
945 | } | |
946 | ||
0da6f3fe BR |
947 | /* cpus */ |
948 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 949 | |
71461b0f AK |
950 | bootlist = get_boot_devices_list(&cb, true); |
951 | if (cb && bootlist) { | |
952 | int offset = fdt_path_offset(fdt, "/chosen"); | |
953 | if (offset < 0) { | |
954 | exit(1); | |
955 | } | |
956 | for (i = 0; i < cb; i++) { | |
957 | if (bootlist[i] == '\n') { | |
958 | bootlist[i] = ' '; | |
959 | } | |
960 | ||
961 | } | |
962 | ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); | |
963 | } | |
964 | ||
5b2128d2 AG |
965 | if (boot_device && strlen(boot_device)) { |
966 | int offset = fdt_path_offset(fdt, "/chosen"); | |
967 | ||
968 | if (offset < 0) { | |
969 | exit(1); | |
970 | } | |
971 | fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); | |
972 | } | |
973 | ||
3fc5acde | 974 | if (!spapr->has_graphics) { |
f28359d8 LZ |
975 | spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
976 | } | |
68f3a94c | 977 | |
c20d332a BR |
978 | if (smc->dr_lmb_enabled) { |
979 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
980 | } | |
981 | ||
4040ab72 DG |
982 | _FDT((fdt_pack(fdt))); |
983 | ||
4d8d5467 | 984 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
730fce59 TH |
985 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", |
986 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
4d8d5467 BH |
987 | exit(1); |
988 | } | |
989 | ||
ad440b4a | 990 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); |
a3467baa | 991 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 992 | |
a21a7a70 | 993 | g_free(bootlist); |
7267c094 | 994 | g_free(fdt); |
9fdf0c29 DG |
995 | } |
996 | ||
997 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
998 | { | |
999 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1000 | } | |
1001 | ||
1b14670a | 1002 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 1003 | { |
1b14670a AF |
1004 | CPUPPCState *env = &cpu->env; |
1005 | ||
efcb9383 DG |
1006 | if (msr_pr) { |
1007 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1008 | env->gpr[3] = H_PRIVILEGE; | |
1009 | } else { | |
aa100fa4 | 1010 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1011 | } |
9fdf0c29 DG |
1012 | } |
1013 | ||
e6b8fd24 SMJ |
1014 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1015 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1016 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1017 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1018 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1019 | ||
b817772a | 1020 | static void spapr_alloc_htab(sPAPRMachineState *spapr) |
7f763a5d DG |
1021 | { |
1022 | long shift; | |
e6b8fd24 | 1023 | int index; |
7f763a5d DG |
1024 | |
1025 | /* allocate hash page table. For now we always make this 16mb, | |
1026 | * later we should probably make it scale to the size of guest | |
1027 | * RAM */ | |
1028 | ||
1029 | shift = kvmppc_reset_htab(spapr->htab_shift); | |
b41d320f BR |
1030 | if (shift < 0) { |
1031 | /* | |
1032 | * For HV KVM, host kernel will return -ENOMEM when requested | |
1033 | * HTAB size can't be allocated. | |
1034 | */ | |
1035 | error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); | |
1036 | } else if (shift > 0) { | |
1037 | /* | |
1038 | * Kernel handles htab, we don't need to allocate one | |
1039 | * | |
1040 | * Older kernels can fall back to lower HTAB shift values, | |
1041 | * but we don't allow booting of such guests. | |
1042 | */ | |
7735feda BR |
1043 | if (shift != spapr->htab_shift) { |
1044 | error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem"); | |
1045 | } | |
1046 | ||
7f763a5d | 1047 | spapr->htab_shift = shift; |
7c43bca0 | 1048 | kvmppc_kern_htab = true; |
b817772a BR |
1049 | } else { |
1050 | /* Allocate htab */ | |
1051 | spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); | |
1052 | ||
1053 | /* And clear it */ | |
1054 | memset(spapr->htab, 0, HTAB_SIZE(spapr)); | |
1055 | ||
1056 | for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { | |
1057 | DIRTY_HPTE(HPTE(spapr->htab, index)); | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Clear HTAB entries during reset. | |
1064 | * | |
1065 | * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is | |
1066 | * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually. | |
1067 | */ | |
1068 | static void spapr_reset_htab(sPAPRMachineState *spapr) | |
1069 | { | |
1070 | long shift; | |
1071 | int index; | |
01a57972 | 1072 | |
b817772a | 1073 | shift = kvmppc_reset_htab(spapr->htab_shift); |
b41d320f BR |
1074 | if (shift < 0) { |
1075 | error_setg(&error_abort, "Failed to reset HTAB"); | |
1076 | } else if (shift > 0) { | |
7735feda BR |
1077 | if (shift != spapr->htab_shift) { |
1078 | error_setg(&error_abort, "Requested HTAB allocation failed during reset"); | |
1079 | } | |
1080 | ||
01a57972 SMJ |
1081 | /* Tell readers to update their file descriptor */ |
1082 | if (spapr->htab_fd >= 0) { | |
1083 | spapr->htab_fd_stale = true; | |
1084 | } | |
7f763a5d | 1085 | } else { |
7f763a5d | 1086 | memset(spapr->htab, 0, HTAB_SIZE(spapr)); |
e6b8fd24 SMJ |
1087 | |
1088 | for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { | |
1089 | DIRTY_HPTE(HPTE(spapr->htab, index)); | |
1090 | } | |
7f763a5d DG |
1091 | } |
1092 | ||
1093 | /* Update the RMA size if necessary */ | |
1094 | if (spapr->vrma_adjust) { | |
b082d65a AK |
1095 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), |
1096 | spapr->htab_shift); | |
7f763a5d | 1097 | } |
9fdf0c29 DG |
1098 | } |
1099 | ||
9e3f9733 AG |
1100 | static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
1101 | { | |
1102 | bool matched = false; | |
1103 | ||
1104 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1105 | matched = true; | |
1106 | } | |
1107 | ||
1108 | if (!matched) { | |
1109 | error_report("Device %s is not supported by this machine yet.", | |
1110 | qdev_fw_name(DEVICE(sbdev))); | |
1111 | exit(1); | |
1112 | } | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
01a57972 SMJ |
1117 | /* |
1118 | * A guest reset will cause spapr->htab_fd to become stale if being used. | |
1119 | * Reopen the file descriptor to make sure the whole HTAB is properly read. | |
1120 | */ | |
28e02042 | 1121 | static int spapr_check_htab_fd(sPAPRMachineState *spapr) |
01a57972 SMJ |
1122 | { |
1123 | int rc = 0; | |
1124 | ||
1125 | if (spapr->htab_fd_stale) { | |
1126 | close(spapr->htab_fd); | |
1127 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1128 | if (spapr->htab_fd < 0) { | |
1129 | error_report("Unable to open fd for reading hash table from KVM: " | |
730fce59 | 1130 | "%s", strerror(errno)); |
01a57972 SMJ |
1131 | rc = -1; |
1132 | } | |
1133 | spapr->htab_fd_stale = false; | |
1134 | } | |
1135 | ||
1136 | return rc; | |
1137 | } | |
1138 | ||
c8787ad4 | 1139 | static void ppc_spapr_reset(void) |
a3467baa | 1140 | { |
28e02042 | 1141 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
182735ef | 1142 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1143 | uint32_t rtas_limit; |
259186a7 | 1144 | |
9e3f9733 AG |
1145 | /* Check for unknown sysbus devices */ |
1146 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1147 | ||
7f763a5d DG |
1148 | /* Reset the hash table & recalc the RMA */ |
1149 | spapr_reset_htab(spapr); | |
a3467baa | 1150 | |
c8787ad4 | 1151 | qemu_devices_reset(); |
a3467baa | 1152 | |
b7d1f77a BH |
1153 | /* |
1154 | * We place the device tree and RTAS just below either the top of the RMA, | |
1155 | * or just below 2GB, whichever is lowere, so that it can be | |
1156 | * processed with 32-bit real mode code if necessary | |
1157 | */ | |
1158 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
1159 | spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; | |
1160 | spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; | |
1161 | ||
a3467baa DG |
1162 | /* Load the fdt */ |
1163 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
1164 | spapr->rtas_size); | |
1165 | ||
b7d1f77a BH |
1166 | /* Copy RTAS over */ |
1167 | cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, | |
1168 | spapr->rtas_size); | |
1169 | ||
a3467baa | 1170 | /* Set up the entry state */ |
182735ef AF |
1171 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1172 | first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; | |
1173 | first_ppc_cpu->env.gpr[5] = 0; | |
1174 | first_cpu->halted = 0; | |
1b718907 | 1175 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa DG |
1176 | |
1177 | } | |
1178 | ||
1bba0dc9 AF |
1179 | static void spapr_cpu_reset(void *opaque) |
1180 | { | |
28e02042 | 1181 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
5b2038e0 | 1182 | PowerPCCPU *cpu = opaque; |
259186a7 | 1183 | CPUState *cs = CPU(cpu); |
048706d9 | 1184 | CPUPPCState *env = &cpu->env; |
1bba0dc9 | 1185 | |
259186a7 | 1186 | cpu_reset(cs); |
048706d9 DG |
1187 | |
1188 | /* All CPUs start halted. CPU0 is unhalted from the machine level | |
1189 | * reset code and the rest are explicitly started up by the guest | |
1190 | * using an RTAS call */ | |
259186a7 | 1191 | cs->halted = 1; |
048706d9 DG |
1192 | |
1193 | env->spr[SPR_HIOR] = 0; | |
7f763a5d | 1194 | |
4be21d56 | 1195 | env->external_htab = (uint8_t *)spapr->htab; |
5736245c AK |
1196 | if (kvm_enabled() && !env->external_htab) { |
1197 | /* | |
1198 | * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* | |
1199 | * functions do the right thing. | |
1200 | */ | |
1201 | env->external_htab = (void *)1; | |
1202 | } | |
7f763a5d | 1203 | env->htab_base = -1; |
f3c75d42 AK |
1204 | /* |
1205 | * htab_mask is the mask used to normalize hash value to PTEG index. | |
1206 | * htab_shift is log2 of hash table size. | |
1207 | * We have 8 hpte per group, and each hpte is 16 bytes. | |
1208 | * ie have 128 bytes per hpte entry. | |
1209 | */ | |
28e02042 | 1210 | env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; |
ec4936e1 | 1211 | env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | |
7f763a5d | 1212 | (spapr->htab_shift - 18); |
1bba0dc9 AF |
1213 | } |
1214 | ||
28e02042 | 1215 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1216 | { |
2ff3de68 | 1217 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1218 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1219 | |
3978b863 | 1220 | if (dinfo) { |
6231a6da MA |
1221 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1222 | &error_fatal); | |
639e8102 DG |
1223 | } |
1224 | ||
1225 | qdev_init_nofail(dev); | |
1226 | ||
1227 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1228 | } | |
1229 | ||
28e02042 | 1230 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 DG |
1231 | { |
1232 | DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); | |
1233 | ||
1234 | qdev_init_nofail(dev); | |
1235 | spapr->rtc = dev; | |
74e5ae28 DG |
1236 | |
1237 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
1238 | OBJECT(spapr->rtc), "date", NULL); | |
28df36a1 DG |
1239 | } |
1240 | ||
8c57b867 | 1241 | /* Returns whether we want to use VGA or not */ |
f28359d8 LZ |
1242 | static int spapr_vga_init(PCIBus *pci_bus) |
1243 | { | |
8c57b867 | 1244 | switch (vga_interface_type) { |
8c57b867 | 1245 | case VGA_NONE: |
7effdaa3 MW |
1246 | return false; |
1247 | case VGA_DEVICE: | |
1248 | return true; | |
1ddcae82 | 1249 | case VGA_STD: |
b798c190 | 1250 | case VGA_VIRTIO: |
1ddcae82 | 1251 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1252 | default: |
f28359d8 LZ |
1253 | fprintf(stderr, "This vga model is not supported," |
1254 | "currently it only supports -vga std\n"); | |
8c57b867 | 1255 | exit(0); |
f28359d8 | 1256 | } |
f28359d8 LZ |
1257 | } |
1258 | ||
880ae7de DG |
1259 | static int spapr_post_load(void *opaque, int version_id) |
1260 | { | |
28e02042 | 1261 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1262 | int err = 0; |
1263 | ||
631b22ea | 1264 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1265 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1266 | * So when migrating from those versions, poke the incoming offset | |
1267 | * value into the RTC device */ | |
1268 | if (version_id < 3) { | |
1269 | err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); | |
1270 | } | |
1271 | ||
1272 | return err; | |
1273 | } | |
1274 | ||
1275 | static bool version_before_3(void *opaque, int version_id) | |
1276 | { | |
1277 | return version_id < 3; | |
1278 | } | |
1279 | ||
4be21d56 DG |
1280 | static const VMStateDescription vmstate_spapr = { |
1281 | .name = "spapr", | |
880ae7de | 1282 | .version_id = 3, |
4be21d56 | 1283 | .minimum_version_id = 1, |
880ae7de | 1284 | .post_load = spapr_post_load, |
3aff6c2f | 1285 | .fields = (VMStateField[]) { |
880ae7de DG |
1286 | /* used to be @next_irq */ |
1287 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1288 | |
1289 | /* RTC offset */ | |
28e02042 | 1290 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1291 | |
28e02042 | 1292 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1293 | VMSTATE_END_OF_LIST() |
1294 | }, | |
1295 | }; | |
1296 | ||
4be21d56 DG |
1297 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1298 | { | |
28e02042 | 1299 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1300 | |
4be21d56 DG |
1301 | /* "Iteration" header */ |
1302 | qemu_put_be32(f, spapr->htab_shift); | |
1303 | ||
e68cb8b4 AK |
1304 | if (spapr->htab) { |
1305 | spapr->htab_save_index = 0; | |
1306 | spapr->htab_first_pass = true; | |
1307 | } else { | |
1308 | assert(kvm_enabled()); | |
1309 | ||
1310 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
01a57972 | 1311 | spapr->htab_fd_stale = false; |
e68cb8b4 AK |
1312 | if (spapr->htab_fd < 0) { |
1313 | fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", | |
1314 | strerror(errno)); | |
1315 | return -1; | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | ||
4be21d56 DG |
1320 | return 0; |
1321 | } | |
1322 | ||
28e02042 | 1323 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1324 | int64_t max_ns) |
1325 | { | |
1326 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1327 | int index = spapr->htab_save_index; | |
bc72ad67 | 1328 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1329 | |
1330 | assert(spapr->htab_first_pass); | |
1331 | ||
1332 | do { | |
1333 | int chunkstart; | |
1334 | ||
1335 | /* Consume invalid HPTEs */ | |
1336 | while ((index < htabslots) | |
1337 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1338 | index++; | |
1339 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1340 | } | |
1341 | ||
1342 | /* Consume valid HPTEs */ | |
1343 | chunkstart = index; | |
338c25b6 | 1344 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1345 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
1346 | index++; | |
1347 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1348 | } | |
1349 | ||
1350 | if (index > chunkstart) { | |
1351 | int n_valid = index - chunkstart; | |
1352 | ||
1353 | qemu_put_be32(f, chunkstart); | |
1354 | qemu_put_be16(f, n_valid); | |
1355 | qemu_put_be16(f, 0); | |
1356 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1357 | HASH_PTE_SIZE_64 * n_valid); | |
1358 | ||
bc72ad67 | 1359 | if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1360 | break; |
1361 | } | |
1362 | } | |
1363 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1364 | ||
1365 | if (index >= htabslots) { | |
1366 | assert(index == htabslots); | |
1367 | index = 0; | |
1368 | spapr->htab_first_pass = false; | |
1369 | } | |
1370 | spapr->htab_save_index = index; | |
1371 | } | |
1372 | ||
28e02042 | 1373 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1374 | int64_t max_ns) |
4be21d56 DG |
1375 | { |
1376 | bool final = max_ns < 0; | |
1377 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1378 | int examined = 0, sent = 0; | |
1379 | int index = spapr->htab_save_index; | |
bc72ad67 | 1380 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1381 | |
1382 | assert(!spapr->htab_first_pass); | |
1383 | ||
1384 | do { | |
1385 | int chunkstart, invalidstart; | |
1386 | ||
1387 | /* Consume non-dirty HPTEs */ | |
1388 | while ((index < htabslots) | |
1389 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1390 | index++; | |
1391 | examined++; | |
1392 | } | |
1393 | ||
1394 | chunkstart = index; | |
1395 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1396 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1397 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1398 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1399 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1400 | index++; | |
1401 | examined++; | |
1402 | } | |
1403 | ||
1404 | invalidstart = index; | |
1405 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1406 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1407 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1408 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1409 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1410 | index++; | |
1411 | examined++; | |
1412 | } | |
1413 | ||
1414 | if (index > chunkstart) { | |
1415 | int n_valid = invalidstart - chunkstart; | |
1416 | int n_invalid = index - invalidstart; | |
1417 | ||
1418 | qemu_put_be32(f, chunkstart); | |
1419 | qemu_put_be16(f, n_valid); | |
1420 | qemu_put_be16(f, n_invalid); | |
1421 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1422 | HASH_PTE_SIZE_64 * n_valid); | |
1423 | sent += index - chunkstart; | |
1424 | ||
bc72ad67 | 1425 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1426 | break; |
1427 | } | |
1428 | } | |
1429 | ||
1430 | if (examined >= htabslots) { | |
1431 | break; | |
1432 | } | |
1433 | ||
1434 | if (index >= htabslots) { | |
1435 | assert(index == htabslots); | |
1436 | index = 0; | |
1437 | } | |
1438 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1439 | ||
1440 | if (index >= htabslots) { | |
1441 | assert(index == htabslots); | |
1442 | index = 0; | |
1443 | } | |
1444 | ||
1445 | spapr->htab_save_index = index; | |
1446 | ||
e68cb8b4 | 1447 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1448 | } |
1449 | ||
e68cb8b4 AK |
1450 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1451 | #define MAX_KVM_BUF_SIZE 2048 | |
1452 | ||
4be21d56 DG |
1453 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1454 | { | |
28e02042 | 1455 | sPAPRMachineState *spapr = opaque; |
e68cb8b4 | 1456 | int rc = 0; |
4be21d56 DG |
1457 | |
1458 | /* Iteration header */ | |
1459 | qemu_put_be32(f, 0); | |
1460 | ||
e68cb8b4 AK |
1461 | if (!spapr->htab) { |
1462 | assert(kvm_enabled()); | |
1463 | ||
01a57972 SMJ |
1464 | rc = spapr_check_htab_fd(spapr); |
1465 | if (rc < 0) { | |
1466 | return rc; | |
1467 | } | |
1468 | ||
e68cb8b4 AK |
1469 | rc = kvmppc_save_htab(f, spapr->htab_fd, |
1470 | MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); | |
1471 | if (rc < 0) { | |
1472 | return rc; | |
1473 | } | |
1474 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1475 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1476 | } else { | |
e68cb8b4 | 1477 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1478 | } |
1479 | ||
1480 | /* End marker */ | |
1481 | qemu_put_be32(f, 0); | |
1482 | qemu_put_be16(f, 0); | |
1483 | qemu_put_be16(f, 0); | |
1484 | ||
e68cb8b4 | 1485 | return rc; |
4be21d56 DG |
1486 | } |
1487 | ||
1488 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1489 | { | |
28e02042 | 1490 | sPAPRMachineState *spapr = opaque; |
4be21d56 DG |
1491 | |
1492 | /* Iteration header */ | |
1493 | qemu_put_be32(f, 0); | |
1494 | ||
e68cb8b4 AK |
1495 | if (!spapr->htab) { |
1496 | int rc; | |
1497 | ||
1498 | assert(kvm_enabled()); | |
1499 | ||
01a57972 SMJ |
1500 | rc = spapr_check_htab_fd(spapr); |
1501 | if (rc < 0) { | |
1502 | return rc; | |
1503 | } | |
1504 | ||
e68cb8b4 AK |
1505 | rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); |
1506 | if (rc < 0) { | |
1507 | return rc; | |
1508 | } | |
1509 | close(spapr->htab_fd); | |
1510 | spapr->htab_fd = -1; | |
1511 | } else { | |
1512 | htab_save_later_pass(f, spapr, -1); | |
1513 | } | |
4be21d56 DG |
1514 | |
1515 | /* End marker */ | |
1516 | qemu_put_be32(f, 0); | |
1517 | qemu_put_be16(f, 0); | |
1518 | qemu_put_be16(f, 0); | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1524 | { | |
28e02042 | 1525 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1526 | uint32_t section_hdr; |
e68cb8b4 | 1527 | int fd = -1; |
4be21d56 DG |
1528 | |
1529 | if (version_id < 1 || version_id > 1) { | |
1530 | fprintf(stderr, "htab_load() bad version\n"); | |
1531 | return -EINVAL; | |
1532 | } | |
1533 | ||
1534 | section_hdr = qemu_get_be32(f); | |
1535 | ||
1536 | if (section_hdr) { | |
1537 | /* First section, just the hash shift */ | |
1538 | if (spapr->htab_shift != section_hdr) { | |
613e7a76 BR |
1539 | error_report("htab_shift mismatch: source %d target %d", |
1540 | section_hdr, spapr->htab_shift); | |
4be21d56 DG |
1541 | return -EINVAL; |
1542 | } | |
1543 | return 0; | |
1544 | } | |
1545 | ||
e68cb8b4 AK |
1546 | if (!spapr->htab) { |
1547 | assert(kvm_enabled()); | |
1548 | ||
1549 | fd = kvmppc_get_htab_fd(true); | |
1550 | if (fd < 0) { | |
1551 | fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", | |
1552 | strerror(errno)); | |
1553 | } | |
1554 | } | |
1555 | ||
4be21d56 DG |
1556 | while (true) { |
1557 | uint32_t index; | |
1558 | uint16_t n_valid, n_invalid; | |
1559 | ||
1560 | index = qemu_get_be32(f); | |
1561 | n_valid = qemu_get_be16(f); | |
1562 | n_invalid = qemu_get_be16(f); | |
1563 | ||
1564 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1565 | /* End of Stream */ | |
1566 | break; | |
1567 | } | |
1568 | ||
e68cb8b4 | 1569 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1570 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1571 | /* Bad index in stream */ | |
1572 | fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " | |
e68cb8b4 AK |
1573 | "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, |
1574 | spapr->htab_shift); | |
4be21d56 DG |
1575 | return -EINVAL; |
1576 | } | |
1577 | ||
e68cb8b4 AK |
1578 | if (spapr->htab) { |
1579 | if (n_valid) { | |
1580 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1581 | HASH_PTE_SIZE_64 * n_valid); | |
1582 | } | |
1583 | if (n_invalid) { | |
1584 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1585 | HASH_PTE_SIZE_64 * n_invalid); | |
1586 | } | |
1587 | } else { | |
1588 | int rc; | |
1589 | ||
1590 | assert(fd >= 0); | |
1591 | ||
1592 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1593 | if (rc < 0) { | |
1594 | return rc; | |
1595 | } | |
4be21d56 DG |
1596 | } |
1597 | } | |
1598 | ||
e68cb8b4 AK |
1599 | if (!spapr->htab) { |
1600 | assert(fd >= 0); | |
1601 | close(fd); | |
1602 | } | |
1603 | ||
4be21d56 DG |
1604 | return 0; |
1605 | } | |
1606 | ||
1607 | static SaveVMHandlers savevm_htab_handlers = { | |
1608 | .save_live_setup = htab_save_setup, | |
1609 | .save_live_iterate = htab_save_iterate, | |
a3e06c3d | 1610 | .save_live_complete_precopy = htab_save_complete, |
4be21d56 DG |
1611 | .load_state = htab_load, |
1612 | }; | |
1613 | ||
5b2128d2 AG |
1614 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1615 | Error **errp) | |
1616 | { | |
1617 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1618 | machine->boot_order = g_strdup(boot_device); | |
1619 | } | |
1620 | ||
bab99ea0 BR |
1621 | static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu) |
1622 | { | |
1623 | CPUPPCState *env = &cpu->env; | |
1624 | ||
1625 | /* Set time-base frequency to 512 MHz */ | |
1626 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
1627 | ||
1628 | /* PAPR always has exception vectors in RAM not ROM. To ensure this, | |
1629 | * MSR[IP] should never be set. | |
1630 | */ | |
1631 | env->msr_mask &= ~(1 << 6); | |
1632 | ||
1633 | /* Tell KVM that we're in PAPR mode */ | |
1634 | if (kvm_enabled()) { | |
1635 | kvmppc_set_papr(cpu); | |
1636 | } | |
1637 | ||
1638 | if (cpu->max_compat) { | |
1639 | if (ppc_set_compat(cpu, cpu->max_compat) < 0) { | |
1640 | exit(1); | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | xics_cpu_setup(spapr->icp, cpu); | |
1645 | ||
1646 | qemu_register_reset(spapr_cpu_reset, cpu); | |
1647 | } | |
1648 | ||
224245bf DG |
1649 | /* |
1650 | * Reset routine for LMB DR devices. | |
1651 | * | |
1652 | * Unlike PCI DR devices, LMB DR devices explicitly register this reset | |
1653 | * routine. Reset for PCI DR devices will be handled by PHB reset routine | |
1654 | * when it walks all its children devices. LMB devices reset occurs | |
1655 | * as part of spapr_ppc_reset(). | |
1656 | */ | |
1657 | static void spapr_drc_reset(void *opaque) | |
1658 | { | |
1659 | sPAPRDRConnector *drc = opaque; | |
1660 | DeviceState *d = DEVICE(drc); | |
1661 | ||
1662 | if (d) { | |
1663 | device_reset(d); | |
1664 | } | |
1665 | } | |
1666 | ||
1667 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) | |
1668 | { | |
1669 | MachineState *machine = MACHINE(spapr); | |
1670 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 1671 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
1672 | int i; |
1673 | ||
1674 | for (i = 0; i < nr_lmbs; i++) { | |
1675 | sPAPRDRConnector *drc; | |
1676 | uint64_t addr; | |
1677 | ||
e8f986fc | 1678 | addr = i * lmb_size + spapr->hotplug_memory.base; |
224245bf DG |
1679 | drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, |
1680 | addr/lmb_size); | |
1681 | qemu_register_reset(spapr_drc_reset, drc); | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | /* | |
1686 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
1687 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
1688 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
1689 | */ | |
1690 | static void spapr_validate_node_memory(MachineState *machine) | |
1691 | { | |
1692 | int i; | |
1693 | ||
1694 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE || | |
1695 | machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
1696 | error_report("Can't support memory configuration where RAM size " | |
1697 | "0x" RAM_ADDR_FMT " or maxmem size " | |
1698 | "0x" RAM_ADDR_FMT " isn't aligned to %llu MB", | |
1699 | machine->ram_size, machine->maxram_size, | |
1700 | SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
1701 | exit(EXIT_FAILURE); | |
1702 | } | |
1703 | ||
1704 | for (i = 0; i < nb_numa_nodes; i++) { | |
1705 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
1706 | error_report("Can't support memory configuration where memory size" | |
1707 | " %" PRIx64 " of node %d isn't aligned to %llu MB", | |
1708 | numa_info[i].node_mem, i, | |
1709 | SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
1710 | exit(EXIT_FAILURE); | |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | ||
9fdf0c29 | 1715 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 1716 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 1717 | { |
28e02042 | 1718 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 1719 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 MA |
1720 | const char *kernel_filename = machine->kernel_filename; |
1721 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1722 | const char *initrd_filename = machine->initrd_filename; | |
05769733 | 1723 | PowerPCCPU *cpu; |
8c9f64df | 1724 | PCIHostState *phb; |
9fdf0c29 | 1725 | int i; |
890c2b77 AK |
1726 | MemoryRegion *sysmem = get_system_memory(); |
1727 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
1728 | MemoryRegion *rma_region; |
1729 | void *rma = NULL; | |
a8170e5e | 1730 | hwaddr rma_alloc_size; |
b082d65a | 1731 | hwaddr node0_size = spapr_node0_size(); |
4d8d5467 BH |
1732 | uint32_t initrd_base = 0; |
1733 | long kernel_size = 0, initrd_size = 0; | |
b7d1f77a | 1734 | long load_limit, fw_size; |
16457e7f | 1735 | bool kernel_le = false; |
39ac8455 | 1736 | char *filename; |
9fdf0c29 | 1737 | |
0ee2c058 AK |
1738 | msi_supported = true; |
1739 | ||
d43b45e2 DG |
1740 | QLIST_INIT(&spapr->phbs); |
1741 | ||
9fdf0c29 DG |
1742 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1743 | ||
354ac20a | 1744 | /* Allocate RMA if necessary */ |
658fa66b | 1745 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
1746 | |
1747 | if (rma_alloc_size == -1) { | |
730fce59 | 1748 | error_report("Unable to create RMA"); |
354ac20a DG |
1749 | exit(1); |
1750 | } | |
7f763a5d | 1751 | |
c4177479 | 1752 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1753 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1754 | } else { |
c4177479 | 1755 | spapr->rma_size = node0_size; |
7f763a5d DG |
1756 | |
1757 | /* With KVM, we don't actually know whether KVM supports an | |
1758 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1759 | * (HV KVM using VRMA), so we always assume the latter | |
1760 | * | |
1761 | * In that case, we also limit the initial allocations for RTAS | |
1762 | * etc... to 256M since we have no way to know what the VRMA size | |
1763 | * is going to be as it depends on the size of the hash table | |
1764 | * isn't determined yet. | |
1765 | */ | |
1766 | if (kvm_enabled()) { | |
1767 | spapr->vrma_adjust = 1; | |
1768 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1769 | } | |
354ac20a DG |
1770 | } |
1771 | ||
c4177479 AK |
1772 | if (spapr->rma_size > node0_size) { |
1773 | fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", | |
1774 | spapr->rma_size); | |
1775 | exit(1); | |
1776 | } | |
1777 | ||
b7d1f77a BH |
1778 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
1779 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 1780 | |
382be75d DG |
1781 | /* We aim for a hash table of size 1/128 the size of RAM. The |
1782 | * normal rule of thumb is 1/64 the size of RAM, but that's much | |
1783 | * more than needed for the Linux guests we support. */ | |
1784 | spapr->htab_shift = 18; /* Minimum architected size */ | |
1785 | while (spapr->htab_shift <= 46) { | |
ce881f77 | 1786 | if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) { |
382be75d DG |
1787 | break; |
1788 | } | |
1789 | spapr->htab_shift++; | |
1790 | } | |
b817772a | 1791 | spapr_alloc_htab(spapr); |
7f763a5d | 1792 | |
7b565160 | 1793 | /* Set up Interrupt Controller before we create the VCPUs */ |
446f16a6 | 1794 | spapr->icp = xics_system_init(machine, |
9e734e3d | 1795 | DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), |
f303f117 | 1796 | smp_threads), |
7b565160 | 1797 | XICS_IRQS); |
7b565160 | 1798 | |
224245bf DG |
1799 | if (smc->dr_lmb_enabled) { |
1800 | spapr_validate_node_memory(machine); | |
1801 | } | |
1802 | ||
9fdf0c29 | 1803 | /* init CPUs */ |
19fb2c36 BR |
1804 | if (machine->cpu_model == NULL) { |
1805 | machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; | |
9fdf0c29 DG |
1806 | } |
1807 | for (i = 0; i < smp_cpus; i++) { | |
19fb2c36 | 1808 | cpu = cpu_ppc_init(machine->cpu_model); |
05769733 | 1809 | if (cpu == NULL) { |
9fdf0c29 DG |
1810 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
1811 | exit(1); | |
1812 | } | |
bab99ea0 | 1813 | spapr_cpu_init(spapr, cpu); |
9fdf0c29 DG |
1814 | } |
1815 | ||
026bfd89 DG |
1816 | if (kvm_enabled()) { |
1817 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
1818 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 1819 | kvmppc_enable_set_mode_hcall(); |
026bfd89 DG |
1820 | } |
1821 | ||
9fdf0c29 | 1822 | /* allocate RAM */ |
f92f5da1 | 1823 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 1824 | machine->ram_size); |
f92f5da1 | 1825 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 1826 | |
658fa66b AK |
1827 | if (rma_alloc_size && rma) { |
1828 | rma_region = g_new(MemoryRegion, 1); | |
1829 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
1830 | rma_alloc_size, rma); | |
1831 | vmstate_register_ram_global(rma_region); | |
1832 | memory_region_add_subregion(sysmem, 0, rma_region); | |
1833 | } | |
1834 | ||
4a1c9cf0 BR |
1835 | /* initialize hotplug memory address space */ |
1836 | if (machine->ram_size < machine->maxram_size) { | |
1837 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
1838 | ||
1839 | if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) { | |
9af9e0fe MA |
1840 | error_report("Specified number of memory slots %" PRIu64 |
1841 | " exceeds max supported %d", | |
19a35c9e | 1842 | machine->ram_slots, SPAPR_MAX_RAM_SLOTS); |
4a1c9cf0 BR |
1843 | exit(EXIT_FAILURE); |
1844 | } | |
1845 | ||
1846 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
1847 | SPAPR_HOTPLUG_MEM_ALIGN); | |
1848 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
1849 | "hotplug-memory", hotplug_mem_size); | |
1850 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
1851 | &spapr->hotplug_memory.mr); | |
1852 | } | |
1853 | ||
224245bf DG |
1854 | if (smc->dr_lmb_enabled) { |
1855 | spapr_create_lmb_dr_connectors(spapr); | |
1856 | } | |
1857 | ||
39ac8455 | 1858 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 1859 | if (!filename) { |
730fce59 | 1860 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
1861 | exit(1); |
1862 | } | |
b7d1f77a BH |
1863 | spapr->rtas_size = get_image_size(filename); |
1864 | spapr->rtas_blob = g_malloc(spapr->rtas_size); | |
1865 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 1866 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
1867 | exit(1); |
1868 | } | |
4d8d5467 | 1869 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
1870 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
1871 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
1872 | exit(1); |
1873 | } | |
7267c094 | 1874 | g_free(filename); |
39ac8455 | 1875 | |
74d042e5 DG |
1876 | /* Set up EPOW events infrastructure */ |
1877 | spapr_events_init(spapr); | |
1878 | ||
12f42174 | 1879 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 1880 | spapr_rtc_create(spapr); |
12f42174 | 1881 | |
b5cec4c5 | 1882 | /* Set up VIO bus */ |
4040ab72 DG |
1883 | spapr->vio_bus = spapr_vio_bus_init(); |
1884 | ||
277f9acf | 1885 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1886 | if (serial_hds[i]) { |
d601fac4 | 1887 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1888 | } |
1889 | } | |
9fdf0c29 | 1890 | |
639e8102 DG |
1891 | /* We always have at least the nvram device on VIO */ |
1892 | spapr_create_nvram(spapr); | |
1893 | ||
3384f95c | 1894 | /* Set up PCI */ |
fa28f71b AK |
1895 | spapr_pci_rtas_init(); |
1896 | ||
89dfd6e1 | 1897 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1898 | |
277f9acf | 1899 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1900 | NICInfo *nd = &nd_table[i]; |
1901 | ||
1902 | if (!nd->model) { | |
7267c094 | 1903 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1904 | } |
1905 | ||
1906 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1907 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1908 | } else { |
29b358f9 | 1909 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1910 | } |
1911 | } | |
1912 | ||
6e270446 | 1913 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1914 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1915 | } |
1916 | ||
f28359d8 | 1917 | /* Graphics */ |
8c9f64df | 1918 | if (spapr_vga_init(phb->bus)) { |
3fc5acde | 1919 | spapr->has_graphics = true; |
c6e76503 | 1920 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
1921 | } |
1922 | ||
4ee9ced9 | 1923 | if (machine->usb) { |
57040d45 TH |
1924 | if (smc->use_ohci_by_default) { |
1925 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
1926 | } else { | |
1927 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
1928 | } | |
c86580b8 | 1929 | |
35139a59 | 1930 | if (spapr->has_graphics) { |
c86580b8 MA |
1931 | USBBus *usb_bus = usb_bus_find(-1); |
1932 | ||
1933 | usb_create_simple(usb_bus, "usb-kbd"); | |
1934 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
1935 | } |
1936 | } | |
1937 | ||
7f763a5d | 1938 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
4d8d5467 BH |
1939 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " |
1940 | "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); | |
1941 | exit(1); | |
1942 | } | |
1943 | ||
9fdf0c29 DG |
1944 | if (kernel_filename) { |
1945 | uint64_t lowaddr = 0; | |
1946 | ||
9fdf0c29 | 1947 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
4ecd4d16 | 1948 | NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0); |
3b66da82 | 1949 | if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { |
16457e7f BH |
1950 | kernel_size = load_elf(kernel_filename, |
1951 | translate_kernel_address, NULL, | |
4ecd4d16 | 1952 | NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0); |
16457e7f BH |
1953 | kernel_le = kernel_size > 0; |
1954 | } | |
9fdf0c29 | 1955 | if (kernel_size < 0) { |
3b66da82 AK |
1956 | fprintf(stderr, "qemu: error loading %s: %s\n", |
1957 | kernel_filename, load_elf_strerror(kernel_size)); | |
9fdf0c29 DG |
1958 | exit(1); |
1959 | } | |
1960 | ||
1961 | /* load initrd */ | |
1962 | if (initrd_filename) { | |
4d8d5467 BH |
1963 | /* Try to locate the initrd in the gap between the kernel |
1964 | * and the firmware. Add a bit of space just in case | |
1965 | */ | |
1966 | initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; | |
9fdf0c29 | 1967 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
4d8d5467 | 1968 | load_limit - initrd_base); |
9fdf0c29 DG |
1969 | if (initrd_size < 0) { |
1970 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
1971 | initrd_filename); | |
1972 | exit(1); | |
1973 | } | |
1974 | } else { | |
1975 | initrd_base = 0; | |
1976 | initrd_size = 0; | |
1977 | } | |
4d8d5467 | 1978 | } |
a3467baa | 1979 | |
8e7ea787 AF |
1980 | if (bios_name == NULL) { |
1981 | bios_name = FW_FILE_NAME; | |
1982 | } | |
1983 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 1984 | if (!filename) { |
68fea5a0 | 1985 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
1986 | exit(1); |
1987 | } | |
4d8d5467 | 1988 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
1989 | if (fw_size <= 0) { |
1990 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
1991 | exit(1); |
1992 | } | |
1993 | g_free(filename); | |
4d8d5467 | 1994 | |
28e02042 DG |
1995 | /* FIXME: Should register things through the MachineState's qdev |
1996 | * interface, this is a legacy from the sPAPREnvironment structure | |
1997 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
1998 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
1999 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2000 | &savevm_htab_handlers, spapr); | |
2001 | ||
9fdf0c29 | 2002 | /* Prepare the device tree */ |
3bbf37f2 | 2003 | spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, |
16457e7f | 2004 | kernel_size, kernel_le, |
31fe14d1 NF |
2005 | kernel_cmdline, |
2006 | spapr->check_exception_irq); | |
a3467baa | 2007 | assert(spapr->fdt_skel != NULL); |
5b2128d2 | 2008 | |
46503c2b MR |
2009 | /* used by RTAS */ |
2010 | QTAILQ_INIT(&spapr->ccs_list); | |
2011 | qemu_register_reset(spapr_ccs_reset_hook, spapr); | |
2012 | ||
5b2128d2 | 2013 | qemu_register_boot_set(spapr_boot_set, spapr); |
9fdf0c29 DG |
2014 | } |
2015 | ||
135a129a AK |
2016 | static int spapr_kvm_type(const char *vm_type) |
2017 | { | |
2018 | if (!vm_type) { | |
2019 | return 0; | |
2020 | } | |
2021 | ||
2022 | if (!strcmp(vm_type, "HV")) { | |
2023 | return 1; | |
2024 | } | |
2025 | ||
2026 | if (!strcmp(vm_type, "PR")) { | |
2027 | return 2; | |
2028 | } | |
2029 | ||
2030 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2031 | exit(1); | |
2032 | } | |
2033 | ||
71461b0f | 2034 | /* |
627b84f4 | 2035 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2036 | * for the bootindex property handling. |
2037 | */ | |
2038 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2039 | DeviceState *dev) | |
2040 | { | |
2041 | #define CAST(type, obj, name) \ | |
2042 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2043 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2044 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
2045 | ||
2046 | if (d) { | |
2047 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2048 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2049 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2050 | ||
2051 | if (spapr) { | |
2052 | /* | |
2053 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2054 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2055 | * in the top 16 bits of the 64-bit LUN | |
2056 | */ | |
2057 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2058 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2059 | (uint64_t)id << 48); | |
2060 | } else if (virtio) { | |
2061 | /* | |
2062 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2063 | * in the top 32 bits of the 64-bit LUN | |
2064 | * Note: the quote above is from SLOF and it is wrong, | |
2065 | * the actual binding is: | |
2066 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2067 | */ | |
2068 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2069 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2070 | (uint64_t)id << 32); | |
2071 | } else if (usb) { | |
2072 | /* | |
2073 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2074 | * in the top 32 bits of the 64-bit LUN | |
2075 | */ | |
2076 | unsigned usb_port = atoi(usb->port->path); | |
2077 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2078 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2079 | (uint64_t)id << 32); | |
2080 | } | |
2081 | } | |
2082 | ||
2083 | if (phb) { | |
2084 | /* Replace "pci" with "pci@800000020000000" */ | |
2085 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2086 | } | |
2087 | ||
2088 | return NULL; | |
2089 | } | |
2090 | ||
23825581 EH |
2091 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2092 | { | |
28e02042 | 2093 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2094 | |
28e02042 | 2095 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2096 | } |
2097 | ||
2098 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2099 | { | |
28e02042 | 2100 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2101 | |
28e02042 DG |
2102 | g_free(spapr->kvm_type); |
2103 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2104 | } |
2105 | ||
2106 | static void spapr_machine_initfn(Object *obj) | |
2107 | { | |
2108 | object_property_add_str(obj, "kvm-type", | |
2109 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2110 | object_property_set_description(obj, "kvm-type", |
2111 | "Specifies the KVM virtualization mode (HV, PR)", | |
2112 | NULL); | |
23825581 EH |
2113 | } |
2114 | ||
87bbdd9c DG |
2115 | static void spapr_machine_finalizefn(Object *obj) |
2116 | { | |
2117 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2118 | ||
2119 | g_free(spapr->kvm_type); | |
2120 | } | |
2121 | ||
34316482 AK |
2122 | static void ppc_cpu_do_nmi_on_cpu(void *arg) |
2123 | { | |
2124 | CPUState *cs = arg; | |
2125 | ||
2126 | cpu_synchronize_state(cs); | |
2127 | ppc_cpu_do_system_reset(cs); | |
2128 | } | |
2129 | ||
2130 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2131 | { | |
2132 | CPUState *cs; | |
2133 | ||
2134 | CPU_FOREACH(cs) { | |
2135 | async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); | |
2136 | } | |
2137 | } | |
2138 | ||
c20d332a BR |
2139 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, |
2140 | uint32_t node, Error **errp) | |
2141 | { | |
2142 | sPAPRDRConnector *drc; | |
2143 | sPAPRDRConnectorClass *drck; | |
2144 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; | |
2145 | int i, fdt_offset, fdt_size; | |
2146 | void *fdt; | |
2147 | ||
2148 | /* | |
2149 | * Check for DRC connectors and send hotplug notification to the | |
2150 | * guest only in case of hotplugged memory. This allows cold plugged | |
2151 | * memory to be specified at boot time. | |
2152 | */ | |
2153 | if (!dev->hotplugged) { | |
2154 | return; | |
2155 | } | |
2156 | ||
2157 | for (i = 0; i < nr_lmbs; i++) { | |
2158 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2159 | addr/SPAPR_MEMORY_BLOCK_SIZE); | |
2160 | g_assert(drc); | |
2161 | ||
2162 | fdt = create_device_tree(&fdt_size); | |
2163 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2164 | SPAPR_MEMORY_BLOCK_SIZE); | |
2165 | ||
2166 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2167 | drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); | |
c20d332a BR |
2168 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2169 | } | |
0a417869 | 2170 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); |
c20d332a BR |
2171 | } |
2172 | ||
2173 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2174 | uint32_t node, Error **errp) | |
2175 | { | |
2176 | Error *local_err = NULL; | |
2177 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2178 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2179 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2180 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2181 | uint64_t align = memory_region_get_alignment(mr); | |
2182 | uint64_t size = memory_region_size(mr); | |
2183 | uint64_t addr; | |
2184 | ||
2185 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2186 | error_setg(&local_err, "Hotplugged memory size must be a multiple of " | |
2187 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
2188 | goto out; | |
2189 | } | |
2190 | ||
d6a9b0b8 | 2191 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2192 | if (local_err) { |
2193 | goto out; | |
2194 | } | |
2195 | ||
2196 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2197 | if (local_err) { | |
2198 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2199 | goto out; | |
2200 | } | |
2201 | ||
2202 | spapr_add_lmbs(dev, addr, size, node, &error_abort); | |
2203 | ||
2204 | out: | |
2205 | error_propagate(errp, local_err); | |
2206 | } | |
2207 | ||
2208 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, | |
2209 | DeviceState *dev, Error **errp) | |
2210 | { | |
2211 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
2212 | ||
2213 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 2214 | int node; |
c20d332a BR |
2215 | |
2216 | if (!smc->dr_lmb_enabled) { | |
2217 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
2218 | return; | |
2219 | } | |
2220 | node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); | |
2221 | if (*errp) { | |
2222 | return; | |
2223 | } | |
2224 | ||
b556854b BR |
2225 | /* |
2226 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
2227 | * memory-less node, but instead will silently add the memory | |
2228 | * to the first node that has some memory. This causes two | |
2229 | * unexpected behaviours for the user. | |
2230 | * | |
2231 | * - Memory gets hotplugged to a different node than what the user | |
2232 | * specified. | |
2233 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
2234 | * to memory-less node, a reboot will set things accordingly | |
2235 | * and the previously hotplugged memory now ends in the right node. | |
2236 | * This appears as if some memory moved from one node to another. | |
2237 | * | |
2238 | * So until kernel starts supporting memory hotplug to memory-less | |
2239 | * nodes, just prevent such attempts upfront in QEMU. | |
2240 | */ | |
2241 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
2242 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
2243 | node); | |
2244 | return; | |
2245 | } | |
2246 | ||
c20d332a BR |
2247 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
2248 | } | |
2249 | } | |
2250 | ||
2251 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, | |
2252 | DeviceState *dev, Error **errp) | |
2253 | { | |
2254 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2255 | error_setg(errp, "Memory hot unplug not supported by sPAPR"); | |
2256 | } | |
2257 | } | |
2258 | ||
2259 | static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, | |
2260 | DeviceState *dev) | |
2261 | { | |
2262 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2263 | return HOTPLUG_HANDLER(machine); | |
2264 | } | |
2265 | return NULL; | |
2266 | } | |
2267 | ||
20bb648d DG |
2268 | static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) |
2269 | { | |
2270 | /* Allocate to NUMA nodes on a "socket" basis (not that concept of | |
2271 | * socket means much for the paravirtualized PAPR platform) */ | |
2272 | return cpu_index / smp_threads / smp_cores; | |
2273 | } | |
2274 | ||
29ee3247 AK |
2275 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
2276 | { | |
2277 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 2278 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 2279 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 2280 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 2281 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
958db90c | 2282 | |
0eb9054c | 2283 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
2284 | |
2285 | /* | |
2286 | * We set up the default / latest behaviour here. The class_init | |
2287 | * functions for the specific versioned machine types can override | |
2288 | * these details for backwards compatibility | |
2289 | */ | |
958db90c MA |
2290 | mc->init = ppc_spapr_init; |
2291 | mc->reset = ppc_spapr_reset; | |
2292 | mc->block_default_type = IF_SCSI; | |
38b02bd8 | 2293 | mc->max_cpus = MAX_CPUMASK_BITS; |
958db90c | 2294 | mc->no_parallel = 1; |
5b2128d2 | 2295 | mc->default_boot_order = ""; |
a34944fe | 2296 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 2297 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 2298 | mc->has_dynamic_sysbus = true; |
e4024630 | 2299 | mc->pci_allow_0_address = true; |
c20d332a BR |
2300 | mc->get_hotplug_handler = spapr_get_hotpug_handler; |
2301 | hc->plug = spapr_machine_device_plug; | |
2302 | hc->unplug = spapr_machine_device_unplug; | |
20bb648d | 2303 | mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; |
00b4fbe2 | 2304 | |
fc9f38c3 | 2305 | smc->dr_lmb_enabled = true; |
71461b0f | 2306 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 2307 | nc->nmi_monitor_handler = spapr_nmi; |
29ee3247 AK |
2308 | } |
2309 | ||
2310 | static const TypeInfo spapr_machine_info = { | |
2311 | .name = TYPE_SPAPR_MACHINE, | |
2312 | .parent = TYPE_MACHINE, | |
4aee7362 | 2313 | .abstract = true, |
6ca1502e | 2314 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 2315 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 2316 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 2317 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 2318 | .class_init = spapr_machine_class_init, |
71461b0f AK |
2319 | .interfaces = (InterfaceInfo[]) { |
2320 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 2321 | { TYPE_NMI }, |
c20d332a | 2322 | { TYPE_HOTPLUG_HANDLER }, |
71461b0f AK |
2323 | { } |
2324 | }, | |
29ee3247 AK |
2325 | }; |
2326 | ||
fccbc785 | 2327 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
2328 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
2329 | void *data) \ | |
2330 | { \ | |
2331 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
2332 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
2333 | if (latest) { \ |
2334 | mc->alias = "pseries"; \ | |
2335 | mc->is_default = 1; \ | |
2336 | } \ | |
5013c547 DG |
2337 | } \ |
2338 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
2339 | { \ | |
2340 | MachineState *machine = MACHINE(obj); \ | |
2341 | spapr_machine_##suffix##_instance_options(machine); \ | |
2342 | } \ | |
2343 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
2344 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
2345 | .parent = TYPE_SPAPR_MACHINE, \ | |
2346 | .class_init = spapr_machine_##suffix##_class_init, \ | |
2347 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
2348 | }; \ | |
2349 | static void spapr_machine_register_##suffix(void) \ | |
2350 | { \ | |
2351 | type_register(&spapr_machine_##suffix##_info); \ | |
2352 | } \ | |
2353 | machine_init(spapr_machine_register_##suffix) | |
2354 | ||
4b23699c DG |
2355 | /* |
2356 | * pseries-2.6 | |
2357 | */ | |
2358 | static void spapr_machine_2_6_instance_options(MachineState *machine) | |
2359 | { | |
2360 | } | |
2361 | ||
2362 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
2363 | { | |
2364 | /* Defaults for the latest behaviour inherited from the base class */ | |
2365 | } | |
2366 | ||
2367 | DEFINE_SPAPR_MACHINE(2_6, "2.6", true); | |
2368 | ||
1c5f29bb DG |
2369 | /* |
2370 | * pseries-2.5 | |
2371 | */ | |
4b23699c DG |
2372 | #define SPAPR_COMPAT_2_5 \ |
2373 | HW_COMPAT_2_5 | |
2374 | ||
5013c547 | 2375 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 2376 | { |
5013c547 DG |
2377 | } |
2378 | ||
2379 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
2380 | { | |
57040d45 TH |
2381 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2382 | ||
4b23699c | 2383 | spapr_machine_2_6_class_options(mc); |
57040d45 | 2384 | smc->use_ohci_by_default = true; |
4b23699c | 2385 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
2386 | } |
2387 | ||
4b23699c | 2388 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
2389 | |
2390 | /* | |
2391 | * pseries-2.4 | |
2392 | */ | |
80fd50f9 CH |
2393 | #define SPAPR_COMPAT_2_4 \ |
2394 | HW_COMPAT_2_4 | |
2395 | ||
5013c547 | 2396 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 2397 | { |
5013c547 DG |
2398 | spapr_machine_2_5_instance_options(machine); |
2399 | } | |
1c5f29bb | 2400 | |
5013c547 DG |
2401 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
2402 | { | |
fc9f38c3 DG |
2403 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2404 | ||
2405 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 2406 | smc->dr_lmb_enabled = false; |
f949b4e5 | 2407 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
2408 | } |
2409 | ||
fccbc785 | 2410 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
2411 | |
2412 | /* | |
2413 | * pseries-2.3 | |
2414 | */ | |
38ff32c6 | 2415 | #define SPAPR_COMPAT_2_3 \ |
80fd50f9 | 2416 | SPAPR_COMPAT_2_4 \ |
7619c7b0 MR |
2417 | HW_COMPAT_2_3 \ |
2418 | {\ | |
2419 | .driver = "spapr-pci-host-bridge",\ | |
2420 | .property = "dynamic-reconfiguration",\ | |
2421 | .value = "off",\ | |
2422 | }, | |
38ff32c6 | 2423 | |
5013c547 | 2424 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 2425 | { |
5013c547 | 2426 | spapr_machine_2_4_instance_options(machine); |
ff14e817 | 2427 | savevm_skip_section_footers(); |
13d16814 | 2428 | global_state_set_optional(); |
d25228e7 JW |
2429 | } |
2430 | ||
5013c547 | 2431 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 2432 | { |
fc9f38c3 | 2433 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 2434 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 2435 | } |
fccbc785 | 2436 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 2437 | |
1c5f29bb DG |
2438 | /* |
2439 | * pseries-2.2 | |
2440 | */ | |
2441 | ||
2442 | #define SPAPR_COMPAT_2_2 \ | |
2443 | SPAPR_COMPAT_2_3 \ | |
2444 | HW_COMPAT_2_2 \ | |
2445 | {\ | |
2446 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2447 | .property = "mem_win_size",\ | |
2448 | .value = "0x20000000",\ | |
2449 | }, | |
2450 | ||
5013c547 | 2451 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 2452 | { |
5013c547 | 2453 | spapr_machine_2_3_instance_options(machine); |
1c5f29bb DG |
2454 | } |
2455 | ||
5013c547 | 2456 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 2457 | { |
fc9f38c3 | 2458 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 2459 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 2460 | } |
fccbc785 | 2461 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 2462 | |
1c5f29bb DG |
2463 | /* |
2464 | * pseries-2.1 | |
2465 | */ | |
2466 | #define SPAPR_COMPAT_2_1 \ | |
2467 | SPAPR_COMPAT_2_2 \ | |
2468 | HW_COMPAT_2_1 | |
3dab0244 | 2469 | |
5013c547 | 2470 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 2471 | { |
5013c547 | 2472 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 2473 | } |
d25228e7 | 2474 | |
5013c547 | 2475 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 2476 | { |
fc9f38c3 | 2477 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 2478 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 2479 | } |
fccbc785 | 2480 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 2481 | |
29ee3247 | 2482 | static void spapr_machine_register_types(void) |
9fdf0c29 | 2483 | { |
29ee3247 | 2484 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
2485 | } |
2486 | ||
29ee3247 | 2487 | type_init(spapr_machine_register_types) |