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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
e35704ba | 30 | #include "sysemu/numa.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
03dd024f | 32 | #include "qemu/log.h" |
71461b0f | 33 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 34 | #include "elf.h" |
1422e32d | 35 | #include "net/net.h" |
ad440b4a | 36 | #include "sysemu/device_tree.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 | 38 | #include "sysemu/cpus.h" |
b3946626 | 39 | #include "sysemu/hw_accel.h" |
e97c3636 | 40 | #include "kvm_ppc.h" |
c4b63b7c | 41 | #include "migration/misc.h" |
84a899de | 42 | #include "migration/global_state.h" |
f2a8f0a6 | 43 | #include "migration/register.h" |
4be21d56 | 44 | #include "mmu-hash64.h" |
b4db5413 | 45 | #include "mmu-book3s-v3.h" |
3794d548 | 46 | #include "qom/cpu.h" |
9fdf0c29 DG |
47 | |
48 | #include "hw/boards.h" | |
0d09e41a | 49 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
50 | #include "hw/loader.h" |
51 | ||
7804c353 | 52 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
53 | #include "hw/ppc/spapr.h" |
54 | #include "hw/ppc/spapr_vio.h" | |
55 | #include "hw/pci-host/spapr.h" | |
56 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 57 | #include "hw/pci/msi.h" |
9fdf0c29 | 58 | |
83c9f4ca | 59 | #include "hw/pci/pci.h" |
71461b0f AK |
60 | #include "hw/scsi/scsi.h" |
61 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 62 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 63 | |
022c62cb | 64 | #include "exec/address-spaces.h" |
35139a59 | 65 | #include "hw/usb.h" |
1de7afc9 | 66 | #include "qemu/config-file.h" |
135a129a | 67 | #include "qemu/error-report.h" |
2a6593cb | 68 | #include "trace.h" |
34316482 | 69 | #include "hw/nmi.h" |
6449da45 | 70 | #include "hw/intc/intc.h" |
890c2b77 | 71 | |
68a27b20 | 72 | #include "hw/compat.h" |
f348b6d1 | 73 | #include "qemu/cutils.h" |
94a94e4c | 74 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 75 | #include "qmp-commands.h" |
68a27b20 | 76 | |
9fdf0c29 DG |
77 | #include <libfdt.h> |
78 | ||
4d8d5467 BH |
79 | /* SLOF memory layout: |
80 | * | |
81 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
82 | * device-tree, then position SLOF itself 31M below that | |
83 | * | |
84 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
85 | * and more | |
86 | * | |
87 | * We load our kernel at 4M, leaving space for SLOF initial image | |
88 | */ | |
38b02bd8 | 89 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 90 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 91 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
92 | #define FW_MAX_SIZE 0x400000 |
93 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
94 | #define FW_OVERHEAD 0x2800000 |
95 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 96 | |
4d8d5467 | 97 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 98 | |
0c103f8e DG |
99 | #define PHANDLE_XICP 0x00001111 |
100 | ||
7f763a5d DG |
101 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
102 | ||
71cd4dac CLG |
103 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
104 | const char *type_ics, | |
105 | int nr_irqs, Error **errp) | |
c04d6cfa | 106 | { |
175d2aa0 | 107 | Error *local_err = NULL; |
71cd4dac | 108 | Object *obj; |
4e4169f7 | 109 | |
71cd4dac | 110 | obj = object_new(type_ics); |
175d2aa0 | 111 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
ad265631 GK |
112 | object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
113 | &error_abort); | |
175d2aa0 GK |
114 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
115 | if (local_err) { | |
116 | goto error; | |
117 | } | |
71cd4dac | 118 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
119 | if (local_err) { |
120 | goto error; | |
4e4169f7 | 121 | } |
4e4169f7 | 122 | |
71cd4dac | 123 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
124 | |
125 | error: | |
126 | error_propagate(errp, local_err); | |
127 | return NULL; | |
c04d6cfa AL |
128 | } |
129 | ||
46f7afa3 GK |
130 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
131 | { | |
132 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
133 | * and newer QEMUs don't even have them. In both cases, we don't want | |
134 | * to send anything on the wire. | |
135 | */ | |
136 | return false; | |
137 | } | |
138 | ||
139 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
140 | .name = "icp/server", | |
141 | .version_id = 1, | |
142 | .minimum_version_id = 1, | |
143 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
144 | .fields = (VMStateField[]) { | |
145 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
146 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
147 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
148 | VMSTATE_END_OF_LIST() | |
149 | }, | |
150 | }; | |
151 | ||
152 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
153 | { | |
154 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
155 | (void *)(uintptr_t) i); | |
156 | } | |
157 | ||
158 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
159 | { | |
160 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
161 | (void *)(uintptr_t) i); | |
162 | } | |
163 | ||
164 | static inline int xics_max_server_number(void) | |
165 | { | |
166 | return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); | |
167 | } | |
168 | ||
71cd4dac | 169 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 170 | { |
71cd4dac | 171 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
46f7afa3 | 172 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
c04d6cfa | 173 | |
11ad93f6 | 174 | if (kvm_enabled()) { |
2192a930 | 175 | if (machine_kernel_irqchip_allowed(machine) && |
71cd4dac CLG |
176 | !xics_kvm_init(spapr, errp)) { |
177 | spapr->icp_type = TYPE_KVM_ICP; | |
3d85885a | 178 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); |
11ad93f6 | 179 | } |
71cd4dac | 180 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
3d85885a GK |
181 | error_prepend(errp, "kernel_irqchip requested but unavailable: "); |
182 | return; | |
11ad93f6 DG |
183 | } |
184 | } | |
185 | ||
71cd4dac | 186 | if (!spapr->ics) { |
f63ebfe0 | 187 | xics_spapr_init(spapr); |
71cd4dac CLG |
188 | spapr->icp_type = TYPE_ICP; |
189 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); | |
3d85885a GK |
190 | if (!spapr->ics) { |
191 | return; | |
192 | } | |
c04d6cfa | 193 | } |
46f7afa3 GK |
194 | |
195 | if (smc->pre_2_10_has_unused_icps) { | |
196 | int i; | |
197 | ||
198 | for (i = 0; i < xics_max_server_number(); i++) { | |
199 | /* Dummy entries get deregistered when real ICPState objects | |
200 | * are registered during CPU core hotplug. | |
201 | */ | |
202 | pre_2_10_vmstate_register_dummy_icp(i); | |
203 | } | |
204 | } | |
c04d6cfa AL |
205 | } |
206 | ||
833d4668 AK |
207 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
208 | int smt_threads) | |
209 | { | |
210 | int i, ret = 0; | |
211 | uint32_t servers_prop[smt_threads]; | |
212 | uint32_t gservers_prop[smt_threads * 2]; | |
213 | int index = ppc_get_vcpu_dt_id(cpu); | |
214 | ||
d6e166c0 DG |
215 | if (cpu->compat_pvr) { |
216 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
217 | if (ret < 0) { |
218 | return ret; | |
219 | } | |
220 | } | |
221 | ||
833d4668 AK |
222 | /* Build interrupt servers and gservers properties */ |
223 | for (i = 0; i < smt_threads; i++) { | |
224 | servers_prop[i] = cpu_to_be32(index + i); | |
225 | /* Hack, direct the group queues back to cpu 0 */ | |
226 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
227 | gservers_prop[i*2 + 1] = 0; | |
228 | } | |
229 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
230 | servers_prop, sizeof(servers_prop)); | |
231 | if (ret < 0) { | |
232 | return ret; | |
233 | } | |
234 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
235 | gservers_prop, sizeof(gservers_prop)); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
99861ecb | 240 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 241 | { |
0da6f3fe BR |
242 | int index = ppc_get_vcpu_dt_id(cpu); |
243 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
244 | cpu_to_be32(0x0), | |
245 | cpu_to_be32(0x0), | |
246 | cpu_to_be32(0x0), | |
15f8b142 | 247 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
248 | cpu_to_be32(index)}; |
249 | ||
250 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 251 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 252 | sizeof(associativity)); |
0da6f3fe BR |
253 | } |
254 | ||
86d5771a | 255 | /* Populate the "ibm,pa-features" property */ |
e957f6a9 SB |
256 | static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, |
257 | bool legacy_guest) | |
86d5771a SB |
258 | { |
259 | uint8_t pa_features_206[] = { 6, 0, | |
260 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
261 | uint8_t pa_features_207[] = { 24, 0, | |
262 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
263 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
264 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
265 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
266 | uint8_t pa_features_300[] = { 66, 0, |
267 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
268 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
269 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
270 | /* 6: DS207 */ | |
271 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
272 | /* 16: Vector */ | |
86d5771a | 273 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 274 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 275 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
276 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
277 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
278 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
279 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
280 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
281 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
282 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
283 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
284 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
285 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
286 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
287 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
288 | /* 60: NM atomic, 62: RNG */ | |
289 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
290 | }; | |
86d5771a SB |
291 | uint8_t *pa_features; |
292 | size_t pa_size; | |
293 | ||
294 | switch (POWERPC_MMU_VER(env->mmu_model)) { | |
295 | case POWERPC_MMU_VER_2_06: | |
296 | pa_features = pa_features_206; | |
297 | pa_size = sizeof(pa_features_206); | |
298 | break; | |
299 | case POWERPC_MMU_VER_2_07: | |
300 | pa_features = pa_features_207; | |
301 | pa_size = sizeof(pa_features_207); | |
302 | break; | |
303 | case POWERPC_MMU_VER_3_00: | |
304 | pa_features = pa_features_300; | |
305 | pa_size = sizeof(pa_features_300); | |
306 | break; | |
307 | default: | |
308 | return; | |
309 | } | |
310 | ||
311 | if (env->ci_large_pages) { | |
312 | /* | |
313 | * Note: we keep CI large pages off by default because a 64K capable | |
314 | * guest provisioned with large pages might otherwise try to map a qemu | |
315 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
316 | * even if that qemu runs on a 4k host. | |
317 | * We dd this bit back here if we are confident this is not an issue | |
318 | */ | |
319 | pa_features[3] |= 0x20; | |
320 | } | |
321 | if (kvmppc_has_cap_htm() && pa_size > 24) { | |
322 | pa_features[24] |= 0x80; /* Transactional memory support */ | |
323 | } | |
e957f6a9 SB |
324 | if (legacy_guest && pa_size > 40) { |
325 | /* Workaround for broken kernels that attempt (guest) radix | |
326 | * mode when they can't handle it, if they see the radix bit set | |
327 | * in pa-features. So hide it from them. */ | |
328 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
329 | } | |
86d5771a SB |
330 | |
331 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
332 | } | |
333 | ||
28e02042 | 334 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 335 | { |
82677ed2 AK |
336 | int ret = 0, offset, cpus_offset; |
337 | CPUState *cs; | |
6e806cc3 BR |
338 | char cpu_model[32]; |
339 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 340 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 341 | |
82677ed2 AK |
342 | CPU_FOREACH(cs) { |
343 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
e957f6a9 | 344 | CPUPPCState *env = &cpu->env; |
82677ed2 AK |
345 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
346 | int index = ppc_get_vcpu_dt_id(cpu); | |
12dbeb16 | 347 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
6e806cc3 | 348 | |
0f20ba62 | 349 | if ((index % smt) != 0) { |
6e806cc3 BR |
350 | continue; |
351 | } | |
352 | ||
82677ed2 | 353 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 354 | |
82677ed2 AK |
355 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
356 | if (cpus_offset < 0) { | |
357 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
358 | "cpus"); | |
359 | if (cpus_offset < 0) { | |
360 | return cpus_offset; | |
361 | } | |
362 | } | |
363 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 364 | if (offset < 0) { |
82677ed2 AK |
365 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
366 | if (offset < 0) { | |
367 | return offset; | |
368 | } | |
6e806cc3 BR |
369 | } |
370 | ||
7f763a5d DG |
371 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
372 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
373 | if (ret < 0) { |
374 | return ret; | |
375 | } | |
833d4668 | 376 | |
99861ecb IM |
377 | if (nb_numa_nodes > 1) { |
378 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
379 | if (ret < 0) { | |
380 | return ret; | |
381 | } | |
0da6f3fe BR |
382 | } |
383 | ||
12dbeb16 | 384 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
385 | if (ret < 0) { |
386 | return ret; | |
387 | } | |
e957f6a9 SB |
388 | |
389 | spapr_populate_pa_features(env, fdt, offset, | |
390 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
391 | } |
392 | return ret; | |
393 | } | |
394 | ||
b082d65a AK |
395 | static hwaddr spapr_node0_size(void) |
396 | { | |
fb164994 DG |
397 | MachineState *machine = MACHINE(qdev_get_machine()); |
398 | ||
b082d65a AK |
399 | if (nb_numa_nodes) { |
400 | int i; | |
401 | for (i = 0; i < nb_numa_nodes; ++i) { | |
402 | if (numa_info[i].node_mem) { | |
fb164994 DG |
403 | return MIN(pow2floor(numa_info[i].node_mem), |
404 | machine->ram_size); | |
b082d65a AK |
405 | } |
406 | } | |
407 | } | |
fb164994 | 408 | return machine->ram_size; |
b082d65a AK |
409 | } |
410 | ||
a1d59c0f AK |
411 | static void add_str(GString *s, const gchar *s1) |
412 | { | |
413 | g_string_append_len(s, s1, strlen(s1) + 1); | |
414 | } | |
7f763a5d | 415 | |
03d196b7 | 416 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
417 | hwaddr size) |
418 | { | |
419 | uint32_t associativity[] = { | |
420 | cpu_to_be32(0x4), /* length */ | |
421 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 422 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
423 | }; |
424 | char mem_name[32]; | |
425 | uint64_t mem_reg_property[2]; | |
426 | int off; | |
427 | ||
428 | mem_reg_property[0] = cpu_to_be64(start); | |
429 | mem_reg_property[1] = cpu_to_be64(size); | |
430 | ||
431 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
432 | off = fdt_add_subnode(fdt, 0, mem_name); | |
433 | _FDT(off); | |
434 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
435 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
436 | sizeof(mem_reg_property)))); | |
437 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
438 | sizeof(associativity)))); | |
03d196b7 | 439 | return off; |
26a8c353 AK |
440 | } |
441 | ||
28e02042 | 442 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 443 | { |
fb164994 | 444 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
445 | hwaddr mem_start, node_size; |
446 | int i, nb_nodes = nb_numa_nodes; | |
447 | NodeInfo *nodes = numa_info; | |
448 | NodeInfo ramnode; | |
449 | ||
450 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
451 | if (!nb_numa_nodes) { | |
452 | nb_nodes = 1; | |
fb164994 | 453 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 454 | nodes = &ramnode; |
5fe269b1 | 455 | } |
7f763a5d | 456 | |
7db8a127 AK |
457 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
458 | if (!nodes[i].node_mem) { | |
459 | continue; | |
460 | } | |
fb164994 | 461 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
462 | node_size = 0; |
463 | } else { | |
7db8a127 | 464 | node_size = nodes[i].node_mem; |
fb164994 DG |
465 | if (node_size > machine->ram_size - mem_start) { |
466 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
467 | } |
468 | } | |
7db8a127 AK |
469 | if (!mem_start) { |
470 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 471 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
472 | mem_start += spapr->rma_size; |
473 | node_size -= spapr->rma_size; | |
474 | } | |
6010818c AK |
475 | for ( ; node_size; ) { |
476 | hwaddr sizetmp = pow2floor(node_size); | |
477 | ||
478 | /* mem_start != 0 here */ | |
479 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
480 | sizetmp = 1ULL << ctzl(mem_start); | |
481 | } | |
482 | ||
483 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
484 | node_size -= sizetmp; | |
485 | mem_start += sizetmp; | |
486 | } | |
7f763a5d DG |
487 | } |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
0da6f3fe BR |
492 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
493 | sPAPRMachineState *spapr) | |
494 | { | |
495 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
496 | CPUPPCState *env = &cpu->env; | |
497 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
498 | int index = ppc_get_vcpu_dt_id(cpu); | |
499 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
500 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
501 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
502 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
503 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
504 | uint32_t page_sizes_prop[64]; | |
505 | size_t page_sizes_prop_size; | |
22419c2a | 506 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 507 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
12dbeb16 | 508 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
af81cf32 | 509 | sPAPRDRConnector *drc; |
af81cf32 | 510 | int drc_index; |
c64abd1f SB |
511 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
512 | int i; | |
af81cf32 | 513 | |
fbf55397 | 514 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 515 | if (drc) { |
0b55aa91 | 516 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
517 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
518 | } | |
0da6f3fe BR |
519 | |
520 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
521 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
522 | ||
523 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
524 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
525 | env->dcache_line_size))); | |
526 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
527 | env->dcache_line_size))); | |
528 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
529 | env->icache_line_size))); | |
530 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
531 | env->icache_line_size))); | |
532 | ||
533 | if (pcc->l1_dcache_size) { | |
534 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
535 | pcc->l1_dcache_size))); | |
536 | } else { | |
3dc6f869 | 537 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
538 | } |
539 | if (pcc->l1_icache_size) { | |
540 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
541 | pcc->l1_icache_size))); | |
542 | } else { | |
3dc6f869 | 543 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
544 | } |
545 | ||
546 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
547 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 548 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
549 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
550 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
551 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
552 | ||
553 | if (env->spr_cb[SPR_PURR].oea_read) { | |
554 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
555 | } | |
556 | ||
557 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
558 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
559 | segs, sizeof(segs)))); | |
560 | } | |
561 | ||
562 | /* Advertise VMX/VSX (vector extensions) if available | |
563 | * 0 / no property == no vector extensions | |
564 | * 1 == VMX / Altivec available | |
565 | * 2 == VSX available */ | |
566 | if (env->insns_flags & PPC_ALTIVEC) { | |
567 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
568 | ||
569 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
570 | } | |
571 | ||
572 | /* Advertise DFP (Decimal Floating Point) if available | |
573 | * 0 / no property == no DFP | |
574 | * 1 == DFP available */ | |
575 | if (env->insns_flags2 & PPC2_DFP) { | |
576 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
577 | } | |
578 | ||
3654fa95 | 579 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
580 | sizeof(page_sizes_prop)); |
581 | if (page_sizes_prop_size) { | |
582 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
583 | page_sizes_prop, page_sizes_prop_size))); | |
584 | } | |
585 | ||
e957f6a9 | 586 | spapr_populate_pa_features(env, fdt, offset, false); |
90da0d5a | 587 | |
0da6f3fe | 588 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 589 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
590 | |
591 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
592 | pft_size_prop, sizeof(pft_size_prop)))); | |
593 | ||
99861ecb IM |
594 | if (nb_numa_nodes > 1) { |
595 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
596 | } | |
0da6f3fe | 597 | |
12dbeb16 | 598 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
599 | |
600 | if (pcc->radix_page_info) { | |
601 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
602 | radix_AP_encodings[i] = | |
603 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
604 | } | |
605 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
606 | radix_AP_encodings, | |
607 | pcc->radix_page_info->count * | |
608 | sizeof(radix_AP_encodings[0])))); | |
609 | } | |
0da6f3fe BR |
610 | } |
611 | ||
612 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
613 | { | |
614 | CPUState *cs; | |
615 | int cpus_offset; | |
616 | char *nodename; | |
617 | int smt = kvmppc_smt_threads(); | |
618 | ||
619 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
620 | _FDT(cpus_offset); | |
621 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
622 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
623 | ||
624 | /* | |
625 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
626 | * created by fdt_add_subnode() end up in the right order in FDT | |
627 | * for the guest kernel the enumerate the CPUs correctly. | |
628 | */ | |
629 | CPU_FOREACH_REVERSE(cs) { | |
630 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
631 | int index = ppc_get_vcpu_dt_id(cpu); | |
632 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
633 | int offset; | |
634 | ||
635 | if ((index % smt) != 0) { | |
636 | continue; | |
637 | } | |
638 | ||
639 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
640 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
641 | g_free(nodename); | |
642 | _FDT(offset); | |
643 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
644 | } | |
645 | ||
646 | } | |
647 | ||
03d196b7 BR |
648 | /* |
649 | * Adds ibm,dynamic-reconfiguration-memory node. | |
650 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
651 | * of this device tree node. | |
652 | */ | |
653 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
654 | { | |
655 | MachineState *machine = MACHINE(spapr); | |
656 | int ret, i, offset; | |
657 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
658 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
659 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
660 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
661 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
662 | lmb_size; | |
03d196b7 | 663 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 664 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 665 | |
16c25aef | 666 | /* |
d0e5a8f2 | 667 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 668 | */ |
d0e5a8f2 | 669 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
670 | return 0; |
671 | } | |
672 | ||
ef001f06 TH |
673 | /* |
674 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
675 | * or ibm,associativity-lookup-arrays | |
676 | */ | |
677 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
678 | * sizeof(uint32_t); | |
03d196b7 BR |
679 | cur_index = int_buf = g_malloc0(buf_len); |
680 | ||
681 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
682 | ||
683 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
684 | sizeof(prop_lmb_size)); | |
685 | if (ret < 0) { | |
686 | goto out; | |
687 | } | |
688 | ||
689 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
690 | if (ret < 0) { | |
691 | goto out; | |
692 | } | |
693 | ||
694 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
695 | if (ret < 0) { | |
696 | goto out; | |
697 | } | |
698 | ||
699 | /* ibm,dynamic-memory */ | |
700 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
701 | cur_index++; | |
702 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 703 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
704 | uint32_t *dynamic_memory = cur_index; |
705 | ||
d0e5a8f2 BR |
706 | if (i >= hotplug_lmb_start) { |
707 | sPAPRDRConnector *drc; | |
d0e5a8f2 | 708 | |
fbf55397 | 709 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 710 | g_assert(drc); |
d0e5a8f2 BR |
711 | |
712 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
713 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 714 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 BR |
715 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
716 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
717 | if (memory_region_present(get_system_memory(), addr)) { | |
718 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
719 | } else { | |
720 | dynamic_memory[5] = cpu_to_be32(0); | |
721 | } | |
03d196b7 | 722 | } else { |
d0e5a8f2 BR |
723 | /* |
724 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
725 | * hotplug memory region -- all these are marked as reserved | |
726 | * and as having no valid DRC. | |
727 | */ | |
728 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
729 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
730 | dynamic_memory[2] = cpu_to_be32(0); | |
731 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
732 | dynamic_memory[4] = cpu_to_be32(-1); | |
733 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
734 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
735 | } |
736 | ||
737 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
738 | } | |
739 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
740 | if (ret < 0) { | |
741 | goto out; | |
742 | } | |
743 | ||
744 | /* ibm,associativity-lookup-arrays */ | |
745 | cur_index = int_buf; | |
6663864e | 746 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
747 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
748 | cur_index += 2; | |
6663864e | 749 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
750 | uint32_t associativity[] = { |
751 | cpu_to_be32(0x0), | |
752 | cpu_to_be32(0x0), | |
753 | cpu_to_be32(0x0), | |
754 | cpu_to_be32(i) | |
755 | }; | |
756 | memcpy(cur_index, associativity, sizeof(associativity)); | |
757 | cur_index += 4; | |
758 | } | |
759 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
760 | (cur_index - int_buf) * sizeof(uint32_t)); | |
761 | out: | |
762 | g_free(int_buf); | |
763 | return ret; | |
764 | } | |
765 | ||
6787d27b MR |
766 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
767 | sPAPROptionVector *ov5_updates) | |
768 | { | |
769 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 770 | int ret = 0, offset; |
6787d27b MR |
771 | |
772 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
773 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
774 | g_assert(smc->dr_lmb_enabled); | |
775 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
776 | if (ret) { |
777 | goto out; | |
778 | } | |
6787d27b MR |
779 | } |
780 | ||
b8768042 CLG |
781 | /* /interrupt controller */ |
782 | if (!spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)) { | |
783 | spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); | |
784 | } | |
785 | ||
417ece33 MR |
786 | offset = fdt_path_offset(fdt, "/chosen"); |
787 | if (offset < 0) { | |
788 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
789 | if (offset < 0) { | |
790 | return offset; | |
791 | } | |
792 | } | |
793 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
794 | "ibm,architecture-vec-5"); | |
795 | ||
796 | out: | |
6787d27b MR |
797 | return ret; |
798 | } | |
799 | ||
03d196b7 BR |
800 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
801 | target_ulong addr, target_ulong size, | |
6787d27b | 802 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
803 | { |
804 | void *fdt, *fdt_skel; | |
805 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 BR |
806 | |
807 | size -= sizeof(hdr); | |
808 | ||
b8768042 | 809 | /* Create skeleton */ |
03d196b7 BR |
810 | fdt_skel = g_malloc0(size); |
811 | _FDT((fdt_create(fdt_skel, size))); | |
812 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
813 | _FDT((fdt_end_node(fdt_skel))); | |
814 | _FDT((fdt_finish(fdt_skel))); | |
815 | fdt = g_malloc0(size); | |
816 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
817 | g_free(fdt_skel); | |
818 | ||
819 | /* Fixup cpu nodes */ | |
5b120785 | 820 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 821 | |
6787d27b MR |
822 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
823 | return -1; | |
03d196b7 BR |
824 | } |
825 | ||
826 | /* Pack resulting tree */ | |
827 | _FDT((fdt_pack(fdt))); | |
828 | ||
829 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
830 | trace_spapr_cas_failed(size); | |
831 | return -1; | |
832 | } | |
833 | ||
834 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
835 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
836 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
837 | g_free(fdt); | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
3f5dabce DG |
842 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
843 | { | |
844 | int rtas; | |
845 | GString *hypertas = g_string_sized_new(256); | |
846 | GString *qemu_hypertas = g_string_sized_new(256); | |
847 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
848 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
849 | memory_region_size(&spapr->hotplug_memory.mr); | |
850 | uint32_t lrdr_capacity[] = { | |
851 | cpu_to_be32(max_hotplug_addr >> 32), | |
852 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
853 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
854 | cpu_to_be32(max_cpus / smp_threads), | |
855 | }; | |
856 | ||
857 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
858 | ||
859 | /* hypertas */ | |
860 | add_str(hypertas, "hcall-pft"); | |
861 | add_str(hypertas, "hcall-term"); | |
862 | add_str(hypertas, "hcall-dabr"); | |
863 | add_str(hypertas, "hcall-interrupt"); | |
864 | add_str(hypertas, "hcall-tce"); | |
865 | add_str(hypertas, "hcall-vio"); | |
866 | add_str(hypertas, "hcall-splpar"); | |
867 | add_str(hypertas, "hcall-bulk"); | |
868 | add_str(hypertas, "hcall-set-mode"); | |
869 | add_str(hypertas, "hcall-sprg0"); | |
870 | add_str(hypertas, "hcall-copy"); | |
871 | add_str(hypertas, "hcall-debug"); | |
872 | add_str(qemu_hypertas, "hcall-memop1"); | |
873 | ||
874 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
875 | add_str(hypertas, "hcall-multi-tce"); | |
876 | } | |
30f4b05b DG |
877 | |
878 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
879 | add_str(hypertas, "hcall-hpt-resize"); | |
880 | } | |
881 | ||
3f5dabce DG |
882 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
883 | hypertas->str, hypertas->len)); | |
884 | g_string_free(hypertas, TRUE); | |
885 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
886 | qemu_hypertas->str, qemu_hypertas->len)); | |
887 | g_string_free(qemu_hypertas, TRUE); | |
888 | ||
889 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
890 | refpoints, sizeof(refpoints))); | |
891 | ||
892 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
893 | RTAS_ERROR_LOG_MAX)); | |
894 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
895 | RTAS_EVENT_SCAN_RATE)); | |
896 | ||
897 | if (msi_nonbroken) { | |
898 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
899 | } | |
900 | ||
901 | /* | |
902 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
903 | * back to the guest cpu. | |
904 | * | |
905 | * While an additional ibm,extended-os-term property indicates | |
906 | * that rtas call return will always occur. Set this property. | |
907 | */ | |
908 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
909 | ||
910 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
911 | lrdr_capacity, sizeof(lrdr_capacity))); | |
912 | ||
913 | spapr_dt_rtas_tokens(fdt, rtas); | |
914 | } | |
915 | ||
9fb4541f SB |
916 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
917 | * that the guest may request and thus the valid values for bytes 24..26 of | |
918 | * option vector 5: */ | |
919 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
920 | { | |
545d6e2b SJS |
921 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
922 | ||
f2b14e3a CLG |
923 | char val[2 * 4] = { |
924 | 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ | |
9fb4541f SB |
925 | 24, 0x00, /* Hash/Radix, filled in below. */ |
926 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
927 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
928 | }; | |
929 | ||
930 | if (kvm_enabled()) { | |
931 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { | |
f2b14e3a | 932 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 933 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 934 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 935 | } else { |
f2b14e3a | 936 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
937 | } |
938 | } else { | |
545d6e2b SJS |
939 | if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { |
940 | /* V3 MMU supports both hash and radix (with dynamic switching) */ | |
f2b14e3a | 941 | val[3] = 0xC0; |
545d6e2b SJS |
942 | } else { |
943 | /* Otherwise we can only do hash */ | |
f2b14e3a | 944 | val[3] = 0x00; |
545d6e2b | 945 | } |
9fb4541f SB |
946 | } |
947 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
948 | val, sizeof(val))); | |
949 | } | |
950 | ||
7c866c6a DG |
951 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
952 | { | |
953 | MachineState *machine = MACHINE(spapr); | |
954 | int chosen; | |
955 | const char *boot_device = machine->boot_order; | |
956 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
957 | size_t cb = 0; | |
958 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
959 | |
960 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
961 | ||
7c866c6a DG |
962 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
963 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
964 | spapr->initrd_base)); | |
965 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
966 | spapr->initrd_base + spapr->initrd_size)); | |
967 | ||
968 | if (spapr->kernel_size) { | |
969 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
970 | cpu_to_be64(spapr->kernel_size) }; | |
971 | ||
972 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
973 | &kprop, sizeof(kprop))); | |
974 | if (spapr->kernel_le) { | |
975 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
976 | } | |
977 | } | |
978 | if (boot_menu) { | |
979 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
980 | } | |
981 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
982 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
983 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
984 | ||
985 | if (cb && bootlist) { | |
986 | int i; | |
987 | ||
988 | for (i = 0; i < cb; i++) { | |
989 | if (bootlist[i] == '\n') { | |
990 | bootlist[i] = ' '; | |
991 | } | |
992 | } | |
993 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
994 | } | |
995 | ||
996 | if (boot_device && strlen(boot_device)) { | |
997 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
998 | } | |
999 | ||
1000 | if (!spapr->has_graphics && stdout_path) { | |
1001 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
1002 | } | |
1003 | ||
9fb4541f SB |
1004 | spapr_dt_ov5_platform_support(fdt, chosen); |
1005 | ||
7c866c6a DG |
1006 | g_free(stdout_path); |
1007 | g_free(bootlist); | |
1008 | } | |
1009 | ||
fca5f2dc DG |
1010 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1011 | { | |
1012 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1013 | * KVM to work under pHyp with some guest co-operation */ | |
1014 | int hypervisor; | |
1015 | uint8_t hypercall[16]; | |
1016 | ||
1017 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1018 | /* indicate KVM hypercall interface */ | |
1019 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1020 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1021 | /* | |
1022 | * Older KVM versions with older guest kernels were broken | |
1023 | * with the magic page, don't allow the guest to map it. | |
1024 | */ | |
1025 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1026 | sizeof(hypercall))) { | |
1027 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1028 | hypercall, sizeof(hypercall))); | |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | ||
997b6cfc DG |
1033 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1034 | hwaddr rtas_addr, | |
1035 | hwaddr rtas_size) | |
a3467baa | 1036 | { |
5b2128d2 | 1037 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c0c47e3 | 1038 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1039 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1040 | int ret; |
a3467baa | 1041 | void *fdt; |
3384f95c | 1042 | sPAPRPHBState *phb; |
398a0bd5 | 1043 | char *buf; |
a3467baa | 1044 | |
398a0bd5 DG |
1045 | fdt = g_malloc0(FDT_MAX_SIZE); |
1046 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1047 | |
398a0bd5 DG |
1048 | /* Root node */ |
1049 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1050 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1051 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1052 | ||
1053 | /* | |
1054 | * Add info to guest to indentify which host is it being run on | |
1055 | * and what is the uuid of the guest | |
1056 | */ | |
1057 | if (kvmppc_get_host_model(&buf)) { | |
1058 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1059 | g_free(buf); | |
1060 | } | |
1061 | if (kvmppc_get_host_serial(&buf)) { | |
1062 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1063 | g_free(buf); | |
1064 | } | |
1065 | ||
1066 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1067 | ||
1068 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1069 | if (qemu_uuid_set) { | |
1070 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1071 | } | |
1072 | g_free(buf); | |
1073 | ||
1074 | if (qemu_get_vm_name()) { | |
1075 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1076 | qemu_get_vm_name())); | |
1077 | } | |
1078 | ||
1079 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1080 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1081 | |
e8f986fc BR |
1082 | ret = spapr_populate_memory(spapr, fdt); |
1083 | if (ret < 0) { | |
ce9863b7 | 1084 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1085 | exit(1); |
7f763a5d DG |
1086 | } |
1087 | ||
bf5a6696 DG |
1088 | /* /vdevice */ |
1089 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1090 | |
4d9392be TH |
1091 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1092 | ret = spapr_rng_populate_dt(fdt); | |
1093 | if (ret < 0) { | |
ce9863b7 | 1094 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1095 | exit(1); |
1096 | } | |
1097 | } | |
1098 | ||
3384f95c | 1099 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1100 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1101 | if (ret < 0) { |
1102 | error_report("couldn't setup PCI devices in fdt"); | |
1103 | exit(1); | |
1104 | } | |
3384f95c DG |
1105 | } |
1106 | ||
0da6f3fe BR |
1107 | /* cpus */ |
1108 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1109 | |
c20d332a BR |
1110 | if (smc->dr_lmb_enabled) { |
1111 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1112 | } | |
1113 | ||
c5514d0e | 1114 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1115 | int offset = fdt_path_offset(fdt, "/cpus"); |
1116 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1117 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1118 | if (ret < 0) { | |
1119 | error_report("Couldn't set up CPU DR device tree properties"); | |
1120 | exit(1); | |
1121 | } | |
1122 | } | |
1123 | ||
ffb1e275 | 1124 | /* /event-sources */ |
ffbb1705 | 1125 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1126 | |
3f5dabce DG |
1127 | /* /rtas */ |
1128 | spapr_dt_rtas(spapr, fdt); | |
1129 | ||
7c866c6a DG |
1130 | /* /chosen */ |
1131 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1132 | |
fca5f2dc DG |
1133 | /* /hypervisor */ |
1134 | if (kvm_enabled()) { | |
1135 | spapr_dt_hypervisor(spapr, fdt); | |
1136 | } | |
1137 | ||
cf6e5223 DG |
1138 | /* Build memory reserve map */ |
1139 | if (spapr->kernel_size) { | |
1140 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1141 | } | |
1142 | if (spapr->initrd_size) { | |
1143 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1144 | } | |
1145 | ||
6787d27b MR |
1146 | /* ibm,client-architecture-support updates */ |
1147 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1148 | if (ret < 0) { | |
1149 | error_report("couldn't setup CAS properties fdt"); | |
1150 | exit(1); | |
1151 | } | |
1152 | ||
997b6cfc | 1153 | return fdt; |
9fdf0c29 DG |
1154 | } |
1155 | ||
1156 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1157 | { | |
1158 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1159 | } | |
1160 | ||
1d1be34d DG |
1161 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1162 | PowerPCCPU *cpu) | |
9fdf0c29 | 1163 | { |
1b14670a AF |
1164 | CPUPPCState *env = &cpu->env; |
1165 | ||
8d04fb55 JK |
1166 | /* The TCG path should also be holding the BQL at this point */ |
1167 | g_assert(qemu_mutex_iothread_locked()); | |
1168 | ||
efcb9383 DG |
1169 | if (msr_pr) { |
1170 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1171 | env->gpr[3] = H_PRIVILEGE; | |
1172 | } else { | |
aa100fa4 | 1173 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1174 | } |
9fdf0c29 DG |
1175 | } |
1176 | ||
9861bb3e SJS |
1177 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1178 | { | |
1179 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1180 | ||
1181 | return spapr->patb_entry; | |
1182 | } | |
1183 | ||
e6b8fd24 SMJ |
1184 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1185 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1186 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1187 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1188 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1189 | ||
715c5407 DG |
1190 | /* |
1191 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1192 | */ | |
1193 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1194 | { | |
1195 | if (spapr->htab_fd >= 0) { | |
1196 | return spapr->htab_fd; | |
1197 | } | |
1198 | ||
1199 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1200 | if (spapr->htab_fd < 0) { | |
1201 | error_report("Unable to open fd for reading hash table from KVM: %s", | |
1202 | strerror(errno)); | |
1203 | } | |
1204 | ||
1205 | return spapr->htab_fd; | |
1206 | } | |
1207 | ||
b4db5413 | 1208 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1209 | { |
1210 | if (spapr->htab_fd >= 0) { | |
1211 | close(spapr->htab_fd); | |
1212 | } | |
1213 | spapr->htab_fd = -1; | |
1214 | } | |
1215 | ||
e57ca75c DG |
1216 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1217 | { | |
1218 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1219 | ||
1220 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1221 | } | |
1222 | ||
1223 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, | |
1224 | hwaddr ptex, int n) | |
1225 | { | |
1226 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1227 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1228 | ||
1229 | if (!spapr->htab) { | |
1230 | /* | |
1231 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1232 | */ | |
1233 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1234 | kvmppc_read_hptes(hptes, ptex, n); | |
1235 | return hptes; | |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | * HTAB is controlled by QEMU. Just point to the internally | |
1240 | * accessible PTEG. | |
1241 | */ | |
1242 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1243 | } | |
1244 | ||
1245 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1246 | const ppc_hash_pte64_t *hptes, | |
1247 | hwaddr ptex, int n) | |
1248 | { | |
1249 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1250 | ||
1251 | if (!spapr->htab) { | |
1252 | g_free((void *)hptes); | |
1253 | } | |
1254 | ||
1255 | /* Nothing to do for qemu managed HPT */ | |
1256 | } | |
1257 | ||
1258 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1259 | uint64_t pte0, uint64_t pte1) | |
1260 | { | |
1261 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1262 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1263 | ||
1264 | if (!spapr->htab) { | |
1265 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1266 | } else { | |
1267 | stq_p(spapr->htab + offset, pte0); | |
1268 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1269 | } | |
1270 | } | |
1271 | ||
8dfe8e7f DG |
1272 | static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1273 | { | |
1274 | int shift; | |
1275 | ||
1276 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1277 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1278 | * that's much more than is needed for Linux guests */ | |
1279 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1280 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1281 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1282 | return shift; | |
1283 | } | |
1284 | ||
06ec79e8 BR |
1285 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1286 | { | |
1287 | g_free(spapr->htab); | |
1288 | spapr->htab = NULL; | |
1289 | spapr->htab_shift = 0; | |
1290 | close_htab_fd(spapr); | |
1291 | } | |
1292 | ||
c5f54f3e DG |
1293 | static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1294 | Error **errp) | |
7f763a5d | 1295 | { |
c5f54f3e DG |
1296 | long rc; |
1297 | ||
1298 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1299 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1300 | |
1301 | rc = kvmppc_reset_htab(shift); | |
1302 | if (rc < 0) { | |
1303 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1304 | error_setg_errno(errp, errno, | |
1305 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1306 | shift); | |
1307 | /* This is almost certainly fatal, but if the caller really | |
1308 | * wants to carry on with shift == 0, it's welcome to try */ | |
1309 | } else if (rc > 0) { | |
1310 | /* kernel-side HPT allocated */ | |
1311 | if (rc != shift) { | |
1312 | error_setg(errp, | |
1313 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1314 | shift, rc); | |
7735feda BR |
1315 | } |
1316 | ||
7f763a5d | 1317 | spapr->htab_shift = shift; |
c18ad9a5 | 1318 | spapr->htab = NULL; |
b817772a | 1319 | } else { |
c5f54f3e DG |
1320 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1321 | size_t size = 1ULL << shift; | |
1322 | int i; | |
b817772a | 1323 | |
c5f54f3e DG |
1324 | spapr->htab = qemu_memalign(size, size); |
1325 | if (!spapr->htab) { | |
1326 | error_setg_errno(errp, errno, | |
1327 | "Could not allocate HPT of order %d", shift); | |
1328 | return; | |
7735feda BR |
1329 | } |
1330 | ||
c5f54f3e DG |
1331 | memset(spapr->htab, 0, size); |
1332 | spapr->htab_shift = shift; | |
e6b8fd24 | 1333 | |
c5f54f3e DG |
1334 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1335 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1336 | } |
7f763a5d | 1337 | } |
9fdf0c29 DG |
1338 | } |
1339 | ||
b4db5413 SJS |
1340 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1341 | { | |
1342 | spapr_reallocate_hpt(spapr, | |
1343 | spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), | |
1344 | &error_fatal); | |
1345 | if (spapr->vrma_adjust) { | |
1346 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), | |
1347 | spapr->htab_shift); | |
1348 | } | |
1349 | /* We're setting up a hash table, so that means we're not radix */ | |
1350 | spapr->patb_entry = 0; | |
1351 | } | |
1352 | ||
4f01a637 | 1353 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1354 | { |
1355 | bool matched = false; | |
1356 | ||
1357 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1358 | matched = true; | |
1359 | } | |
1360 | ||
1361 | if (!matched) { | |
1362 | error_report("Device %s is not supported by this machine yet.", | |
1363 | qdev_fw_name(DEVICE(sbdev))); | |
1364 | exit(1); | |
1365 | } | |
9e3f9733 AG |
1366 | } |
1367 | ||
c8787ad4 | 1368 | static void ppc_spapr_reset(void) |
a3467baa | 1369 | { |
c5f54f3e DG |
1370 | MachineState *machine = MACHINE(qdev_get_machine()); |
1371 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1372 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1373 | uint32_t rtas_limit; |
cae172ab | 1374 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1375 | void *fdt; |
1376 | int rc; | |
259186a7 | 1377 | |
9e3f9733 AG |
1378 | /* Check for unknown sysbus devices */ |
1379 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1380 | ||
b4db5413 SJS |
1381 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { |
1382 | /* If using KVM with radix mode available, VCPUs can be started | |
1383 | * without a HPT because KVM will start them in radix mode. | |
1384 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1385 | spapr->patb_entry = PATBE1_GR; | |
1386 | } else { | |
b4db5413 | 1387 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1388 | } |
a3467baa | 1389 | |
c8787ad4 | 1390 | qemu_devices_reset(); |
a3467baa | 1391 | |
b7d1f77a BH |
1392 | /* |
1393 | * We place the device tree and RTAS just below either the top of the RMA, | |
1394 | * or just below 2GB, whichever is lowere, so that it can be | |
1395 | * processed with 32-bit real mode code if necessary | |
1396 | */ | |
1397 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1398 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1399 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1400 | |
6787d27b MR |
1401 | /* if this reset wasn't generated by CAS, we should reset our |
1402 | * negotiated options and start from scratch */ | |
1403 | if (!spapr->cas_reboot) { | |
1404 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1405 | spapr->ov5_cas = spapr_ovec_new(); | |
66d5c492 DG |
1406 | |
1407 | ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); | |
6787d27b MR |
1408 | } |
1409 | ||
cae172ab | 1410 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1411 | |
2cac78c1 | 1412 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1413 | |
997b6cfc DG |
1414 | rc = fdt_pack(fdt); |
1415 | ||
1416 | /* Should only fail if we've built a corrupted tree */ | |
1417 | assert(rc == 0); | |
1418 | ||
1419 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1420 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1421 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1422 | exit(1); | |
1423 | } | |
1424 | ||
1425 | /* Load the fdt */ | |
1426 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1427 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1428 | g_free(fdt); |
1429 | ||
a3467baa | 1430 | /* Set up the entry state */ |
182735ef | 1431 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
cae172ab | 1432 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1433 | first_ppc_cpu->env.gpr[5] = 0; |
1434 | first_cpu->halted = 0; | |
1b718907 | 1435 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1436 | |
6787d27b | 1437 | spapr->cas_reboot = false; |
a3467baa DG |
1438 | } |
1439 | ||
28e02042 | 1440 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1441 | { |
2ff3de68 | 1442 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1443 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1444 | |
3978b863 | 1445 | if (dinfo) { |
6231a6da MA |
1446 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1447 | &error_fatal); | |
639e8102 DG |
1448 | } |
1449 | ||
1450 | qdev_init_nofail(dev); | |
1451 | ||
1452 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1453 | } | |
1454 | ||
28e02042 | 1455 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1456 | { |
147ff807 CLG |
1457 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1458 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1459 | &error_fatal); | |
1460 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1461 | &error_fatal); | |
1462 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1463 | "date", &error_fatal); | |
28df36a1 DG |
1464 | } |
1465 | ||
8c57b867 | 1466 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1467 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1468 | { |
8c57b867 | 1469 | switch (vga_interface_type) { |
8c57b867 | 1470 | case VGA_NONE: |
7effdaa3 MW |
1471 | return false; |
1472 | case VGA_DEVICE: | |
1473 | return true; | |
1ddcae82 | 1474 | case VGA_STD: |
b798c190 | 1475 | case VGA_VIRTIO: |
1ddcae82 | 1476 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1477 | default: |
14c6a894 DG |
1478 | error_setg(errp, |
1479 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1480 | return false; | |
f28359d8 | 1481 | } |
f28359d8 LZ |
1482 | } |
1483 | ||
880ae7de DG |
1484 | static int spapr_post_load(void *opaque, int version_id) |
1485 | { | |
28e02042 | 1486 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1487 | int err = 0; |
1488 | ||
a7ff1212 | 1489 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1490 | CPUState *cs; |
1491 | CPU_FOREACH(cs) { | |
1492 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1493 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1494 | } |
1495 | } | |
1496 | ||
631b22ea | 1497 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1498 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1499 | * So when migrating from those versions, poke the incoming offset | |
1500 | * value into the RTC device */ | |
1501 | if (version_id < 3) { | |
147ff807 | 1502 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1503 | } |
1504 | ||
d39c90f5 BR |
1505 | if (spapr->patb_entry) { |
1506 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); | |
1507 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1508 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1509 | ||
1510 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1511 | if (err) { | |
1512 | error_report("Process table config unsupported by the host"); | |
1513 | return -EINVAL; | |
1514 | } | |
1515 | } | |
1516 | ||
880ae7de DG |
1517 | return err; |
1518 | } | |
1519 | ||
1520 | static bool version_before_3(void *opaque, int version_id) | |
1521 | { | |
1522 | return version_id < 3; | |
1523 | } | |
1524 | ||
fd38804b DHB |
1525 | static bool spapr_pending_events_needed(void *opaque) |
1526 | { | |
1527 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1528 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1529 | } | |
1530 | ||
1531 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1532 | .name = "spapr_event_log_entry", | |
1533 | .version_id = 1, | |
1534 | .minimum_version_id = 1, | |
1535 | .fields = (VMStateField[]) { | |
5341258e DG |
1536 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1537 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1538 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1539 | NULL, extended_length), |
fd38804b DHB |
1540 | VMSTATE_END_OF_LIST() |
1541 | }, | |
1542 | }; | |
1543 | ||
1544 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1545 | .name = "spapr_pending_events", | |
1546 | .version_id = 1, | |
1547 | .minimum_version_id = 1, | |
1548 | .needed = spapr_pending_events_needed, | |
1549 | .fields = (VMStateField[]) { | |
1550 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1551 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1552 | VMSTATE_END_OF_LIST() | |
1553 | }, | |
1554 | }; | |
1555 | ||
62ef3760 MR |
1556 | static bool spapr_ov5_cas_needed(void *opaque) |
1557 | { | |
1558 | sPAPRMachineState *spapr = opaque; | |
1559 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1560 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1561 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1562 | bool cas_needed; | |
1563 | ||
1564 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1565 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1566 | * Both of these options encode machine topology into the device-tree | |
1567 | * in such a way that the now-booted OS should still be able to interact | |
1568 | * appropriately with QEMU regardless of what options were actually | |
1569 | * negotiatied on the source side. | |
1570 | * | |
1571 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1572 | * are the only options available on the current machine/platform. | |
1573 | * Since these are the only options available for pseries-2.7 and | |
1574 | * earlier, this allows us to maintain old->new/new->old migration | |
1575 | * compatibility. | |
1576 | * | |
1577 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1578 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1579 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1580 | * of the actual CAS-negotiated values to continue working properly. For | |
1581 | * example, availability of memory unplug depends on knowing whether | |
1582 | * OV5_HP_EVT was negotiated via CAS. | |
1583 | * | |
1584 | * Thus, for any cases where the set of available CAS-negotiatable | |
1585 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
1586 | * include the CAS-negotiated options in the migration stream. | |
1587 | */ | |
1588 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1589 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
1590 | ||
1591 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1592 | * the mask itself since in the future it's possible "legacy" bits may be | |
1593 | * removed via machine options, which could generate a false positive | |
1594 | * that breaks migration. | |
1595 | */ | |
1596 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1597 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1598 | ||
1599 | spapr_ovec_cleanup(ov5_mask); | |
1600 | spapr_ovec_cleanup(ov5_legacy); | |
1601 | spapr_ovec_cleanup(ov5_removed); | |
1602 | ||
1603 | return cas_needed; | |
1604 | } | |
1605 | ||
1606 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1607 | .name = "spapr_option_vector_ov5_cas", | |
1608 | .version_id = 1, | |
1609 | .minimum_version_id = 1, | |
1610 | .needed = spapr_ov5_cas_needed, | |
1611 | .fields = (VMStateField[]) { | |
1612 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1613 | vmstate_spapr_ovec, sPAPROptionVector), | |
1614 | VMSTATE_END_OF_LIST() | |
1615 | }, | |
1616 | }; | |
1617 | ||
9861bb3e SJS |
1618 | static bool spapr_patb_entry_needed(void *opaque) |
1619 | { | |
1620 | sPAPRMachineState *spapr = opaque; | |
1621 | ||
1622 | return !!spapr->patb_entry; | |
1623 | } | |
1624 | ||
1625 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1626 | .name = "spapr_patb_entry", | |
1627 | .version_id = 1, | |
1628 | .minimum_version_id = 1, | |
1629 | .needed = spapr_patb_entry_needed, | |
1630 | .fields = (VMStateField[]) { | |
1631 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1632 | VMSTATE_END_OF_LIST() | |
1633 | }, | |
1634 | }; | |
1635 | ||
4be21d56 DG |
1636 | static const VMStateDescription vmstate_spapr = { |
1637 | .name = "spapr", | |
880ae7de | 1638 | .version_id = 3, |
4be21d56 | 1639 | .minimum_version_id = 1, |
880ae7de | 1640 | .post_load = spapr_post_load, |
3aff6c2f | 1641 | .fields = (VMStateField[]) { |
880ae7de DG |
1642 | /* used to be @next_irq */ |
1643 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1644 | |
1645 | /* RTC offset */ | |
28e02042 | 1646 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1647 | |
28e02042 | 1648 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1649 | VMSTATE_END_OF_LIST() |
1650 | }, | |
62ef3760 MR |
1651 | .subsections = (const VMStateDescription*[]) { |
1652 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1653 | &vmstate_spapr_patb_entry, |
fd38804b | 1654 | &vmstate_spapr_pending_events, |
62ef3760 MR |
1655 | NULL |
1656 | } | |
4be21d56 DG |
1657 | }; |
1658 | ||
4be21d56 DG |
1659 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1660 | { | |
28e02042 | 1661 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1662 | |
4be21d56 | 1663 | /* "Iteration" header */ |
3a384297 BR |
1664 | if (!spapr->htab_shift) { |
1665 | qemu_put_be32(f, -1); | |
1666 | } else { | |
1667 | qemu_put_be32(f, spapr->htab_shift); | |
1668 | } | |
4be21d56 | 1669 | |
e68cb8b4 AK |
1670 | if (spapr->htab) { |
1671 | spapr->htab_save_index = 0; | |
1672 | spapr->htab_first_pass = true; | |
1673 | } else { | |
3a384297 BR |
1674 | if (spapr->htab_shift) { |
1675 | assert(kvm_enabled()); | |
1676 | } | |
e68cb8b4 AK |
1677 | } |
1678 | ||
1679 | ||
4be21d56 DG |
1680 | return 0; |
1681 | } | |
1682 | ||
28e02042 | 1683 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1684 | int64_t max_ns) |
1685 | { | |
378bc217 | 1686 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1687 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1688 | int index = spapr->htab_save_index; | |
bc72ad67 | 1689 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1690 | |
1691 | assert(spapr->htab_first_pass); | |
1692 | ||
1693 | do { | |
1694 | int chunkstart; | |
1695 | ||
1696 | /* Consume invalid HPTEs */ | |
1697 | while ((index < htabslots) | |
1698 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 1699 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1700 | index++; |
4be21d56 DG |
1701 | } |
1702 | ||
1703 | /* Consume valid HPTEs */ | |
1704 | chunkstart = index; | |
338c25b6 | 1705 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 1706 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 1707 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1708 | index++; |
4be21d56 DG |
1709 | } |
1710 | ||
1711 | if (index > chunkstart) { | |
1712 | int n_valid = index - chunkstart; | |
1713 | ||
1714 | qemu_put_be32(f, chunkstart); | |
1715 | qemu_put_be16(f, n_valid); | |
1716 | qemu_put_be16(f, 0); | |
1717 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1718 | HASH_PTE_SIZE_64 * n_valid); | |
1719 | ||
378bc217 DG |
1720 | if (has_timeout && |
1721 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1722 | break; |
1723 | } | |
1724 | } | |
1725 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1726 | ||
1727 | if (index >= htabslots) { | |
1728 | assert(index == htabslots); | |
1729 | index = 0; | |
1730 | spapr->htab_first_pass = false; | |
1731 | } | |
1732 | spapr->htab_save_index = index; | |
1733 | } | |
1734 | ||
28e02042 | 1735 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1736 | int64_t max_ns) |
4be21d56 DG |
1737 | { |
1738 | bool final = max_ns < 0; | |
1739 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1740 | int examined = 0, sent = 0; | |
1741 | int index = spapr->htab_save_index; | |
bc72ad67 | 1742 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1743 | |
1744 | assert(!spapr->htab_first_pass); | |
1745 | ||
1746 | do { | |
1747 | int chunkstart, invalidstart; | |
1748 | ||
1749 | /* Consume non-dirty HPTEs */ | |
1750 | while ((index < htabslots) | |
1751 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1752 | index++; | |
1753 | examined++; | |
1754 | } | |
1755 | ||
1756 | chunkstart = index; | |
1757 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1758 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1759 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1760 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1761 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1762 | index++; | |
1763 | examined++; | |
1764 | } | |
1765 | ||
1766 | invalidstart = index; | |
1767 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1768 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1769 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1770 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1771 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1772 | index++; | |
1773 | examined++; | |
1774 | } | |
1775 | ||
1776 | if (index > chunkstart) { | |
1777 | int n_valid = invalidstart - chunkstart; | |
1778 | int n_invalid = index - invalidstart; | |
1779 | ||
1780 | qemu_put_be32(f, chunkstart); | |
1781 | qemu_put_be16(f, n_valid); | |
1782 | qemu_put_be16(f, n_invalid); | |
1783 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1784 | HASH_PTE_SIZE_64 * n_valid); | |
1785 | sent += index - chunkstart; | |
1786 | ||
bc72ad67 | 1787 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1788 | break; |
1789 | } | |
1790 | } | |
1791 | ||
1792 | if (examined >= htabslots) { | |
1793 | break; | |
1794 | } | |
1795 | ||
1796 | if (index >= htabslots) { | |
1797 | assert(index == htabslots); | |
1798 | index = 0; | |
1799 | } | |
1800 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1801 | ||
1802 | if (index >= htabslots) { | |
1803 | assert(index == htabslots); | |
1804 | index = 0; | |
1805 | } | |
1806 | ||
1807 | spapr->htab_save_index = index; | |
1808 | ||
e68cb8b4 | 1809 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1810 | } |
1811 | ||
e68cb8b4 AK |
1812 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1813 | #define MAX_KVM_BUF_SIZE 2048 | |
1814 | ||
4be21d56 DG |
1815 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1816 | { | |
28e02042 | 1817 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1818 | int fd; |
e68cb8b4 | 1819 | int rc = 0; |
4be21d56 DG |
1820 | |
1821 | /* Iteration header */ | |
3a384297 BR |
1822 | if (!spapr->htab_shift) { |
1823 | qemu_put_be32(f, -1); | |
1824 | return 0; | |
1825 | } else { | |
1826 | qemu_put_be32(f, 0); | |
1827 | } | |
4be21d56 | 1828 | |
e68cb8b4 AK |
1829 | if (!spapr->htab) { |
1830 | assert(kvm_enabled()); | |
1831 | ||
715c5407 DG |
1832 | fd = get_htab_fd(spapr); |
1833 | if (fd < 0) { | |
1834 | return fd; | |
01a57972 SMJ |
1835 | } |
1836 | ||
715c5407 | 1837 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1838 | if (rc < 0) { |
1839 | return rc; | |
1840 | } | |
1841 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1842 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1843 | } else { | |
e68cb8b4 | 1844 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1845 | } |
1846 | ||
1847 | /* End marker */ | |
1848 | qemu_put_be32(f, 0); | |
1849 | qemu_put_be16(f, 0); | |
1850 | qemu_put_be16(f, 0); | |
1851 | ||
e68cb8b4 | 1852 | return rc; |
4be21d56 DG |
1853 | } |
1854 | ||
1855 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1856 | { | |
28e02042 | 1857 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1858 | int fd; |
4be21d56 DG |
1859 | |
1860 | /* Iteration header */ | |
3a384297 BR |
1861 | if (!spapr->htab_shift) { |
1862 | qemu_put_be32(f, -1); | |
1863 | return 0; | |
1864 | } else { | |
1865 | qemu_put_be32(f, 0); | |
1866 | } | |
4be21d56 | 1867 | |
e68cb8b4 AK |
1868 | if (!spapr->htab) { |
1869 | int rc; | |
1870 | ||
1871 | assert(kvm_enabled()); | |
1872 | ||
715c5407 DG |
1873 | fd = get_htab_fd(spapr); |
1874 | if (fd < 0) { | |
1875 | return fd; | |
01a57972 SMJ |
1876 | } |
1877 | ||
715c5407 | 1878 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1879 | if (rc < 0) { |
1880 | return rc; | |
1881 | } | |
e68cb8b4 | 1882 | } else { |
378bc217 DG |
1883 | if (spapr->htab_first_pass) { |
1884 | htab_save_first_pass(f, spapr, -1); | |
1885 | } | |
e68cb8b4 AK |
1886 | htab_save_later_pass(f, spapr, -1); |
1887 | } | |
4be21d56 DG |
1888 | |
1889 | /* End marker */ | |
1890 | qemu_put_be32(f, 0); | |
1891 | qemu_put_be16(f, 0); | |
1892 | qemu_put_be16(f, 0); | |
1893 | ||
1894 | return 0; | |
1895 | } | |
1896 | ||
1897 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1898 | { | |
28e02042 | 1899 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1900 | uint32_t section_hdr; |
e68cb8b4 | 1901 | int fd = -1; |
4be21d56 DG |
1902 | |
1903 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 1904 | error_report("htab_load() bad version"); |
4be21d56 DG |
1905 | return -EINVAL; |
1906 | } | |
1907 | ||
1908 | section_hdr = qemu_get_be32(f); | |
1909 | ||
3a384297 BR |
1910 | if (section_hdr == -1) { |
1911 | spapr_free_hpt(spapr); | |
1912 | return 0; | |
1913 | } | |
1914 | ||
4be21d56 | 1915 | if (section_hdr) { |
9897e462 | 1916 | Error *local_err = NULL; |
c5f54f3e DG |
1917 | |
1918 | /* First section gives the htab size */ | |
1919 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
1920 | if (local_err) { | |
1921 | error_report_err(local_err); | |
4be21d56 DG |
1922 | return -EINVAL; |
1923 | } | |
1924 | return 0; | |
1925 | } | |
1926 | ||
e68cb8b4 AK |
1927 | if (!spapr->htab) { |
1928 | assert(kvm_enabled()); | |
1929 | ||
1930 | fd = kvmppc_get_htab_fd(true); | |
1931 | if (fd < 0) { | |
98a5d100 DG |
1932 | error_report("Unable to open fd to restore KVM hash table: %s", |
1933 | strerror(errno)); | |
e68cb8b4 AK |
1934 | } |
1935 | } | |
1936 | ||
4be21d56 DG |
1937 | while (true) { |
1938 | uint32_t index; | |
1939 | uint16_t n_valid, n_invalid; | |
1940 | ||
1941 | index = qemu_get_be32(f); | |
1942 | n_valid = qemu_get_be16(f); | |
1943 | n_invalid = qemu_get_be16(f); | |
1944 | ||
1945 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1946 | /* End of Stream */ | |
1947 | break; | |
1948 | } | |
1949 | ||
e68cb8b4 | 1950 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1951 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1952 | /* Bad index in stream */ | |
98a5d100 DG |
1953 | error_report( |
1954 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
1955 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
1956 | return -EINVAL; |
1957 | } | |
1958 | ||
e68cb8b4 AK |
1959 | if (spapr->htab) { |
1960 | if (n_valid) { | |
1961 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1962 | HASH_PTE_SIZE_64 * n_valid); | |
1963 | } | |
1964 | if (n_invalid) { | |
1965 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1966 | HASH_PTE_SIZE_64 * n_invalid); | |
1967 | } | |
1968 | } else { | |
1969 | int rc; | |
1970 | ||
1971 | assert(fd >= 0); | |
1972 | ||
1973 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1974 | if (rc < 0) { | |
1975 | return rc; | |
1976 | } | |
4be21d56 DG |
1977 | } |
1978 | } | |
1979 | ||
e68cb8b4 AK |
1980 | if (!spapr->htab) { |
1981 | assert(fd >= 0); | |
1982 | close(fd); | |
1983 | } | |
1984 | ||
4be21d56 DG |
1985 | return 0; |
1986 | } | |
1987 | ||
70f794fc | 1988 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
1989 | { |
1990 | sPAPRMachineState *spapr = opaque; | |
1991 | ||
1992 | close_htab_fd(spapr); | |
1993 | } | |
1994 | ||
4be21d56 | 1995 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 1996 | .save_setup = htab_save_setup, |
4be21d56 | 1997 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 1998 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 1999 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2000 | .load_state = htab_load, |
2001 | }; | |
2002 | ||
5b2128d2 AG |
2003 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2004 | Error **errp) | |
2005 | { | |
2006 | MachineState *machine = MACHINE(qdev_get_machine()); | |
2007 | machine->boot_order = g_strdup(boot_device); | |
2008 | } | |
2009 | ||
224245bf DG |
2010 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2011 | { | |
2012 | MachineState *machine = MACHINE(spapr); | |
2013 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2014 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2015 | int i; |
2016 | ||
2017 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2018 | uint64_t addr; |
2019 | ||
e8f986fc | 2020 | addr = i * lmb_size + spapr->hotplug_memory.base; |
6caf3ac6 DG |
2021 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2022 | addr / lmb_size); | |
224245bf DG |
2023 | } |
2024 | } | |
2025 | ||
2026 | /* | |
2027 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2028 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2029 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2030 | */ | |
7c150d6f | 2031 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2032 | { |
2033 | int i; | |
2034 | ||
7c150d6f DG |
2035 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2036 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
2037 | " is not aligned to %llu MiB", | |
2038 | machine->ram_size, | |
2039 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2040 | return; | |
2041 | } | |
2042 | ||
2043 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2044 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
2045 | " is not aligned to %llu MiB", | |
2046 | machine->ram_size, | |
2047 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2048 | return; | |
224245bf DG |
2049 | } |
2050 | ||
2051 | for (i = 0; i < nb_numa_nodes; i++) { | |
2052 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2053 | error_setg(errp, |
2054 | "Node %d memory size 0x%" PRIx64 | |
2055 | " is not aligned to %llu MiB", | |
2056 | i, numa_info[i].node_mem, | |
2057 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2058 | return; | |
224245bf DG |
2059 | } |
2060 | } | |
2061 | } | |
2062 | ||
535455fd IM |
2063 | /* find cpu slot in machine->possible_cpus by core_id */ |
2064 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2065 | { | |
2066 | int index = id / smp_threads; | |
2067 | ||
2068 | if (index >= ms->possible_cpus->len) { | |
2069 | return NULL; | |
2070 | } | |
2071 | if (idx) { | |
2072 | *idx = index; | |
2073 | } | |
2074 | return &ms->possible_cpus->cpus[index]; | |
2075 | } | |
2076 | ||
0c86d0fd DG |
2077 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2078 | { | |
2079 | MachineState *machine = MACHINE(spapr); | |
2080 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2081 | char *type = spapr_get_cpu_core_type(machine->cpu_model); | |
2082 | int smt = kvmppc_smt_threads(); | |
535455fd IM |
2083 | const CPUArchIdList *possible_cpus; |
2084 | int boot_cores_nr = smp_cpus / smp_threads; | |
0c86d0fd DG |
2085 | int i; |
2086 | ||
2087 | if (!type) { | |
2088 | error_report("Unable to find sPAPR CPU Core definition"); | |
2089 | exit(1); | |
2090 | } | |
2091 | ||
535455fd | 2092 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
c5514d0e | 2093 | if (mc->has_hotpluggable_cpus) { |
0c86d0fd DG |
2094 | if (smp_cpus % smp_threads) { |
2095 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2096 | smp_cpus, smp_threads); | |
2097 | exit(1); | |
2098 | } | |
2099 | if (max_cpus % smp_threads) { | |
2100 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2101 | max_cpus, smp_threads); | |
2102 | exit(1); | |
2103 | } | |
0c86d0fd DG |
2104 | } else { |
2105 | if (max_cpus != smp_cpus) { | |
2106 | error_report("This machine version does not support CPU hotplug"); | |
2107 | exit(1); | |
2108 | } | |
535455fd | 2109 | boot_cores_nr = possible_cpus->len; |
0c86d0fd DG |
2110 | } |
2111 | ||
535455fd | 2112 | for (i = 0; i < possible_cpus->len; i++) { |
0c86d0fd DG |
2113 | int core_id = i * smp_threads; |
2114 | ||
c5514d0e | 2115 | if (mc->has_hotpluggable_cpus) { |
6caf3ac6 DG |
2116 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, |
2117 | (core_id / smp_threads) * smt); | |
0c86d0fd DG |
2118 | } |
2119 | ||
535455fd | 2120 | if (i < boot_cores_nr) { |
0c86d0fd DG |
2121 | Object *core = object_new(type); |
2122 | int nr_threads = smp_threads; | |
2123 | ||
2124 | /* Handle the partially filled core for older machine types */ | |
2125 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2126 | nr_threads = smp_cpus - i * smp_threads; | |
2127 | } | |
2128 | ||
2129 | object_property_set_int(core, nr_threads, "nr-threads", | |
2130 | &error_fatal); | |
2131 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2132 | &error_fatal); | |
2133 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2134 | } | |
2135 | } | |
2136 | g_free(type); | |
2137 | } | |
2138 | ||
9fdf0c29 | 2139 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 2140 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 2141 | { |
28e02042 | 2142 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2143 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2144 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2145 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2146 | PCIHostState *phb; |
9fdf0c29 | 2147 | int i; |
890c2b77 AK |
2148 | MemoryRegion *sysmem = get_system_memory(); |
2149 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
2150 | MemoryRegion *rma_region; |
2151 | void *rma = NULL; | |
a8170e5e | 2152 | hwaddr rma_alloc_size; |
b082d65a | 2153 | hwaddr node0_size = spapr_node0_size(); |
b7d1f77a | 2154 | long load_limit, fw_size; |
39ac8455 | 2155 | char *filename; |
30f4b05b | 2156 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2157 | |
226419d6 | 2158 | msi_nonbroken = true; |
0ee2c058 | 2159 | |
d43b45e2 | 2160 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2161 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2162 | |
30f4b05b DG |
2163 | /* Check HPT resizing availability */ |
2164 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); | |
2165 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2166 | /* | |
2167 | * If the user explicitly requested a mode we should either | |
2168 | * supply it, or fail completely (which we do below). But if | |
2169 | * it's not set explicitly, we reset our mode to something | |
2170 | * that works | |
2171 | */ | |
2172 | if (resize_hpt_err) { | |
2173 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2174 | error_free(resize_hpt_err); | |
2175 | resize_hpt_err = NULL; | |
2176 | } else { | |
2177 | spapr->resize_hpt = smc->resize_hpt_default; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2182 | ||
2183 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2184 | /* | |
2185 | * User requested HPT resize, but this host can't supply it. Bail out | |
2186 | */ | |
2187 | error_report_err(resize_hpt_err); | |
2188 | exit(1); | |
2189 | } | |
2190 | ||
354ac20a | 2191 | /* Allocate RMA if necessary */ |
658fa66b | 2192 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
2193 | |
2194 | if (rma_alloc_size == -1) { | |
730fce59 | 2195 | error_report("Unable to create RMA"); |
354ac20a DG |
2196 | exit(1); |
2197 | } | |
7f763a5d | 2198 | |
c4177479 | 2199 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 2200 | spapr->rma_size = rma_alloc_size; |
354ac20a | 2201 | } else { |
c4177479 | 2202 | spapr->rma_size = node0_size; |
7f763a5d DG |
2203 | |
2204 | /* With KVM, we don't actually know whether KVM supports an | |
2205 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2206 | * (HV KVM using VRMA), so we always assume the latter | |
2207 | * | |
2208 | * In that case, we also limit the initial allocations for RTAS | |
2209 | * etc... to 256M since we have no way to know what the VRMA size | |
2210 | * is going to be as it depends on the size of the hash table | |
2211 | * isn't determined yet. | |
2212 | */ | |
2213 | if (kvm_enabled()) { | |
2214 | spapr->vrma_adjust = 1; | |
2215 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
2216 | } | |
912acdf4 BH |
2217 | |
2218 | /* Actually we don't support unbounded RMA anymore since we | |
2219 | * added proper emulation of HV mode. The max we can get is | |
2220 | * 16G which also happens to be what we configure for PAPR | |
2221 | * mode so make sure we don't do anything bigger than that | |
2222 | */ | |
2223 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
2224 | } |
2225 | ||
c4177479 | 2226 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2227 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2228 | spapr->rma_size); | |
c4177479 AK |
2229 | exit(1); |
2230 | } | |
2231 | ||
b7d1f77a BH |
2232 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2233 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2234 | |
7b565160 | 2235 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2236 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2237 | |
facdb8b6 MR |
2238 | /* Set up containers for ibm,client-set-architecture negotiated options */ |
2239 | spapr->ov5 = spapr_ovec_new(); | |
2240 | spapr->ov5_cas = spapr_ovec_new(); | |
2241 | ||
224245bf | 2242 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2243 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2244 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2245 | } |
2246 | ||
417ece33 | 2247 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
545d6e2b SJS |
2248 | if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { |
2249 | /* KVM and TCG always allow GTSE with radix... */ | |
9fb4541f SB |
2250 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2251 | } | |
2252 | /* ... but not with hash (currently). */ | |
417ece33 | 2253 | |
ffbb1705 MR |
2254 | /* advertise support for dedicated HP event source to guests */ |
2255 | if (spapr->use_hotplug_event_source) { | |
2256 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2257 | } | |
2258 | ||
9fdf0c29 | 2259 | /* init CPUs */ |
19fb2c36 | 2260 | if (machine->cpu_model == NULL) { |
3daa4a9f | 2261 | machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; |
9fdf0c29 | 2262 | } |
94a94e4c | 2263 | |
7843c0d6 | 2264 | spapr_cpu_parse_features(spapr); |
e703d2f7 | 2265 | |
0c86d0fd | 2266 | spapr_init_cpus(spapr); |
9fdf0c29 | 2267 | |
026bfd89 DG |
2268 | if (kvm_enabled()) { |
2269 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2270 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2271 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2272 | |
2273 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2274 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2275 | } |
2276 | ||
9fdf0c29 | 2277 | /* allocate RAM */ |
f92f5da1 | 2278 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2279 | machine->ram_size); |
f92f5da1 | 2280 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2281 | |
658fa66b AK |
2282 | if (rma_alloc_size && rma) { |
2283 | rma_region = g_new(MemoryRegion, 1); | |
2284 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
2285 | rma_alloc_size, rma); | |
2286 | vmstate_register_ram_global(rma_region); | |
2287 | memory_region_add_subregion(sysmem, 0, rma_region); | |
2288 | } | |
2289 | ||
4a1c9cf0 BR |
2290 | /* initialize hotplug memory address space */ |
2291 | if (machine->ram_size < machine->maxram_size) { | |
2292 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
2293 | /* |
2294 | * Limit the number of hotpluggable memory slots to half the number | |
2295 | * slots that KVM supports, leaving the other half for PCI and other | |
2296 | * devices. However ensure that number of slots doesn't drop below 32. | |
2297 | */ | |
2298 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2299 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2300 | |
71c9a3dd BR |
2301 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2302 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2303 | } | |
2304 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2305 | error_report("Specified number of memory slots %" |
2306 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2307 | machine->ram_slots, max_memslots); |
d54e4d76 | 2308 | exit(1); |
4a1c9cf0 BR |
2309 | } |
2310 | ||
2311 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
2312 | SPAPR_HOTPLUG_MEM_ALIGN); | |
2313 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
2314 | "hotplug-memory", hotplug_mem_size); | |
2315 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
2316 | &spapr->hotplug_memory.mr); | |
2317 | } | |
2318 | ||
224245bf DG |
2319 | if (smc->dr_lmb_enabled) { |
2320 | spapr_create_lmb_dr_connectors(spapr); | |
2321 | } | |
2322 | ||
39ac8455 | 2323 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2324 | if (!filename) { |
730fce59 | 2325 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2326 | exit(1); |
2327 | } | |
b7d1f77a | 2328 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2329 | if (spapr->rtas_size < 0) { |
2330 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2331 | exit(1); | |
2332 | } | |
b7d1f77a BH |
2333 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2334 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2335 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2336 | exit(1); |
2337 | } | |
4d8d5467 | 2338 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2339 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2340 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2341 | exit(1); |
2342 | } | |
7267c094 | 2343 | g_free(filename); |
39ac8455 | 2344 | |
ffbb1705 | 2345 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2346 | spapr_events_init(spapr); |
2347 | ||
12f42174 | 2348 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2349 | spapr_rtc_create(spapr); |
12f42174 | 2350 | |
b5cec4c5 | 2351 | /* Set up VIO bus */ |
4040ab72 DG |
2352 | spapr->vio_bus = spapr_vio_bus_init(); |
2353 | ||
277f9acf | 2354 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 2355 | if (serial_hds[i]) { |
d601fac4 | 2356 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
2357 | } |
2358 | } | |
9fdf0c29 | 2359 | |
639e8102 DG |
2360 | /* We always have at least the nvram device on VIO */ |
2361 | spapr_create_nvram(spapr); | |
2362 | ||
3384f95c | 2363 | /* Set up PCI */ |
fa28f71b AK |
2364 | spapr_pci_rtas_init(); |
2365 | ||
89dfd6e1 | 2366 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2367 | |
277f9acf | 2368 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2369 | NICInfo *nd = &nd_table[i]; |
2370 | ||
2371 | if (!nd->model) { | |
7267c094 | 2372 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
2373 | } |
2374 | ||
2375 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 2376 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2377 | } else { |
29b358f9 | 2378 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2379 | } |
2380 | } | |
2381 | ||
6e270446 | 2382 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2383 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2384 | } |
2385 | ||
f28359d8 | 2386 | /* Graphics */ |
14c6a894 | 2387 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2388 | spapr->has_graphics = true; |
c6e76503 | 2389 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2390 | } |
2391 | ||
4ee9ced9 | 2392 | if (machine->usb) { |
57040d45 TH |
2393 | if (smc->use_ohci_by_default) { |
2394 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2395 | } else { | |
2396 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2397 | } | |
c86580b8 | 2398 | |
35139a59 | 2399 | if (spapr->has_graphics) { |
c86580b8 MA |
2400 | USBBus *usb_bus = usb_bus_find(-1); |
2401 | ||
2402 | usb_create_simple(usb_bus, "usb-kbd"); | |
2403 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2404 | } |
2405 | } | |
2406 | ||
7f763a5d | 2407 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2408 | error_report( |
2409 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2410 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2411 | exit(1); |
2412 | } | |
2413 | ||
9fdf0c29 DG |
2414 | if (kernel_filename) { |
2415 | uint64_t lowaddr = 0; | |
2416 | ||
a19f7fb0 DG |
2417 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2418 | NULL, NULL, &lowaddr, NULL, 1, | |
2419 | PPC_ELF_MACHINE, 0, 0); | |
2420 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2421 | spapr->kernel_size = load_elf(kernel_filename, | |
2422 | translate_kernel_address, NULL, NULL, | |
2423 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2424 | 0, 0); | |
2425 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2426 | } |
a19f7fb0 DG |
2427 | if (spapr->kernel_size < 0) { |
2428 | error_report("error loading %s: %s", kernel_filename, | |
2429 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2430 | exit(1); |
2431 | } | |
2432 | ||
2433 | /* load initrd */ | |
2434 | if (initrd_filename) { | |
4d8d5467 BH |
2435 | /* Try to locate the initrd in the gap between the kernel |
2436 | * and the firmware. Add a bit of space just in case | |
2437 | */ | |
a19f7fb0 DG |
2438 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2439 | + 0x1ffff) & ~0xffff; | |
2440 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2441 | spapr->initrd_base, | |
2442 | load_limit | |
2443 | - spapr->initrd_base); | |
2444 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2445 | error_report("could not load initial ram disk '%s'", |
2446 | initrd_filename); | |
9fdf0c29 DG |
2447 | exit(1); |
2448 | } | |
9fdf0c29 | 2449 | } |
4d8d5467 | 2450 | } |
a3467baa | 2451 | |
8e7ea787 AF |
2452 | if (bios_name == NULL) { |
2453 | bios_name = FW_FILE_NAME; | |
2454 | } | |
2455 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2456 | if (!filename) { |
68fea5a0 | 2457 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2458 | exit(1); |
2459 | } | |
4d8d5467 | 2460 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2461 | if (fw_size <= 0) { |
2462 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2463 | exit(1); |
2464 | } | |
2465 | g_free(filename); | |
4d8d5467 | 2466 | |
28e02042 DG |
2467 | /* FIXME: Should register things through the MachineState's qdev |
2468 | * interface, this is a legacy from the sPAPREnvironment structure | |
2469 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2470 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2471 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2472 | &savevm_htab_handlers, spapr); | |
2473 | ||
5b2128d2 | 2474 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2475 | |
42043e4f | 2476 | if (kvm_enabled()) { |
3dc410ae | 2477 | /* to stop and start vmclock */ |
42043e4f LV |
2478 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2479 | &spapr->tb); | |
3dc410ae AK |
2480 | |
2481 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2482 | } |
9fdf0c29 DG |
2483 | } |
2484 | ||
135a129a AK |
2485 | static int spapr_kvm_type(const char *vm_type) |
2486 | { | |
2487 | if (!vm_type) { | |
2488 | return 0; | |
2489 | } | |
2490 | ||
2491 | if (!strcmp(vm_type, "HV")) { | |
2492 | return 1; | |
2493 | } | |
2494 | ||
2495 | if (!strcmp(vm_type, "PR")) { | |
2496 | return 2; | |
2497 | } | |
2498 | ||
2499 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2500 | exit(1); | |
2501 | } | |
2502 | ||
71461b0f | 2503 | /* |
627b84f4 | 2504 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2505 | * for the bootindex property handling. |
2506 | */ | |
2507 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2508 | DeviceState *dev) | |
2509 | { | |
2510 | #define CAST(type, obj, name) \ | |
2511 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2512 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2513 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2514 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2515 | |
2516 | if (d) { | |
2517 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2518 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2519 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2520 | ||
2521 | if (spapr) { | |
2522 | /* | |
2523 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2524 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2525 | * in the top 16 bits of the 64-bit LUN | |
2526 | */ | |
2527 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2528 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2529 | (uint64_t)id << 48); | |
2530 | } else if (virtio) { | |
2531 | /* | |
2532 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2533 | * in the top 32 bits of the 64-bit LUN | |
2534 | * Note: the quote above is from SLOF and it is wrong, | |
2535 | * the actual binding is: | |
2536 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2537 | */ | |
2538 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2539 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2540 | (uint64_t)id << 32); | |
2541 | } else if (usb) { | |
2542 | /* | |
2543 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2544 | * in the top 32 bits of the 64-bit LUN | |
2545 | */ | |
2546 | unsigned usb_port = atoi(usb->port->path); | |
2547 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2548 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2549 | (uint64_t)id << 32); | |
2550 | } | |
2551 | } | |
2552 | ||
b99260eb TH |
2553 | /* |
2554 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2555 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2556 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2557 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2558 | */ | |
2559 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2560 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2561 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2562 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2563 | } | |
2564 | } | |
2565 | ||
71461b0f AK |
2566 | if (phb) { |
2567 | /* Replace "pci" with "pci@800000020000000" */ | |
2568 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2569 | } | |
2570 | ||
c4e13492 FF |
2571 | if (vsc) { |
2572 | /* Same logic as virtio above */ | |
2573 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2574 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2575 | } | |
2576 | ||
4871dd4c TH |
2577 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2578 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2579 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2580 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2581 | } | |
2582 | ||
71461b0f AK |
2583 | return NULL; |
2584 | } | |
2585 | ||
23825581 EH |
2586 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2587 | { | |
28e02042 | 2588 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2589 | |
28e02042 | 2590 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2591 | } |
2592 | ||
2593 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2594 | { | |
28e02042 | 2595 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2596 | |
28e02042 DG |
2597 | g_free(spapr->kvm_type); |
2598 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2599 | } |
2600 | ||
f6229214 MR |
2601 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2602 | { | |
2603 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2604 | ||
2605 | return spapr->use_hotplug_event_source; | |
2606 | } | |
2607 | ||
2608 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2609 | Error **errp) | |
2610 | { | |
2611 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2612 | ||
2613 | spapr->use_hotplug_event_source = value; | |
2614 | } | |
2615 | ||
30f4b05b DG |
2616 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2617 | { | |
2618 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2619 | ||
2620 | switch (spapr->resize_hpt) { | |
2621 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2622 | return g_strdup("default"); | |
2623 | case SPAPR_RESIZE_HPT_DISABLED: | |
2624 | return g_strdup("disabled"); | |
2625 | case SPAPR_RESIZE_HPT_ENABLED: | |
2626 | return g_strdup("enabled"); | |
2627 | case SPAPR_RESIZE_HPT_REQUIRED: | |
2628 | return g_strdup("required"); | |
2629 | } | |
2630 | g_assert_not_reached(); | |
2631 | } | |
2632 | ||
2633 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
2634 | { | |
2635 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2636 | ||
2637 | if (strcmp(value, "default") == 0) { | |
2638 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
2639 | } else if (strcmp(value, "disabled") == 0) { | |
2640 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2641 | } else if (strcmp(value, "enabled") == 0) { | |
2642 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
2643 | } else if (strcmp(value, "required") == 0) { | |
2644 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
2645 | } else { | |
2646 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
2647 | } | |
2648 | } | |
2649 | ||
23825581 EH |
2650 | static void spapr_machine_initfn(Object *obj) |
2651 | { | |
715c5407 DG |
2652 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2653 | ||
2654 | spapr->htab_fd = -1; | |
f6229214 | 2655 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2656 | object_property_add_str(obj, "kvm-type", |
2657 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2658 | object_property_set_description(obj, "kvm-type", |
2659 | "Specifies the KVM virtualization mode (HV, PR)", | |
2660 | NULL); | |
f6229214 MR |
2661 | object_property_add_bool(obj, "modern-hotplug-events", |
2662 | spapr_get_modern_hotplug_events, | |
2663 | spapr_set_modern_hotplug_events, | |
2664 | NULL); | |
2665 | object_property_set_description(obj, "modern-hotplug-events", | |
2666 | "Use dedicated hotplug event mechanism in" | |
2667 | " place of standard EPOW events when possible" | |
2668 | " (required for memory hot-unplug support)", | |
2669 | NULL); | |
7843c0d6 DG |
2670 | |
2671 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, | |
2672 | "Maximum permitted CPU compatibility mode", | |
2673 | &error_fatal); | |
30f4b05b DG |
2674 | |
2675 | object_property_add_str(obj, "resize-hpt", | |
2676 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
2677 | object_property_set_description(obj, "resize-hpt", | |
2678 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
2679 | NULL); | |
23825581 EH |
2680 | } |
2681 | ||
87bbdd9c DG |
2682 | static void spapr_machine_finalizefn(Object *obj) |
2683 | { | |
2684 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2685 | ||
2686 | g_free(spapr->kvm_type); | |
2687 | } | |
2688 | ||
1c7ad77e | 2689 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 2690 | { |
34316482 AK |
2691 | cpu_synchronize_state(cs); |
2692 | ppc_cpu_do_system_reset(cs); | |
2693 | } | |
2694 | ||
2695 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2696 | { | |
2697 | CPUState *cs; | |
2698 | ||
2699 | CPU_FOREACH(cs) { | |
1c7ad77e | 2700 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
2701 | } |
2702 | } | |
2703 | ||
79b78a6b MR |
2704 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2705 | uint32_t node, bool dedicated_hp_event_source, | |
2706 | Error **errp) | |
c20d332a BR |
2707 | { |
2708 | sPAPRDRConnector *drc; | |
c20d332a BR |
2709 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
2710 | int i, fdt_offset, fdt_size; | |
2711 | void *fdt; | |
79b78a6b | 2712 | uint64_t addr = addr_start; |
94fd9cba | 2713 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 2714 | Error *local_err = NULL; |
c20d332a | 2715 | |
c20d332a | 2716 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
2717 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2718 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
2719 | g_assert(drc); |
2720 | ||
2721 | fdt = create_device_tree(&fdt_size); | |
2722 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2723 | SPAPR_MEMORY_BLOCK_SIZE); | |
2724 | ||
160bb678 GK |
2725 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
2726 | if (local_err) { | |
2727 | while (addr > addr_start) { | |
2728 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
2729 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
2730 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 2731 | spapr_drc_detach(drc); |
160bb678 GK |
2732 | } |
2733 | g_free(fdt); | |
2734 | error_propagate(errp, local_err); | |
2735 | return; | |
2736 | } | |
94fd9cba LV |
2737 | if (!hotplugged) { |
2738 | spapr_drc_reset(drc); | |
2739 | } | |
c20d332a BR |
2740 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2741 | } | |
5dd5238c JD |
2742 | /* send hotplug notification to the |
2743 | * guest only in case of hotplugged memory | |
2744 | */ | |
94fd9cba | 2745 | if (hotplugged) { |
79b78a6b | 2746 | if (dedicated_hp_event_source) { |
fbf55397 DG |
2747 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2748 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
2749 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
2750 | nr_lmbs, | |
0b55aa91 | 2751 | spapr_drc_index(drc)); |
79b78a6b MR |
2752 | } else { |
2753 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2754 | nr_lmbs); | |
2755 | } | |
5dd5238c | 2756 | } |
c20d332a BR |
2757 | } |
2758 | ||
2759 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2760 | uint32_t node, Error **errp) | |
2761 | { | |
2762 | Error *local_err = NULL; | |
2763 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2764 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2765 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2766 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2767 | uint64_t align = memory_region_get_alignment(mr); | |
2768 | uint64_t size = memory_region_size(mr); | |
2769 | uint64_t addr; | |
df587133 | 2770 | |
d6a9b0b8 | 2771 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2772 | if (local_err) { |
2773 | goto out; | |
2774 | } | |
2775 | ||
9ed442b8 MAL |
2776 | addr = object_property_get_uint(OBJECT(dimm), |
2777 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 2778 | if (local_err) { |
160bb678 | 2779 | goto out_unplug; |
c20d332a BR |
2780 | } |
2781 | ||
79b78a6b MR |
2782 | spapr_add_lmbs(dev, addr, size, node, |
2783 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
2784 | &local_err); |
2785 | if (local_err) { | |
2786 | goto out_unplug; | |
2787 | } | |
2788 | ||
2789 | return; | |
c20d332a | 2790 | |
160bb678 GK |
2791 | out_unplug: |
2792 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
c20d332a BR |
2793 | out: |
2794 | error_propagate(errp, local_err); | |
2795 | } | |
2796 | ||
c871bc70 LV |
2797 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2798 | Error **errp) | |
2799 | { | |
2800 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2801 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2802 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2803 | uint64_t size = memory_region_size(mr); | |
2804 | char *mem_dev; | |
2805 | ||
2806 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2807 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
2808 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2809 | return; | |
2810 | } | |
2811 | ||
2812 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
2813 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
2814 | error_setg(errp, "Memory backend has bad page size. " | |
2815 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 2816 | goto out; |
c871bc70 | 2817 | } |
8a9e0e7b GK |
2818 | |
2819 | out: | |
2820 | g_free(mem_dev); | |
c871bc70 LV |
2821 | } |
2822 | ||
0cffce56 DG |
2823 | struct sPAPRDIMMState { |
2824 | PCDIMMDevice *dimm; | |
cf632463 | 2825 | uint32_t nr_lmbs; |
0cffce56 DG |
2826 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
2827 | }; | |
2828 | ||
2829 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
2830 | PCDIMMDevice *dimm) | |
2831 | { | |
2832 | sPAPRDIMMState *dimm_state = NULL; | |
2833 | ||
2834 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
2835 | if (dimm_state->dimm == dimm) { | |
2836 | break; | |
2837 | } | |
2838 | } | |
2839 | return dimm_state; | |
2840 | } | |
2841 | ||
2842 | static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, | |
2843 | sPAPRDIMMState *dimm_state) | |
2844 | { | |
2845 | g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); | |
2846 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); | |
2847 | } | |
2848 | ||
2849 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
2850 | sPAPRDIMMState *dimm_state) | |
2851 | { | |
2852 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
2853 | g_free(dimm_state); | |
2854 | } | |
cf632463 | 2855 | |
16ee9980 DHB |
2856 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
2857 | PCDIMMDevice *dimm) | |
2858 | { | |
2859 | sPAPRDRConnector *drc; | |
2860 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2861 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2862 | uint64_t size = memory_region_size(mr); | |
2863 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
2864 | uint32_t avail_lmbs = 0; | |
2865 | uint64_t addr_start, addr; | |
2866 | int i; | |
2867 | sPAPRDIMMState *ds; | |
2868 | ||
2869 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
2870 | &error_abort); | |
2871 | ||
2872 | addr = addr_start; | |
2873 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
2874 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2875 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 2876 | g_assert(drc); |
454b580a | 2877 | if (drc->dev) { |
16ee9980 DHB |
2878 | avail_lmbs++; |
2879 | } | |
2880 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
2881 | } | |
2882 | ||
2883 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
2884 | ds->nr_lmbs = avail_lmbs; | |
2885 | ds->dimm = dimm; | |
2886 | spapr_pending_dimm_unplugs_add(ms, ds); | |
2887 | return ds; | |
2888 | } | |
2889 | ||
31834723 DHB |
2890 | /* Callback to be called during DRC release. */ |
2891 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 2892 | { |
765d1bdd DG |
2893 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); |
2894 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2895 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2896 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
0cffce56 | 2897 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 2898 | |
16ee9980 DHB |
2899 | /* This information will get lost if a migration occurs |
2900 | * during the unplug process. In this case recover it. */ | |
2901 | if (ds == NULL) { | |
2902 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
454b580a DG |
2903 | /* The DRC being examined by the caller at least must be counted */ |
2904 | g_assert(ds->nr_lmbs); | |
2905 | } | |
2906 | ||
2907 | if (--ds->nr_lmbs) { | |
cf632463 BR |
2908 | return; |
2909 | } | |
2910 | ||
0cffce56 | 2911 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
2912 | |
2913 | /* | |
2914 | * Now that all the LMBs have been removed by the guest, call the | |
2915 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
2916 | */ | |
765d1bdd | 2917 | pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); |
cf632463 BR |
2918 | object_unparent(OBJECT(dev)); |
2919 | } | |
2920 | ||
2921 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
2922 | DeviceState *dev, Error **errp) | |
2923 | { | |
0cffce56 | 2924 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
2925 | Error *local_err = NULL; |
2926 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2927 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2928 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2929 | uint64_t size = memory_region_size(mr); | |
0cffce56 DG |
2930 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
2931 | uint64_t addr_start, addr; | |
2932 | int i; | |
2933 | sPAPRDRConnector *drc; | |
0cffce56 | 2934 | sPAPRDIMMState *ds; |
cf632463 | 2935 | |
9ed442b8 | 2936 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 2937 | &local_err); |
cf632463 BR |
2938 | if (local_err) { |
2939 | goto out; | |
2940 | } | |
2941 | ||
0cffce56 DG |
2942 | ds = g_malloc0(sizeof(sPAPRDIMMState)); |
2943 | ds->nr_lmbs = nr_lmbs; | |
2944 | ds->dimm = dimm; | |
2945 | spapr_pending_dimm_unplugs_add(spapr, ds); | |
2946 | ||
2947 | addr = addr_start; | |
2948 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
2949 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2950 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
2951 | g_assert(drc); |
2952 | ||
a8dc47fd | 2953 | spapr_drc_detach(drc); |
0cffce56 DG |
2954 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2955 | } | |
2956 | ||
fbf55397 DG |
2957 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2958 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 2959 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 2960 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
2961 | out: |
2962 | error_propagate(errp, local_err); | |
2963 | } | |
2964 | ||
04d0ffbd GK |
2965 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
2966 | sPAPRMachineState *spapr) | |
af81cf32 BR |
2967 | { |
2968 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2969 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2970 | int id = ppc_get_vcpu_dt_id(cpu); | |
2971 | void *fdt; | |
2972 | int offset, fdt_size; | |
2973 | char *nodename; | |
2974 | ||
2975 | fdt = create_device_tree(&fdt_size); | |
2976 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
2977 | offset = fdt_add_subnode(fdt, 0, nodename); | |
2978 | ||
2979 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
2980 | g_free(nodename); | |
2981 | ||
2982 | *fdt_offset = offset; | |
2983 | return fdt; | |
2984 | } | |
2985 | ||
765d1bdd DG |
2986 | /* Callback to be called during DRC release. */ |
2987 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 2988 | { |
765d1bdd | 2989 | MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); |
46f7afa3 | 2990 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 2991 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 2992 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 2993 | |
46f7afa3 GK |
2994 | if (smc->pre_2_10_has_unused_icps) { |
2995 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
2996 | sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); | |
2997 | const char *typename = object_class_get_name(scc->cpu_class); | |
2998 | size_t size = object_type_get_instance_size(typename); | |
2999 | int i; | |
3000 | ||
3001 | for (i = 0; i < cc->nr_threads; i++) { | |
3002 | CPUState *cs = CPU(sc->threads + i * size); | |
3003 | ||
3004 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3005 | } | |
3006 | } | |
3007 | ||
07572c06 | 3008 | assert(core_slot); |
535455fd | 3009 | core_slot->cpu = NULL; |
ff9006dd IM |
3010 | object_unparent(OBJECT(dev)); |
3011 | } | |
3012 | ||
115debf2 IM |
3013 | static |
3014 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3015 | Error **errp) | |
ff9006dd | 3016 | { |
535455fd IM |
3017 | int index; |
3018 | sPAPRDRConnector *drc; | |
535455fd IM |
3019 | CPUCore *cc = CPU_CORE(dev); |
3020 | int smt = kvmppc_smt_threads(); | |
ff9006dd | 3021 | |
535455fd IM |
3022 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3023 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3024 | cc->core_id); | |
3025 | return; | |
3026 | } | |
ff9006dd IM |
3027 | if (index == 0) { |
3028 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3029 | return; | |
3030 | } | |
3031 | ||
fbf55397 | 3032 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd IM |
3033 | g_assert(drc); |
3034 | ||
a8dc47fd | 3035 | spapr_drc_detach(drc); |
ff9006dd IM |
3036 | |
3037 | spapr_hotplug_req_remove_by_index(drc); | |
3038 | } | |
3039 | ||
3040 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3041 | Error **errp) | |
3042 | { | |
3043 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3044 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3045 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3046 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3047 | CPUCore *cc = CPU_CORE(dev); | |
3048 | CPUState *cs = CPU(core->threads); | |
3049 | sPAPRDRConnector *drc; | |
3050 | Error *local_err = NULL; | |
ff9006dd | 3051 | int smt = kvmppc_smt_threads(); |
535455fd IM |
3052 | CPUArchId *core_slot; |
3053 | int index; | |
94fd9cba | 3054 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3055 | |
535455fd IM |
3056 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3057 | if (!core_slot) { | |
3058 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3059 | cc->core_id); | |
3060 | return; | |
3061 | } | |
fbf55397 | 3062 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd | 3063 | |
c5514d0e | 3064 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3065 | |
ff9006dd | 3066 | if (drc) { |
e49c63d5 GK |
3067 | void *fdt; |
3068 | int fdt_offset; | |
3069 | ||
3070 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3071 | ||
5c1da812 | 3072 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3073 | if (local_err) { |
3074 | g_free(fdt); | |
ff9006dd IM |
3075 | error_propagate(errp, local_err); |
3076 | return; | |
3077 | } | |
ff9006dd | 3078 | |
94fd9cba LV |
3079 | if (hotplugged) { |
3080 | /* | |
3081 | * Send hotplug notification interrupt to the guest only | |
3082 | * in case of hotplugged CPUs. | |
3083 | */ | |
3084 | spapr_hotplug_req_add_by_index(drc); | |
3085 | } else { | |
3086 | spapr_drc_reset(drc); | |
3087 | } | |
ff9006dd | 3088 | } |
94fd9cba | 3089 | |
535455fd | 3090 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3091 | |
3092 | if (smc->pre_2_10_has_unused_icps) { | |
3093 | sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); | |
3094 | const char *typename = object_class_get_name(scc->cpu_class); | |
3095 | size_t size = object_type_get_instance_size(typename); | |
3096 | int i; | |
3097 | ||
3098 | for (i = 0; i < cc->nr_threads; i++) { | |
3099 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); | |
3100 | void *obj = sc->threads + i * size; | |
3101 | ||
3102 | cs = CPU(obj); | |
3103 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); | |
3104 | } | |
3105 | } | |
ff9006dd IM |
3106 | } |
3107 | ||
3108 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3109 | Error **errp) | |
3110 | { | |
3111 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3112 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3113 | Error *local_err = NULL; |
3114 | CPUCore *cc = CPU_CORE(dev); | |
3115 | char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); | |
3116 | const char *type = object_get_typename(OBJECT(dev)); | |
535455fd IM |
3117 | CPUArchId *core_slot; |
3118 | int index; | |
ff9006dd | 3119 | |
c5514d0e | 3120 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3121 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3122 | goto out; | |
3123 | } | |
3124 | ||
3125 | if (strcmp(base_core_type, type)) { | |
3126 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3127 | goto out; | |
3128 | } | |
3129 | ||
3130 | if (cc->core_id % smp_threads) { | |
3131 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3132 | goto out; | |
3133 | } | |
3134 | ||
459264ef DG |
3135 | /* |
3136 | * In general we should have homogeneous threads-per-core, but old | |
3137 | * (pre hotplug support) machine types allow the last core to have | |
3138 | * reduced threads as a compatibility hack for when we allowed | |
3139 | * total vcpus not a multiple of threads-per-core. | |
3140 | */ | |
3141 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
8149e299 DG |
3142 | error_setg(errp, "invalid nr-threads %d, must be %d", |
3143 | cc->nr_threads, smp_threads); | |
3144 | return; | |
3145 | } | |
3146 | ||
535455fd IM |
3147 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3148 | if (!core_slot) { | |
ff9006dd IM |
3149 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3150 | goto out; | |
3151 | } | |
3152 | ||
535455fd | 3153 | if (core_slot->cpu) { |
ff9006dd IM |
3154 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3155 | goto out; | |
3156 | } | |
3157 | ||
a0ceb640 | 3158 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3159 | |
ff9006dd IM |
3160 | out: |
3161 | g_free(base_core_type); | |
3162 | error_propagate(errp, local_err); | |
3163 | } | |
3164 | ||
c20d332a BR |
3165 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3166 | DeviceState *dev, Error **errp) | |
3167 | { | |
3168 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
3169 | ||
3170 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 3171 | int node; |
c20d332a BR |
3172 | |
3173 | if (!smc->dr_lmb_enabled) { | |
3174 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3175 | return; | |
3176 | } | |
9ed442b8 | 3177 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); |
c20d332a BR |
3178 | if (*errp) { |
3179 | return; | |
3180 | } | |
1a5512bb GA |
3181 | if (node < 0 || node >= MAX_NODES) { |
3182 | error_setg(errp, "Invaild node %d", node); | |
3183 | return; | |
3184 | } | |
c20d332a | 3185 | |
b556854b BR |
3186 | /* |
3187 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
3188 | * memory-less node, but instead will silently add the memory | |
3189 | * to the first node that has some memory. This causes two | |
3190 | * unexpected behaviours for the user. | |
3191 | * | |
3192 | * - Memory gets hotplugged to a different node than what the user | |
3193 | * specified. | |
3194 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
3195 | * to memory-less node, a reboot will set things accordingly | |
3196 | * and the previously hotplugged memory now ends in the right node. | |
3197 | * This appears as if some memory moved from one node to another. | |
3198 | * | |
3199 | * So until kernel starts supporting memory hotplug to memory-less | |
3200 | * nodes, just prevent such attempts upfront in QEMU. | |
3201 | */ | |
3202 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
3203 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
3204 | node); | |
3205 | return; | |
3206 | } | |
3207 | ||
c20d332a | 3208 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
3209 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3210 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3211 | } |
3212 | } | |
3213 | ||
cf632463 BR |
3214 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3215 | DeviceState *dev, Error **errp) | |
3216 | { | |
3217 | sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); | |
3218 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | |
3219 | ||
3220 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3221 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3222 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3223 | } else { | |
3224 | /* NOTE: this means there is a window after guest reset, prior to | |
3225 | * CAS negotiation, where unplug requests will fail due to the | |
3226 | * capability not being detected yet. This is a bit different than | |
3227 | * the case with PCI unplug, where the events will be queued and | |
3228 | * eventually handled by the guest after boot | |
3229 | */ | |
3230 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3231 | } | |
6f4b5c3e | 3232 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3233 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3234 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3235 | return; | |
3236 | } | |
115debf2 | 3237 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3238 | } |
3239 | } | |
3240 | ||
94a94e4c BR |
3241 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3242 | DeviceState *dev, Error **errp) | |
3243 | { | |
c871bc70 LV |
3244 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3245 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3246 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3247 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3248 | } | |
3249 | } | |
3250 | ||
7ebaf795 BR |
3251 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3252 | DeviceState *dev) | |
c20d332a | 3253 | { |
94a94e4c BR |
3254 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3255 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3256 | return HOTPLUG_HANDLER(machine); |
3257 | } | |
3258 | return NULL; | |
3259 | } | |
3260 | ||
ea089eeb IM |
3261 | static CpuInstanceProperties |
3262 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3263 | { |
ea089eeb IM |
3264 | CPUArchId *core_slot; |
3265 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3266 | ||
3267 | /* make sure possible_cpu are intialized */ | |
3268 | mc->possible_cpu_arch_ids(machine); | |
3269 | /* get CPU core slot containing thread that matches cpu_index */ | |
3270 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3271 | assert(core_slot); | |
3272 | return core_slot->props; | |
20bb648d DG |
3273 | } |
3274 | ||
535455fd IM |
3275 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3276 | { | |
3277 | int i; | |
3278 | int spapr_max_cores = max_cpus / smp_threads; | |
3279 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3280 | ||
c5514d0e | 3281 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3282 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3283 | } | |
3284 | if (machine->possible_cpus) { | |
3285 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3286 | return machine->possible_cpus; | |
3287 | } | |
3288 | ||
3289 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
3290 | sizeof(CPUArchId) * spapr_max_cores); | |
3291 | machine->possible_cpus->len = spapr_max_cores; | |
3292 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3293 | int core_id = i * smp_threads; | |
3294 | ||
f2d672c2 | 3295 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3296 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3297 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3298 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
ea089eeb IM |
3299 | |
3300 | /* default distribution of CPUs over NUMA nodes */ | |
3301 | if (nb_numa_nodes) { | |
3302 | /* preset values but do not enable them i.e. 'has_node_id = false', | |
3303 | * numa init code will enable them later if manual mapping wasn't | |
3304 | * present on CLI */ | |
3305 | machine->possible_cpus->cpus[i].props.node_id = | |
3306 | core_id / smp_threads / smp_cores % nb_numa_nodes; | |
3307 | } | |
535455fd IM |
3308 | } |
3309 | return machine->possible_cpus; | |
3310 | } | |
3311 | ||
6737d9ad | 3312 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3313 | uint64_t *buid, hwaddr *pio, |
3314 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3315 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3316 | { | |
357d1e3b DG |
3317 | /* |
3318 | * New-style PHB window placement. | |
3319 | * | |
3320 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3321 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3322 | * windows. | |
3323 | * | |
3324 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3325 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3326 | * | |
3327 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3328 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3329 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3330 | * 1TiB 64-bit MMIO windows for each PHB. | |
3331 | */ | |
6737d9ad | 3332 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3333 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3334 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3335 | int i; |
3336 | ||
357d1e3b DG |
3337 | /* Sanity check natural alignments */ |
3338 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3339 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3340 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3341 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3342 | /* Sanity check bounds */ | |
25e6a118 MT |
3343 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3344 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3345 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3346 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3347 | ||
3348 | if (index >= SPAPR_MAX_PHBS) { | |
3349 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3350 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3351 | return; |
3352 | } | |
3353 | ||
3354 | *buid = base_buid + index; | |
3355 | for (i = 0; i < n_dma; ++i) { | |
3356 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3357 | } | |
3358 | ||
357d1e3b DG |
3359 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3360 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3361 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3362 | } |
3363 | ||
7844e12b CLG |
3364 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3365 | { | |
3366 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3367 | ||
3368 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3369 | } | |
3370 | ||
3371 | static void spapr_ics_resend(XICSFabric *dev) | |
3372 | { | |
3373 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3374 | ||
3375 | ics_resend(spapr->ics); | |
3376 | } | |
3377 | ||
06747ba6 | 3378 | static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) |
b2fc59aa | 3379 | { |
5bc8d26d | 3380 | PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); |
b2fc59aa | 3381 | |
5bc8d26d | 3382 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3383 | } |
3384 | ||
6449da45 CLG |
3385 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3386 | Monitor *mon) | |
3387 | { | |
3388 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3389 | CPUState *cs; |
3390 | ||
3391 | CPU_FOREACH(cs) { | |
3392 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3393 | |
5bc8d26d | 3394 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3395 | } |
3396 | ||
3397 | ics_pic_print_info(spapr->ics, mon); | |
3398 | } | |
3399 | ||
29ee3247 AK |
3400 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3401 | { | |
3402 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3403 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3404 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3405 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3406 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3407 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3408 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3409 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3410 | |
0eb9054c | 3411 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3412 | |
3413 | /* | |
3414 | * We set up the default / latest behaviour here. The class_init | |
3415 | * functions for the specific versioned machine types can override | |
3416 | * these details for backwards compatibility | |
3417 | */ | |
958db90c MA |
3418 | mc->init = ppc_spapr_init; |
3419 | mc->reset = ppc_spapr_reset; | |
3420 | mc->block_default_type = IF_SCSI; | |
6244bb7e | 3421 | mc->max_cpus = 1024; |
958db90c | 3422 | mc->no_parallel = 1; |
5b2128d2 | 3423 | mc->default_boot_order = ""; |
a34944fe | 3424 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 3425 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 3426 | mc->has_dynamic_sysbus = true; |
e4024630 | 3427 | mc->pci_allow_0_address = true; |
7ebaf795 | 3428 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3429 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 3430 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 3431 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
535455fd | 3432 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3433 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 3434 | |
fc9f38c3 | 3435 | smc->dr_lmb_enabled = true; |
3daa4a9f | 3436 | smc->tcg_default_cpu = "POWER8"; |
c5514d0e | 3437 | mc->has_hotpluggable_cpus = true; |
30f4b05b | 3438 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
71461b0f | 3439 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3440 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3441 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3442 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3443 | vhc->hpt_mask = spapr_hpt_mask; |
3444 | vhc->map_hptes = spapr_map_hptes; | |
3445 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3446 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3447 | vhc->get_patbe = spapr_get_patbe; |
7844e12b CLG |
3448 | xic->ics_get = spapr_ics_get; |
3449 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3450 | xic->icp_get = spapr_icp_get; |
6449da45 | 3451 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3452 | /* Force NUMA node memory size to be a multiple of |
3453 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3454 | * in which LMBs are represented and hot-added | |
3455 | */ | |
3456 | mc->numa_mem_align_shift = 28; | |
29ee3247 AK |
3457 | } |
3458 | ||
3459 | static const TypeInfo spapr_machine_info = { | |
3460 | .name = TYPE_SPAPR_MACHINE, | |
3461 | .parent = TYPE_MACHINE, | |
4aee7362 | 3462 | .abstract = true, |
6ca1502e | 3463 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 3464 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 3465 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3466 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3467 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3468 | .interfaces = (InterfaceInfo[]) { |
3469 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3470 | { TYPE_NMI }, |
c20d332a | 3471 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3472 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3473 | { TYPE_XICS_FABRIC }, |
6449da45 | 3474 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3475 | { } |
3476 | }, | |
29ee3247 AK |
3477 | }; |
3478 | ||
fccbc785 | 3479 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3480 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3481 | void *data) \ | |
3482 | { \ | |
3483 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3484 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3485 | if (latest) { \ |
3486 | mc->alias = "pseries"; \ | |
3487 | mc->is_default = 1; \ | |
3488 | } \ | |
5013c547 DG |
3489 | } \ |
3490 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
3491 | { \ | |
3492 | MachineState *machine = MACHINE(obj); \ | |
3493 | spapr_machine_##suffix##_instance_options(machine); \ | |
3494 | } \ | |
3495 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
3496 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3497 | .parent = TYPE_SPAPR_MACHINE, \ | |
3498 | .class_init = spapr_machine_##suffix##_class_init, \ | |
3499 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
3500 | }; \ | |
3501 | static void spapr_machine_register_##suffix(void) \ | |
3502 | { \ | |
3503 | type_register(&spapr_machine_##suffix##_info); \ | |
3504 | } \ | |
0e6aac87 | 3505 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3506 | |
3fa14fbe DG |
3507 | /* |
3508 | * pseries-2.10 | |
3509 | */ | |
3510 | static void spapr_machine_2_10_instance_options(MachineState *machine) | |
3511 | { | |
3512 | } | |
3513 | ||
3514 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
3515 | { | |
3516 | /* Defaults for the latest behaviour inherited from the base class */ | |
3517 | } | |
3518 | ||
3519 | DEFINE_SPAPR_MACHINE(2_10, "2.10", true); | |
3520 | ||
fa325e6c DG |
3521 | /* |
3522 | * pseries-2.9 | |
3523 | */ | |
3fa14fbe | 3524 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
3525 | HW_COMPAT_2_9 \ |
3526 | { \ | |
3527 | .driver = TYPE_POWERPC_CPU, \ | |
3528 | .property = "pre-2.10-migration", \ | |
3529 | .value = "on", \ | |
3530 | }, \ | |
3fa14fbe | 3531 | |
fa325e6c DG |
3532 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
3533 | { | |
3fa14fbe | 3534 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
3535 | } |
3536 | ||
3537 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
3538 | { | |
46f7afa3 GK |
3539 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3540 | ||
3fa14fbe DG |
3541 | spapr_machine_2_10_class_options(mc); |
3542 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 3543 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 3544 | smc->pre_2_10_has_unused_icps = true; |
fa325e6c DG |
3545 | } |
3546 | ||
3fa14fbe | 3547 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 3548 | |
db800b21 DG |
3549 | /* |
3550 | * pseries-2.8 | |
3551 | */ | |
82516263 DG |
3552 | #define SPAPR_COMPAT_2_8 \ |
3553 | HW_COMPAT_2_8 \ | |
3554 | { \ | |
3555 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3556 | .property = "pcie-extended-configuration-space", \ | |
3557 | .value = "off", \ | |
3558 | }, | |
fa325e6c | 3559 | |
db800b21 DG |
3560 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
3561 | { | |
fa325e6c | 3562 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
3563 | } |
3564 | ||
3565 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
3566 | { | |
fa325e6c DG |
3567 | spapr_machine_2_9_class_options(mc); |
3568 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 3569 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
3570 | } |
3571 | ||
fa325e6c | 3572 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 3573 | |
1ea1eefc BR |
3574 | /* |
3575 | * pseries-2.7 | |
3576 | */ | |
357d1e3b DG |
3577 | #define SPAPR_COMPAT_2_7 \ |
3578 | HW_COMPAT_2_7 \ | |
3579 | { \ | |
3580 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3581 | .property = "mem_win_size", \ | |
3582 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
3583 | }, \ | |
3584 | { \ | |
3585 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3586 | .property = "mem64_win_size", \ | |
3587 | .value = "0", \ | |
146c11f1 DG |
3588 | }, \ |
3589 | { \ | |
3590 | .driver = TYPE_POWERPC_CPU, \ | |
3591 | .property = "pre-2.8-migration", \ | |
3592 | .value = "on", \ | |
5c4537bd DG |
3593 | }, \ |
3594 | { \ | |
3595 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3596 | .property = "pre-2.8-migration", \ | |
3597 | .value = "on", \ | |
357d1e3b DG |
3598 | }, |
3599 | ||
3600 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
3601 | uint64_t *buid, hwaddr *pio, | |
3602 | hwaddr *mmio32, hwaddr *mmio64, | |
3603 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
3604 | { | |
3605 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
3606 | const uint64_t base_buid = 0x800000020000000ULL; | |
3607 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
3608 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
3609 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
3610 | const uint32_t max_index = 255; | |
3611 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
3612 | ||
3613 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
3614 | hwaddr phb0_base, phb_base; | |
3615 | int i; | |
3616 | ||
3617 | /* Do we have hotpluggable memory? */ | |
3618 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
3619 | /* Can't just use maxram_size, because there may be an | |
3620 | * alignment gap between normal and hotpluggable memory | |
3621 | * regions */ | |
3622 | ram_top = spapr->hotplug_memory.base + | |
3623 | memory_region_size(&spapr->hotplug_memory.mr); | |
3624 | } | |
3625 | ||
3626 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
3627 | ||
3628 | if (index > max_index) { | |
3629 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
3630 | max_index); | |
3631 | return; | |
3632 | } | |
3633 | ||
3634 | *buid = base_buid + index; | |
3635 | for (i = 0; i < n_dma; ++i) { | |
3636 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3637 | } | |
3638 | ||
3639 | phb_base = phb0_base + index * phb_spacing; | |
3640 | *pio = phb_base + pio_offset; | |
3641 | *mmio32 = phb_base + mmio_offset; | |
3642 | /* | |
3643 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
3644 | * fallback behaviour of automatically splitting a large "32-bit" | |
3645 | * window into contiguous 32-bit and 64-bit windows | |
3646 | */ | |
3647 | } | |
db800b21 | 3648 | |
1ea1eefc BR |
3649 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
3650 | { | |
f6229214 MR |
3651 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3652 | ||
672de881 | 3653 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 3654 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
3655 | } |
3656 | ||
3657 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
3658 | { | |
3daa4a9f TH |
3659 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3660 | ||
db800b21 | 3661 | spapr_machine_2_8_class_options(mc); |
3daa4a9f | 3662 | smc->tcg_default_cpu = "POWER7"; |
db800b21 | 3663 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 3664 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
3665 | } |
3666 | ||
db800b21 | 3667 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 3668 | |
4b23699c DG |
3669 | /* |
3670 | * pseries-2.6 | |
3671 | */ | |
1ea1eefc | 3672 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
3673 | HW_COMPAT_2_6 \ |
3674 | { \ | |
3675 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
3676 | .property = "ddw",\ | |
3677 | .value = stringify(off),\ | |
3678 | }, | |
1ea1eefc | 3679 | |
4b23699c DG |
3680 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
3681 | { | |
672de881 | 3682 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
3683 | } |
3684 | ||
3685 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
3686 | { | |
1ea1eefc | 3687 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 3688 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 3689 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
3690 | } |
3691 | ||
1ea1eefc | 3692 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 3693 | |
1c5f29bb DG |
3694 | /* |
3695 | * pseries-2.5 | |
3696 | */ | |
4b23699c | 3697 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
3698 | HW_COMPAT_2_5 \ |
3699 | { \ | |
3700 | .driver = "spapr-vlan", \ | |
3701 | .property = "use-rx-buffer-pools", \ | |
3702 | .value = "off", \ | |
3703 | }, | |
4b23699c | 3704 | |
5013c547 | 3705 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 3706 | { |
672de881 | 3707 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
3708 | } |
3709 | ||
3710 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
3711 | { | |
57040d45 TH |
3712 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3713 | ||
4b23699c | 3714 | spapr_machine_2_6_class_options(mc); |
57040d45 | 3715 | smc->use_ohci_by_default = true; |
4b23699c | 3716 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
3717 | } |
3718 | ||
4b23699c | 3719 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
3720 | |
3721 | /* | |
3722 | * pseries-2.4 | |
3723 | */ | |
80fd50f9 CH |
3724 | #define SPAPR_COMPAT_2_4 \ |
3725 | HW_COMPAT_2_4 | |
3726 | ||
5013c547 | 3727 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 3728 | { |
5013c547 DG |
3729 | spapr_machine_2_5_instance_options(machine); |
3730 | } | |
1c5f29bb | 3731 | |
5013c547 DG |
3732 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
3733 | { | |
fc9f38c3 DG |
3734 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3735 | ||
3736 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 3737 | smc->dr_lmb_enabled = false; |
f949b4e5 | 3738 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
3739 | } |
3740 | ||
fccbc785 | 3741 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
3742 | |
3743 | /* | |
3744 | * pseries-2.3 | |
3745 | */ | |
38ff32c6 | 3746 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
3747 | HW_COMPAT_2_3 \ |
3748 | {\ | |
3749 | .driver = "spapr-pci-host-bridge",\ | |
3750 | .property = "dynamic-reconfiguration",\ | |
3751 | .value = "off",\ | |
3752 | }, | |
38ff32c6 | 3753 | |
5013c547 | 3754 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 3755 | { |
5013c547 | 3756 | spapr_machine_2_4_instance_options(machine); |
d25228e7 JW |
3757 | } |
3758 | ||
5013c547 | 3759 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 3760 | { |
fc9f38c3 | 3761 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 3762 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 3763 | } |
fccbc785 | 3764 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 3765 | |
1c5f29bb DG |
3766 | /* |
3767 | * pseries-2.2 | |
3768 | */ | |
3769 | ||
3770 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
3771 | HW_COMPAT_2_2 \ |
3772 | {\ | |
3773 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
3774 | .property = "mem_win_size",\ | |
3775 | .value = "0x20000000",\ | |
3776 | }, | |
3777 | ||
5013c547 | 3778 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 3779 | { |
5013c547 | 3780 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 3781 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
3782 | } |
3783 | ||
5013c547 | 3784 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 3785 | { |
fc9f38c3 | 3786 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 3787 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 3788 | } |
fccbc785 | 3789 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 3790 | |
1c5f29bb DG |
3791 | /* |
3792 | * pseries-2.1 | |
3793 | */ | |
3794 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 3795 | HW_COMPAT_2_1 |
3dab0244 | 3796 | |
5013c547 | 3797 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 3798 | { |
5013c547 | 3799 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 3800 | } |
d25228e7 | 3801 | |
5013c547 | 3802 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 3803 | { |
fc9f38c3 | 3804 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 3805 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 3806 | } |
fccbc785 | 3807 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 3808 | |
29ee3247 | 3809 | static void spapr_machine_register_types(void) |
9fdf0c29 | 3810 | { |
29ee3247 | 3811 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
3812 | } |
3813 | ||
29ee3247 | 3814 | type_init(spapr_machine_register_types) |