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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
e35704ba | 30 | #include "sysemu/numa.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
03dd024f | 32 | #include "qemu/log.h" |
71461b0f | 33 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 34 | #include "elf.h" |
1422e32d | 35 | #include "net/net.h" |
ad440b4a | 36 | #include "sysemu/device_tree.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 | 38 | #include "sysemu/cpus.h" |
b3946626 | 39 | #include "sysemu/hw_accel.h" |
e97c3636 | 40 | #include "kvm_ppc.h" |
ff14e817 | 41 | #include "migration/migration.h" |
4be21d56 | 42 | #include "mmu-hash64.h" |
b4db5413 | 43 | #include "mmu-book3s-v3.h" |
3794d548 | 44 | #include "qom/cpu.h" |
9fdf0c29 DG |
45 | |
46 | #include "hw/boards.h" | |
0d09e41a | 47 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
48 | #include "hw/loader.h" |
49 | ||
7804c353 | 50 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
51 | #include "hw/ppc/spapr.h" |
52 | #include "hw/ppc/spapr_vio.h" | |
53 | #include "hw/pci-host/spapr.h" | |
54 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 55 | #include "hw/pci/msi.h" |
9fdf0c29 | 56 | |
83c9f4ca | 57 | #include "hw/pci/pci.h" |
71461b0f AK |
58 | #include "hw/scsi/scsi.h" |
59 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 60 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 61 | |
022c62cb | 62 | #include "exec/address-spaces.h" |
35139a59 | 63 | #include "hw/usb.h" |
1de7afc9 | 64 | #include "qemu/config-file.h" |
135a129a | 65 | #include "qemu/error-report.h" |
2a6593cb | 66 | #include "trace.h" |
34316482 | 67 | #include "hw/nmi.h" |
6449da45 | 68 | #include "hw/intc/intc.h" |
890c2b77 | 69 | |
68a27b20 | 70 | #include "hw/compat.h" |
f348b6d1 | 71 | #include "qemu/cutils.h" |
94a94e4c | 72 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 73 | #include "qmp-commands.h" |
68a27b20 | 74 | |
9fdf0c29 DG |
75 | #include <libfdt.h> |
76 | ||
4d8d5467 BH |
77 | /* SLOF memory layout: |
78 | * | |
79 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
80 | * device-tree, then position SLOF itself 31M below that | |
81 | * | |
82 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
83 | * and more | |
84 | * | |
85 | * We load our kernel at 4M, leaving space for SLOF initial image | |
86 | */ | |
38b02bd8 | 87 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 88 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 89 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
90 | #define FW_MAX_SIZE 0x400000 |
91 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
92 | #define FW_OVERHEAD 0x2800000 |
93 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 94 | |
4d8d5467 | 95 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 96 | |
0c103f8e DG |
97 | #define PHANDLE_XICP 0x00001111 |
98 | ||
7f763a5d DG |
99 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
100 | ||
71cd4dac CLG |
101 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
102 | const char *type_ics, | |
103 | int nr_irqs, Error **errp) | |
c04d6cfa | 104 | { |
175d2aa0 | 105 | Error *local_err = NULL; |
71cd4dac | 106 | Object *obj; |
4e4169f7 | 107 | |
71cd4dac | 108 | obj = object_new(type_ics); |
175d2aa0 | 109 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
71cd4dac | 110 | object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort); |
175d2aa0 GK |
111 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
112 | if (local_err) { | |
113 | goto error; | |
114 | } | |
71cd4dac | 115 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
116 | if (local_err) { |
117 | goto error; | |
4e4169f7 | 118 | } |
4e4169f7 | 119 | |
71cd4dac | 120 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
121 | |
122 | error: | |
123 | error_propagate(errp, local_err); | |
124 | return NULL; | |
c04d6cfa AL |
125 | } |
126 | ||
71cd4dac | 127 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 128 | { |
71cd4dac | 129 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
c04d6cfa | 130 | |
11ad93f6 | 131 | if (kvm_enabled()) { |
2192a930 | 132 | if (machine_kernel_irqchip_allowed(machine) && |
71cd4dac CLG |
133 | !xics_kvm_init(spapr, errp)) { |
134 | spapr->icp_type = TYPE_KVM_ICP; | |
3d85885a | 135 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); |
11ad93f6 | 136 | } |
71cd4dac | 137 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
3d85885a GK |
138 | error_prepend(errp, "kernel_irqchip requested but unavailable: "); |
139 | return; | |
11ad93f6 DG |
140 | } |
141 | } | |
142 | ||
71cd4dac | 143 | if (!spapr->ics) { |
f63ebfe0 | 144 | xics_spapr_init(spapr); |
71cd4dac CLG |
145 | spapr->icp_type = TYPE_ICP; |
146 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); | |
3d85885a GK |
147 | if (!spapr->ics) { |
148 | return; | |
149 | } | |
c04d6cfa | 150 | } |
c04d6cfa AL |
151 | } |
152 | ||
833d4668 AK |
153 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
154 | int smt_threads) | |
155 | { | |
156 | int i, ret = 0; | |
157 | uint32_t servers_prop[smt_threads]; | |
158 | uint32_t gservers_prop[smt_threads * 2]; | |
159 | int index = ppc_get_vcpu_dt_id(cpu); | |
160 | ||
d6e166c0 DG |
161 | if (cpu->compat_pvr) { |
162 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
163 | if (ret < 0) { |
164 | return ret; | |
165 | } | |
166 | } | |
167 | ||
833d4668 AK |
168 | /* Build interrupt servers and gservers properties */ |
169 | for (i = 0; i < smt_threads; i++) { | |
170 | servers_prop[i] = cpu_to_be32(index + i); | |
171 | /* Hack, direct the group queues back to cpu 0 */ | |
172 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
173 | gservers_prop[i*2 + 1] = 0; | |
174 | } | |
175 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
176 | servers_prop, sizeof(servers_prop)); | |
177 | if (ret < 0) { | |
178 | return ret; | |
179 | } | |
180 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
181 | gservers_prop, sizeof(gservers_prop)); | |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
99861ecb | 186 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 187 | { |
0da6f3fe BR |
188 | int index = ppc_get_vcpu_dt_id(cpu); |
189 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
190 | cpu_to_be32(0x0), | |
191 | cpu_to_be32(0x0), | |
192 | cpu_to_be32(0x0), | |
15f8b142 | 193 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
194 | cpu_to_be32(index)}; |
195 | ||
196 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 197 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 198 | sizeof(associativity)); |
0da6f3fe BR |
199 | } |
200 | ||
86d5771a | 201 | /* Populate the "ibm,pa-features" property */ |
e957f6a9 SB |
202 | static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, |
203 | bool legacy_guest) | |
86d5771a SB |
204 | { |
205 | uint8_t pa_features_206[] = { 6, 0, | |
206 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
207 | uint8_t pa_features_207[] = { 24, 0, | |
208 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
209 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
210 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
211 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
212 | uint8_t pa_features_300[] = { 66, 0, |
213 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
214 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
215 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
216 | /* 6: DS207 */ | |
217 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
218 | /* 16: Vector */ | |
86d5771a | 219 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 220 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 221 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
222 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
223 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
224 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
225 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
226 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
227 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
228 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
229 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
230 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
231 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
232 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
233 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
234 | /* 60: NM atomic, 62: RNG */ | |
235 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
236 | }; | |
86d5771a SB |
237 | uint8_t *pa_features; |
238 | size_t pa_size; | |
239 | ||
240 | switch (POWERPC_MMU_VER(env->mmu_model)) { | |
241 | case POWERPC_MMU_VER_2_06: | |
242 | pa_features = pa_features_206; | |
243 | pa_size = sizeof(pa_features_206); | |
244 | break; | |
245 | case POWERPC_MMU_VER_2_07: | |
246 | pa_features = pa_features_207; | |
247 | pa_size = sizeof(pa_features_207); | |
248 | break; | |
249 | case POWERPC_MMU_VER_3_00: | |
250 | pa_features = pa_features_300; | |
251 | pa_size = sizeof(pa_features_300); | |
252 | break; | |
253 | default: | |
254 | return; | |
255 | } | |
256 | ||
257 | if (env->ci_large_pages) { | |
258 | /* | |
259 | * Note: we keep CI large pages off by default because a 64K capable | |
260 | * guest provisioned with large pages might otherwise try to map a qemu | |
261 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
262 | * even if that qemu runs on a 4k host. | |
263 | * We dd this bit back here if we are confident this is not an issue | |
264 | */ | |
265 | pa_features[3] |= 0x20; | |
266 | } | |
267 | if (kvmppc_has_cap_htm() && pa_size > 24) { | |
268 | pa_features[24] |= 0x80; /* Transactional memory support */ | |
269 | } | |
e957f6a9 SB |
270 | if (legacy_guest && pa_size > 40) { |
271 | /* Workaround for broken kernels that attempt (guest) radix | |
272 | * mode when they can't handle it, if they see the radix bit set | |
273 | * in pa-features. So hide it from them. */ | |
274 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
275 | } | |
86d5771a SB |
276 | |
277 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
278 | } | |
279 | ||
28e02042 | 280 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 281 | { |
82677ed2 AK |
282 | int ret = 0, offset, cpus_offset; |
283 | CPUState *cs; | |
6e806cc3 BR |
284 | char cpu_model[32]; |
285 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 286 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 287 | |
82677ed2 AK |
288 | CPU_FOREACH(cs) { |
289 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
e957f6a9 | 290 | CPUPPCState *env = &cpu->env; |
82677ed2 AK |
291 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
292 | int index = ppc_get_vcpu_dt_id(cpu); | |
12dbeb16 | 293 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
6e806cc3 | 294 | |
0f20ba62 | 295 | if ((index % smt) != 0) { |
6e806cc3 BR |
296 | continue; |
297 | } | |
298 | ||
82677ed2 | 299 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 300 | |
82677ed2 AK |
301 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
302 | if (cpus_offset < 0) { | |
303 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
304 | "cpus"); | |
305 | if (cpus_offset < 0) { | |
306 | return cpus_offset; | |
307 | } | |
308 | } | |
309 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 310 | if (offset < 0) { |
82677ed2 AK |
311 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
312 | if (offset < 0) { | |
313 | return offset; | |
314 | } | |
6e806cc3 BR |
315 | } |
316 | ||
7f763a5d DG |
317 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
318 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
319 | if (ret < 0) { |
320 | return ret; | |
321 | } | |
833d4668 | 322 | |
99861ecb IM |
323 | if (nb_numa_nodes > 1) { |
324 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
325 | if (ret < 0) { | |
326 | return ret; | |
327 | } | |
0da6f3fe BR |
328 | } |
329 | ||
12dbeb16 | 330 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
331 | if (ret < 0) { |
332 | return ret; | |
333 | } | |
e957f6a9 SB |
334 | |
335 | spapr_populate_pa_features(env, fdt, offset, | |
336 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
337 | } |
338 | return ret; | |
339 | } | |
340 | ||
b082d65a AK |
341 | static hwaddr spapr_node0_size(void) |
342 | { | |
fb164994 DG |
343 | MachineState *machine = MACHINE(qdev_get_machine()); |
344 | ||
b082d65a AK |
345 | if (nb_numa_nodes) { |
346 | int i; | |
347 | for (i = 0; i < nb_numa_nodes; ++i) { | |
348 | if (numa_info[i].node_mem) { | |
fb164994 DG |
349 | return MIN(pow2floor(numa_info[i].node_mem), |
350 | machine->ram_size); | |
b082d65a AK |
351 | } |
352 | } | |
353 | } | |
fb164994 | 354 | return machine->ram_size; |
b082d65a AK |
355 | } |
356 | ||
a1d59c0f AK |
357 | static void add_str(GString *s, const gchar *s1) |
358 | { | |
359 | g_string_append_len(s, s1, strlen(s1) + 1); | |
360 | } | |
7f763a5d | 361 | |
03d196b7 | 362 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
363 | hwaddr size) |
364 | { | |
365 | uint32_t associativity[] = { | |
366 | cpu_to_be32(0x4), /* length */ | |
367 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 368 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
369 | }; |
370 | char mem_name[32]; | |
371 | uint64_t mem_reg_property[2]; | |
372 | int off; | |
373 | ||
374 | mem_reg_property[0] = cpu_to_be64(start); | |
375 | mem_reg_property[1] = cpu_to_be64(size); | |
376 | ||
377 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
378 | off = fdt_add_subnode(fdt, 0, mem_name); | |
379 | _FDT(off); | |
380 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
381 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
382 | sizeof(mem_reg_property)))); | |
383 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
384 | sizeof(associativity)))); | |
03d196b7 | 385 | return off; |
26a8c353 AK |
386 | } |
387 | ||
28e02042 | 388 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 389 | { |
fb164994 | 390 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
391 | hwaddr mem_start, node_size; |
392 | int i, nb_nodes = nb_numa_nodes; | |
393 | NodeInfo *nodes = numa_info; | |
394 | NodeInfo ramnode; | |
395 | ||
396 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
397 | if (!nb_numa_nodes) { | |
398 | nb_nodes = 1; | |
fb164994 | 399 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 400 | nodes = &ramnode; |
5fe269b1 | 401 | } |
7f763a5d | 402 | |
7db8a127 AK |
403 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
404 | if (!nodes[i].node_mem) { | |
405 | continue; | |
406 | } | |
fb164994 | 407 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
408 | node_size = 0; |
409 | } else { | |
7db8a127 | 410 | node_size = nodes[i].node_mem; |
fb164994 DG |
411 | if (node_size > machine->ram_size - mem_start) { |
412 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
413 | } |
414 | } | |
7db8a127 AK |
415 | if (!mem_start) { |
416 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 417 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
418 | mem_start += spapr->rma_size; |
419 | node_size -= spapr->rma_size; | |
420 | } | |
6010818c AK |
421 | for ( ; node_size; ) { |
422 | hwaddr sizetmp = pow2floor(node_size); | |
423 | ||
424 | /* mem_start != 0 here */ | |
425 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
426 | sizetmp = 1ULL << ctzl(mem_start); | |
427 | } | |
428 | ||
429 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
430 | node_size -= sizetmp; | |
431 | mem_start += sizetmp; | |
432 | } | |
7f763a5d DG |
433 | } |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
0da6f3fe BR |
438 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
439 | sPAPRMachineState *spapr) | |
440 | { | |
441 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
442 | CPUPPCState *env = &cpu->env; | |
443 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
444 | int index = ppc_get_vcpu_dt_id(cpu); | |
445 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
446 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
447 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
448 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
449 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
450 | uint32_t page_sizes_prop[64]; | |
451 | size_t page_sizes_prop_size; | |
22419c2a | 452 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 453 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
12dbeb16 | 454 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
af81cf32 | 455 | sPAPRDRConnector *drc; |
af81cf32 | 456 | int drc_index; |
c64abd1f SB |
457 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
458 | int i; | |
af81cf32 | 459 | |
fbf55397 | 460 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 461 | if (drc) { |
0b55aa91 | 462 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
463 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
464 | } | |
0da6f3fe BR |
465 | |
466 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
467 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
468 | ||
469 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
470 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
471 | env->dcache_line_size))); | |
472 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
473 | env->dcache_line_size))); | |
474 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
475 | env->icache_line_size))); | |
476 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
477 | env->icache_line_size))); | |
478 | ||
479 | if (pcc->l1_dcache_size) { | |
480 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
481 | pcc->l1_dcache_size))); | |
482 | } else { | |
ce9863b7 | 483 | error_report("Warning: Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
484 | } |
485 | if (pcc->l1_icache_size) { | |
486 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
487 | pcc->l1_icache_size))); | |
488 | } else { | |
ce9863b7 | 489 | error_report("Warning: Unknown L1 icache size for cpu"); |
0da6f3fe BR |
490 | } |
491 | ||
492 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
493 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 494 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
495 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
496 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
497 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
498 | ||
499 | if (env->spr_cb[SPR_PURR].oea_read) { | |
500 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
501 | } | |
502 | ||
503 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
504 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
505 | segs, sizeof(segs)))); | |
506 | } | |
507 | ||
508 | /* Advertise VMX/VSX (vector extensions) if available | |
509 | * 0 / no property == no vector extensions | |
510 | * 1 == VMX / Altivec available | |
511 | * 2 == VSX available */ | |
512 | if (env->insns_flags & PPC_ALTIVEC) { | |
513 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
514 | ||
515 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
516 | } | |
517 | ||
518 | /* Advertise DFP (Decimal Floating Point) if available | |
519 | * 0 / no property == no DFP | |
520 | * 1 == DFP available */ | |
521 | if (env->insns_flags2 & PPC2_DFP) { | |
522 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
523 | } | |
524 | ||
3654fa95 | 525 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
526 | sizeof(page_sizes_prop)); |
527 | if (page_sizes_prop_size) { | |
528 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
529 | page_sizes_prop, page_sizes_prop_size))); | |
530 | } | |
531 | ||
e957f6a9 | 532 | spapr_populate_pa_features(env, fdt, offset, false); |
90da0d5a | 533 | |
0da6f3fe | 534 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 535 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
536 | |
537 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
538 | pft_size_prop, sizeof(pft_size_prop)))); | |
539 | ||
99861ecb IM |
540 | if (nb_numa_nodes > 1) { |
541 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
542 | } | |
0da6f3fe | 543 | |
12dbeb16 | 544 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
545 | |
546 | if (pcc->radix_page_info) { | |
547 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
548 | radix_AP_encodings[i] = | |
549 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
550 | } | |
551 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
552 | radix_AP_encodings, | |
553 | pcc->radix_page_info->count * | |
554 | sizeof(radix_AP_encodings[0])))); | |
555 | } | |
0da6f3fe BR |
556 | } |
557 | ||
558 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
559 | { | |
560 | CPUState *cs; | |
561 | int cpus_offset; | |
562 | char *nodename; | |
563 | int smt = kvmppc_smt_threads(); | |
564 | ||
565 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
566 | _FDT(cpus_offset); | |
567 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
568 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
569 | ||
570 | /* | |
571 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
572 | * created by fdt_add_subnode() end up in the right order in FDT | |
573 | * for the guest kernel the enumerate the CPUs correctly. | |
574 | */ | |
575 | CPU_FOREACH_REVERSE(cs) { | |
576 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
577 | int index = ppc_get_vcpu_dt_id(cpu); | |
578 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
579 | int offset; | |
580 | ||
581 | if ((index % smt) != 0) { | |
582 | continue; | |
583 | } | |
584 | ||
585 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
586 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
587 | g_free(nodename); | |
588 | _FDT(offset); | |
589 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
590 | } | |
591 | ||
592 | } | |
593 | ||
03d196b7 BR |
594 | /* |
595 | * Adds ibm,dynamic-reconfiguration-memory node. | |
596 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
597 | * of this device tree node. | |
598 | */ | |
599 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
600 | { | |
601 | MachineState *machine = MACHINE(spapr); | |
602 | int ret, i, offset; | |
603 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
604 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
605 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
606 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
607 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
608 | lmb_size; | |
03d196b7 | 609 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 610 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 611 | |
16c25aef | 612 | /* |
d0e5a8f2 | 613 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 614 | */ |
d0e5a8f2 | 615 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
616 | return 0; |
617 | } | |
618 | ||
ef001f06 TH |
619 | /* |
620 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
621 | * or ibm,associativity-lookup-arrays | |
622 | */ | |
623 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
624 | * sizeof(uint32_t); | |
03d196b7 BR |
625 | cur_index = int_buf = g_malloc0(buf_len); |
626 | ||
627 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
628 | ||
629 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
630 | sizeof(prop_lmb_size)); | |
631 | if (ret < 0) { | |
632 | goto out; | |
633 | } | |
634 | ||
635 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
636 | if (ret < 0) { | |
637 | goto out; | |
638 | } | |
639 | ||
640 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
641 | if (ret < 0) { | |
642 | goto out; | |
643 | } | |
644 | ||
645 | /* ibm,dynamic-memory */ | |
646 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
647 | cur_index++; | |
648 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 649 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
650 | uint32_t *dynamic_memory = cur_index; |
651 | ||
d0e5a8f2 BR |
652 | if (i >= hotplug_lmb_start) { |
653 | sPAPRDRConnector *drc; | |
d0e5a8f2 | 654 | |
fbf55397 | 655 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 656 | g_assert(drc); |
d0e5a8f2 BR |
657 | |
658 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
659 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 660 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 BR |
661 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
662 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
663 | if (memory_region_present(get_system_memory(), addr)) { | |
664 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
665 | } else { | |
666 | dynamic_memory[5] = cpu_to_be32(0); | |
667 | } | |
03d196b7 | 668 | } else { |
d0e5a8f2 BR |
669 | /* |
670 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
671 | * hotplug memory region -- all these are marked as reserved | |
672 | * and as having no valid DRC. | |
673 | */ | |
674 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
675 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
676 | dynamic_memory[2] = cpu_to_be32(0); | |
677 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
678 | dynamic_memory[4] = cpu_to_be32(-1); | |
679 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
680 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
681 | } |
682 | ||
683 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
684 | } | |
685 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
686 | if (ret < 0) { | |
687 | goto out; | |
688 | } | |
689 | ||
690 | /* ibm,associativity-lookup-arrays */ | |
691 | cur_index = int_buf; | |
6663864e | 692 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
693 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
694 | cur_index += 2; | |
6663864e | 695 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
696 | uint32_t associativity[] = { |
697 | cpu_to_be32(0x0), | |
698 | cpu_to_be32(0x0), | |
699 | cpu_to_be32(0x0), | |
700 | cpu_to_be32(i) | |
701 | }; | |
702 | memcpy(cur_index, associativity, sizeof(associativity)); | |
703 | cur_index += 4; | |
704 | } | |
705 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
706 | (cur_index - int_buf) * sizeof(uint32_t)); | |
707 | out: | |
708 | g_free(int_buf); | |
709 | return ret; | |
710 | } | |
711 | ||
6787d27b MR |
712 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
713 | sPAPROptionVector *ov5_updates) | |
714 | { | |
715 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 716 | int ret = 0, offset; |
6787d27b MR |
717 | |
718 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
719 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
720 | g_assert(smc->dr_lmb_enabled); | |
721 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
722 | if (ret) { |
723 | goto out; | |
724 | } | |
6787d27b MR |
725 | } |
726 | ||
417ece33 MR |
727 | offset = fdt_path_offset(fdt, "/chosen"); |
728 | if (offset < 0) { | |
729 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
730 | if (offset < 0) { | |
731 | return offset; | |
732 | } | |
733 | } | |
734 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
735 | "ibm,architecture-vec-5"); | |
736 | ||
737 | out: | |
6787d27b MR |
738 | return ret; |
739 | } | |
740 | ||
03d196b7 BR |
741 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
742 | target_ulong addr, target_ulong size, | |
6787d27b | 743 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
744 | { |
745 | void *fdt, *fdt_skel; | |
746 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 BR |
747 | |
748 | size -= sizeof(hdr); | |
749 | ||
750 | /* Create sceleton */ | |
751 | fdt_skel = g_malloc0(size); | |
752 | _FDT((fdt_create(fdt_skel, size))); | |
753 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
754 | _FDT((fdt_end_node(fdt_skel))); | |
755 | _FDT((fdt_finish(fdt_skel))); | |
756 | fdt = g_malloc0(size); | |
757 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
758 | g_free(fdt_skel); | |
759 | ||
760 | /* Fixup cpu nodes */ | |
5b120785 | 761 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 762 | |
6787d27b MR |
763 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
764 | return -1; | |
03d196b7 BR |
765 | } |
766 | ||
767 | /* Pack resulting tree */ | |
768 | _FDT((fdt_pack(fdt))); | |
769 | ||
770 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
771 | trace_spapr_cas_failed(size); | |
772 | return -1; | |
773 | } | |
774 | ||
775 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
776 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
777 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
778 | g_free(fdt); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
3f5dabce DG |
783 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
784 | { | |
785 | int rtas; | |
786 | GString *hypertas = g_string_sized_new(256); | |
787 | GString *qemu_hypertas = g_string_sized_new(256); | |
788 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
789 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
790 | memory_region_size(&spapr->hotplug_memory.mr); | |
791 | uint32_t lrdr_capacity[] = { | |
792 | cpu_to_be32(max_hotplug_addr >> 32), | |
793 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
794 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
795 | cpu_to_be32(max_cpus / smp_threads), | |
796 | }; | |
797 | ||
798 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
799 | ||
800 | /* hypertas */ | |
801 | add_str(hypertas, "hcall-pft"); | |
802 | add_str(hypertas, "hcall-term"); | |
803 | add_str(hypertas, "hcall-dabr"); | |
804 | add_str(hypertas, "hcall-interrupt"); | |
805 | add_str(hypertas, "hcall-tce"); | |
806 | add_str(hypertas, "hcall-vio"); | |
807 | add_str(hypertas, "hcall-splpar"); | |
808 | add_str(hypertas, "hcall-bulk"); | |
809 | add_str(hypertas, "hcall-set-mode"); | |
810 | add_str(hypertas, "hcall-sprg0"); | |
811 | add_str(hypertas, "hcall-copy"); | |
812 | add_str(hypertas, "hcall-debug"); | |
813 | add_str(qemu_hypertas, "hcall-memop1"); | |
814 | ||
815 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
816 | add_str(hypertas, "hcall-multi-tce"); | |
817 | } | |
818 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", | |
819 | hypertas->str, hypertas->len)); | |
820 | g_string_free(hypertas, TRUE); | |
821 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
822 | qemu_hypertas->str, qemu_hypertas->len)); | |
823 | g_string_free(qemu_hypertas, TRUE); | |
824 | ||
825 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
826 | refpoints, sizeof(refpoints))); | |
827 | ||
828 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
829 | RTAS_ERROR_LOG_MAX)); | |
830 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
831 | RTAS_EVENT_SCAN_RATE)); | |
832 | ||
833 | if (msi_nonbroken) { | |
834 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
835 | } | |
836 | ||
837 | /* | |
838 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
839 | * back to the guest cpu. | |
840 | * | |
841 | * While an additional ibm,extended-os-term property indicates | |
842 | * that rtas call return will always occur. Set this property. | |
843 | */ | |
844 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
845 | ||
846 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
847 | lrdr_capacity, sizeof(lrdr_capacity))); | |
848 | ||
849 | spapr_dt_rtas_tokens(fdt, rtas); | |
850 | } | |
851 | ||
9fb4541f SB |
852 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
853 | * that the guest may request and thus the valid values for bytes 24..26 of | |
854 | * option vector 5: */ | |
855 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
856 | { | |
545d6e2b SJS |
857 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
858 | ||
9fb4541f SB |
859 | char val[2 * 3] = { |
860 | 24, 0x00, /* Hash/Radix, filled in below. */ | |
861 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
862 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
863 | }; | |
864 | ||
865 | if (kvm_enabled()) { | |
866 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { | |
867 | val[1] = 0x80; /* OV5_MMU_BOTH */ | |
868 | } else if (kvmppc_has_cap_mmu_radix()) { | |
869 | val[1] = 0x40; /* OV5_MMU_RADIX_300 */ | |
870 | } else { | |
871 | val[1] = 0x00; /* Hash */ | |
872 | } | |
873 | } else { | |
545d6e2b SJS |
874 | if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { |
875 | /* V3 MMU supports both hash and radix (with dynamic switching) */ | |
876 | val[1] = 0xC0; | |
877 | } else { | |
878 | /* Otherwise we can only do hash */ | |
879 | val[1] = 0x00; | |
880 | } | |
9fb4541f SB |
881 | } |
882 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
883 | val, sizeof(val))); | |
884 | } | |
885 | ||
7c866c6a DG |
886 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
887 | { | |
888 | MachineState *machine = MACHINE(spapr); | |
889 | int chosen; | |
890 | const char *boot_device = machine->boot_order; | |
891 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
892 | size_t cb = 0; | |
893 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
894 | |
895 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
896 | ||
7c866c6a DG |
897 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
898 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
899 | spapr->initrd_base)); | |
900 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
901 | spapr->initrd_base + spapr->initrd_size)); | |
902 | ||
903 | if (spapr->kernel_size) { | |
904 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
905 | cpu_to_be64(spapr->kernel_size) }; | |
906 | ||
907 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
908 | &kprop, sizeof(kprop))); | |
909 | if (spapr->kernel_le) { | |
910 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
911 | } | |
912 | } | |
913 | if (boot_menu) { | |
914 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
915 | } | |
916 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
917 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
918 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
919 | ||
920 | if (cb && bootlist) { | |
921 | int i; | |
922 | ||
923 | for (i = 0; i < cb; i++) { | |
924 | if (bootlist[i] == '\n') { | |
925 | bootlist[i] = ' '; | |
926 | } | |
927 | } | |
928 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
929 | } | |
930 | ||
931 | if (boot_device && strlen(boot_device)) { | |
932 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
933 | } | |
934 | ||
935 | if (!spapr->has_graphics && stdout_path) { | |
936 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
937 | } | |
938 | ||
9fb4541f SB |
939 | spapr_dt_ov5_platform_support(fdt, chosen); |
940 | ||
7c866c6a DG |
941 | g_free(stdout_path); |
942 | g_free(bootlist); | |
943 | } | |
944 | ||
fca5f2dc DG |
945 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
946 | { | |
947 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
948 | * KVM to work under pHyp with some guest co-operation */ | |
949 | int hypervisor; | |
950 | uint8_t hypercall[16]; | |
951 | ||
952 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
953 | /* indicate KVM hypercall interface */ | |
954 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
955 | if (kvmppc_has_cap_fixup_hcalls()) { | |
956 | /* | |
957 | * Older KVM versions with older guest kernels were broken | |
958 | * with the magic page, don't allow the guest to map it. | |
959 | */ | |
960 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
961 | sizeof(hypercall))) { | |
962 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
963 | hypercall, sizeof(hypercall))); | |
964 | } | |
965 | } | |
966 | } | |
967 | ||
997b6cfc DG |
968 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
969 | hwaddr rtas_addr, | |
970 | hwaddr rtas_size) | |
a3467baa | 971 | { |
5b2128d2 | 972 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c0c47e3 | 973 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 974 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 975 | int ret; |
a3467baa | 976 | void *fdt; |
3384f95c | 977 | sPAPRPHBState *phb; |
398a0bd5 | 978 | char *buf; |
71cd4dac | 979 | int smt = kvmppc_smt_threads(); |
a3467baa | 980 | |
398a0bd5 DG |
981 | fdt = g_malloc0(FDT_MAX_SIZE); |
982 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 983 | |
398a0bd5 DG |
984 | /* Root node */ |
985 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
986 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
987 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
988 | ||
989 | /* | |
990 | * Add info to guest to indentify which host is it being run on | |
991 | * and what is the uuid of the guest | |
992 | */ | |
993 | if (kvmppc_get_host_model(&buf)) { | |
994 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
995 | g_free(buf); | |
996 | } | |
997 | if (kvmppc_get_host_serial(&buf)) { | |
998 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
999 | g_free(buf); | |
1000 | } | |
1001 | ||
1002 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1003 | ||
1004 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1005 | if (qemu_uuid_set) { | |
1006 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1007 | } | |
1008 | g_free(buf); | |
1009 | ||
1010 | if (qemu_get_vm_name()) { | |
1011 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1012 | qemu_get_vm_name())); | |
1013 | } | |
1014 | ||
1015 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1016 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1017 | |
9b9a1908 | 1018 | /* /interrupt controller */ |
71cd4dac | 1019 | spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP); |
9b9a1908 | 1020 | |
e8f986fc BR |
1021 | ret = spapr_populate_memory(spapr, fdt); |
1022 | if (ret < 0) { | |
ce9863b7 | 1023 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1024 | exit(1); |
7f763a5d DG |
1025 | } |
1026 | ||
bf5a6696 DG |
1027 | /* /vdevice */ |
1028 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1029 | |
4d9392be TH |
1030 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1031 | ret = spapr_rng_populate_dt(fdt); | |
1032 | if (ret < 0) { | |
ce9863b7 | 1033 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1034 | exit(1); |
1035 | } | |
1036 | } | |
1037 | ||
3384f95c | 1038 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1039 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1040 | if (ret < 0) { |
1041 | error_report("couldn't setup PCI devices in fdt"); | |
1042 | exit(1); | |
1043 | } | |
3384f95c DG |
1044 | } |
1045 | ||
0da6f3fe BR |
1046 | /* cpus */ |
1047 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1048 | |
c20d332a BR |
1049 | if (smc->dr_lmb_enabled) { |
1050 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1051 | } | |
1052 | ||
c5514d0e | 1053 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1054 | int offset = fdt_path_offset(fdt, "/cpus"); |
1055 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1056 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1057 | if (ret < 0) { | |
1058 | error_report("Couldn't set up CPU DR device tree properties"); | |
1059 | exit(1); | |
1060 | } | |
1061 | } | |
1062 | ||
ffb1e275 | 1063 | /* /event-sources */ |
ffbb1705 | 1064 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1065 | |
3f5dabce DG |
1066 | /* /rtas */ |
1067 | spapr_dt_rtas(spapr, fdt); | |
1068 | ||
7c866c6a DG |
1069 | /* /chosen */ |
1070 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1071 | |
fca5f2dc DG |
1072 | /* /hypervisor */ |
1073 | if (kvm_enabled()) { | |
1074 | spapr_dt_hypervisor(spapr, fdt); | |
1075 | } | |
1076 | ||
cf6e5223 DG |
1077 | /* Build memory reserve map */ |
1078 | if (spapr->kernel_size) { | |
1079 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1080 | } | |
1081 | if (spapr->initrd_size) { | |
1082 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1083 | } | |
1084 | ||
6787d27b MR |
1085 | /* ibm,client-architecture-support updates */ |
1086 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1087 | if (ret < 0) { | |
1088 | error_report("couldn't setup CAS properties fdt"); | |
1089 | exit(1); | |
1090 | } | |
1091 | ||
997b6cfc | 1092 | return fdt; |
9fdf0c29 DG |
1093 | } |
1094 | ||
1095 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1096 | { | |
1097 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1098 | } | |
1099 | ||
1d1be34d DG |
1100 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1101 | PowerPCCPU *cpu) | |
9fdf0c29 | 1102 | { |
1b14670a AF |
1103 | CPUPPCState *env = &cpu->env; |
1104 | ||
8d04fb55 JK |
1105 | /* The TCG path should also be holding the BQL at this point */ |
1106 | g_assert(qemu_mutex_iothread_locked()); | |
1107 | ||
efcb9383 DG |
1108 | if (msr_pr) { |
1109 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1110 | env->gpr[3] = H_PRIVILEGE; | |
1111 | } else { | |
aa100fa4 | 1112 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1113 | } |
9fdf0c29 DG |
1114 | } |
1115 | ||
9861bb3e SJS |
1116 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1117 | { | |
1118 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1119 | ||
1120 | return spapr->patb_entry; | |
1121 | } | |
1122 | ||
e6b8fd24 SMJ |
1123 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1124 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1125 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1126 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1127 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1128 | ||
715c5407 DG |
1129 | /* |
1130 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1131 | */ | |
1132 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1133 | { | |
1134 | if (spapr->htab_fd >= 0) { | |
1135 | return spapr->htab_fd; | |
1136 | } | |
1137 | ||
1138 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1139 | if (spapr->htab_fd < 0) { | |
1140 | error_report("Unable to open fd for reading hash table from KVM: %s", | |
1141 | strerror(errno)); | |
1142 | } | |
1143 | ||
1144 | return spapr->htab_fd; | |
1145 | } | |
1146 | ||
b4db5413 | 1147 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1148 | { |
1149 | if (spapr->htab_fd >= 0) { | |
1150 | close(spapr->htab_fd); | |
1151 | } | |
1152 | spapr->htab_fd = -1; | |
1153 | } | |
1154 | ||
e57ca75c DG |
1155 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1156 | { | |
1157 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1158 | ||
1159 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1160 | } | |
1161 | ||
1162 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, | |
1163 | hwaddr ptex, int n) | |
1164 | { | |
1165 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1166 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1167 | ||
1168 | if (!spapr->htab) { | |
1169 | /* | |
1170 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1171 | */ | |
1172 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1173 | kvmppc_read_hptes(hptes, ptex, n); | |
1174 | return hptes; | |
1175 | } | |
1176 | ||
1177 | /* | |
1178 | * HTAB is controlled by QEMU. Just point to the internally | |
1179 | * accessible PTEG. | |
1180 | */ | |
1181 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1182 | } | |
1183 | ||
1184 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1185 | const ppc_hash_pte64_t *hptes, | |
1186 | hwaddr ptex, int n) | |
1187 | { | |
1188 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1189 | ||
1190 | if (!spapr->htab) { | |
1191 | g_free((void *)hptes); | |
1192 | } | |
1193 | ||
1194 | /* Nothing to do for qemu managed HPT */ | |
1195 | } | |
1196 | ||
1197 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1198 | uint64_t pte0, uint64_t pte1) | |
1199 | { | |
1200 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1201 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1202 | ||
1203 | if (!spapr->htab) { | |
1204 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1205 | } else { | |
1206 | stq_p(spapr->htab + offset, pte0); | |
1207 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1208 | } | |
1209 | } | |
1210 | ||
8dfe8e7f DG |
1211 | static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1212 | { | |
1213 | int shift; | |
1214 | ||
1215 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1216 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1217 | * that's much more than is needed for Linux guests */ | |
1218 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1219 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1220 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1221 | return shift; | |
1222 | } | |
1223 | ||
06ec79e8 BR |
1224 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1225 | { | |
1226 | g_free(spapr->htab); | |
1227 | spapr->htab = NULL; | |
1228 | spapr->htab_shift = 0; | |
1229 | close_htab_fd(spapr); | |
1230 | } | |
1231 | ||
c5f54f3e DG |
1232 | static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1233 | Error **errp) | |
7f763a5d | 1234 | { |
c5f54f3e DG |
1235 | long rc; |
1236 | ||
1237 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1238 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1239 | |
1240 | rc = kvmppc_reset_htab(shift); | |
1241 | if (rc < 0) { | |
1242 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1243 | error_setg_errno(errp, errno, | |
1244 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1245 | shift); | |
1246 | /* This is almost certainly fatal, but if the caller really | |
1247 | * wants to carry on with shift == 0, it's welcome to try */ | |
1248 | } else if (rc > 0) { | |
1249 | /* kernel-side HPT allocated */ | |
1250 | if (rc != shift) { | |
1251 | error_setg(errp, | |
1252 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1253 | shift, rc); | |
7735feda BR |
1254 | } |
1255 | ||
7f763a5d | 1256 | spapr->htab_shift = shift; |
c18ad9a5 | 1257 | spapr->htab = NULL; |
b817772a | 1258 | } else { |
c5f54f3e DG |
1259 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1260 | size_t size = 1ULL << shift; | |
1261 | int i; | |
b817772a | 1262 | |
c5f54f3e DG |
1263 | spapr->htab = qemu_memalign(size, size); |
1264 | if (!spapr->htab) { | |
1265 | error_setg_errno(errp, errno, | |
1266 | "Could not allocate HPT of order %d", shift); | |
1267 | return; | |
7735feda BR |
1268 | } |
1269 | ||
c5f54f3e DG |
1270 | memset(spapr->htab, 0, size); |
1271 | spapr->htab_shift = shift; | |
e6b8fd24 | 1272 | |
c5f54f3e DG |
1273 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1274 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1275 | } |
7f763a5d | 1276 | } |
9fdf0c29 DG |
1277 | } |
1278 | ||
b4db5413 SJS |
1279 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1280 | { | |
1281 | spapr_reallocate_hpt(spapr, | |
1282 | spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), | |
1283 | &error_fatal); | |
1284 | if (spapr->vrma_adjust) { | |
1285 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), | |
1286 | spapr->htab_shift); | |
1287 | } | |
1288 | /* We're setting up a hash table, so that means we're not radix */ | |
1289 | spapr->patb_entry = 0; | |
1290 | } | |
1291 | ||
4f01a637 | 1292 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1293 | { |
1294 | bool matched = false; | |
1295 | ||
1296 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1297 | matched = true; | |
1298 | } | |
1299 | ||
1300 | if (!matched) { | |
1301 | error_report("Device %s is not supported by this machine yet.", | |
1302 | qdev_fw_name(DEVICE(sbdev))); | |
1303 | exit(1); | |
1304 | } | |
9e3f9733 AG |
1305 | } |
1306 | ||
c8787ad4 | 1307 | static void ppc_spapr_reset(void) |
a3467baa | 1308 | { |
c5f54f3e DG |
1309 | MachineState *machine = MACHINE(qdev_get_machine()); |
1310 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1311 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1312 | uint32_t rtas_limit; |
cae172ab | 1313 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1314 | void *fdt; |
1315 | int rc; | |
259186a7 | 1316 | |
9e3f9733 AG |
1317 | /* Check for unknown sysbus devices */ |
1318 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1319 | ||
b4db5413 SJS |
1320 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { |
1321 | /* If using KVM with radix mode available, VCPUs can be started | |
1322 | * without a HPT because KVM will start them in radix mode. | |
1323 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1324 | spapr->patb_entry = PATBE1_GR; | |
1325 | } else { | |
1326 | spapr->patb_entry = 0; | |
1327 | spapr_setup_hpt_and_vrma(spapr); | |
c5f54f3e | 1328 | } |
a3467baa | 1329 | |
c8787ad4 | 1330 | qemu_devices_reset(); |
a3467baa | 1331 | |
b7d1f77a BH |
1332 | /* |
1333 | * We place the device tree and RTAS just below either the top of the RMA, | |
1334 | * or just below 2GB, whichever is lowere, so that it can be | |
1335 | * processed with 32-bit real mode code if necessary | |
1336 | */ | |
1337 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1338 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1339 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1340 | |
6787d27b MR |
1341 | /* if this reset wasn't generated by CAS, we should reset our |
1342 | * negotiated options and start from scratch */ | |
1343 | if (!spapr->cas_reboot) { | |
1344 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1345 | spapr->ov5_cas = spapr_ovec_new(); | |
1346 | } | |
1347 | ||
cae172ab | 1348 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1349 | |
2cac78c1 | 1350 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1351 | |
997b6cfc DG |
1352 | rc = fdt_pack(fdt); |
1353 | ||
1354 | /* Should only fail if we've built a corrupted tree */ | |
1355 | assert(rc == 0); | |
1356 | ||
1357 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1358 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1359 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1360 | exit(1); | |
1361 | } | |
1362 | ||
1363 | /* Load the fdt */ | |
1364 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1365 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1366 | g_free(fdt); |
1367 | ||
a3467baa | 1368 | /* Set up the entry state */ |
182735ef | 1369 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
cae172ab | 1370 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1371 | first_ppc_cpu->env.gpr[5] = 0; |
1372 | first_cpu->halted = 0; | |
1b718907 | 1373 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1374 | |
6787d27b | 1375 | spapr->cas_reboot = false; |
a3467baa DG |
1376 | } |
1377 | ||
28e02042 | 1378 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1379 | { |
2ff3de68 | 1380 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1381 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1382 | |
3978b863 | 1383 | if (dinfo) { |
6231a6da MA |
1384 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1385 | &error_fatal); | |
639e8102 DG |
1386 | } |
1387 | ||
1388 | qdev_init_nofail(dev); | |
1389 | ||
1390 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1391 | } | |
1392 | ||
28e02042 | 1393 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1394 | { |
147ff807 CLG |
1395 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1396 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1397 | &error_fatal); | |
1398 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1399 | &error_fatal); | |
1400 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1401 | "date", &error_fatal); | |
28df36a1 DG |
1402 | } |
1403 | ||
8c57b867 | 1404 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1405 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1406 | { |
8c57b867 | 1407 | switch (vga_interface_type) { |
8c57b867 | 1408 | case VGA_NONE: |
7effdaa3 MW |
1409 | return false; |
1410 | case VGA_DEVICE: | |
1411 | return true; | |
1ddcae82 | 1412 | case VGA_STD: |
b798c190 | 1413 | case VGA_VIRTIO: |
1ddcae82 | 1414 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1415 | default: |
14c6a894 DG |
1416 | error_setg(errp, |
1417 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1418 | return false; | |
f28359d8 | 1419 | } |
f28359d8 LZ |
1420 | } |
1421 | ||
880ae7de DG |
1422 | static int spapr_post_load(void *opaque, int version_id) |
1423 | { | |
28e02042 | 1424 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1425 | int err = 0; |
1426 | ||
a7ff1212 | 1427 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1428 | CPUState *cs; |
1429 | CPU_FOREACH(cs) { | |
1430 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1431 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1432 | } |
1433 | } | |
1434 | ||
631b22ea | 1435 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1436 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1437 | * So when migrating from those versions, poke the incoming offset | |
1438 | * value into the RTC device */ | |
1439 | if (version_id < 3) { | |
147ff807 | 1440 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1441 | } |
1442 | ||
1443 | return err; | |
1444 | } | |
1445 | ||
1446 | static bool version_before_3(void *opaque, int version_id) | |
1447 | { | |
1448 | return version_id < 3; | |
1449 | } | |
1450 | ||
62ef3760 MR |
1451 | static bool spapr_ov5_cas_needed(void *opaque) |
1452 | { | |
1453 | sPAPRMachineState *spapr = opaque; | |
1454 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1455 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1456 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1457 | bool cas_needed; | |
1458 | ||
1459 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1460 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1461 | * Both of these options encode machine topology into the device-tree | |
1462 | * in such a way that the now-booted OS should still be able to interact | |
1463 | * appropriately with QEMU regardless of what options were actually | |
1464 | * negotiatied on the source side. | |
1465 | * | |
1466 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1467 | * are the only options available on the current machine/platform. | |
1468 | * Since these are the only options available for pseries-2.7 and | |
1469 | * earlier, this allows us to maintain old->new/new->old migration | |
1470 | * compatibility. | |
1471 | * | |
1472 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1473 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1474 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1475 | * of the actual CAS-negotiated values to continue working properly. For | |
1476 | * example, availability of memory unplug depends on knowing whether | |
1477 | * OV5_HP_EVT was negotiated via CAS. | |
1478 | * | |
1479 | * Thus, for any cases where the set of available CAS-negotiatable | |
1480 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
1481 | * include the CAS-negotiated options in the migration stream. | |
1482 | */ | |
1483 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1484 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
1485 | ||
1486 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1487 | * the mask itself since in the future it's possible "legacy" bits may be | |
1488 | * removed via machine options, which could generate a false positive | |
1489 | * that breaks migration. | |
1490 | */ | |
1491 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1492 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1493 | ||
1494 | spapr_ovec_cleanup(ov5_mask); | |
1495 | spapr_ovec_cleanup(ov5_legacy); | |
1496 | spapr_ovec_cleanup(ov5_removed); | |
1497 | ||
1498 | return cas_needed; | |
1499 | } | |
1500 | ||
1501 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1502 | .name = "spapr_option_vector_ov5_cas", | |
1503 | .version_id = 1, | |
1504 | .minimum_version_id = 1, | |
1505 | .needed = spapr_ov5_cas_needed, | |
1506 | .fields = (VMStateField[]) { | |
1507 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1508 | vmstate_spapr_ovec, sPAPROptionVector), | |
1509 | VMSTATE_END_OF_LIST() | |
1510 | }, | |
1511 | }; | |
1512 | ||
9861bb3e SJS |
1513 | static bool spapr_patb_entry_needed(void *opaque) |
1514 | { | |
1515 | sPAPRMachineState *spapr = opaque; | |
1516 | ||
1517 | return !!spapr->patb_entry; | |
1518 | } | |
1519 | ||
1520 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1521 | .name = "spapr_patb_entry", | |
1522 | .version_id = 1, | |
1523 | .minimum_version_id = 1, | |
1524 | .needed = spapr_patb_entry_needed, | |
1525 | .fields = (VMStateField[]) { | |
1526 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1527 | VMSTATE_END_OF_LIST() | |
1528 | }, | |
1529 | }; | |
1530 | ||
4be21d56 DG |
1531 | static const VMStateDescription vmstate_spapr = { |
1532 | .name = "spapr", | |
880ae7de | 1533 | .version_id = 3, |
4be21d56 | 1534 | .minimum_version_id = 1, |
880ae7de | 1535 | .post_load = spapr_post_load, |
3aff6c2f | 1536 | .fields = (VMStateField[]) { |
880ae7de DG |
1537 | /* used to be @next_irq */ |
1538 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1539 | |
1540 | /* RTC offset */ | |
28e02042 | 1541 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1542 | |
28e02042 | 1543 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1544 | VMSTATE_END_OF_LIST() |
1545 | }, | |
62ef3760 MR |
1546 | .subsections = (const VMStateDescription*[]) { |
1547 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1548 | &vmstate_spapr_patb_entry, |
62ef3760 MR |
1549 | NULL |
1550 | } | |
4be21d56 DG |
1551 | }; |
1552 | ||
4be21d56 DG |
1553 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1554 | { | |
28e02042 | 1555 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1556 | |
4be21d56 DG |
1557 | /* "Iteration" header */ |
1558 | qemu_put_be32(f, spapr->htab_shift); | |
1559 | ||
e68cb8b4 AK |
1560 | if (spapr->htab) { |
1561 | spapr->htab_save_index = 0; | |
1562 | spapr->htab_first_pass = true; | |
1563 | } else { | |
1564 | assert(kvm_enabled()); | |
e68cb8b4 AK |
1565 | } |
1566 | ||
1567 | ||
4be21d56 DG |
1568 | return 0; |
1569 | } | |
1570 | ||
28e02042 | 1571 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1572 | int64_t max_ns) |
1573 | { | |
378bc217 | 1574 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1575 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1576 | int index = spapr->htab_save_index; | |
bc72ad67 | 1577 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1578 | |
1579 | assert(spapr->htab_first_pass); | |
1580 | ||
1581 | do { | |
1582 | int chunkstart; | |
1583 | ||
1584 | /* Consume invalid HPTEs */ | |
1585 | while ((index < htabslots) | |
1586 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 1587 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1588 | index++; |
4be21d56 DG |
1589 | } |
1590 | ||
1591 | /* Consume valid HPTEs */ | |
1592 | chunkstart = index; | |
338c25b6 | 1593 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 1594 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 1595 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1596 | index++; |
4be21d56 DG |
1597 | } |
1598 | ||
1599 | if (index > chunkstart) { | |
1600 | int n_valid = index - chunkstart; | |
1601 | ||
1602 | qemu_put_be32(f, chunkstart); | |
1603 | qemu_put_be16(f, n_valid); | |
1604 | qemu_put_be16(f, 0); | |
1605 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1606 | HASH_PTE_SIZE_64 * n_valid); | |
1607 | ||
378bc217 DG |
1608 | if (has_timeout && |
1609 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1610 | break; |
1611 | } | |
1612 | } | |
1613 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1614 | ||
1615 | if (index >= htabslots) { | |
1616 | assert(index == htabslots); | |
1617 | index = 0; | |
1618 | spapr->htab_first_pass = false; | |
1619 | } | |
1620 | spapr->htab_save_index = index; | |
1621 | } | |
1622 | ||
28e02042 | 1623 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1624 | int64_t max_ns) |
4be21d56 DG |
1625 | { |
1626 | bool final = max_ns < 0; | |
1627 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1628 | int examined = 0, sent = 0; | |
1629 | int index = spapr->htab_save_index; | |
bc72ad67 | 1630 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1631 | |
1632 | assert(!spapr->htab_first_pass); | |
1633 | ||
1634 | do { | |
1635 | int chunkstart, invalidstart; | |
1636 | ||
1637 | /* Consume non-dirty HPTEs */ | |
1638 | while ((index < htabslots) | |
1639 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1640 | index++; | |
1641 | examined++; | |
1642 | } | |
1643 | ||
1644 | chunkstart = index; | |
1645 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1646 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1647 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1648 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1649 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1650 | index++; | |
1651 | examined++; | |
1652 | } | |
1653 | ||
1654 | invalidstart = index; | |
1655 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1656 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1657 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1658 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1659 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1660 | index++; | |
1661 | examined++; | |
1662 | } | |
1663 | ||
1664 | if (index > chunkstart) { | |
1665 | int n_valid = invalidstart - chunkstart; | |
1666 | int n_invalid = index - invalidstart; | |
1667 | ||
1668 | qemu_put_be32(f, chunkstart); | |
1669 | qemu_put_be16(f, n_valid); | |
1670 | qemu_put_be16(f, n_invalid); | |
1671 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1672 | HASH_PTE_SIZE_64 * n_valid); | |
1673 | sent += index - chunkstart; | |
1674 | ||
bc72ad67 | 1675 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1676 | break; |
1677 | } | |
1678 | } | |
1679 | ||
1680 | if (examined >= htabslots) { | |
1681 | break; | |
1682 | } | |
1683 | ||
1684 | if (index >= htabslots) { | |
1685 | assert(index == htabslots); | |
1686 | index = 0; | |
1687 | } | |
1688 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1689 | ||
1690 | if (index >= htabslots) { | |
1691 | assert(index == htabslots); | |
1692 | index = 0; | |
1693 | } | |
1694 | ||
1695 | spapr->htab_save_index = index; | |
1696 | ||
e68cb8b4 | 1697 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1698 | } |
1699 | ||
e68cb8b4 AK |
1700 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1701 | #define MAX_KVM_BUF_SIZE 2048 | |
1702 | ||
4be21d56 DG |
1703 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1704 | { | |
28e02042 | 1705 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1706 | int fd; |
e68cb8b4 | 1707 | int rc = 0; |
4be21d56 DG |
1708 | |
1709 | /* Iteration header */ | |
1710 | qemu_put_be32(f, 0); | |
1711 | ||
e68cb8b4 AK |
1712 | if (!spapr->htab) { |
1713 | assert(kvm_enabled()); | |
1714 | ||
715c5407 DG |
1715 | fd = get_htab_fd(spapr); |
1716 | if (fd < 0) { | |
1717 | return fd; | |
01a57972 SMJ |
1718 | } |
1719 | ||
715c5407 | 1720 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1721 | if (rc < 0) { |
1722 | return rc; | |
1723 | } | |
1724 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1725 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1726 | } else { | |
e68cb8b4 | 1727 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1728 | } |
1729 | ||
1730 | /* End marker */ | |
1731 | qemu_put_be32(f, 0); | |
1732 | qemu_put_be16(f, 0); | |
1733 | qemu_put_be16(f, 0); | |
1734 | ||
e68cb8b4 | 1735 | return rc; |
4be21d56 DG |
1736 | } |
1737 | ||
1738 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1739 | { | |
28e02042 | 1740 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1741 | int fd; |
4be21d56 DG |
1742 | |
1743 | /* Iteration header */ | |
1744 | qemu_put_be32(f, 0); | |
1745 | ||
e68cb8b4 AK |
1746 | if (!spapr->htab) { |
1747 | int rc; | |
1748 | ||
1749 | assert(kvm_enabled()); | |
1750 | ||
715c5407 DG |
1751 | fd = get_htab_fd(spapr); |
1752 | if (fd < 0) { | |
1753 | return fd; | |
01a57972 SMJ |
1754 | } |
1755 | ||
715c5407 | 1756 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1757 | if (rc < 0) { |
1758 | return rc; | |
1759 | } | |
e68cb8b4 | 1760 | } else { |
378bc217 DG |
1761 | if (spapr->htab_first_pass) { |
1762 | htab_save_first_pass(f, spapr, -1); | |
1763 | } | |
e68cb8b4 AK |
1764 | htab_save_later_pass(f, spapr, -1); |
1765 | } | |
4be21d56 DG |
1766 | |
1767 | /* End marker */ | |
1768 | qemu_put_be32(f, 0); | |
1769 | qemu_put_be16(f, 0); | |
1770 | qemu_put_be16(f, 0); | |
1771 | ||
1772 | return 0; | |
1773 | } | |
1774 | ||
1775 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1776 | { | |
28e02042 | 1777 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1778 | uint32_t section_hdr; |
e68cb8b4 | 1779 | int fd = -1; |
4be21d56 DG |
1780 | |
1781 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 1782 | error_report("htab_load() bad version"); |
4be21d56 DG |
1783 | return -EINVAL; |
1784 | } | |
1785 | ||
1786 | section_hdr = qemu_get_be32(f); | |
1787 | ||
1788 | if (section_hdr) { | |
9897e462 | 1789 | Error *local_err = NULL; |
c5f54f3e DG |
1790 | |
1791 | /* First section gives the htab size */ | |
1792 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
1793 | if (local_err) { | |
1794 | error_report_err(local_err); | |
4be21d56 DG |
1795 | return -EINVAL; |
1796 | } | |
1797 | return 0; | |
1798 | } | |
1799 | ||
e68cb8b4 AK |
1800 | if (!spapr->htab) { |
1801 | assert(kvm_enabled()); | |
1802 | ||
1803 | fd = kvmppc_get_htab_fd(true); | |
1804 | if (fd < 0) { | |
98a5d100 DG |
1805 | error_report("Unable to open fd to restore KVM hash table: %s", |
1806 | strerror(errno)); | |
e68cb8b4 AK |
1807 | } |
1808 | } | |
1809 | ||
4be21d56 DG |
1810 | while (true) { |
1811 | uint32_t index; | |
1812 | uint16_t n_valid, n_invalid; | |
1813 | ||
1814 | index = qemu_get_be32(f); | |
1815 | n_valid = qemu_get_be16(f); | |
1816 | n_invalid = qemu_get_be16(f); | |
1817 | ||
1818 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1819 | /* End of Stream */ | |
1820 | break; | |
1821 | } | |
1822 | ||
e68cb8b4 | 1823 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1824 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1825 | /* Bad index in stream */ | |
98a5d100 DG |
1826 | error_report( |
1827 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
1828 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
1829 | return -EINVAL; |
1830 | } | |
1831 | ||
e68cb8b4 AK |
1832 | if (spapr->htab) { |
1833 | if (n_valid) { | |
1834 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1835 | HASH_PTE_SIZE_64 * n_valid); | |
1836 | } | |
1837 | if (n_invalid) { | |
1838 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1839 | HASH_PTE_SIZE_64 * n_invalid); | |
1840 | } | |
1841 | } else { | |
1842 | int rc; | |
1843 | ||
1844 | assert(fd >= 0); | |
1845 | ||
1846 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1847 | if (rc < 0) { | |
1848 | return rc; | |
1849 | } | |
4be21d56 DG |
1850 | } |
1851 | } | |
1852 | ||
e68cb8b4 AK |
1853 | if (!spapr->htab) { |
1854 | assert(fd >= 0); | |
1855 | close(fd); | |
1856 | } | |
1857 | ||
4be21d56 DG |
1858 | return 0; |
1859 | } | |
1860 | ||
c573fc03 TH |
1861 | static void htab_cleanup(void *opaque) |
1862 | { | |
1863 | sPAPRMachineState *spapr = opaque; | |
1864 | ||
1865 | close_htab_fd(spapr); | |
1866 | } | |
1867 | ||
4be21d56 DG |
1868 | static SaveVMHandlers savevm_htab_handlers = { |
1869 | .save_live_setup = htab_save_setup, | |
1870 | .save_live_iterate = htab_save_iterate, | |
a3e06c3d | 1871 | .save_live_complete_precopy = htab_save_complete, |
c573fc03 | 1872 | .cleanup = htab_cleanup, |
4be21d56 DG |
1873 | .load_state = htab_load, |
1874 | }; | |
1875 | ||
5b2128d2 AG |
1876 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1877 | Error **errp) | |
1878 | { | |
1879 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1880 | machine->boot_order = g_strdup(boot_device); | |
1881 | } | |
1882 | ||
224245bf DG |
1883 | /* |
1884 | * Reset routine for LMB DR devices. | |
1885 | * | |
1886 | * Unlike PCI DR devices, LMB DR devices explicitly register this reset | |
1887 | * routine. Reset for PCI DR devices will be handled by PHB reset routine | |
1888 | * when it walks all its children devices. LMB devices reset occurs | |
1889 | * as part of spapr_ppc_reset(). | |
1890 | */ | |
1891 | static void spapr_drc_reset(void *opaque) | |
1892 | { | |
1893 | sPAPRDRConnector *drc = opaque; | |
1894 | DeviceState *d = DEVICE(drc); | |
1895 | ||
1896 | if (d) { | |
1897 | device_reset(d); | |
1898 | } | |
1899 | } | |
1900 | ||
1901 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) | |
1902 | { | |
1903 | MachineState *machine = MACHINE(spapr); | |
1904 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 1905 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
1906 | int i; |
1907 | ||
1908 | for (i = 0; i < nr_lmbs; i++) { | |
1909 | sPAPRDRConnector *drc; | |
1910 | uint64_t addr; | |
1911 | ||
e8f986fc | 1912 | addr = i * lmb_size + spapr->hotplug_memory.base; |
2d335818 | 1913 | drc = spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
224245bf DG |
1914 | addr/lmb_size); |
1915 | qemu_register_reset(spapr_drc_reset, drc); | |
1916 | } | |
1917 | } | |
1918 | ||
1919 | /* | |
1920 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
1921 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
1922 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
1923 | */ | |
7c150d6f | 1924 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
1925 | { |
1926 | int i; | |
1927 | ||
7c150d6f DG |
1928 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
1929 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
1930 | " is not aligned to %llu MiB", | |
1931 | machine->ram_size, | |
1932 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1933 | return; | |
1934 | } | |
1935 | ||
1936 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
1937 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
1938 | " is not aligned to %llu MiB", | |
1939 | machine->ram_size, | |
1940 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1941 | return; | |
224245bf DG |
1942 | } |
1943 | ||
1944 | for (i = 0; i < nb_numa_nodes; i++) { | |
1945 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
1946 | error_setg(errp, |
1947 | "Node %d memory size 0x%" PRIx64 | |
1948 | " is not aligned to %llu MiB", | |
1949 | i, numa_info[i].node_mem, | |
1950 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1951 | return; | |
224245bf DG |
1952 | } |
1953 | } | |
1954 | } | |
1955 | ||
535455fd IM |
1956 | /* find cpu slot in machine->possible_cpus by core_id */ |
1957 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
1958 | { | |
1959 | int index = id / smp_threads; | |
1960 | ||
1961 | if (index >= ms->possible_cpus->len) { | |
1962 | return NULL; | |
1963 | } | |
1964 | if (idx) { | |
1965 | *idx = index; | |
1966 | } | |
1967 | return &ms->possible_cpus->cpus[index]; | |
1968 | } | |
1969 | ||
0c86d0fd DG |
1970 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
1971 | { | |
1972 | MachineState *machine = MACHINE(spapr); | |
1973 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1974 | char *type = spapr_get_cpu_core_type(machine->cpu_model); | |
1975 | int smt = kvmppc_smt_threads(); | |
535455fd IM |
1976 | const CPUArchIdList *possible_cpus; |
1977 | int boot_cores_nr = smp_cpus / smp_threads; | |
0c86d0fd DG |
1978 | int i; |
1979 | ||
1980 | if (!type) { | |
1981 | error_report("Unable to find sPAPR CPU Core definition"); | |
1982 | exit(1); | |
1983 | } | |
1984 | ||
535455fd | 1985 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
c5514d0e | 1986 | if (mc->has_hotpluggable_cpus) { |
0c86d0fd DG |
1987 | if (smp_cpus % smp_threads) { |
1988 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
1989 | smp_cpus, smp_threads); | |
1990 | exit(1); | |
1991 | } | |
1992 | if (max_cpus % smp_threads) { | |
1993 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
1994 | max_cpus, smp_threads); | |
1995 | exit(1); | |
1996 | } | |
0c86d0fd DG |
1997 | } else { |
1998 | if (max_cpus != smp_cpus) { | |
1999 | error_report("This machine version does not support CPU hotplug"); | |
2000 | exit(1); | |
2001 | } | |
535455fd | 2002 | boot_cores_nr = possible_cpus->len; |
0c86d0fd DG |
2003 | } |
2004 | ||
535455fd | 2005 | for (i = 0; i < possible_cpus->len; i++) { |
0c86d0fd DG |
2006 | int core_id = i * smp_threads; |
2007 | ||
c5514d0e | 2008 | if (mc->has_hotpluggable_cpus) { |
0c86d0fd | 2009 | sPAPRDRConnector *drc = |
2d335818 | 2010 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, |
0c86d0fd DG |
2011 | (core_id / smp_threads) * smt); |
2012 | ||
2013 | qemu_register_reset(spapr_drc_reset, drc); | |
2014 | } | |
2015 | ||
535455fd | 2016 | if (i < boot_cores_nr) { |
0c86d0fd DG |
2017 | Object *core = object_new(type); |
2018 | int nr_threads = smp_threads; | |
2019 | ||
2020 | /* Handle the partially filled core for older machine types */ | |
2021 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2022 | nr_threads = smp_cpus - i * smp_threads; | |
2023 | } | |
2024 | ||
2025 | object_property_set_int(core, nr_threads, "nr-threads", | |
2026 | &error_fatal); | |
2027 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2028 | &error_fatal); | |
2029 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2030 | } | |
2031 | } | |
2032 | g_free(type); | |
2033 | } | |
2034 | ||
9fdf0c29 | 2035 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 2036 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 2037 | { |
28e02042 | 2038 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2039 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2040 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2041 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2042 | PCIHostState *phb; |
9fdf0c29 | 2043 | int i; |
890c2b77 AK |
2044 | MemoryRegion *sysmem = get_system_memory(); |
2045 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
2046 | MemoryRegion *rma_region; |
2047 | void *rma = NULL; | |
a8170e5e | 2048 | hwaddr rma_alloc_size; |
b082d65a | 2049 | hwaddr node0_size = spapr_node0_size(); |
b7d1f77a | 2050 | long load_limit, fw_size; |
39ac8455 | 2051 | char *filename; |
9fdf0c29 | 2052 | |
226419d6 | 2053 | msi_nonbroken = true; |
0ee2c058 | 2054 | |
d43b45e2 | 2055 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2056 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2057 | |
354ac20a | 2058 | /* Allocate RMA if necessary */ |
658fa66b | 2059 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
2060 | |
2061 | if (rma_alloc_size == -1) { | |
730fce59 | 2062 | error_report("Unable to create RMA"); |
354ac20a DG |
2063 | exit(1); |
2064 | } | |
7f763a5d | 2065 | |
c4177479 | 2066 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 2067 | spapr->rma_size = rma_alloc_size; |
354ac20a | 2068 | } else { |
c4177479 | 2069 | spapr->rma_size = node0_size; |
7f763a5d DG |
2070 | |
2071 | /* With KVM, we don't actually know whether KVM supports an | |
2072 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2073 | * (HV KVM using VRMA), so we always assume the latter | |
2074 | * | |
2075 | * In that case, we also limit the initial allocations for RTAS | |
2076 | * etc... to 256M since we have no way to know what the VRMA size | |
2077 | * is going to be as it depends on the size of the hash table | |
2078 | * isn't determined yet. | |
2079 | */ | |
2080 | if (kvm_enabled()) { | |
2081 | spapr->vrma_adjust = 1; | |
2082 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
2083 | } | |
912acdf4 BH |
2084 | |
2085 | /* Actually we don't support unbounded RMA anymore since we | |
2086 | * added proper emulation of HV mode. The max we can get is | |
2087 | * 16G which also happens to be what we configure for PAPR | |
2088 | * mode so make sure we don't do anything bigger than that | |
2089 | */ | |
2090 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
2091 | } |
2092 | ||
c4177479 | 2093 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2094 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2095 | spapr->rma_size); | |
c4177479 AK |
2096 | exit(1); |
2097 | } | |
2098 | ||
b7d1f77a BH |
2099 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2100 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2101 | |
7b565160 | 2102 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2103 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2104 | |
facdb8b6 MR |
2105 | /* Set up containers for ibm,client-set-architecture negotiated options */ |
2106 | spapr->ov5 = spapr_ovec_new(); | |
2107 | spapr->ov5_cas = spapr_ovec_new(); | |
2108 | ||
224245bf | 2109 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2110 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2111 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2112 | } |
2113 | ||
417ece33 | 2114 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
545d6e2b SJS |
2115 | if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { |
2116 | /* KVM and TCG always allow GTSE with radix... */ | |
9fb4541f SB |
2117 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2118 | } | |
2119 | /* ... but not with hash (currently). */ | |
417ece33 | 2120 | |
ffbb1705 MR |
2121 | /* advertise support for dedicated HP event source to guests */ |
2122 | if (spapr->use_hotplug_event_source) { | |
2123 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2124 | } | |
2125 | ||
9fdf0c29 | 2126 | /* init CPUs */ |
19fb2c36 | 2127 | if (machine->cpu_model == NULL) { |
3daa4a9f | 2128 | machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; |
9fdf0c29 | 2129 | } |
94a94e4c | 2130 | |
e703d2f7 GK |
2131 | ppc_cpu_parse_features(machine->cpu_model); |
2132 | ||
0c86d0fd | 2133 | spapr_init_cpus(spapr); |
9fdf0c29 | 2134 | |
026bfd89 DG |
2135 | if (kvm_enabled()) { |
2136 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2137 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2138 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2139 | |
2140 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2141 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2142 | } |
2143 | ||
9fdf0c29 | 2144 | /* allocate RAM */ |
f92f5da1 | 2145 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2146 | machine->ram_size); |
f92f5da1 | 2147 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2148 | |
658fa66b AK |
2149 | if (rma_alloc_size && rma) { |
2150 | rma_region = g_new(MemoryRegion, 1); | |
2151 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
2152 | rma_alloc_size, rma); | |
2153 | vmstate_register_ram_global(rma_region); | |
2154 | memory_region_add_subregion(sysmem, 0, rma_region); | |
2155 | } | |
2156 | ||
4a1c9cf0 BR |
2157 | /* initialize hotplug memory address space */ |
2158 | if (machine->ram_size < machine->maxram_size) { | |
2159 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
2160 | /* |
2161 | * Limit the number of hotpluggable memory slots to half the number | |
2162 | * slots that KVM supports, leaving the other half for PCI and other | |
2163 | * devices. However ensure that number of slots doesn't drop below 32. | |
2164 | */ | |
2165 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2166 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2167 | |
71c9a3dd BR |
2168 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2169 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2170 | } | |
2171 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2172 | error_report("Specified number of memory slots %" |
2173 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2174 | machine->ram_slots, max_memslots); |
d54e4d76 | 2175 | exit(1); |
4a1c9cf0 BR |
2176 | } |
2177 | ||
2178 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
2179 | SPAPR_HOTPLUG_MEM_ALIGN); | |
2180 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
2181 | "hotplug-memory", hotplug_mem_size); | |
2182 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
2183 | &spapr->hotplug_memory.mr); | |
2184 | } | |
2185 | ||
224245bf DG |
2186 | if (smc->dr_lmb_enabled) { |
2187 | spapr_create_lmb_dr_connectors(spapr); | |
2188 | } | |
2189 | ||
39ac8455 | 2190 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2191 | if (!filename) { |
730fce59 | 2192 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2193 | exit(1); |
2194 | } | |
b7d1f77a | 2195 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2196 | if (spapr->rtas_size < 0) { |
2197 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2198 | exit(1); | |
2199 | } | |
b7d1f77a BH |
2200 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2201 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2202 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2203 | exit(1); |
2204 | } | |
4d8d5467 | 2205 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2206 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2207 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2208 | exit(1); |
2209 | } | |
7267c094 | 2210 | g_free(filename); |
39ac8455 | 2211 | |
ffbb1705 | 2212 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2213 | spapr_events_init(spapr); |
2214 | ||
12f42174 | 2215 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2216 | spapr_rtc_create(spapr); |
12f42174 | 2217 | |
b5cec4c5 | 2218 | /* Set up VIO bus */ |
4040ab72 DG |
2219 | spapr->vio_bus = spapr_vio_bus_init(); |
2220 | ||
277f9acf | 2221 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 2222 | if (serial_hds[i]) { |
d601fac4 | 2223 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
2224 | } |
2225 | } | |
9fdf0c29 | 2226 | |
639e8102 DG |
2227 | /* We always have at least the nvram device on VIO */ |
2228 | spapr_create_nvram(spapr); | |
2229 | ||
3384f95c | 2230 | /* Set up PCI */ |
fa28f71b AK |
2231 | spapr_pci_rtas_init(); |
2232 | ||
89dfd6e1 | 2233 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2234 | |
277f9acf | 2235 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2236 | NICInfo *nd = &nd_table[i]; |
2237 | ||
2238 | if (!nd->model) { | |
7267c094 | 2239 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
2240 | } |
2241 | ||
2242 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 2243 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2244 | } else { |
29b358f9 | 2245 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2246 | } |
2247 | } | |
2248 | ||
6e270446 | 2249 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2250 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2251 | } |
2252 | ||
f28359d8 | 2253 | /* Graphics */ |
14c6a894 | 2254 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2255 | spapr->has_graphics = true; |
c6e76503 | 2256 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2257 | } |
2258 | ||
4ee9ced9 | 2259 | if (machine->usb) { |
57040d45 TH |
2260 | if (smc->use_ohci_by_default) { |
2261 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2262 | } else { | |
2263 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2264 | } | |
c86580b8 | 2265 | |
35139a59 | 2266 | if (spapr->has_graphics) { |
c86580b8 MA |
2267 | USBBus *usb_bus = usb_bus_find(-1); |
2268 | ||
2269 | usb_create_simple(usb_bus, "usb-kbd"); | |
2270 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2271 | } |
2272 | } | |
2273 | ||
7f763a5d | 2274 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2275 | error_report( |
2276 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2277 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2278 | exit(1); |
2279 | } | |
2280 | ||
9fdf0c29 DG |
2281 | if (kernel_filename) { |
2282 | uint64_t lowaddr = 0; | |
2283 | ||
a19f7fb0 DG |
2284 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2285 | NULL, NULL, &lowaddr, NULL, 1, | |
2286 | PPC_ELF_MACHINE, 0, 0); | |
2287 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2288 | spapr->kernel_size = load_elf(kernel_filename, | |
2289 | translate_kernel_address, NULL, NULL, | |
2290 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2291 | 0, 0); | |
2292 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2293 | } |
a19f7fb0 DG |
2294 | if (spapr->kernel_size < 0) { |
2295 | error_report("error loading %s: %s", kernel_filename, | |
2296 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2297 | exit(1); |
2298 | } | |
2299 | ||
2300 | /* load initrd */ | |
2301 | if (initrd_filename) { | |
4d8d5467 BH |
2302 | /* Try to locate the initrd in the gap between the kernel |
2303 | * and the firmware. Add a bit of space just in case | |
2304 | */ | |
a19f7fb0 DG |
2305 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2306 | + 0x1ffff) & ~0xffff; | |
2307 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2308 | spapr->initrd_base, | |
2309 | load_limit | |
2310 | - spapr->initrd_base); | |
2311 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2312 | error_report("could not load initial ram disk '%s'", |
2313 | initrd_filename); | |
9fdf0c29 DG |
2314 | exit(1); |
2315 | } | |
9fdf0c29 | 2316 | } |
4d8d5467 | 2317 | } |
a3467baa | 2318 | |
8e7ea787 AF |
2319 | if (bios_name == NULL) { |
2320 | bios_name = FW_FILE_NAME; | |
2321 | } | |
2322 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2323 | if (!filename) { |
68fea5a0 | 2324 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2325 | exit(1); |
2326 | } | |
4d8d5467 | 2327 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2328 | if (fw_size <= 0) { |
2329 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2330 | exit(1); |
2331 | } | |
2332 | g_free(filename); | |
4d8d5467 | 2333 | |
28e02042 DG |
2334 | /* FIXME: Should register things through the MachineState's qdev |
2335 | * interface, this is a legacy from the sPAPREnvironment structure | |
2336 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2337 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2338 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2339 | &savevm_htab_handlers, spapr); | |
2340 | ||
5b2128d2 | 2341 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2342 | |
42043e4f | 2343 | if (kvm_enabled()) { |
3dc410ae | 2344 | /* to stop and start vmclock */ |
42043e4f LV |
2345 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2346 | &spapr->tb); | |
3dc410ae AK |
2347 | |
2348 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2349 | } |
9fdf0c29 DG |
2350 | } |
2351 | ||
135a129a AK |
2352 | static int spapr_kvm_type(const char *vm_type) |
2353 | { | |
2354 | if (!vm_type) { | |
2355 | return 0; | |
2356 | } | |
2357 | ||
2358 | if (!strcmp(vm_type, "HV")) { | |
2359 | return 1; | |
2360 | } | |
2361 | ||
2362 | if (!strcmp(vm_type, "PR")) { | |
2363 | return 2; | |
2364 | } | |
2365 | ||
2366 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2367 | exit(1); | |
2368 | } | |
2369 | ||
71461b0f | 2370 | /* |
627b84f4 | 2371 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2372 | * for the bootindex property handling. |
2373 | */ | |
2374 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2375 | DeviceState *dev) | |
2376 | { | |
2377 | #define CAST(type, obj, name) \ | |
2378 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2379 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2380 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2381 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2382 | |
2383 | if (d) { | |
2384 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2385 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2386 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2387 | ||
2388 | if (spapr) { | |
2389 | /* | |
2390 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2391 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2392 | * in the top 16 bits of the 64-bit LUN | |
2393 | */ | |
2394 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2395 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2396 | (uint64_t)id << 48); | |
2397 | } else if (virtio) { | |
2398 | /* | |
2399 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2400 | * in the top 32 bits of the 64-bit LUN | |
2401 | * Note: the quote above is from SLOF and it is wrong, | |
2402 | * the actual binding is: | |
2403 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2404 | */ | |
2405 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2406 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2407 | (uint64_t)id << 32); | |
2408 | } else if (usb) { | |
2409 | /* | |
2410 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2411 | * in the top 32 bits of the 64-bit LUN | |
2412 | */ | |
2413 | unsigned usb_port = atoi(usb->port->path); | |
2414 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2415 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2416 | (uint64_t)id << 32); | |
2417 | } | |
2418 | } | |
2419 | ||
b99260eb TH |
2420 | /* |
2421 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2422 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2423 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2424 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2425 | */ | |
2426 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2427 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2428 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2429 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2430 | } | |
2431 | } | |
2432 | ||
71461b0f AK |
2433 | if (phb) { |
2434 | /* Replace "pci" with "pci@800000020000000" */ | |
2435 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2436 | } | |
2437 | ||
c4e13492 FF |
2438 | if (vsc) { |
2439 | /* Same logic as virtio above */ | |
2440 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2441 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2442 | } | |
2443 | ||
4871dd4c TH |
2444 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2445 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2446 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2447 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2448 | } | |
2449 | ||
71461b0f AK |
2450 | return NULL; |
2451 | } | |
2452 | ||
23825581 EH |
2453 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2454 | { | |
28e02042 | 2455 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2456 | |
28e02042 | 2457 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2458 | } |
2459 | ||
2460 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2461 | { | |
28e02042 | 2462 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2463 | |
28e02042 DG |
2464 | g_free(spapr->kvm_type); |
2465 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2466 | } |
2467 | ||
f6229214 MR |
2468 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2469 | { | |
2470 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2471 | ||
2472 | return spapr->use_hotplug_event_source; | |
2473 | } | |
2474 | ||
2475 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2476 | Error **errp) | |
2477 | { | |
2478 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2479 | ||
2480 | spapr->use_hotplug_event_source = value; | |
2481 | } | |
2482 | ||
23825581 EH |
2483 | static void spapr_machine_initfn(Object *obj) |
2484 | { | |
715c5407 DG |
2485 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2486 | ||
2487 | spapr->htab_fd = -1; | |
f6229214 | 2488 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2489 | object_property_add_str(obj, "kvm-type", |
2490 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2491 | object_property_set_description(obj, "kvm-type", |
2492 | "Specifies the KVM virtualization mode (HV, PR)", | |
2493 | NULL); | |
f6229214 MR |
2494 | object_property_add_bool(obj, "modern-hotplug-events", |
2495 | spapr_get_modern_hotplug_events, | |
2496 | spapr_set_modern_hotplug_events, | |
2497 | NULL); | |
2498 | object_property_set_description(obj, "modern-hotplug-events", | |
2499 | "Use dedicated hotplug event mechanism in" | |
2500 | " place of standard EPOW events when possible" | |
2501 | " (required for memory hot-unplug support)", | |
2502 | NULL); | |
23825581 EH |
2503 | } |
2504 | ||
87bbdd9c DG |
2505 | static void spapr_machine_finalizefn(Object *obj) |
2506 | { | |
2507 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2508 | ||
2509 | g_free(spapr->kvm_type); | |
2510 | } | |
2511 | ||
1c7ad77e | 2512 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 2513 | { |
34316482 AK |
2514 | cpu_synchronize_state(cs); |
2515 | ppc_cpu_do_system_reset(cs); | |
2516 | } | |
2517 | ||
2518 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2519 | { | |
2520 | CPUState *cs; | |
2521 | ||
2522 | CPU_FOREACH(cs) { | |
1c7ad77e | 2523 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
2524 | } |
2525 | } | |
2526 | ||
79b78a6b MR |
2527 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2528 | uint32_t node, bool dedicated_hp_event_source, | |
2529 | Error **errp) | |
c20d332a BR |
2530 | { |
2531 | sPAPRDRConnector *drc; | |
c20d332a BR |
2532 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
2533 | int i, fdt_offset, fdt_size; | |
2534 | void *fdt; | |
79b78a6b | 2535 | uint64_t addr = addr_start; |
c20d332a | 2536 | |
c20d332a | 2537 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
2538 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2539 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
2540 | g_assert(drc); |
2541 | ||
2542 | fdt = create_device_tree(&fdt_size); | |
2543 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2544 | SPAPR_MEMORY_BLOCK_SIZE); | |
2545 | ||
0be4e886 | 2546 | spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); |
c20d332a | 2547 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
5c0139a8 | 2548 | if (!dev->hotplugged) { |
0be4e886 | 2549 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
5c0139a8 MR |
2550 | /* guests expect coldplugged LMBs to be pre-allocated */ |
2551 | drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); | |
2552 | drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); | |
2553 | } | |
c20d332a | 2554 | } |
5dd5238c JD |
2555 | /* send hotplug notification to the |
2556 | * guest only in case of hotplugged memory | |
2557 | */ | |
2558 | if (dev->hotplugged) { | |
79b78a6b | 2559 | if (dedicated_hp_event_source) { |
fbf55397 DG |
2560 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2561 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
2562 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
2563 | nr_lmbs, | |
0b55aa91 | 2564 | spapr_drc_index(drc)); |
79b78a6b MR |
2565 | } else { |
2566 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2567 | nr_lmbs); | |
2568 | } | |
5dd5238c | 2569 | } |
c20d332a BR |
2570 | } |
2571 | ||
2572 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2573 | uint32_t node, Error **errp) | |
2574 | { | |
2575 | Error *local_err = NULL; | |
2576 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2577 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2578 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2579 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2580 | uint64_t align = memory_region_get_alignment(mr); | |
2581 | uint64_t size = memory_region_size(mr); | |
2582 | uint64_t addr; | |
df587133 | 2583 | |
d6a9b0b8 | 2584 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2585 | if (local_err) { |
2586 | goto out; | |
2587 | } | |
2588 | ||
2589 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2590 | if (local_err) { | |
2591 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2592 | goto out; | |
2593 | } | |
2594 | ||
79b78a6b MR |
2595 | spapr_add_lmbs(dev, addr, size, node, |
2596 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
2597 | &error_abort); | |
c20d332a BR |
2598 | |
2599 | out: | |
2600 | error_propagate(errp, local_err); | |
2601 | } | |
2602 | ||
c871bc70 LV |
2603 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2604 | Error **errp) | |
2605 | { | |
2606 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2607 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2608 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2609 | uint64_t size = memory_region_size(mr); | |
2610 | char *mem_dev; | |
2611 | ||
2612 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2613 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
2614 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2615 | return; | |
2616 | } | |
2617 | ||
2618 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
2619 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
2620 | error_setg(errp, "Memory backend has bad page size. " | |
2621 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 2622 | goto out; |
c871bc70 | 2623 | } |
8a9e0e7b GK |
2624 | |
2625 | out: | |
2626 | g_free(mem_dev); | |
c871bc70 LV |
2627 | } |
2628 | ||
0cffce56 DG |
2629 | struct sPAPRDIMMState { |
2630 | PCDIMMDevice *dimm; | |
cf632463 | 2631 | uint32_t nr_lmbs; |
0cffce56 DG |
2632 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
2633 | }; | |
2634 | ||
2635 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
2636 | PCDIMMDevice *dimm) | |
2637 | { | |
2638 | sPAPRDIMMState *dimm_state = NULL; | |
2639 | ||
2640 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
2641 | if (dimm_state->dimm == dimm) { | |
2642 | break; | |
2643 | } | |
2644 | } | |
2645 | return dimm_state; | |
2646 | } | |
2647 | ||
2648 | static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, | |
2649 | sPAPRDIMMState *dimm_state) | |
2650 | { | |
2651 | g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm)); | |
2652 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next); | |
2653 | } | |
2654 | ||
2655 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
2656 | sPAPRDIMMState *dimm_state) | |
2657 | { | |
2658 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
2659 | g_free(dimm_state); | |
2660 | } | |
cf632463 | 2661 | |
16ee9980 DHB |
2662 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
2663 | PCDIMMDevice *dimm) | |
2664 | { | |
2665 | sPAPRDRConnector *drc; | |
2666 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2667 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2668 | uint64_t size = memory_region_size(mr); | |
2669 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
2670 | uint32_t avail_lmbs = 0; | |
2671 | uint64_t addr_start, addr; | |
2672 | int i; | |
2673 | sPAPRDIMMState *ds; | |
2674 | ||
2675 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
2676 | &error_abort); | |
2677 | ||
2678 | addr = addr_start; | |
2679 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
2680 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2681 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 2682 | g_assert(drc); |
454b580a | 2683 | if (drc->dev) { |
16ee9980 DHB |
2684 | avail_lmbs++; |
2685 | } | |
2686 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
2687 | } | |
2688 | ||
2689 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
2690 | ds->nr_lmbs = avail_lmbs; | |
2691 | ds->dimm = dimm; | |
2692 | spapr_pending_dimm_unplugs_add(ms, ds); | |
2693 | return ds; | |
2694 | } | |
2695 | ||
31834723 DHB |
2696 | /* Callback to be called during DRC release. */ |
2697 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 2698 | { |
0cffce56 DG |
2699 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
2700 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); | |
2701 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); | |
cf632463 | 2702 | |
16ee9980 DHB |
2703 | /* This information will get lost if a migration occurs |
2704 | * during the unplug process. In this case recover it. */ | |
2705 | if (ds == NULL) { | |
2706 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
454b580a DG |
2707 | /* The DRC being examined by the caller at least must be counted */ |
2708 | g_assert(ds->nr_lmbs); | |
2709 | } | |
2710 | ||
2711 | if (--ds->nr_lmbs) { | |
cf632463 BR |
2712 | return; |
2713 | } | |
2714 | ||
0cffce56 | 2715 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
2716 | |
2717 | /* | |
2718 | * Now that all the LMBs have been removed by the guest, call the | |
2719 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
2720 | */ | |
cf632463 BR |
2721 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
2722 | } | |
2723 | ||
cf632463 BR |
2724 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2725 | Error **errp) | |
2726 | { | |
2727 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2728 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2729 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2730 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2731 | ||
2732 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2733 | object_unparent(OBJECT(dev)); | |
2734 | } | |
2735 | ||
2736 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
2737 | DeviceState *dev, Error **errp) | |
2738 | { | |
0cffce56 | 2739 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
2740 | Error *local_err = NULL; |
2741 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2742 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2743 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2744 | uint64_t size = memory_region_size(mr); | |
0cffce56 DG |
2745 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
2746 | uint64_t addr_start, addr; | |
2747 | int i; | |
2748 | sPAPRDRConnector *drc; | |
0cffce56 | 2749 | sPAPRDIMMState *ds; |
cf632463 | 2750 | |
0cffce56 DG |
2751 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
2752 | &local_err); | |
cf632463 BR |
2753 | if (local_err) { |
2754 | goto out; | |
2755 | } | |
2756 | ||
0cffce56 DG |
2757 | ds = g_malloc0(sizeof(sPAPRDIMMState)); |
2758 | ds->nr_lmbs = nr_lmbs; | |
2759 | ds->dimm = dimm; | |
2760 | spapr_pending_dimm_unplugs_add(spapr, ds); | |
2761 | ||
2762 | addr = addr_start; | |
2763 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
2764 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2765 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
2766 | g_assert(drc); |
2767 | ||
0be4e886 | 2768 | spapr_drc_detach(drc, dev, errp); |
0cffce56 DG |
2769 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2770 | } | |
2771 | ||
fbf55397 DG |
2772 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2773 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 2774 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 2775 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
2776 | out: |
2777 | error_propagate(errp, local_err); | |
2778 | } | |
2779 | ||
af81cf32 BR |
2780 | void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
2781 | sPAPRMachineState *spapr) | |
2782 | { | |
2783 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2784 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2785 | int id = ppc_get_vcpu_dt_id(cpu); | |
2786 | void *fdt; | |
2787 | int offset, fdt_size; | |
2788 | char *nodename; | |
2789 | ||
2790 | fdt = create_device_tree(&fdt_size); | |
2791 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
2792 | offset = fdt_add_subnode(fdt, 0, nodename); | |
2793 | ||
2794 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
2795 | g_free(nodename); | |
2796 | ||
2797 | *fdt_offset = offset; | |
2798 | return fdt; | |
2799 | } | |
2800 | ||
115debf2 IM |
2801 | static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2802 | Error **errp) | |
ff9006dd | 2803 | { |
535455fd | 2804 | MachineState *ms = MACHINE(qdev_get_machine()); |
ff9006dd | 2805 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 2806 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 2807 | |
07572c06 | 2808 | assert(core_slot); |
535455fd | 2809 | core_slot->cpu = NULL; |
ff9006dd IM |
2810 | object_unparent(OBJECT(dev)); |
2811 | } | |
2812 | ||
31834723 DHB |
2813 | /* Callback to be called during DRC release. */ |
2814 | void spapr_core_release(DeviceState *dev) | |
115debf2 IM |
2815 | { |
2816 | HotplugHandler *hotplug_ctrl; | |
2817 | ||
2818 | hotplug_ctrl = qdev_get_hotplug_handler(dev); | |
2819 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
2820 | } | |
2821 | ||
2822 | static | |
2823 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2824 | Error **errp) | |
ff9006dd | 2825 | { |
535455fd IM |
2826 | int index; |
2827 | sPAPRDRConnector *drc; | |
ff9006dd | 2828 | Error *local_err = NULL; |
535455fd IM |
2829 | CPUCore *cc = CPU_CORE(dev); |
2830 | int smt = kvmppc_smt_threads(); | |
ff9006dd | 2831 | |
535455fd IM |
2832 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
2833 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
2834 | cc->core_id); | |
2835 | return; | |
2836 | } | |
ff9006dd IM |
2837 | if (index == 0) { |
2838 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
2839 | return; | |
2840 | } | |
2841 | ||
fbf55397 | 2842 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd IM |
2843 | g_assert(drc); |
2844 | ||
0be4e886 | 2845 | spapr_drc_detach(drc, dev, &local_err); |
ff9006dd IM |
2846 | if (local_err) { |
2847 | error_propagate(errp, local_err); | |
2848 | return; | |
2849 | } | |
2850 | ||
2851 | spapr_hotplug_req_remove_by_index(drc); | |
2852 | } | |
2853 | ||
2854 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2855 | Error **errp) | |
2856 | { | |
2857 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
2858 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
2859 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); | |
2860 | CPUCore *cc = CPU_CORE(dev); | |
2861 | CPUState *cs = CPU(core->threads); | |
2862 | sPAPRDRConnector *drc; | |
2863 | Error *local_err = NULL; | |
2864 | void *fdt = NULL; | |
2865 | int fdt_offset = 0; | |
ff9006dd | 2866 | int smt = kvmppc_smt_threads(); |
535455fd IM |
2867 | CPUArchId *core_slot; |
2868 | int index; | |
ff9006dd | 2869 | |
535455fd IM |
2870 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
2871 | if (!core_slot) { | |
2872 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
2873 | cc->core_id); | |
2874 | return; | |
2875 | } | |
fbf55397 | 2876 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd | 2877 | |
c5514d0e | 2878 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd IM |
2879 | |
2880 | /* | |
2881 | * Setup CPU DT entries only for hotplugged CPUs. For boot time or | |
2882 | * coldplugged CPUs DT entries are setup in spapr_build_fdt(). | |
2883 | */ | |
2884 | if (dev->hotplugged) { | |
2885 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
2886 | } | |
2887 | ||
2888 | if (drc) { | |
0be4e886 DG |
2889 | spapr_drc_attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, |
2890 | &local_err); | |
ff9006dd IM |
2891 | if (local_err) { |
2892 | g_free(fdt); | |
ff9006dd IM |
2893 | error_propagate(errp, local_err); |
2894 | return; | |
2895 | } | |
2896 | } | |
2897 | ||
2898 | if (dev->hotplugged) { | |
2899 | /* | |
2900 | * Send hotplug notification interrupt to the guest only in case | |
2901 | * of hotplugged CPUs. | |
2902 | */ | |
2903 | spapr_hotplug_req_add_by_index(drc); | |
2904 | } else { | |
2905 | /* | |
2906 | * Set the right DRC states for cold plugged CPU. | |
2907 | */ | |
2908 | if (drc) { | |
2909 | sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2910 | drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); | |
2911 | drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); | |
2912 | } | |
2913 | } | |
535455fd | 2914 | core_slot->cpu = OBJECT(dev); |
ff9006dd IM |
2915 | } |
2916 | ||
2917 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2918 | Error **errp) | |
2919 | { | |
2920 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
2921 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
2922 | Error *local_err = NULL; |
2923 | CPUCore *cc = CPU_CORE(dev); | |
2924 | char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); | |
2925 | const char *type = object_get_typename(OBJECT(dev)); | |
535455fd IM |
2926 | CPUArchId *core_slot; |
2927 | int index; | |
ff9006dd | 2928 | |
c5514d0e | 2929 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
2930 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
2931 | goto out; | |
2932 | } | |
2933 | ||
2934 | if (strcmp(base_core_type, type)) { | |
2935 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
2936 | goto out; | |
2937 | } | |
2938 | ||
2939 | if (cc->core_id % smp_threads) { | |
2940 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
2941 | goto out; | |
2942 | } | |
2943 | ||
459264ef DG |
2944 | /* |
2945 | * In general we should have homogeneous threads-per-core, but old | |
2946 | * (pre hotplug support) machine types allow the last core to have | |
2947 | * reduced threads as a compatibility hack for when we allowed | |
2948 | * total vcpus not a multiple of threads-per-core. | |
2949 | */ | |
2950 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
8149e299 DG |
2951 | error_setg(errp, "invalid nr-threads %d, must be %d", |
2952 | cc->nr_threads, smp_threads); | |
2953 | return; | |
2954 | } | |
2955 | ||
535455fd IM |
2956 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
2957 | if (!core_slot) { | |
ff9006dd IM |
2958 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
2959 | goto out; | |
2960 | } | |
2961 | ||
535455fd | 2962 | if (core_slot->cpu) { |
ff9006dd IM |
2963 | error_setg(&local_err, "core %d already populated", cc->core_id); |
2964 | goto out; | |
2965 | } | |
2966 | ||
a0ceb640 | 2967 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 2968 | |
ff9006dd IM |
2969 | out: |
2970 | g_free(base_core_type); | |
2971 | error_propagate(errp, local_err); | |
2972 | } | |
2973 | ||
c20d332a BR |
2974 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
2975 | DeviceState *dev, Error **errp) | |
2976 | { | |
2977 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
2978 | ||
2979 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 2980 | int node; |
c20d332a BR |
2981 | |
2982 | if (!smc->dr_lmb_enabled) { | |
2983 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
2984 | return; | |
2985 | } | |
2986 | node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); | |
2987 | if (*errp) { | |
2988 | return; | |
2989 | } | |
1a5512bb GA |
2990 | if (node < 0 || node >= MAX_NODES) { |
2991 | error_setg(errp, "Invaild node %d", node); | |
2992 | return; | |
2993 | } | |
c20d332a | 2994 | |
b556854b BR |
2995 | /* |
2996 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
2997 | * memory-less node, but instead will silently add the memory | |
2998 | * to the first node that has some memory. This causes two | |
2999 | * unexpected behaviours for the user. | |
3000 | * | |
3001 | * - Memory gets hotplugged to a different node than what the user | |
3002 | * specified. | |
3003 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
3004 | * to memory-less node, a reboot will set things accordingly | |
3005 | * and the previously hotplugged memory now ends in the right node. | |
3006 | * This appears as if some memory moved from one node to another. | |
3007 | * | |
3008 | * So until kernel starts supporting memory hotplug to memory-less | |
3009 | * nodes, just prevent such attempts upfront in QEMU. | |
3010 | */ | |
3011 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
3012 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
3013 | node); | |
3014 | return; | |
3015 | } | |
3016 | ||
c20d332a | 3017 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
3018 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3019 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3020 | } |
3021 | } | |
3022 | ||
3023 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, | |
3024 | DeviceState *dev, Error **errp) | |
3025 | { | |
cf632463 | 3026 | sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); |
3c0c47e3 | 3027 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
6f4b5c3e | 3028 | |
c20d332a | 3029 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
cf632463 BR |
3030 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { |
3031 | spapr_memory_unplug(hotplug_dev, dev, errp); | |
3032 | } else { | |
3033 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3034 | } | |
3035 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c5514d0e | 3036 | if (!mc->has_hotpluggable_cpus) { |
cf632463 BR |
3037 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3038 | return; | |
3039 | } | |
3040 | spapr_core_unplug(hotplug_dev, dev, errp); | |
3041 | } | |
3042 | } | |
3043 | ||
3044 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, | |
3045 | DeviceState *dev, Error **errp) | |
3046 | { | |
3047 | sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); | |
3048 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | |
3049 | ||
3050 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3051 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3052 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3053 | } else { | |
3054 | /* NOTE: this means there is a window after guest reset, prior to | |
3055 | * CAS negotiation, where unplug requests will fail due to the | |
3056 | * capability not being detected yet. This is a bit different than | |
3057 | * the case with PCI unplug, where the events will be queued and | |
3058 | * eventually handled by the guest after boot | |
3059 | */ | |
3060 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3061 | } | |
6f4b5c3e | 3062 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3063 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3064 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3065 | return; | |
3066 | } | |
115debf2 | 3067 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3068 | } |
3069 | } | |
3070 | ||
94a94e4c BR |
3071 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3072 | DeviceState *dev, Error **errp) | |
3073 | { | |
c871bc70 LV |
3074 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3075 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3076 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3077 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3078 | } | |
3079 | } | |
3080 | ||
7ebaf795 BR |
3081 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3082 | DeviceState *dev) | |
c20d332a | 3083 | { |
94a94e4c BR |
3084 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3085 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3086 | return HOTPLUG_HANDLER(machine); |
3087 | } | |
3088 | return NULL; | |
3089 | } | |
3090 | ||
ea089eeb IM |
3091 | static CpuInstanceProperties |
3092 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3093 | { |
ea089eeb IM |
3094 | CPUArchId *core_slot; |
3095 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3096 | ||
3097 | /* make sure possible_cpu are intialized */ | |
3098 | mc->possible_cpu_arch_ids(machine); | |
3099 | /* get CPU core slot containing thread that matches cpu_index */ | |
3100 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3101 | assert(core_slot); | |
3102 | return core_slot->props; | |
20bb648d DG |
3103 | } |
3104 | ||
535455fd IM |
3105 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3106 | { | |
3107 | int i; | |
3108 | int spapr_max_cores = max_cpus / smp_threads; | |
3109 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3110 | ||
c5514d0e | 3111 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3112 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3113 | } | |
3114 | if (machine->possible_cpus) { | |
3115 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3116 | return machine->possible_cpus; | |
3117 | } | |
3118 | ||
3119 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
3120 | sizeof(CPUArchId) * spapr_max_cores); | |
3121 | machine->possible_cpus->len = spapr_max_cores; | |
3122 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3123 | int core_id = i * smp_threads; | |
3124 | ||
f2d672c2 | 3125 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3126 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3127 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3128 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
ea089eeb IM |
3129 | |
3130 | /* default distribution of CPUs over NUMA nodes */ | |
3131 | if (nb_numa_nodes) { | |
3132 | /* preset values but do not enable them i.e. 'has_node_id = false', | |
3133 | * numa init code will enable them later if manual mapping wasn't | |
3134 | * present on CLI */ | |
3135 | machine->possible_cpus->cpus[i].props.node_id = | |
3136 | core_id / smp_threads / smp_cores % nb_numa_nodes; | |
3137 | } | |
535455fd IM |
3138 | } |
3139 | return machine->possible_cpus; | |
3140 | } | |
3141 | ||
6737d9ad | 3142 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3143 | uint64_t *buid, hwaddr *pio, |
3144 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3145 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3146 | { | |
357d1e3b DG |
3147 | /* |
3148 | * New-style PHB window placement. | |
3149 | * | |
3150 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3151 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3152 | * windows. | |
3153 | * | |
3154 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3155 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3156 | * | |
3157 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3158 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3159 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3160 | * 1TiB 64-bit MMIO windows for each PHB. | |
3161 | */ | |
6737d9ad | 3162 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3163 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3164 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3165 | int i; |
3166 | ||
357d1e3b DG |
3167 | /* Sanity check natural alignments */ |
3168 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3169 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3170 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3171 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3172 | /* Sanity check bounds */ | |
25e6a118 MT |
3173 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3174 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3175 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3176 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3177 | ||
3178 | if (index >= SPAPR_MAX_PHBS) { | |
3179 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3180 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3181 | return; |
3182 | } | |
3183 | ||
3184 | *buid = base_buid + index; | |
3185 | for (i = 0; i < n_dma; ++i) { | |
3186 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3187 | } | |
3188 | ||
357d1e3b DG |
3189 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3190 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3191 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3192 | } |
3193 | ||
7844e12b CLG |
3194 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3195 | { | |
3196 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3197 | ||
3198 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3199 | } | |
3200 | ||
3201 | static void spapr_ics_resend(XICSFabric *dev) | |
3202 | { | |
3203 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3204 | ||
3205 | ics_resend(spapr->ics); | |
3206 | } | |
3207 | ||
06747ba6 | 3208 | static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) |
b2fc59aa | 3209 | { |
5bc8d26d | 3210 | PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); |
b2fc59aa | 3211 | |
5bc8d26d | 3212 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3213 | } |
3214 | ||
6449da45 CLG |
3215 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3216 | Monitor *mon) | |
3217 | { | |
3218 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3219 | CPUState *cs; |
3220 | ||
3221 | CPU_FOREACH(cs) { | |
3222 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3223 | |
5bc8d26d | 3224 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3225 | } |
3226 | ||
3227 | ics_pic_print_info(spapr->ics, mon); | |
3228 | } | |
3229 | ||
29ee3247 AK |
3230 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3231 | { | |
3232 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3233 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3234 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3235 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3236 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3237 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3238 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3239 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3240 | |
0eb9054c | 3241 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3242 | |
3243 | /* | |
3244 | * We set up the default / latest behaviour here. The class_init | |
3245 | * functions for the specific versioned machine types can override | |
3246 | * these details for backwards compatibility | |
3247 | */ | |
958db90c MA |
3248 | mc->init = ppc_spapr_init; |
3249 | mc->reset = ppc_spapr_reset; | |
3250 | mc->block_default_type = IF_SCSI; | |
6244bb7e | 3251 | mc->max_cpus = 1024; |
958db90c | 3252 | mc->no_parallel = 1; |
5b2128d2 | 3253 | mc->default_boot_order = ""; |
a34944fe | 3254 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 3255 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 3256 | mc->has_dynamic_sysbus = true; |
e4024630 | 3257 | mc->pci_allow_0_address = true; |
7ebaf795 | 3258 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3259 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a BR |
3260 | hc->plug = spapr_machine_device_plug; |
3261 | hc->unplug = spapr_machine_device_unplug; | |
ea089eeb | 3262 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
535455fd | 3263 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3264 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 3265 | |
fc9f38c3 | 3266 | smc->dr_lmb_enabled = true; |
3daa4a9f | 3267 | smc->tcg_default_cpu = "POWER8"; |
c5514d0e | 3268 | mc->has_hotpluggable_cpus = true; |
71461b0f | 3269 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3270 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3271 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3272 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3273 | vhc->hpt_mask = spapr_hpt_mask; |
3274 | vhc->map_hptes = spapr_map_hptes; | |
3275 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3276 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3277 | vhc->get_patbe = spapr_get_patbe; |
7844e12b CLG |
3278 | xic->ics_get = spapr_ics_get; |
3279 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3280 | xic->icp_get = spapr_icp_get; |
6449da45 | 3281 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3282 | /* Force NUMA node memory size to be a multiple of |
3283 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3284 | * in which LMBs are represented and hot-added | |
3285 | */ | |
3286 | mc->numa_mem_align_shift = 28; | |
29ee3247 AK |
3287 | } |
3288 | ||
3289 | static const TypeInfo spapr_machine_info = { | |
3290 | .name = TYPE_SPAPR_MACHINE, | |
3291 | .parent = TYPE_MACHINE, | |
4aee7362 | 3292 | .abstract = true, |
6ca1502e | 3293 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 3294 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 3295 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3296 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3297 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3298 | .interfaces = (InterfaceInfo[]) { |
3299 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3300 | { TYPE_NMI }, |
c20d332a | 3301 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3302 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3303 | { TYPE_XICS_FABRIC }, |
6449da45 | 3304 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3305 | { } |
3306 | }, | |
29ee3247 AK |
3307 | }; |
3308 | ||
fccbc785 | 3309 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3310 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3311 | void *data) \ | |
3312 | { \ | |
3313 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3314 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3315 | if (latest) { \ |
3316 | mc->alias = "pseries"; \ | |
3317 | mc->is_default = 1; \ | |
3318 | } \ | |
5013c547 DG |
3319 | } \ |
3320 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
3321 | { \ | |
3322 | MachineState *machine = MACHINE(obj); \ | |
3323 | spapr_machine_##suffix##_instance_options(machine); \ | |
3324 | } \ | |
3325 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
3326 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3327 | .parent = TYPE_SPAPR_MACHINE, \ | |
3328 | .class_init = spapr_machine_##suffix##_class_init, \ | |
3329 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
3330 | }; \ | |
3331 | static void spapr_machine_register_##suffix(void) \ | |
3332 | { \ | |
3333 | type_register(&spapr_machine_##suffix##_info); \ | |
3334 | } \ | |
0e6aac87 | 3335 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3336 | |
3fa14fbe DG |
3337 | /* |
3338 | * pseries-2.10 | |
3339 | */ | |
3340 | static void spapr_machine_2_10_instance_options(MachineState *machine) | |
3341 | { | |
3342 | } | |
3343 | ||
3344 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
3345 | { | |
3346 | /* Defaults for the latest behaviour inherited from the base class */ | |
3347 | } | |
3348 | ||
3349 | DEFINE_SPAPR_MACHINE(2_10, "2.10", true); | |
3350 | ||
fa325e6c DG |
3351 | /* |
3352 | * pseries-2.9 | |
3353 | */ | |
3fa14fbe DG |
3354 | #define SPAPR_COMPAT_2_9 \ |
3355 | HW_COMPAT_2_9 | |
3356 | ||
fa325e6c DG |
3357 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
3358 | { | |
3fa14fbe | 3359 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
3360 | } |
3361 | ||
3362 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
3363 | { | |
3fa14fbe DG |
3364 | spapr_machine_2_10_class_options(mc); |
3365 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 3366 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
fa325e6c DG |
3367 | } |
3368 | ||
3fa14fbe | 3369 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 3370 | |
db800b21 DG |
3371 | /* |
3372 | * pseries-2.8 | |
3373 | */ | |
82516263 DG |
3374 | #define SPAPR_COMPAT_2_8 \ |
3375 | HW_COMPAT_2_8 \ | |
3376 | { \ | |
3377 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3378 | .property = "pcie-extended-configuration-space", \ | |
3379 | .value = "off", \ | |
3380 | }, | |
fa325e6c | 3381 | |
db800b21 DG |
3382 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
3383 | { | |
fa325e6c | 3384 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
3385 | } |
3386 | ||
3387 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
3388 | { | |
fa325e6c DG |
3389 | spapr_machine_2_9_class_options(mc); |
3390 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 3391 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
3392 | } |
3393 | ||
fa325e6c | 3394 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 3395 | |
1ea1eefc BR |
3396 | /* |
3397 | * pseries-2.7 | |
3398 | */ | |
357d1e3b DG |
3399 | #define SPAPR_COMPAT_2_7 \ |
3400 | HW_COMPAT_2_7 \ | |
3401 | { \ | |
3402 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3403 | .property = "mem_win_size", \ | |
3404 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
3405 | }, \ | |
3406 | { \ | |
3407 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3408 | .property = "mem64_win_size", \ | |
3409 | .value = "0", \ | |
146c11f1 DG |
3410 | }, \ |
3411 | { \ | |
3412 | .driver = TYPE_POWERPC_CPU, \ | |
3413 | .property = "pre-2.8-migration", \ | |
3414 | .value = "on", \ | |
5c4537bd DG |
3415 | }, \ |
3416 | { \ | |
3417 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3418 | .property = "pre-2.8-migration", \ | |
3419 | .value = "on", \ | |
357d1e3b DG |
3420 | }, |
3421 | ||
3422 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
3423 | uint64_t *buid, hwaddr *pio, | |
3424 | hwaddr *mmio32, hwaddr *mmio64, | |
3425 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
3426 | { | |
3427 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
3428 | const uint64_t base_buid = 0x800000020000000ULL; | |
3429 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
3430 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
3431 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
3432 | const uint32_t max_index = 255; | |
3433 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
3434 | ||
3435 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
3436 | hwaddr phb0_base, phb_base; | |
3437 | int i; | |
3438 | ||
3439 | /* Do we have hotpluggable memory? */ | |
3440 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
3441 | /* Can't just use maxram_size, because there may be an | |
3442 | * alignment gap between normal and hotpluggable memory | |
3443 | * regions */ | |
3444 | ram_top = spapr->hotplug_memory.base + | |
3445 | memory_region_size(&spapr->hotplug_memory.mr); | |
3446 | } | |
3447 | ||
3448 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
3449 | ||
3450 | if (index > max_index) { | |
3451 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
3452 | max_index); | |
3453 | return; | |
3454 | } | |
3455 | ||
3456 | *buid = base_buid + index; | |
3457 | for (i = 0; i < n_dma; ++i) { | |
3458 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3459 | } | |
3460 | ||
3461 | phb_base = phb0_base + index * phb_spacing; | |
3462 | *pio = phb_base + pio_offset; | |
3463 | *mmio32 = phb_base + mmio_offset; | |
3464 | /* | |
3465 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
3466 | * fallback behaviour of automatically splitting a large "32-bit" | |
3467 | * window into contiguous 32-bit and 64-bit windows | |
3468 | */ | |
3469 | } | |
db800b21 | 3470 | |
1ea1eefc BR |
3471 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
3472 | { | |
f6229214 MR |
3473 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3474 | ||
672de881 | 3475 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 3476 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
3477 | } |
3478 | ||
3479 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
3480 | { | |
3daa4a9f TH |
3481 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3482 | ||
db800b21 | 3483 | spapr_machine_2_8_class_options(mc); |
3daa4a9f | 3484 | smc->tcg_default_cpu = "POWER7"; |
db800b21 | 3485 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 3486 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
3487 | } |
3488 | ||
db800b21 | 3489 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 3490 | |
4b23699c DG |
3491 | /* |
3492 | * pseries-2.6 | |
3493 | */ | |
1ea1eefc | 3494 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
3495 | HW_COMPAT_2_6 \ |
3496 | { \ | |
3497 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
3498 | .property = "ddw",\ | |
3499 | .value = stringify(off),\ | |
3500 | }, | |
1ea1eefc | 3501 | |
4b23699c DG |
3502 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
3503 | { | |
672de881 | 3504 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
3505 | } |
3506 | ||
3507 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
3508 | { | |
1ea1eefc | 3509 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 3510 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 3511 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
3512 | } |
3513 | ||
1ea1eefc | 3514 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 3515 | |
1c5f29bb DG |
3516 | /* |
3517 | * pseries-2.5 | |
3518 | */ | |
4b23699c | 3519 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
3520 | HW_COMPAT_2_5 \ |
3521 | { \ | |
3522 | .driver = "spapr-vlan", \ | |
3523 | .property = "use-rx-buffer-pools", \ | |
3524 | .value = "off", \ | |
3525 | }, | |
4b23699c | 3526 | |
5013c547 | 3527 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 3528 | { |
672de881 | 3529 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
3530 | } |
3531 | ||
3532 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
3533 | { | |
57040d45 TH |
3534 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3535 | ||
4b23699c | 3536 | spapr_machine_2_6_class_options(mc); |
57040d45 | 3537 | smc->use_ohci_by_default = true; |
4b23699c | 3538 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
3539 | } |
3540 | ||
4b23699c | 3541 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
3542 | |
3543 | /* | |
3544 | * pseries-2.4 | |
3545 | */ | |
80fd50f9 CH |
3546 | #define SPAPR_COMPAT_2_4 \ |
3547 | HW_COMPAT_2_4 | |
3548 | ||
5013c547 | 3549 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 3550 | { |
5013c547 DG |
3551 | spapr_machine_2_5_instance_options(machine); |
3552 | } | |
1c5f29bb | 3553 | |
5013c547 DG |
3554 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
3555 | { | |
fc9f38c3 DG |
3556 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3557 | ||
3558 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 3559 | smc->dr_lmb_enabled = false; |
f949b4e5 | 3560 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
3561 | } |
3562 | ||
fccbc785 | 3563 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
3564 | |
3565 | /* | |
3566 | * pseries-2.3 | |
3567 | */ | |
38ff32c6 | 3568 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
3569 | HW_COMPAT_2_3 \ |
3570 | {\ | |
3571 | .driver = "spapr-pci-host-bridge",\ | |
3572 | .property = "dynamic-reconfiguration",\ | |
3573 | .value = "off",\ | |
3574 | }, | |
38ff32c6 | 3575 | |
5013c547 | 3576 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 3577 | { |
5013c547 | 3578 | spapr_machine_2_4_instance_options(machine); |
ff14e817 | 3579 | savevm_skip_section_footers(); |
13d16814 | 3580 | global_state_set_optional(); |
09b5e30d | 3581 | savevm_skip_configuration(); |
d25228e7 JW |
3582 | } |
3583 | ||
5013c547 | 3584 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 3585 | { |
fc9f38c3 | 3586 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 3587 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 3588 | } |
fccbc785 | 3589 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 3590 | |
1c5f29bb DG |
3591 | /* |
3592 | * pseries-2.2 | |
3593 | */ | |
3594 | ||
3595 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
3596 | HW_COMPAT_2_2 \ |
3597 | {\ | |
3598 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
3599 | .property = "mem_win_size",\ | |
3600 | .value = "0x20000000",\ | |
3601 | }, | |
3602 | ||
5013c547 | 3603 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 3604 | { |
5013c547 | 3605 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 3606 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
3607 | } |
3608 | ||
5013c547 | 3609 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 3610 | { |
fc9f38c3 | 3611 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 3612 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 3613 | } |
fccbc785 | 3614 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 3615 | |
1c5f29bb DG |
3616 | /* |
3617 | * pseries-2.1 | |
3618 | */ | |
3619 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 3620 | HW_COMPAT_2_1 |
3dab0244 | 3621 | |
5013c547 | 3622 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 3623 | { |
5013c547 | 3624 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 3625 | } |
d25228e7 | 3626 | |
5013c547 | 3627 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 3628 | { |
fc9f38c3 | 3629 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 3630 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 3631 | } |
fccbc785 | 3632 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 3633 | |
29ee3247 | 3634 | static void spapr_machine_register_types(void) |
9fdf0c29 | 3635 | { |
29ee3247 | 3636 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
3637 | } |
3638 | ||
29ee3247 | 3639 | type_init(spapr_machine_register_types) |