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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
fa98fbfc | 29 | #include "qapi/visitor.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
e35704ba | 31 | #include "sysemu/numa.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
03dd024f | 33 | #include "qemu/log.h" |
71461b0f | 34 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 35 | #include "elf.h" |
1422e32d | 36 | #include "net/net.h" |
ad440b4a | 37 | #include "sysemu/device_tree.h" |
fa1d36df | 38 | #include "sysemu/block-backend.h" |
9c17d615 | 39 | #include "sysemu/cpus.h" |
b3946626 | 40 | #include "sysemu/hw_accel.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
c4b63b7c | 42 | #include "migration/misc.h" |
84a899de | 43 | #include "migration/global_state.h" |
f2a8f0a6 | 44 | #include "migration/register.h" |
4be21d56 | 45 | #include "mmu-hash64.h" |
b4db5413 | 46 | #include "mmu-book3s-v3.h" |
7abd43ba | 47 | #include "cpu-models.h" |
3794d548 | 48 | #include "qom/cpu.h" |
9fdf0c29 DG |
49 | |
50 | #include "hw/boards.h" | |
0d09e41a | 51 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
52 | #include "hw/loader.h" |
53 | ||
7804c353 | 54 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
55 | #include "hw/ppc/spapr.h" |
56 | #include "hw/ppc/spapr_vio.h" | |
57 | #include "hw/pci-host/spapr.h" | |
58 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 59 | #include "hw/pci/msi.h" |
9fdf0c29 | 60 | |
83c9f4ca | 61 | #include "hw/pci/pci.h" |
71461b0f AK |
62 | #include "hw/scsi/scsi.h" |
63 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 64 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 65 | |
022c62cb | 66 | #include "exec/address-spaces.h" |
35139a59 | 67 | #include "hw/usb.h" |
1de7afc9 | 68 | #include "qemu/config-file.h" |
135a129a | 69 | #include "qemu/error-report.h" |
2a6593cb | 70 | #include "trace.h" |
34316482 | 71 | #include "hw/nmi.h" |
6449da45 | 72 | #include "hw/intc/intc.h" |
890c2b77 | 73 | |
68a27b20 | 74 | #include "hw/compat.h" |
f348b6d1 | 75 | #include "qemu/cutils.h" |
94a94e4c | 76 | #include "hw/ppc/spapr_cpu_core.h" |
68a27b20 | 77 | |
9fdf0c29 DG |
78 | #include <libfdt.h> |
79 | ||
4d8d5467 BH |
80 | /* SLOF memory layout: |
81 | * | |
82 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
83 | * device-tree, then position SLOF itself 31M below that | |
84 | * | |
85 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
86 | * and more | |
87 | * | |
88 | * We load our kernel at 4M, leaving space for SLOF initial image | |
89 | */ | |
38b02bd8 | 90 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 91 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 92 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
93 | #define FW_MAX_SIZE 0x400000 |
94 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
95 | #define FW_OVERHEAD 0x2800000 |
96 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 97 | |
4d8d5467 | 98 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 99 | |
0c103f8e DG |
100 | #define PHANDLE_XICP 0x00001111 |
101 | ||
5d0fb150 GK |
102 | /* These two functions implement the VCPU id numbering: one to compute them |
103 | * all and one to identify thread 0 of a VCORE. Any change to the first one | |
104 | * is likely to have an impact on the second one, so let's keep them close. | |
105 | */ | |
106 | static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) | |
107 | { | |
1a5008fc | 108 | assert(spapr->vsmt); |
5d0fb150 GK |
109 | return |
110 | (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; | |
111 | } | |
112 | static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, | |
113 | PowerPCCPU *cpu) | |
114 | { | |
1a5008fc | 115 | assert(spapr->vsmt); |
5d0fb150 GK |
116 | return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; |
117 | } | |
118 | ||
71cd4dac CLG |
119 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
120 | const char *type_ics, | |
121 | int nr_irqs, Error **errp) | |
c04d6cfa | 122 | { |
175d2aa0 | 123 | Error *local_err = NULL; |
71cd4dac | 124 | Object *obj; |
4e4169f7 | 125 | |
71cd4dac | 126 | obj = object_new(type_ics); |
175d2aa0 | 127 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
ad265631 GK |
128 | object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
129 | &error_abort); | |
175d2aa0 GK |
130 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
131 | if (local_err) { | |
132 | goto error; | |
133 | } | |
71cd4dac | 134 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
135 | if (local_err) { |
136 | goto error; | |
4e4169f7 | 137 | } |
4e4169f7 | 138 | |
71cd4dac | 139 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
140 | |
141 | error: | |
142 | error_propagate(errp, local_err); | |
143 | return NULL; | |
c04d6cfa AL |
144 | } |
145 | ||
46f7afa3 GK |
146 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
147 | { | |
148 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
149 | * and newer QEMUs don't even have them. In both cases, we don't want | |
150 | * to send anything on the wire. | |
151 | */ | |
152 | return false; | |
153 | } | |
154 | ||
155 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
156 | .name = "icp/server", | |
157 | .version_id = 1, | |
158 | .minimum_version_id = 1, | |
159 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
160 | .fields = (VMStateField[]) { | |
161 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
162 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
163 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
164 | VMSTATE_END_OF_LIST() | |
165 | }, | |
166 | }; | |
167 | ||
168 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
169 | { | |
170 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
171 | (void *)(uintptr_t) i); | |
172 | } | |
173 | ||
174 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
175 | { | |
176 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
177 | (void *)(uintptr_t) i); | |
178 | } | |
179 | ||
72194664 | 180 | static int xics_max_server_number(sPAPRMachineState *spapr) |
46f7afa3 | 181 | { |
1a5008fc | 182 | assert(spapr->vsmt); |
72194664 | 183 | return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); |
46f7afa3 GK |
184 | } |
185 | ||
71cd4dac | 186 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 187 | { |
71cd4dac | 188 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
c04d6cfa | 189 | |
11ad93f6 | 190 | if (kvm_enabled()) { |
2192a930 | 191 | if (machine_kernel_irqchip_allowed(machine) && |
71cd4dac CLG |
192 | !xics_kvm_init(spapr, errp)) { |
193 | spapr->icp_type = TYPE_KVM_ICP; | |
3d85885a | 194 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); |
11ad93f6 | 195 | } |
71cd4dac | 196 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
3d85885a GK |
197 | error_prepend(errp, "kernel_irqchip requested but unavailable: "); |
198 | return; | |
11ad93f6 DG |
199 | } |
200 | } | |
201 | ||
71cd4dac | 202 | if (!spapr->ics) { |
f63ebfe0 | 203 | xics_spapr_init(spapr); |
71cd4dac CLG |
204 | spapr->icp_type = TYPE_ICP; |
205 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); | |
3d85885a GK |
206 | if (!spapr->ics) { |
207 | return; | |
208 | } | |
c04d6cfa | 209 | } |
c04d6cfa AL |
210 | } |
211 | ||
833d4668 AK |
212 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
213 | int smt_threads) | |
214 | { | |
215 | int i, ret = 0; | |
216 | uint32_t servers_prop[smt_threads]; | |
217 | uint32_t gservers_prop[smt_threads * 2]; | |
14bb4486 | 218 | int index = spapr_get_vcpu_id(cpu); |
833d4668 | 219 | |
d6e166c0 DG |
220 | if (cpu->compat_pvr) { |
221 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
222 | if (ret < 0) { |
223 | return ret; | |
224 | } | |
225 | } | |
226 | ||
833d4668 AK |
227 | /* Build interrupt servers and gservers properties */ |
228 | for (i = 0; i < smt_threads; i++) { | |
229 | servers_prop[i] = cpu_to_be32(index + i); | |
230 | /* Hack, direct the group queues back to cpu 0 */ | |
231 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
232 | gservers_prop[i*2 + 1] = 0; | |
233 | } | |
234 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
235 | servers_prop, sizeof(servers_prop)); | |
236 | if (ret < 0) { | |
237 | return ret; | |
238 | } | |
239 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
240 | gservers_prop, sizeof(gservers_prop)); | |
241 | ||
242 | return ret; | |
243 | } | |
244 | ||
99861ecb | 245 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 246 | { |
14bb4486 | 247 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
248 | uint32_t associativity[] = {cpu_to_be32(0x5), |
249 | cpu_to_be32(0x0), | |
250 | cpu_to_be32(0x0), | |
251 | cpu_to_be32(0x0), | |
15f8b142 | 252 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
253 | cpu_to_be32(index)}; |
254 | ||
255 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 256 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 257 | sizeof(associativity)); |
0da6f3fe BR |
258 | } |
259 | ||
86d5771a | 260 | /* Populate the "ibm,pa-features" property */ |
ee76a09f DG |
261 | static void spapr_populate_pa_features(sPAPRMachineState *spapr, |
262 | PowerPCCPU *cpu, | |
263 | void *fdt, int offset, | |
7abd43ba | 264 | bool legacy_guest) |
86d5771a | 265 | { |
7abd43ba | 266 | CPUPPCState *env = &cpu->env; |
86d5771a SB |
267 | uint8_t pa_features_206[] = { 6, 0, |
268 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
269 | uint8_t pa_features_207[] = { 24, 0, | |
270 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
271 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
272 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
273 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
274 | uint8_t pa_features_300[] = { 66, 0, |
275 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
276 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
277 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
278 | /* 6: DS207 */ | |
279 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
280 | /* 16: Vector */ | |
86d5771a | 281 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 282 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 283 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
284 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
285 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
286 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
287 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
288 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
289 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
290 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
291 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
292 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
293 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
294 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
295 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
296 | /* 60: NM atomic, 62: RNG */ | |
297 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
298 | }; | |
7abd43ba | 299 | uint8_t *pa_features = NULL; |
86d5771a SB |
300 | size_t pa_size; |
301 | ||
7abd43ba | 302 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
303 | pa_features = pa_features_206; |
304 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
305 | } |
306 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
307 | pa_features = pa_features_207; |
308 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
309 | } |
310 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
311 | pa_features = pa_features_300; |
312 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
313 | } |
314 | if (!pa_features) { | |
86d5771a SB |
315 | return; |
316 | } | |
317 | ||
318 | if (env->ci_large_pages) { | |
319 | /* | |
320 | * Note: we keep CI large pages off by default because a 64K capable | |
321 | * guest provisioned with large pages might otherwise try to map a qemu | |
322 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
323 | * even if that qemu runs on a 4k host. | |
324 | * We dd this bit back here if we are confident this is not an issue | |
325 | */ | |
326 | pa_features[3] |= 0x20; | |
327 | } | |
4e5fe368 | 328 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
86d5771a SB |
329 | pa_features[24] |= 0x80; /* Transactional memory support */ |
330 | } | |
e957f6a9 SB |
331 | if (legacy_guest && pa_size > 40) { |
332 | /* Workaround for broken kernels that attempt (guest) radix | |
333 | * mode when they can't handle it, if they see the radix bit set | |
334 | * in pa-features. So hide it from them. */ | |
335 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
336 | } | |
86d5771a SB |
337 | |
338 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
339 | } | |
340 | ||
28e02042 | 341 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 342 | { |
82677ed2 AK |
343 | int ret = 0, offset, cpus_offset; |
344 | CPUState *cs; | |
6e806cc3 | 345 | char cpu_model[32]; |
7f763a5d | 346 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 347 | |
82677ed2 AK |
348 | CPU_FOREACH(cs) { |
349 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
350 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 351 | int index = spapr_get_vcpu_id(cpu); |
abbc1247 | 352 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
6e806cc3 | 353 | |
5d0fb150 | 354 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
6e806cc3 BR |
355 | continue; |
356 | } | |
357 | ||
82677ed2 | 358 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 359 | |
82677ed2 AK |
360 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
361 | if (cpus_offset < 0) { | |
a4f3885c | 362 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
82677ed2 AK |
363 | if (cpus_offset < 0) { |
364 | return cpus_offset; | |
365 | } | |
366 | } | |
367 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 368 | if (offset < 0) { |
82677ed2 AK |
369 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
370 | if (offset < 0) { | |
371 | return offset; | |
372 | } | |
6e806cc3 BR |
373 | } |
374 | ||
7f763a5d DG |
375 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
376 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
377 | if (ret < 0) { |
378 | return ret; | |
379 | } | |
833d4668 | 380 | |
99861ecb IM |
381 | if (nb_numa_nodes > 1) { |
382 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
383 | if (ret < 0) { | |
384 | return ret; | |
385 | } | |
0da6f3fe BR |
386 | } |
387 | ||
12dbeb16 | 388 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
389 | if (ret < 0) { |
390 | return ret; | |
391 | } | |
e957f6a9 | 392 | |
ee76a09f DG |
393 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
394 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
395 | } |
396 | return ret; | |
397 | } | |
398 | ||
c86c1aff | 399 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a AK |
400 | { |
401 | if (nb_numa_nodes) { | |
402 | int i; | |
403 | for (i = 0; i < nb_numa_nodes; ++i) { | |
404 | if (numa_info[i].node_mem) { | |
fb164994 DG |
405 | return MIN(pow2floor(numa_info[i].node_mem), |
406 | machine->ram_size); | |
b082d65a AK |
407 | } |
408 | } | |
409 | } | |
fb164994 | 410 | return machine->ram_size; |
b082d65a AK |
411 | } |
412 | ||
a1d59c0f AK |
413 | static void add_str(GString *s, const gchar *s1) |
414 | { | |
415 | g_string_append_len(s, s1, strlen(s1) + 1); | |
416 | } | |
7f763a5d | 417 | |
03d196b7 | 418 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
419 | hwaddr size) |
420 | { | |
421 | uint32_t associativity[] = { | |
422 | cpu_to_be32(0x4), /* length */ | |
423 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 424 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
425 | }; |
426 | char mem_name[32]; | |
427 | uint64_t mem_reg_property[2]; | |
428 | int off; | |
429 | ||
430 | mem_reg_property[0] = cpu_to_be64(start); | |
431 | mem_reg_property[1] = cpu_to_be64(size); | |
432 | ||
433 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
434 | off = fdt_add_subnode(fdt, 0, mem_name); | |
435 | _FDT(off); | |
436 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
437 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
438 | sizeof(mem_reg_property)))); | |
439 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
440 | sizeof(associativity)))); | |
03d196b7 | 441 | return off; |
26a8c353 AK |
442 | } |
443 | ||
28e02042 | 444 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 445 | { |
fb164994 | 446 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
447 | hwaddr mem_start, node_size; |
448 | int i, nb_nodes = nb_numa_nodes; | |
449 | NodeInfo *nodes = numa_info; | |
450 | NodeInfo ramnode; | |
451 | ||
452 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
453 | if (!nb_numa_nodes) { | |
454 | nb_nodes = 1; | |
fb164994 | 455 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 456 | nodes = &ramnode; |
5fe269b1 | 457 | } |
7f763a5d | 458 | |
7db8a127 AK |
459 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
460 | if (!nodes[i].node_mem) { | |
461 | continue; | |
462 | } | |
fb164994 | 463 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
464 | node_size = 0; |
465 | } else { | |
7db8a127 | 466 | node_size = nodes[i].node_mem; |
fb164994 DG |
467 | if (node_size > machine->ram_size - mem_start) { |
468 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
469 | } |
470 | } | |
7db8a127 | 471 | if (!mem_start) { |
b472b1a7 DHB |
472 | /* spapr_machine_init() checks for rma_size <= node0_size |
473 | * already */ | |
e8f986fc | 474 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
475 | mem_start += spapr->rma_size; |
476 | node_size -= spapr->rma_size; | |
477 | } | |
6010818c AK |
478 | for ( ; node_size; ) { |
479 | hwaddr sizetmp = pow2floor(node_size); | |
480 | ||
481 | /* mem_start != 0 here */ | |
482 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
483 | sizetmp = 1ULL << ctzl(mem_start); | |
484 | } | |
485 | ||
486 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
487 | node_size -= sizetmp; | |
488 | mem_start += sizetmp; | |
489 | } | |
7f763a5d DG |
490 | } |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
0da6f3fe BR |
495 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
496 | sPAPRMachineState *spapr) | |
497 | { | |
498 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
499 | CPUPPCState *env = &cpu->env; | |
500 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
14bb4486 | 501 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
502 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
503 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
504 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
505 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
506 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
507 | uint32_t page_sizes_prop[64]; | |
508 | size_t page_sizes_prop_size; | |
22419c2a | 509 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 510 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
abbc1247 | 511 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
af81cf32 | 512 | sPAPRDRConnector *drc; |
af81cf32 | 513 | int drc_index; |
c64abd1f SB |
514 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
515 | int i; | |
af81cf32 | 516 | |
fbf55397 | 517 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 518 | if (drc) { |
0b55aa91 | 519 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
520 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
521 | } | |
0da6f3fe BR |
522 | |
523 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
524 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
525 | ||
526 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
527 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
528 | env->dcache_line_size))); | |
529 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
530 | env->dcache_line_size))); | |
531 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
532 | env->icache_line_size))); | |
533 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
534 | env->icache_line_size))); | |
535 | ||
536 | if (pcc->l1_dcache_size) { | |
537 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
538 | pcc->l1_dcache_size))); | |
539 | } else { | |
3dc6f869 | 540 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
541 | } |
542 | if (pcc->l1_icache_size) { | |
543 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
544 | pcc->l1_icache_size))); | |
545 | } else { | |
3dc6f869 | 546 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
547 | } |
548 | ||
549 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
550 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 551 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
552 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
553 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
554 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
555 | ||
556 | if (env->spr_cb[SPR_PURR].oea_read) { | |
557 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
558 | } | |
559 | ||
560 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
561 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
562 | segs, sizeof(segs)))); | |
563 | } | |
564 | ||
29386642 | 565 | /* Advertise VSX (vector extensions) if available |
0da6f3fe | 566 | * 1 == VMX / Altivec available |
29386642 DG |
567 | * 2 == VSX available |
568 | * | |
569 | * Only CPUs for which we create core types in spapr_cpu_core.c | |
570 | * are possible, and all of those have VMX */ | |
4e5fe368 | 571 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { |
29386642 DG |
572 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); |
573 | } else { | |
574 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); | |
0da6f3fe BR |
575 | } |
576 | ||
577 | /* Advertise DFP (Decimal Floating Point) if available | |
578 | * 0 / no property == no DFP | |
579 | * 1 == DFP available */ | |
4e5fe368 | 580 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { |
0da6f3fe BR |
581 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); |
582 | } | |
583 | ||
3654fa95 | 584 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
585 | sizeof(page_sizes_prop)); |
586 | if (page_sizes_prop_size) { | |
587 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
588 | page_sizes_prop, page_sizes_prop_size))); | |
589 | } | |
590 | ||
ee76a09f | 591 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
90da0d5a | 592 | |
0da6f3fe | 593 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 594 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
595 | |
596 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
597 | pft_size_prop, sizeof(pft_size_prop)))); | |
598 | ||
99861ecb IM |
599 | if (nb_numa_nodes > 1) { |
600 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
601 | } | |
0da6f3fe | 602 | |
12dbeb16 | 603 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
604 | |
605 | if (pcc->radix_page_info) { | |
606 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
607 | radix_AP_encodings[i] = | |
608 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
609 | } | |
610 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
611 | radix_AP_encodings, | |
612 | pcc->radix_page_info->count * | |
613 | sizeof(radix_AP_encodings[0])))); | |
614 | } | |
0da6f3fe BR |
615 | } |
616 | ||
617 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
618 | { | |
619 | CPUState *cs; | |
620 | int cpus_offset; | |
621 | char *nodename; | |
0da6f3fe BR |
622 | |
623 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
624 | _FDT(cpus_offset); | |
625 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
626 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
627 | ||
628 | /* | |
629 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
630 | * created by fdt_add_subnode() end up in the right order in FDT | |
631 | * for the guest kernel the enumerate the CPUs correctly. | |
632 | */ | |
633 | CPU_FOREACH_REVERSE(cs) { | |
634 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
14bb4486 | 635 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
636 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
637 | int offset; | |
638 | ||
5d0fb150 | 639 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
0da6f3fe BR |
640 | continue; |
641 | } | |
642 | ||
643 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
644 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
645 | g_free(nodename); | |
646 | _FDT(offset); | |
647 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
648 | } | |
649 | ||
650 | } | |
651 | ||
f47bd1c8 IM |
652 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
653 | { | |
654 | MemoryDeviceInfoList *info; | |
655 | ||
656 | for (info = list; info; info = info->next) { | |
657 | MemoryDeviceInfo *value = info->value; | |
658 | ||
659 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
660 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
661 | ||
662 | if (pcdimm_info->addr >= addr && | |
663 | addr < (pcdimm_info->addr + pcdimm_info->size)) { | |
664 | return pcdimm_info->node; | |
665 | } | |
666 | } | |
667 | } | |
668 | ||
669 | return -1; | |
670 | } | |
671 | ||
03d196b7 BR |
672 | /* |
673 | * Adds ibm,dynamic-reconfiguration-memory node. | |
674 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
675 | * of this device tree node. | |
676 | */ | |
677 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
678 | { | |
679 | MachineState *machine = MACHINE(spapr); | |
680 | int ret, i, offset; | |
681 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
682 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
683 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
684 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
685 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
686 | lmb_size; | |
03d196b7 | 687 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 688 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
f47bd1c8 | 689 | MemoryDeviceInfoList *dimms = NULL; |
03d196b7 | 690 | |
16c25aef | 691 | /* |
d0e5a8f2 | 692 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 693 | */ |
d0e5a8f2 | 694 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
695 | return 0; |
696 | } | |
697 | ||
ef001f06 TH |
698 | /* |
699 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
700 | * or ibm,associativity-lookup-arrays | |
701 | */ | |
702 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
703 | * sizeof(uint32_t); | |
03d196b7 BR |
704 | cur_index = int_buf = g_malloc0(buf_len); |
705 | ||
706 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
707 | ||
708 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
709 | sizeof(prop_lmb_size)); | |
710 | if (ret < 0) { | |
711 | goto out; | |
712 | } | |
713 | ||
714 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
715 | if (ret < 0) { | |
716 | goto out; | |
717 | } | |
718 | ||
719 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
720 | if (ret < 0) { | |
721 | goto out; | |
722 | } | |
723 | ||
f47bd1c8 IM |
724 | if (hotplug_lmb_start) { |
725 | MemoryDeviceInfoList **prev = &dimms; | |
726 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
727 | } | |
728 | ||
03d196b7 BR |
729 | /* ibm,dynamic-memory */ |
730 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
731 | cur_index++; | |
732 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 733 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
734 | uint32_t *dynamic_memory = cur_index; |
735 | ||
d0e5a8f2 BR |
736 | if (i >= hotplug_lmb_start) { |
737 | sPAPRDRConnector *drc; | |
d0e5a8f2 | 738 | |
fbf55397 | 739 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 740 | g_assert(drc); |
d0e5a8f2 BR |
741 | |
742 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
743 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 744 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 745 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 746 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
747 | if (memory_region_present(get_system_memory(), addr)) { |
748 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
749 | } else { | |
750 | dynamic_memory[5] = cpu_to_be32(0); | |
751 | } | |
03d196b7 | 752 | } else { |
d0e5a8f2 BR |
753 | /* |
754 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
755 | * hotplug memory region -- all these are marked as reserved | |
756 | * and as having no valid DRC. | |
757 | */ | |
758 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
759 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
760 | dynamic_memory[2] = cpu_to_be32(0); | |
761 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
762 | dynamic_memory[4] = cpu_to_be32(-1); | |
763 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
764 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
765 | } |
766 | ||
767 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
768 | } | |
f47bd1c8 | 769 | qapi_free_MemoryDeviceInfoList(dimms); |
03d196b7 BR |
770 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); |
771 | if (ret < 0) { | |
772 | goto out; | |
773 | } | |
774 | ||
775 | /* ibm,associativity-lookup-arrays */ | |
776 | cur_index = int_buf; | |
6663864e | 777 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
778 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
779 | cur_index += 2; | |
6663864e | 780 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
781 | uint32_t associativity[] = { |
782 | cpu_to_be32(0x0), | |
783 | cpu_to_be32(0x0), | |
784 | cpu_to_be32(0x0), | |
785 | cpu_to_be32(i) | |
786 | }; | |
787 | memcpy(cur_index, associativity, sizeof(associativity)); | |
788 | cur_index += 4; | |
789 | } | |
790 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
791 | (cur_index - int_buf) * sizeof(uint32_t)); | |
792 | out: | |
793 | g_free(int_buf); | |
794 | return ret; | |
795 | } | |
796 | ||
6787d27b MR |
797 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
798 | sPAPROptionVector *ov5_updates) | |
799 | { | |
800 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 801 | int ret = 0, offset; |
6787d27b MR |
802 | |
803 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
804 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
805 | g_assert(smc->dr_lmb_enabled); | |
806 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
807 | if (ret) { |
808 | goto out; | |
809 | } | |
6787d27b MR |
810 | } |
811 | ||
417ece33 MR |
812 | offset = fdt_path_offset(fdt, "/chosen"); |
813 | if (offset < 0) { | |
814 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
815 | if (offset < 0) { | |
816 | return offset; | |
817 | } | |
818 | } | |
819 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
820 | "ibm,architecture-vec-5"); | |
821 | ||
822 | out: | |
6787d27b MR |
823 | return ret; |
824 | } | |
825 | ||
10f12e64 DHB |
826 | static bool spapr_hotplugged_dev_before_cas(void) |
827 | { | |
828 | Object *drc_container, *obj; | |
829 | ObjectProperty *prop; | |
830 | ObjectPropertyIterator iter; | |
831 | ||
832 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
833 | object_property_iter_init(&iter, drc_container); | |
834 | while ((prop = object_property_iter_next(&iter))) { | |
835 | if (!strstart(prop->type, "link<", NULL)) { | |
836 | continue; | |
837 | } | |
838 | obj = object_property_get_link(drc_container, prop->name, NULL); | |
839 | if (spapr_drc_needed(obj)) { | |
840 | return true; | |
841 | } | |
842 | } | |
843 | return false; | |
844 | } | |
845 | ||
03d196b7 BR |
846 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
847 | target_ulong addr, target_ulong size, | |
6787d27b | 848 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
849 | { |
850 | void *fdt, *fdt_skel; | |
851 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 | 852 | |
10f12e64 DHB |
853 | if (spapr_hotplugged_dev_before_cas()) { |
854 | return 1; | |
855 | } | |
856 | ||
827b17c4 GK |
857 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
858 | error_report("SLOF provided an unexpected CAS buffer size " | |
859 | TARGET_FMT_lu " (min: %zu, max: %u)", | |
860 | size, sizeof(hdr), FW_MAX_SIZE); | |
861 | exit(EXIT_FAILURE); | |
862 | } | |
863 | ||
03d196b7 BR |
864 | size -= sizeof(hdr); |
865 | ||
10f12e64 | 866 | /* Create skeleton */ |
03d196b7 BR |
867 | fdt_skel = g_malloc0(size); |
868 | _FDT((fdt_create(fdt_skel, size))); | |
869 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
870 | _FDT((fdt_end_node(fdt_skel))); | |
871 | _FDT((fdt_finish(fdt_skel))); | |
872 | fdt = g_malloc0(size); | |
873 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
874 | g_free(fdt_skel); | |
875 | ||
876 | /* Fixup cpu nodes */ | |
5b120785 | 877 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 878 | |
6787d27b MR |
879 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
880 | return -1; | |
03d196b7 BR |
881 | } |
882 | ||
883 | /* Pack resulting tree */ | |
884 | _FDT((fdt_pack(fdt))); | |
885 | ||
886 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
887 | trace_spapr_cas_failed(size); | |
888 | return -1; | |
889 | } | |
890 | ||
891 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
892 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
893 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
894 | g_free(fdt); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
3f5dabce DG |
899 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
900 | { | |
901 | int rtas; | |
902 | GString *hypertas = g_string_sized_new(256); | |
903 | GString *qemu_hypertas = g_string_sized_new(256); | |
904 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
905 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
906 | memory_region_size(&spapr->hotplug_memory.mr); | |
907 | uint32_t lrdr_capacity[] = { | |
908 | cpu_to_be32(max_hotplug_addr >> 32), | |
909 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
910 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
911 | cpu_to_be32(max_cpus / smp_threads), | |
912 | }; | |
913 | ||
914 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
915 | ||
916 | /* hypertas */ | |
917 | add_str(hypertas, "hcall-pft"); | |
918 | add_str(hypertas, "hcall-term"); | |
919 | add_str(hypertas, "hcall-dabr"); | |
920 | add_str(hypertas, "hcall-interrupt"); | |
921 | add_str(hypertas, "hcall-tce"); | |
922 | add_str(hypertas, "hcall-vio"); | |
923 | add_str(hypertas, "hcall-splpar"); | |
924 | add_str(hypertas, "hcall-bulk"); | |
925 | add_str(hypertas, "hcall-set-mode"); | |
926 | add_str(hypertas, "hcall-sprg0"); | |
927 | add_str(hypertas, "hcall-copy"); | |
928 | add_str(hypertas, "hcall-debug"); | |
929 | add_str(qemu_hypertas, "hcall-memop1"); | |
930 | ||
931 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
932 | add_str(hypertas, "hcall-multi-tce"); | |
933 | } | |
30f4b05b DG |
934 | |
935 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
936 | add_str(hypertas, "hcall-hpt-resize"); | |
937 | } | |
938 | ||
3f5dabce DG |
939 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
940 | hypertas->str, hypertas->len)); | |
941 | g_string_free(hypertas, TRUE); | |
942 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
943 | qemu_hypertas->str, qemu_hypertas->len)); | |
944 | g_string_free(qemu_hypertas, TRUE); | |
945 | ||
946 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
947 | refpoints, sizeof(refpoints))); | |
948 | ||
949 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
950 | RTAS_ERROR_LOG_MAX)); | |
951 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
952 | RTAS_EVENT_SCAN_RATE)); | |
953 | ||
4f441474 DG |
954 | g_assert(msi_nonbroken); |
955 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
956 | |
957 | /* | |
958 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
959 | * back to the guest cpu. | |
960 | * | |
961 | * While an additional ibm,extended-os-term property indicates | |
962 | * that rtas call return will always occur. Set this property. | |
963 | */ | |
964 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
965 | ||
966 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
967 | lrdr_capacity, sizeof(lrdr_capacity))); | |
968 | ||
969 | spapr_dt_rtas_tokens(fdt, rtas); | |
970 | } | |
971 | ||
9fb4541f SB |
972 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
973 | * that the guest may request and thus the valid values for bytes 24..26 of | |
974 | * option vector 5: */ | |
975 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
976 | { | |
545d6e2b SJS |
977 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
978 | ||
f2b14e3a | 979 | char val[2 * 4] = { |
21f3f8db | 980 | 23, 0x00, /* Xive mode, filled in below. */ |
9fb4541f SB |
981 | 24, 0x00, /* Hash/Radix, filled in below. */ |
982 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
983 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
984 | }; | |
985 | ||
7abd43ba SJS |
986 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
987 | first_ppc_cpu->compat_pvr)) { | |
988 | /* If we're in a pre POWER9 compat mode then the guest should do hash */ | |
989 | val[3] = 0x00; /* Hash */ | |
990 | } else if (kvm_enabled()) { | |
9fb4541f | 991 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 992 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 993 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 994 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 995 | } else { |
f2b14e3a | 996 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
997 | } |
998 | } else { | |
7abd43ba SJS |
999 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
1000 | val[3] = 0xC0; | |
9fb4541f SB |
1001 | } |
1002 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
1003 | val, sizeof(val))); | |
1004 | } | |
1005 | ||
7c866c6a DG |
1006 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
1007 | { | |
1008 | MachineState *machine = MACHINE(spapr); | |
1009 | int chosen; | |
1010 | const char *boot_device = machine->boot_order; | |
1011 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1012 | size_t cb = 0; | |
1013 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
1014 | |
1015 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1016 | ||
7c866c6a DG |
1017 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
1018 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1019 | spapr->initrd_base)); | |
1020 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1021 | spapr->initrd_base + spapr->initrd_size)); | |
1022 | ||
1023 | if (spapr->kernel_size) { | |
1024 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
1025 | cpu_to_be64(spapr->kernel_size) }; | |
1026 | ||
1027 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
1028 | &kprop, sizeof(kprop))); | |
1029 | if (spapr->kernel_le) { | |
1030 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1031 | } | |
1032 | } | |
1033 | if (boot_menu) { | |
1034 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1035 | } | |
1036 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1037 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1038 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
1039 | ||
1040 | if (cb && bootlist) { | |
1041 | int i; | |
1042 | ||
1043 | for (i = 0; i < cb; i++) { | |
1044 | if (bootlist[i] == '\n') { | |
1045 | bootlist[i] = ' '; | |
1046 | } | |
1047 | } | |
1048 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
1049 | } | |
1050 | ||
1051 | if (boot_device && strlen(boot_device)) { | |
1052 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1053 | } | |
1054 | ||
1055 | if (!spapr->has_graphics && stdout_path) { | |
90ee4e01 ND |
1056 | /* |
1057 | * "linux,stdout-path" and "stdout" properties are deprecated by linux | |
1058 | * kernel. New platforms should only use the "stdout-path" property. Set | |
1059 | * the new property and continue using older property to remain | |
1060 | * compatible with the existing firmware. | |
1061 | */ | |
7c866c6a | 1062 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); |
90ee4e01 | 1063 | _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); |
7c866c6a DG |
1064 | } |
1065 | ||
9fb4541f SB |
1066 | spapr_dt_ov5_platform_support(fdt, chosen); |
1067 | ||
7c866c6a DG |
1068 | g_free(stdout_path); |
1069 | g_free(bootlist); | |
1070 | } | |
1071 | ||
fca5f2dc DG |
1072 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1073 | { | |
1074 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1075 | * KVM to work under pHyp with some guest co-operation */ | |
1076 | int hypervisor; | |
1077 | uint8_t hypercall[16]; | |
1078 | ||
1079 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1080 | /* indicate KVM hypercall interface */ | |
1081 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1082 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1083 | /* | |
1084 | * Older KVM versions with older guest kernels were broken | |
1085 | * with the magic page, don't allow the guest to map it. | |
1086 | */ | |
1087 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1088 | sizeof(hypercall))) { | |
1089 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1090 | hypercall, sizeof(hypercall))); | |
1091 | } | |
1092 | } | |
1093 | } | |
1094 | ||
997b6cfc DG |
1095 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1096 | hwaddr rtas_addr, | |
1097 | hwaddr rtas_size) | |
a3467baa | 1098 | { |
c86c1aff | 1099 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1100 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1101 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1102 | int ret; |
a3467baa | 1103 | void *fdt; |
3384f95c | 1104 | sPAPRPHBState *phb; |
398a0bd5 | 1105 | char *buf; |
a3467baa | 1106 | |
398a0bd5 DG |
1107 | fdt = g_malloc0(FDT_MAX_SIZE); |
1108 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1109 | |
398a0bd5 DG |
1110 | /* Root node */ |
1111 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1112 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1113 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1114 | ||
1115 | /* | |
1116 | * Add info to guest to indentify which host is it being run on | |
1117 | * and what is the uuid of the guest | |
1118 | */ | |
1119 | if (kvmppc_get_host_model(&buf)) { | |
1120 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1121 | g_free(buf); | |
1122 | } | |
1123 | if (kvmppc_get_host_serial(&buf)) { | |
1124 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1125 | g_free(buf); | |
1126 | } | |
1127 | ||
1128 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1129 | ||
1130 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1131 | if (qemu_uuid_set) { | |
1132 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1133 | } | |
1134 | g_free(buf); | |
1135 | ||
1136 | if (qemu_get_vm_name()) { | |
1137 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1138 | qemu_get_vm_name())); | |
1139 | } | |
1140 | ||
1141 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1142 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1143 | |
fc7e0765 | 1144 | /* /interrupt controller */ |
72194664 | 1145 | spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP); |
fc7e0765 | 1146 | |
e8f986fc BR |
1147 | ret = spapr_populate_memory(spapr, fdt); |
1148 | if (ret < 0) { | |
ce9863b7 | 1149 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1150 | exit(1); |
7f763a5d DG |
1151 | } |
1152 | ||
bf5a6696 DG |
1153 | /* /vdevice */ |
1154 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1155 | |
4d9392be TH |
1156 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1157 | ret = spapr_rng_populate_dt(fdt); | |
1158 | if (ret < 0) { | |
ce9863b7 | 1159 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1160 | exit(1); |
1161 | } | |
1162 | } | |
1163 | ||
3384f95c | 1164 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1165 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1166 | if (ret < 0) { |
1167 | error_report("couldn't setup PCI devices in fdt"); | |
1168 | exit(1); | |
1169 | } | |
3384f95c DG |
1170 | } |
1171 | ||
0da6f3fe BR |
1172 | /* cpus */ |
1173 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1174 | |
c20d332a BR |
1175 | if (smc->dr_lmb_enabled) { |
1176 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1177 | } | |
1178 | ||
c5514d0e | 1179 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1180 | int offset = fdt_path_offset(fdt, "/cpus"); |
1181 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1182 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1183 | if (ret < 0) { | |
1184 | error_report("Couldn't set up CPU DR device tree properties"); | |
1185 | exit(1); | |
1186 | } | |
1187 | } | |
1188 | ||
ffb1e275 | 1189 | /* /event-sources */ |
ffbb1705 | 1190 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1191 | |
3f5dabce DG |
1192 | /* /rtas */ |
1193 | spapr_dt_rtas(spapr, fdt); | |
1194 | ||
7c866c6a DG |
1195 | /* /chosen */ |
1196 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1197 | |
fca5f2dc DG |
1198 | /* /hypervisor */ |
1199 | if (kvm_enabled()) { | |
1200 | spapr_dt_hypervisor(spapr, fdt); | |
1201 | } | |
1202 | ||
cf6e5223 DG |
1203 | /* Build memory reserve map */ |
1204 | if (spapr->kernel_size) { | |
1205 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1206 | } | |
1207 | if (spapr->initrd_size) { | |
1208 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1209 | } | |
1210 | ||
6787d27b MR |
1211 | /* ibm,client-architecture-support updates */ |
1212 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1213 | if (ret < 0) { | |
1214 | error_report("couldn't setup CAS properties fdt"); | |
1215 | exit(1); | |
1216 | } | |
1217 | ||
997b6cfc | 1218 | return fdt; |
9fdf0c29 DG |
1219 | } |
1220 | ||
1221 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1222 | { | |
1223 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1224 | } | |
1225 | ||
1d1be34d DG |
1226 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1227 | PowerPCCPU *cpu) | |
9fdf0c29 | 1228 | { |
1b14670a AF |
1229 | CPUPPCState *env = &cpu->env; |
1230 | ||
8d04fb55 JK |
1231 | /* The TCG path should also be holding the BQL at this point */ |
1232 | g_assert(qemu_mutex_iothread_locked()); | |
1233 | ||
efcb9383 DG |
1234 | if (msr_pr) { |
1235 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1236 | env->gpr[3] = H_PRIVILEGE; | |
1237 | } else { | |
aa100fa4 | 1238 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1239 | } |
9fdf0c29 DG |
1240 | } |
1241 | ||
9861bb3e SJS |
1242 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1243 | { | |
1244 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1245 | ||
1246 | return spapr->patb_entry; | |
1247 | } | |
1248 | ||
e6b8fd24 SMJ |
1249 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1250 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1251 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1252 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1253 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1254 | ||
715c5407 DG |
1255 | /* |
1256 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1257 | */ | |
1258 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1259 | { | |
14b0d748 GK |
1260 | Error *local_err = NULL; |
1261 | ||
715c5407 DG |
1262 | if (spapr->htab_fd >= 0) { |
1263 | return spapr->htab_fd; | |
1264 | } | |
1265 | ||
14b0d748 | 1266 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1267 | if (spapr->htab_fd < 0) { |
14b0d748 | 1268 | error_report_err(local_err); |
715c5407 DG |
1269 | } |
1270 | ||
1271 | return spapr->htab_fd; | |
1272 | } | |
1273 | ||
b4db5413 | 1274 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1275 | { |
1276 | if (spapr->htab_fd >= 0) { | |
1277 | close(spapr->htab_fd); | |
1278 | } | |
1279 | spapr->htab_fd = -1; | |
1280 | } | |
1281 | ||
e57ca75c DG |
1282 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1283 | { | |
1284 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1285 | ||
1286 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1287 | } | |
1288 | ||
1ec26c75 GK |
1289 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1290 | { | |
1291 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1292 | ||
1293 | assert(kvm_enabled()); | |
1294 | ||
1295 | if (!spapr->htab) { | |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1300 | } | |
1301 | ||
e57ca75c DG |
1302 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1303 | hwaddr ptex, int n) | |
1304 | { | |
1305 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1306 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1307 | ||
1308 | if (!spapr->htab) { | |
1309 | /* | |
1310 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1311 | */ | |
1312 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1313 | kvmppc_read_hptes(hptes, ptex, n); | |
1314 | return hptes; | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * HTAB is controlled by QEMU. Just point to the internally | |
1319 | * accessible PTEG. | |
1320 | */ | |
1321 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1322 | } | |
1323 | ||
1324 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1325 | const ppc_hash_pte64_t *hptes, | |
1326 | hwaddr ptex, int n) | |
1327 | { | |
1328 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1329 | ||
1330 | if (!spapr->htab) { | |
1331 | g_free((void *)hptes); | |
1332 | } | |
1333 | ||
1334 | /* Nothing to do for qemu managed HPT */ | |
1335 | } | |
1336 | ||
1337 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1338 | uint64_t pte0, uint64_t pte1) | |
1339 | { | |
1340 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1341 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1342 | ||
1343 | if (!spapr->htab) { | |
1344 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1345 | } else { | |
1346 | stq_p(spapr->htab + offset, pte0); | |
1347 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1348 | } | |
1349 | } | |
1350 | ||
0b0b8310 | 1351 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1352 | { |
1353 | int shift; | |
1354 | ||
1355 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1356 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1357 | * that's much more than is needed for Linux guests */ | |
1358 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1359 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1360 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1361 | return shift; | |
1362 | } | |
1363 | ||
06ec79e8 BR |
1364 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1365 | { | |
1366 | g_free(spapr->htab); | |
1367 | spapr->htab = NULL; | |
1368 | spapr->htab_shift = 0; | |
1369 | close_htab_fd(spapr); | |
1370 | } | |
1371 | ||
2772cf6b DG |
1372 | void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1373 | Error **errp) | |
7f763a5d | 1374 | { |
c5f54f3e DG |
1375 | long rc; |
1376 | ||
1377 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1378 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1379 | |
1380 | rc = kvmppc_reset_htab(shift); | |
1381 | if (rc < 0) { | |
1382 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1383 | error_setg_errno(errp, errno, | |
1384 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1385 | shift); | |
1386 | /* This is almost certainly fatal, but if the caller really | |
1387 | * wants to carry on with shift == 0, it's welcome to try */ | |
1388 | } else if (rc > 0) { | |
1389 | /* kernel-side HPT allocated */ | |
1390 | if (rc != shift) { | |
1391 | error_setg(errp, | |
1392 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1393 | shift, rc); | |
7735feda BR |
1394 | } |
1395 | ||
7f763a5d | 1396 | spapr->htab_shift = shift; |
c18ad9a5 | 1397 | spapr->htab = NULL; |
b817772a | 1398 | } else { |
c5f54f3e DG |
1399 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1400 | size_t size = 1ULL << shift; | |
1401 | int i; | |
b817772a | 1402 | |
c5f54f3e DG |
1403 | spapr->htab = qemu_memalign(size, size); |
1404 | if (!spapr->htab) { | |
1405 | error_setg_errno(errp, errno, | |
1406 | "Could not allocate HPT of order %d", shift); | |
1407 | return; | |
7735feda BR |
1408 | } |
1409 | ||
c5f54f3e DG |
1410 | memset(spapr->htab, 0, size); |
1411 | spapr->htab_shift = shift; | |
e6b8fd24 | 1412 | |
c5f54f3e DG |
1413 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1414 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1415 | } |
7f763a5d | 1416 | } |
ee4d9ecc SJS |
1417 | /* We're setting up a hash table, so that means we're not radix */ |
1418 | spapr->patb_entry = 0; | |
9fdf0c29 DG |
1419 | } |
1420 | ||
b4db5413 SJS |
1421 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1422 | { | |
2772cf6b DG |
1423 | int hpt_shift; |
1424 | ||
1425 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) | |
1426 | || (spapr->cas_reboot | |
1427 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { | |
1428 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1429 | } else { | |
768a20f3 DG |
1430 | uint64_t current_ram_size; |
1431 | ||
1432 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1433 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1434 | } |
1435 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1436 | ||
b4db5413 | 1437 | if (spapr->vrma_adjust) { |
c86c1aff | 1438 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
b4db5413 SJS |
1439 | spapr->htab_shift); |
1440 | } | |
b4db5413 SJS |
1441 | } |
1442 | ||
4f01a637 | 1443 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1444 | { |
1445 | bool matched = false; | |
1446 | ||
1447 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1448 | matched = true; | |
1449 | } | |
1450 | ||
1451 | if (!matched) { | |
1452 | error_report("Device %s is not supported by this machine yet.", | |
1453 | qdev_fw_name(DEVICE(sbdev))); | |
1454 | exit(1); | |
1455 | } | |
9e3f9733 AG |
1456 | } |
1457 | ||
82512483 GK |
1458 | static int spapr_reset_drcs(Object *child, void *opaque) |
1459 | { | |
1460 | sPAPRDRConnector *drc = | |
1461 | (sPAPRDRConnector *) object_dynamic_cast(child, | |
1462 | TYPE_SPAPR_DR_CONNECTOR); | |
1463 | ||
1464 | if (drc) { | |
1465 | spapr_drc_reset(drc); | |
1466 | } | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | ||
bcb5ce08 | 1471 | static void spapr_machine_reset(void) |
a3467baa | 1472 | { |
c5f54f3e DG |
1473 | MachineState *machine = MACHINE(qdev_get_machine()); |
1474 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1475 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1476 | uint32_t rtas_limit; |
cae172ab | 1477 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1478 | void *fdt; |
1479 | int rc; | |
259186a7 | 1480 | |
9e3f9733 AG |
1481 | /* Check for unknown sysbus devices */ |
1482 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1483 | ||
33face6b DG |
1484 | spapr_caps_reset(spapr); |
1485 | ||
1481fe5f LV |
1486 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1487 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
1488 | ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, | |
1489 | spapr->max_compat_pvr)) { | |
b4db5413 SJS |
1490 | /* If using KVM with radix mode available, VCPUs can be started |
1491 | * without a HPT because KVM will start them in radix mode. | |
1492 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1493 | spapr->patb_entry = PATBE1_GR; | |
1494 | } else { | |
b4db5413 | 1495 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1496 | } |
a3467baa | 1497 | |
9012a53f GK |
1498 | /* if this reset wasn't generated by CAS, we should reset our |
1499 | * negotiated options and start from scratch */ | |
1500 | if (!spapr->cas_reboot) { | |
1501 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1502 | spapr->ov5_cas = spapr_ovec_new(); | |
1503 | ||
1504 | ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); | |
1505 | } | |
1506 | ||
c8787ad4 | 1507 | qemu_devices_reset(); |
82512483 GK |
1508 | |
1509 | /* DRC reset may cause a device to be unplugged. This will cause troubles | |
1510 | * if this device is used by another device (eg, a running vhost backend | |
1511 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1512 | * situations, we reset DRCs after all devices have been reset. | |
1513 | */ | |
1514 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1515 | ||
56258174 | 1516 | spapr_clear_pending_events(spapr); |
a3467baa | 1517 | |
b7d1f77a BH |
1518 | /* |
1519 | * We place the device tree and RTAS just below either the top of the RMA, | |
1520 | * or just below 2GB, whichever is lowere, so that it can be | |
1521 | * processed with 32-bit real mode code if necessary | |
1522 | */ | |
1523 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1524 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1525 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1526 | |
cae172ab | 1527 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1528 | |
2cac78c1 | 1529 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1530 | |
997b6cfc DG |
1531 | rc = fdt_pack(fdt); |
1532 | ||
1533 | /* Should only fail if we've built a corrupted tree */ | |
1534 | assert(rc == 0); | |
1535 | ||
1536 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1537 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1538 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1539 | exit(1); | |
1540 | } | |
1541 | ||
1542 | /* Load the fdt */ | |
1543 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1544 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1545 | g_free(fdt); |
1546 | ||
a3467baa | 1547 | /* Set up the entry state */ |
cae172ab | 1548 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1549 | first_ppc_cpu->env.gpr[5] = 0; |
1550 | first_cpu->halted = 0; | |
1b718907 | 1551 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1552 | |
6787d27b | 1553 | spapr->cas_reboot = false; |
a3467baa DG |
1554 | } |
1555 | ||
28e02042 | 1556 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1557 | { |
2ff3de68 | 1558 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1559 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1560 | |
3978b863 | 1561 | if (dinfo) { |
6231a6da MA |
1562 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1563 | &error_fatal); | |
639e8102 DG |
1564 | } |
1565 | ||
1566 | qdev_init_nofail(dev); | |
1567 | ||
1568 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1569 | } | |
1570 | ||
28e02042 | 1571 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1572 | { |
147ff807 CLG |
1573 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1574 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1575 | &error_fatal); | |
1576 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1577 | &error_fatal); | |
1578 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1579 | "date", &error_fatal); | |
28df36a1 DG |
1580 | } |
1581 | ||
8c57b867 | 1582 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1583 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1584 | { |
8c57b867 | 1585 | switch (vga_interface_type) { |
8c57b867 | 1586 | case VGA_NONE: |
7effdaa3 MW |
1587 | return false; |
1588 | case VGA_DEVICE: | |
1589 | return true; | |
1ddcae82 | 1590 | case VGA_STD: |
b798c190 | 1591 | case VGA_VIRTIO: |
1ddcae82 | 1592 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1593 | default: |
14c6a894 DG |
1594 | error_setg(errp, |
1595 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1596 | return false; | |
f28359d8 | 1597 | } |
f28359d8 LZ |
1598 | } |
1599 | ||
4e5fe368 SJS |
1600 | static int spapr_pre_load(void *opaque) |
1601 | { | |
1602 | int rc; | |
1603 | ||
1604 | rc = spapr_caps_pre_load(opaque); | |
1605 | if (rc) { | |
1606 | return rc; | |
1607 | } | |
1608 | ||
1609 | return 0; | |
1610 | } | |
1611 | ||
880ae7de DG |
1612 | static int spapr_post_load(void *opaque, int version_id) |
1613 | { | |
28e02042 | 1614 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1615 | int err = 0; |
1616 | ||
be85537d DG |
1617 | err = spapr_caps_post_migration(spapr); |
1618 | if (err) { | |
1619 | return err; | |
1620 | } | |
1621 | ||
a7ff1212 | 1622 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1623 | CPUState *cs; |
1624 | CPU_FOREACH(cs) { | |
1625 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1626 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1627 | } |
1628 | } | |
1629 | ||
631b22ea | 1630 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1631 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1632 | * So when migrating from those versions, poke the incoming offset | |
1633 | * value into the RTC device */ | |
1634 | if (version_id < 3) { | |
147ff807 | 1635 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1636 | } |
1637 | ||
0c86b2df | 1638 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 BR |
1639 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1640 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1641 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1642 | ||
1643 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1644 | if (err) { | |
1645 | error_report("Process table config unsupported by the host"); | |
1646 | return -EINVAL; | |
1647 | } | |
1648 | } | |
1649 | ||
880ae7de DG |
1650 | return err; |
1651 | } | |
1652 | ||
4e5fe368 SJS |
1653 | static int spapr_pre_save(void *opaque) |
1654 | { | |
1655 | int rc; | |
1656 | ||
1657 | rc = spapr_caps_pre_save(opaque); | |
1658 | if (rc) { | |
1659 | return rc; | |
1660 | } | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
880ae7de DG |
1665 | static bool version_before_3(void *opaque, int version_id) |
1666 | { | |
1667 | return version_id < 3; | |
1668 | } | |
1669 | ||
fd38804b DHB |
1670 | static bool spapr_pending_events_needed(void *opaque) |
1671 | { | |
1672 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1673 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1674 | } | |
1675 | ||
1676 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1677 | .name = "spapr_event_log_entry", | |
1678 | .version_id = 1, | |
1679 | .minimum_version_id = 1, | |
1680 | .fields = (VMStateField[]) { | |
5341258e DG |
1681 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1682 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1683 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1684 | NULL, extended_length), |
fd38804b DHB |
1685 | VMSTATE_END_OF_LIST() |
1686 | }, | |
1687 | }; | |
1688 | ||
1689 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1690 | .name = "spapr_pending_events", | |
1691 | .version_id = 1, | |
1692 | .minimum_version_id = 1, | |
1693 | .needed = spapr_pending_events_needed, | |
1694 | .fields = (VMStateField[]) { | |
1695 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1696 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1697 | VMSTATE_END_OF_LIST() | |
1698 | }, | |
1699 | }; | |
1700 | ||
62ef3760 MR |
1701 | static bool spapr_ov5_cas_needed(void *opaque) |
1702 | { | |
1703 | sPAPRMachineState *spapr = opaque; | |
1704 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1705 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1706 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1707 | bool cas_needed; | |
1708 | ||
1709 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1710 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1711 | * Both of these options encode machine topology into the device-tree | |
1712 | * in such a way that the now-booted OS should still be able to interact | |
1713 | * appropriately with QEMU regardless of what options were actually | |
1714 | * negotiatied on the source side. | |
1715 | * | |
1716 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1717 | * are the only options available on the current machine/platform. | |
1718 | * Since these are the only options available for pseries-2.7 and | |
1719 | * earlier, this allows us to maintain old->new/new->old migration | |
1720 | * compatibility. | |
1721 | * | |
1722 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1723 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1724 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1725 | * of the actual CAS-negotiated values to continue working properly. For | |
1726 | * example, availability of memory unplug depends on knowing whether | |
1727 | * OV5_HP_EVT was negotiated via CAS. | |
1728 | * | |
1729 | * Thus, for any cases where the set of available CAS-negotiatable | |
1730 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
1731 | * include the CAS-negotiated options in the migration stream. | |
1732 | */ | |
1733 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1734 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
1735 | ||
1736 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1737 | * the mask itself since in the future it's possible "legacy" bits may be | |
1738 | * removed via machine options, which could generate a false positive | |
1739 | * that breaks migration. | |
1740 | */ | |
1741 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1742 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1743 | ||
1744 | spapr_ovec_cleanup(ov5_mask); | |
1745 | spapr_ovec_cleanup(ov5_legacy); | |
1746 | spapr_ovec_cleanup(ov5_removed); | |
1747 | ||
1748 | return cas_needed; | |
1749 | } | |
1750 | ||
1751 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1752 | .name = "spapr_option_vector_ov5_cas", | |
1753 | .version_id = 1, | |
1754 | .minimum_version_id = 1, | |
1755 | .needed = spapr_ov5_cas_needed, | |
1756 | .fields = (VMStateField[]) { | |
1757 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1758 | vmstate_spapr_ovec, sPAPROptionVector), | |
1759 | VMSTATE_END_OF_LIST() | |
1760 | }, | |
1761 | }; | |
1762 | ||
9861bb3e SJS |
1763 | static bool spapr_patb_entry_needed(void *opaque) |
1764 | { | |
1765 | sPAPRMachineState *spapr = opaque; | |
1766 | ||
1767 | return !!spapr->patb_entry; | |
1768 | } | |
1769 | ||
1770 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1771 | .name = "spapr_patb_entry", | |
1772 | .version_id = 1, | |
1773 | .minimum_version_id = 1, | |
1774 | .needed = spapr_patb_entry_needed, | |
1775 | .fields = (VMStateField[]) { | |
1776 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1777 | VMSTATE_END_OF_LIST() | |
1778 | }, | |
1779 | }; | |
1780 | ||
4be21d56 DG |
1781 | static const VMStateDescription vmstate_spapr = { |
1782 | .name = "spapr", | |
880ae7de | 1783 | .version_id = 3, |
4be21d56 | 1784 | .minimum_version_id = 1, |
4e5fe368 | 1785 | .pre_load = spapr_pre_load, |
880ae7de | 1786 | .post_load = spapr_post_load, |
4e5fe368 | 1787 | .pre_save = spapr_pre_save, |
3aff6c2f | 1788 | .fields = (VMStateField[]) { |
880ae7de DG |
1789 | /* used to be @next_irq */ |
1790 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1791 | |
1792 | /* RTC offset */ | |
28e02042 | 1793 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1794 | |
28e02042 | 1795 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1796 | VMSTATE_END_OF_LIST() |
1797 | }, | |
62ef3760 MR |
1798 | .subsections = (const VMStateDescription*[]) { |
1799 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1800 | &vmstate_spapr_patb_entry, |
fd38804b | 1801 | &vmstate_spapr_pending_events, |
4e5fe368 SJS |
1802 | &vmstate_spapr_cap_htm, |
1803 | &vmstate_spapr_cap_vsx, | |
1804 | &vmstate_spapr_cap_dfp, | |
8f38eaf8 | 1805 | &vmstate_spapr_cap_cfpc, |
09114fd8 | 1806 | &vmstate_spapr_cap_sbbc, |
4be8d4e7 | 1807 | &vmstate_spapr_cap_ibs, |
62ef3760 MR |
1808 | NULL |
1809 | } | |
4be21d56 DG |
1810 | }; |
1811 | ||
4be21d56 DG |
1812 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1813 | { | |
28e02042 | 1814 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1815 | |
4be21d56 | 1816 | /* "Iteration" header */ |
3a384297 BR |
1817 | if (!spapr->htab_shift) { |
1818 | qemu_put_be32(f, -1); | |
1819 | } else { | |
1820 | qemu_put_be32(f, spapr->htab_shift); | |
1821 | } | |
4be21d56 | 1822 | |
e68cb8b4 AK |
1823 | if (spapr->htab) { |
1824 | spapr->htab_save_index = 0; | |
1825 | spapr->htab_first_pass = true; | |
1826 | } else { | |
3a384297 BR |
1827 | if (spapr->htab_shift) { |
1828 | assert(kvm_enabled()); | |
1829 | } | |
e68cb8b4 AK |
1830 | } |
1831 | ||
1832 | ||
4be21d56 DG |
1833 | return 0; |
1834 | } | |
1835 | ||
332f7721 GK |
1836 | static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, |
1837 | int chunkstart, int n_valid, int n_invalid) | |
1838 | { | |
1839 | qemu_put_be32(f, chunkstart); | |
1840 | qemu_put_be16(f, n_valid); | |
1841 | qemu_put_be16(f, n_invalid); | |
1842 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1843 | HASH_PTE_SIZE_64 * n_valid); | |
1844 | } | |
1845 | ||
1846 | static void htab_save_end_marker(QEMUFile *f) | |
1847 | { | |
1848 | qemu_put_be32(f, 0); | |
1849 | qemu_put_be16(f, 0); | |
1850 | qemu_put_be16(f, 0); | |
1851 | } | |
1852 | ||
28e02042 | 1853 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1854 | int64_t max_ns) |
1855 | { | |
378bc217 | 1856 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1857 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1858 | int index = spapr->htab_save_index; | |
bc72ad67 | 1859 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1860 | |
1861 | assert(spapr->htab_first_pass); | |
1862 | ||
1863 | do { | |
1864 | int chunkstart; | |
1865 | ||
1866 | /* Consume invalid HPTEs */ | |
1867 | while ((index < htabslots) | |
1868 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 1869 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1870 | index++; |
4be21d56 DG |
1871 | } |
1872 | ||
1873 | /* Consume valid HPTEs */ | |
1874 | chunkstart = index; | |
338c25b6 | 1875 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 1876 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 1877 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1878 | index++; |
4be21d56 DG |
1879 | } |
1880 | ||
1881 | if (index > chunkstart) { | |
1882 | int n_valid = index - chunkstart; | |
1883 | ||
332f7721 | 1884 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 1885 | |
378bc217 DG |
1886 | if (has_timeout && |
1887 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1888 | break; |
1889 | } | |
1890 | } | |
1891 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1892 | ||
1893 | if (index >= htabslots) { | |
1894 | assert(index == htabslots); | |
1895 | index = 0; | |
1896 | spapr->htab_first_pass = false; | |
1897 | } | |
1898 | spapr->htab_save_index = index; | |
1899 | } | |
1900 | ||
28e02042 | 1901 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1902 | int64_t max_ns) |
4be21d56 DG |
1903 | { |
1904 | bool final = max_ns < 0; | |
1905 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1906 | int examined = 0, sent = 0; | |
1907 | int index = spapr->htab_save_index; | |
bc72ad67 | 1908 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1909 | |
1910 | assert(!spapr->htab_first_pass); | |
1911 | ||
1912 | do { | |
1913 | int chunkstart, invalidstart; | |
1914 | ||
1915 | /* Consume non-dirty HPTEs */ | |
1916 | while ((index < htabslots) | |
1917 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1918 | index++; | |
1919 | examined++; | |
1920 | } | |
1921 | ||
1922 | chunkstart = index; | |
1923 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1924 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1925 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1926 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1927 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1928 | index++; | |
1929 | examined++; | |
1930 | } | |
1931 | ||
1932 | invalidstart = index; | |
1933 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1934 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1935 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1936 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1937 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1938 | index++; | |
1939 | examined++; | |
1940 | } | |
1941 | ||
1942 | if (index > chunkstart) { | |
1943 | int n_valid = invalidstart - chunkstart; | |
1944 | int n_invalid = index - invalidstart; | |
1945 | ||
332f7721 | 1946 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
1947 | sent += index - chunkstart; |
1948 | ||
bc72ad67 | 1949 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1950 | break; |
1951 | } | |
1952 | } | |
1953 | ||
1954 | if (examined >= htabslots) { | |
1955 | break; | |
1956 | } | |
1957 | ||
1958 | if (index >= htabslots) { | |
1959 | assert(index == htabslots); | |
1960 | index = 0; | |
1961 | } | |
1962 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1963 | ||
1964 | if (index >= htabslots) { | |
1965 | assert(index == htabslots); | |
1966 | index = 0; | |
1967 | } | |
1968 | ||
1969 | spapr->htab_save_index = index; | |
1970 | ||
e68cb8b4 | 1971 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1972 | } |
1973 | ||
e68cb8b4 AK |
1974 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1975 | #define MAX_KVM_BUF_SIZE 2048 | |
1976 | ||
4be21d56 DG |
1977 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1978 | { | |
28e02042 | 1979 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1980 | int fd; |
e68cb8b4 | 1981 | int rc = 0; |
4be21d56 DG |
1982 | |
1983 | /* Iteration header */ | |
3a384297 BR |
1984 | if (!spapr->htab_shift) { |
1985 | qemu_put_be32(f, -1); | |
e8cd4247 | 1986 | return 1; |
3a384297 BR |
1987 | } else { |
1988 | qemu_put_be32(f, 0); | |
1989 | } | |
4be21d56 | 1990 | |
e68cb8b4 AK |
1991 | if (!spapr->htab) { |
1992 | assert(kvm_enabled()); | |
1993 | ||
715c5407 DG |
1994 | fd = get_htab_fd(spapr); |
1995 | if (fd < 0) { | |
1996 | return fd; | |
01a57972 SMJ |
1997 | } |
1998 | ||
715c5407 | 1999 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
2000 | if (rc < 0) { |
2001 | return rc; | |
2002 | } | |
2003 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
2004 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
2005 | } else { | |
e68cb8b4 | 2006 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
2007 | } |
2008 | ||
332f7721 | 2009 | htab_save_end_marker(f); |
4be21d56 | 2010 | |
e68cb8b4 | 2011 | return rc; |
4be21d56 DG |
2012 | } |
2013 | ||
2014 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
2015 | { | |
28e02042 | 2016 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2017 | int fd; |
4be21d56 DG |
2018 | |
2019 | /* Iteration header */ | |
3a384297 BR |
2020 | if (!spapr->htab_shift) { |
2021 | qemu_put_be32(f, -1); | |
2022 | return 0; | |
2023 | } else { | |
2024 | qemu_put_be32(f, 0); | |
2025 | } | |
4be21d56 | 2026 | |
e68cb8b4 AK |
2027 | if (!spapr->htab) { |
2028 | int rc; | |
2029 | ||
2030 | assert(kvm_enabled()); | |
2031 | ||
715c5407 DG |
2032 | fd = get_htab_fd(spapr); |
2033 | if (fd < 0) { | |
2034 | return fd; | |
01a57972 SMJ |
2035 | } |
2036 | ||
715c5407 | 2037 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
2038 | if (rc < 0) { |
2039 | return rc; | |
2040 | } | |
e68cb8b4 | 2041 | } else { |
378bc217 DG |
2042 | if (spapr->htab_first_pass) { |
2043 | htab_save_first_pass(f, spapr, -1); | |
2044 | } | |
e68cb8b4 AK |
2045 | htab_save_later_pass(f, spapr, -1); |
2046 | } | |
4be21d56 DG |
2047 | |
2048 | /* End marker */ | |
332f7721 | 2049 | htab_save_end_marker(f); |
4be21d56 DG |
2050 | |
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2055 | { | |
28e02042 | 2056 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 2057 | uint32_t section_hdr; |
e68cb8b4 | 2058 | int fd = -1; |
14b0d748 | 2059 | Error *local_err = NULL; |
4be21d56 DG |
2060 | |
2061 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2062 | error_report("htab_load() bad version"); |
4be21d56 DG |
2063 | return -EINVAL; |
2064 | } | |
2065 | ||
2066 | section_hdr = qemu_get_be32(f); | |
2067 | ||
3a384297 BR |
2068 | if (section_hdr == -1) { |
2069 | spapr_free_hpt(spapr); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
4be21d56 | 2073 | if (section_hdr) { |
c5f54f3e DG |
2074 | /* First section gives the htab size */ |
2075 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2076 | if (local_err) { | |
2077 | error_report_err(local_err); | |
4be21d56 DG |
2078 | return -EINVAL; |
2079 | } | |
2080 | return 0; | |
2081 | } | |
2082 | ||
e68cb8b4 AK |
2083 | if (!spapr->htab) { |
2084 | assert(kvm_enabled()); | |
2085 | ||
14b0d748 | 2086 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2087 | if (fd < 0) { |
14b0d748 | 2088 | error_report_err(local_err); |
82be8e73 | 2089 | return fd; |
e68cb8b4 AK |
2090 | } |
2091 | } | |
2092 | ||
4be21d56 DG |
2093 | while (true) { |
2094 | uint32_t index; | |
2095 | uint16_t n_valid, n_invalid; | |
2096 | ||
2097 | index = qemu_get_be32(f); | |
2098 | n_valid = qemu_get_be16(f); | |
2099 | n_invalid = qemu_get_be16(f); | |
2100 | ||
2101 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2102 | /* End of Stream */ | |
2103 | break; | |
2104 | } | |
2105 | ||
e68cb8b4 | 2106 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2107 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2108 | /* Bad index in stream */ | |
98a5d100 DG |
2109 | error_report( |
2110 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2111 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2112 | return -EINVAL; |
2113 | } | |
2114 | ||
e68cb8b4 AK |
2115 | if (spapr->htab) { |
2116 | if (n_valid) { | |
2117 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2118 | HASH_PTE_SIZE_64 * n_valid); | |
2119 | } | |
2120 | if (n_invalid) { | |
2121 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2122 | HASH_PTE_SIZE_64 * n_invalid); | |
2123 | } | |
2124 | } else { | |
2125 | int rc; | |
2126 | ||
2127 | assert(fd >= 0); | |
2128 | ||
2129 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2130 | if (rc < 0) { | |
2131 | return rc; | |
2132 | } | |
4be21d56 DG |
2133 | } |
2134 | } | |
2135 | ||
e68cb8b4 AK |
2136 | if (!spapr->htab) { |
2137 | assert(fd >= 0); | |
2138 | close(fd); | |
2139 | } | |
2140 | ||
4be21d56 DG |
2141 | return 0; |
2142 | } | |
2143 | ||
70f794fc | 2144 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
2145 | { |
2146 | sPAPRMachineState *spapr = opaque; | |
2147 | ||
2148 | close_htab_fd(spapr); | |
2149 | } | |
2150 | ||
4be21d56 | 2151 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2152 | .save_setup = htab_save_setup, |
4be21d56 | 2153 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2154 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2155 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2156 | .load_state = htab_load, |
2157 | }; | |
2158 | ||
5b2128d2 AG |
2159 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2160 | Error **errp) | |
2161 | { | |
c86c1aff | 2162 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2163 | machine->boot_order = g_strdup(boot_device); |
2164 | } | |
2165 | ||
224245bf DG |
2166 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2167 | { | |
2168 | MachineState *machine = MACHINE(spapr); | |
2169 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2170 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2171 | int i; |
2172 | ||
2173 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2174 | uint64_t addr; |
2175 | ||
e8f986fc | 2176 | addr = i * lmb_size + spapr->hotplug_memory.base; |
6caf3ac6 DG |
2177 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2178 | addr / lmb_size); | |
224245bf DG |
2179 | } |
2180 | } | |
2181 | ||
2182 | /* | |
2183 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2184 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2185 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2186 | */ | |
7c150d6f | 2187 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2188 | { |
2189 | int i; | |
2190 | ||
7c150d6f DG |
2191 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2192 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
2193 | " is not aligned to %llu MiB", | |
2194 | machine->ram_size, | |
2195 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2196 | return; | |
2197 | } | |
2198 | ||
2199 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2200 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
2201 | " is not aligned to %llu MiB", | |
2202 | machine->ram_size, | |
2203 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2204 | return; | |
224245bf DG |
2205 | } |
2206 | ||
2207 | for (i = 0; i < nb_numa_nodes; i++) { | |
2208 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2209 | error_setg(errp, |
2210 | "Node %d memory size 0x%" PRIx64 | |
2211 | " is not aligned to %llu MiB", | |
2212 | i, numa_info[i].node_mem, | |
2213 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2214 | return; | |
224245bf DG |
2215 | } |
2216 | } | |
2217 | } | |
2218 | ||
535455fd IM |
2219 | /* find cpu slot in machine->possible_cpus by core_id */ |
2220 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2221 | { | |
2222 | int index = id / smp_threads; | |
2223 | ||
2224 | if (index >= ms->possible_cpus->len) { | |
2225 | return NULL; | |
2226 | } | |
2227 | if (idx) { | |
2228 | *idx = index; | |
2229 | } | |
2230 | return &ms->possible_cpus->cpus[index]; | |
2231 | } | |
2232 | ||
fa98fbfc SB |
2233 | static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) |
2234 | { | |
2235 | Error *local_err = NULL; | |
2236 | bool vsmt_user = !!spapr->vsmt; | |
2237 | int kvm_smt = kvmppc_smt_threads(); | |
2238 | int ret; | |
2239 | ||
2240 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2241 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2242 | "on a pseries machine"); | |
2243 | goto out; | |
2244 | } | |
2245 | if (!is_power_of_2(smp_threads)) { | |
2246 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2247 | "machine because it must be a power of 2", smp_threads); | |
2248 | goto out; | |
2249 | } | |
2250 | ||
2251 | /* Detemine the VSMT mode to use: */ | |
2252 | if (vsmt_user) { | |
2253 | if (spapr->vsmt < smp_threads) { | |
2254 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2255 | " because it must be >= threads/core (%d)", | |
2256 | spapr->vsmt, smp_threads); | |
2257 | goto out; | |
2258 | } | |
2259 | /* In this case, spapr->vsmt has been set by the command line */ | |
2260 | } else { | |
8904e5a7 DG |
2261 | /* |
2262 | * Default VSMT value is tricky, because we need it to be as | |
2263 | * consistent as possible (for migration), but this requires | |
2264 | * changing it for at least some existing cases. We pick 8 as | |
2265 | * the value that we'd get with KVM on POWER8, the | |
2266 | * overwhelmingly common case in production systems. | |
2267 | */ | |
4ad64cbd | 2268 | spapr->vsmt = MAX(8, smp_threads); |
fa98fbfc SB |
2269 | } |
2270 | ||
2271 | /* KVM: If necessary, set the SMT mode: */ | |
2272 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2273 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2274 | if (ret) { | |
1f20f2e0 | 2275 | /* Looks like KVM isn't able to change VSMT mode */ |
fa98fbfc SB |
2276 | error_setg(&local_err, |
2277 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2278 | spapr->vsmt, ret); | |
1f20f2e0 DG |
2279 | /* We can live with that if the default one is big enough |
2280 | * for the number of threads, and a submultiple of the one | |
2281 | * we want. In this case we'll waste some vcpu ids, but | |
2282 | * behaviour will be correct */ | |
2283 | if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { | |
2284 | warn_report_err(local_err); | |
2285 | local_err = NULL; | |
2286 | goto out; | |
2287 | } else { | |
2288 | if (!vsmt_user) { | |
2289 | error_append_hint(&local_err, | |
2290 | "On PPC, a VM with %d threads/core" | |
2291 | " on a host with %d threads/core" | |
2292 | " requires the use of VSMT mode %d.\n", | |
2293 | smp_threads, kvm_smt, spapr->vsmt); | |
2294 | } | |
2295 | kvmppc_hint_smt_possible(&local_err); | |
2296 | goto out; | |
fa98fbfc | 2297 | } |
fa98fbfc SB |
2298 | } |
2299 | } | |
2300 | /* else TCG: nothing to do currently */ | |
2301 | out: | |
2302 | error_propagate(errp, local_err); | |
2303 | } | |
2304 | ||
1a5008fc GK |
2305 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2306 | { | |
2307 | MachineState *machine = MACHINE(spapr); | |
2308 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2309 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); | |
2310 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); | |
2311 | const CPUArchIdList *possible_cpus; | |
2312 | int boot_cores_nr = smp_cpus / smp_threads; | |
2313 | int i; | |
2314 | ||
2315 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
2316 | if (mc->has_hotpluggable_cpus) { | |
2317 | if (smp_cpus % smp_threads) { | |
2318 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2319 | smp_cpus, smp_threads); | |
2320 | exit(1); | |
2321 | } | |
2322 | if (max_cpus % smp_threads) { | |
2323 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2324 | max_cpus, smp_threads); | |
2325 | exit(1); | |
2326 | } | |
2327 | } else { | |
2328 | if (max_cpus != smp_cpus) { | |
2329 | error_report("This machine version does not support CPU hotplug"); | |
2330 | exit(1); | |
2331 | } | |
2332 | boot_cores_nr = possible_cpus->len; | |
2333 | } | |
2334 | ||
2335 | /* VSMT must be set in order to be able to compute VCPU ids, ie to | |
2336 | * call xics_max_server_number() or spapr_vcpu_id(). | |
2337 | */ | |
2338 | spapr_set_vsmt_mode(spapr, &error_fatal); | |
2339 | ||
2340 | if (smc->pre_2_10_has_unused_icps) { | |
2341 | int i; | |
2342 | ||
2343 | for (i = 0; i < xics_max_server_number(spapr); i++) { | |
2344 | /* Dummy entries get deregistered when real ICPState objects | |
2345 | * are registered during CPU core hotplug. | |
2346 | */ | |
2347 | pre_2_10_vmstate_register_dummy_icp(i); | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | for (i = 0; i < possible_cpus->len; i++) { | |
2352 | int core_id = i * smp_threads; | |
2353 | ||
2354 | if (mc->has_hotpluggable_cpus) { | |
2355 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, | |
2356 | spapr_vcpu_id(spapr, core_id)); | |
2357 | } | |
2358 | ||
2359 | if (i < boot_cores_nr) { | |
2360 | Object *core = object_new(type); | |
2361 | int nr_threads = smp_threads; | |
2362 | ||
2363 | /* Handle the partially filled core for older machine types */ | |
2364 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2365 | nr_threads = smp_cpus - i * smp_threads; | |
2366 | } | |
2367 | ||
2368 | object_property_set_int(core, nr_threads, "nr-threads", | |
2369 | &error_fatal); | |
2370 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2371 | &error_fatal); | |
2372 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2373 | } | |
2374 | } | |
2375 | } | |
2376 | ||
9fdf0c29 | 2377 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2378 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2379 | { |
28e02042 | 2380 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2381 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2382 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2383 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2384 | PCIHostState *phb; |
9fdf0c29 | 2385 | int i; |
890c2b77 AK |
2386 | MemoryRegion *sysmem = get_system_memory(); |
2387 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
2388 | MemoryRegion *rma_region; |
2389 | void *rma = NULL; | |
a8170e5e | 2390 | hwaddr rma_alloc_size; |
c86c1aff | 2391 | hwaddr node0_size = spapr_node0_size(machine); |
b7d1f77a | 2392 | long load_limit, fw_size; |
39ac8455 | 2393 | char *filename; |
30f4b05b | 2394 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2395 | |
226419d6 | 2396 | msi_nonbroken = true; |
0ee2c058 | 2397 | |
d43b45e2 | 2398 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2399 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2400 | |
30f4b05b DG |
2401 | /* Check HPT resizing availability */ |
2402 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); | |
2403 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2404 | /* | |
2405 | * If the user explicitly requested a mode we should either | |
2406 | * supply it, or fail completely (which we do below). But if | |
2407 | * it's not set explicitly, we reset our mode to something | |
2408 | * that works | |
2409 | */ | |
2410 | if (resize_hpt_err) { | |
2411 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2412 | error_free(resize_hpt_err); | |
2413 | resize_hpt_err = NULL; | |
2414 | } else { | |
2415 | spapr->resize_hpt = smc->resize_hpt_default; | |
2416 | } | |
2417 | } | |
2418 | ||
2419 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2420 | ||
2421 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2422 | /* | |
2423 | * User requested HPT resize, but this host can't supply it. Bail out | |
2424 | */ | |
2425 | error_report_err(resize_hpt_err); | |
2426 | exit(1); | |
2427 | } | |
2428 | ||
354ac20a | 2429 | /* Allocate RMA if necessary */ |
658fa66b | 2430 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
2431 | |
2432 | if (rma_alloc_size == -1) { | |
730fce59 | 2433 | error_report("Unable to create RMA"); |
354ac20a DG |
2434 | exit(1); |
2435 | } | |
7f763a5d | 2436 | |
c4177479 | 2437 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 2438 | spapr->rma_size = rma_alloc_size; |
354ac20a | 2439 | } else { |
c4177479 | 2440 | spapr->rma_size = node0_size; |
7f763a5d DG |
2441 | |
2442 | /* With KVM, we don't actually know whether KVM supports an | |
2443 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2444 | * (HV KVM using VRMA), so we always assume the latter | |
2445 | * | |
2446 | * In that case, we also limit the initial allocations for RTAS | |
2447 | * etc... to 256M since we have no way to know what the VRMA size | |
2448 | * is going to be as it depends on the size of the hash table | |
2449 | * isn't determined yet. | |
2450 | */ | |
2451 | if (kvm_enabled()) { | |
2452 | spapr->vrma_adjust = 1; | |
2453 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
2454 | } | |
912acdf4 BH |
2455 | |
2456 | /* Actually we don't support unbounded RMA anymore since we | |
2457 | * added proper emulation of HV mode. The max we can get is | |
2458 | * 16G which also happens to be what we configure for PAPR | |
2459 | * mode so make sure we don't do anything bigger than that | |
2460 | */ | |
2461 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
2462 | } |
2463 | ||
c4177479 | 2464 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2465 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2466 | spapr->rma_size); | |
c4177479 AK |
2467 | exit(1); |
2468 | } | |
2469 | ||
b7d1f77a BH |
2470 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2471 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2472 | |
7b565160 | 2473 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2474 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2475 | |
dc1b5eee GK |
2476 | /* Set up containers for ibm,client-architecture-support negotiated options |
2477 | */ | |
facdb8b6 MR |
2478 | spapr->ov5 = spapr_ovec_new(); |
2479 | spapr->ov5_cas = spapr_ovec_new(); | |
2480 | ||
224245bf | 2481 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2482 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2483 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2484 | } |
2485 | ||
417ece33 | 2486 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
545d6e2b SJS |
2487 | if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { |
2488 | /* KVM and TCG always allow GTSE with radix... */ | |
9fb4541f SB |
2489 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2490 | } | |
2491 | /* ... but not with hash (currently). */ | |
417ece33 | 2492 | |
ffbb1705 MR |
2493 | /* advertise support for dedicated HP event source to guests */ |
2494 | if (spapr->use_hotplug_event_source) { | |
2495 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2496 | } | |
2497 | ||
2772cf6b DG |
2498 | /* advertise support for HPT resizing */ |
2499 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2500 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2501 | } | |
2502 | ||
9fdf0c29 | 2503 | /* init CPUs */ |
0c86d0fd | 2504 | spapr_init_cpus(spapr); |
9fdf0c29 | 2505 | |
026bfd89 DG |
2506 | if (kvm_enabled()) { |
2507 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2508 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2509 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2510 | |
2511 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2512 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2513 | } |
2514 | ||
9fdf0c29 | 2515 | /* allocate RAM */ |
f92f5da1 | 2516 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2517 | machine->ram_size); |
f92f5da1 | 2518 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2519 | |
658fa66b AK |
2520 | if (rma_alloc_size && rma) { |
2521 | rma_region = g_new(MemoryRegion, 1); | |
2522 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
2523 | rma_alloc_size, rma); | |
2524 | vmstate_register_ram_global(rma_region); | |
2525 | memory_region_add_subregion(sysmem, 0, rma_region); | |
2526 | } | |
2527 | ||
4a1c9cf0 BR |
2528 | /* initialize hotplug memory address space */ |
2529 | if (machine->ram_size < machine->maxram_size) { | |
2530 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
2531 | /* |
2532 | * Limit the number of hotpluggable memory slots to half the number | |
2533 | * slots that KVM supports, leaving the other half for PCI and other | |
2534 | * devices. However ensure that number of slots doesn't drop below 32. | |
2535 | */ | |
2536 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2537 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2538 | |
71c9a3dd BR |
2539 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2540 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2541 | } | |
2542 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2543 | error_report("Specified number of memory slots %" |
2544 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2545 | machine->ram_slots, max_memslots); |
d54e4d76 | 2546 | exit(1); |
4a1c9cf0 BR |
2547 | } |
2548 | ||
2549 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
2550 | SPAPR_HOTPLUG_MEM_ALIGN); | |
2551 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
2552 | "hotplug-memory", hotplug_mem_size); | |
2553 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
2554 | &spapr->hotplug_memory.mr); | |
2555 | } | |
2556 | ||
224245bf DG |
2557 | if (smc->dr_lmb_enabled) { |
2558 | spapr_create_lmb_dr_connectors(spapr); | |
2559 | } | |
2560 | ||
39ac8455 | 2561 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2562 | if (!filename) { |
730fce59 | 2563 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2564 | exit(1); |
2565 | } | |
b7d1f77a | 2566 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2567 | if (spapr->rtas_size < 0) { |
2568 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2569 | exit(1); | |
2570 | } | |
b7d1f77a BH |
2571 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2572 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2573 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2574 | exit(1); |
2575 | } | |
4d8d5467 | 2576 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2577 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2578 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2579 | exit(1); |
2580 | } | |
7267c094 | 2581 | g_free(filename); |
39ac8455 | 2582 | |
ffbb1705 | 2583 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2584 | spapr_events_init(spapr); |
2585 | ||
12f42174 | 2586 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2587 | spapr_rtc_create(spapr); |
12f42174 | 2588 | |
b5cec4c5 | 2589 | /* Set up VIO bus */ |
4040ab72 DG |
2590 | spapr->vio_bus = spapr_vio_bus_init(); |
2591 | ||
277f9acf | 2592 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 2593 | if (serial_hds[i]) { |
d601fac4 | 2594 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
2595 | } |
2596 | } | |
9fdf0c29 | 2597 | |
639e8102 DG |
2598 | /* We always have at least the nvram device on VIO */ |
2599 | spapr_create_nvram(spapr); | |
2600 | ||
3384f95c | 2601 | /* Set up PCI */ |
fa28f71b AK |
2602 | spapr_pci_rtas_init(); |
2603 | ||
89dfd6e1 | 2604 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2605 | |
277f9acf | 2606 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2607 | NICInfo *nd = &nd_table[i]; |
2608 | ||
2609 | if (!nd->model) { | |
7267c094 | 2610 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
2611 | } |
2612 | ||
2613 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 2614 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2615 | } else { |
29b358f9 | 2616 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2617 | } |
2618 | } | |
2619 | ||
6e270446 | 2620 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2621 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2622 | } |
2623 | ||
f28359d8 | 2624 | /* Graphics */ |
14c6a894 | 2625 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2626 | spapr->has_graphics = true; |
c6e76503 | 2627 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2628 | } |
2629 | ||
4ee9ced9 | 2630 | if (machine->usb) { |
57040d45 TH |
2631 | if (smc->use_ohci_by_default) { |
2632 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2633 | } else { | |
2634 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2635 | } | |
c86580b8 | 2636 | |
35139a59 | 2637 | if (spapr->has_graphics) { |
c86580b8 MA |
2638 | USBBus *usb_bus = usb_bus_find(-1); |
2639 | ||
2640 | usb_create_simple(usb_bus, "usb-kbd"); | |
2641 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2642 | } |
2643 | } | |
2644 | ||
7f763a5d | 2645 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2646 | error_report( |
2647 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2648 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2649 | exit(1); |
2650 | } | |
2651 | ||
9fdf0c29 DG |
2652 | if (kernel_filename) { |
2653 | uint64_t lowaddr = 0; | |
2654 | ||
a19f7fb0 DG |
2655 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2656 | NULL, NULL, &lowaddr, NULL, 1, | |
2657 | PPC_ELF_MACHINE, 0, 0); | |
2658 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2659 | spapr->kernel_size = load_elf(kernel_filename, | |
2660 | translate_kernel_address, NULL, NULL, | |
2661 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2662 | 0, 0); | |
2663 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2664 | } |
a19f7fb0 DG |
2665 | if (spapr->kernel_size < 0) { |
2666 | error_report("error loading %s: %s", kernel_filename, | |
2667 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2668 | exit(1); |
2669 | } | |
2670 | ||
2671 | /* load initrd */ | |
2672 | if (initrd_filename) { | |
4d8d5467 BH |
2673 | /* Try to locate the initrd in the gap between the kernel |
2674 | * and the firmware. Add a bit of space just in case | |
2675 | */ | |
a19f7fb0 DG |
2676 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2677 | + 0x1ffff) & ~0xffff; | |
2678 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2679 | spapr->initrd_base, | |
2680 | load_limit | |
2681 | - spapr->initrd_base); | |
2682 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2683 | error_report("could not load initial ram disk '%s'", |
2684 | initrd_filename); | |
9fdf0c29 DG |
2685 | exit(1); |
2686 | } | |
9fdf0c29 | 2687 | } |
4d8d5467 | 2688 | } |
a3467baa | 2689 | |
8e7ea787 AF |
2690 | if (bios_name == NULL) { |
2691 | bios_name = FW_FILE_NAME; | |
2692 | } | |
2693 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2694 | if (!filename) { |
68fea5a0 | 2695 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2696 | exit(1); |
2697 | } | |
4d8d5467 | 2698 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2699 | if (fw_size <= 0) { |
2700 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2701 | exit(1); |
2702 | } | |
2703 | g_free(filename); | |
4d8d5467 | 2704 | |
28e02042 DG |
2705 | /* FIXME: Should register things through the MachineState's qdev |
2706 | * interface, this is a legacy from the sPAPREnvironment structure | |
2707 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2708 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2709 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2710 | &savevm_htab_handlers, spapr); | |
2711 | ||
5b2128d2 | 2712 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2713 | |
42043e4f | 2714 | if (kvm_enabled()) { |
3dc410ae | 2715 | /* to stop and start vmclock */ |
42043e4f LV |
2716 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2717 | &spapr->tb); | |
3dc410ae AK |
2718 | |
2719 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2720 | } |
9fdf0c29 DG |
2721 | } |
2722 | ||
135a129a AK |
2723 | static int spapr_kvm_type(const char *vm_type) |
2724 | { | |
2725 | if (!vm_type) { | |
2726 | return 0; | |
2727 | } | |
2728 | ||
2729 | if (!strcmp(vm_type, "HV")) { | |
2730 | return 1; | |
2731 | } | |
2732 | ||
2733 | if (!strcmp(vm_type, "PR")) { | |
2734 | return 2; | |
2735 | } | |
2736 | ||
2737 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2738 | exit(1); | |
2739 | } | |
2740 | ||
71461b0f | 2741 | /* |
627b84f4 | 2742 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2743 | * for the bootindex property handling. |
2744 | */ | |
2745 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2746 | DeviceState *dev) | |
2747 | { | |
2748 | #define CAST(type, obj, name) \ | |
2749 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2750 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2751 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2752 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2753 | |
2754 | if (d) { | |
2755 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2756 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2757 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2758 | ||
2759 | if (spapr) { | |
2760 | /* | |
2761 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2762 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2763 | * in the top 16 bits of the 64-bit LUN | |
2764 | */ | |
2765 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2766 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2767 | (uint64_t)id << 48); | |
2768 | } else if (virtio) { | |
2769 | /* | |
2770 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2771 | * in the top 32 bits of the 64-bit LUN | |
2772 | * Note: the quote above is from SLOF and it is wrong, | |
2773 | * the actual binding is: | |
2774 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2775 | */ | |
2776 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
2777 | if (d->lun >= 256) { |
2778 | /* Use the LUN "flat space addressing method" */ | |
2779 | id |= 0x4000; | |
2780 | } | |
71461b0f AK |
2781 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
2782 | (uint64_t)id << 32); | |
2783 | } else if (usb) { | |
2784 | /* | |
2785 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2786 | * in the top 32 bits of the 64-bit LUN | |
2787 | */ | |
2788 | unsigned usb_port = atoi(usb->port->path); | |
2789 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2790 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2791 | (uint64_t)id << 32); | |
2792 | } | |
2793 | } | |
2794 | ||
b99260eb TH |
2795 | /* |
2796 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2797 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2798 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2799 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2800 | */ | |
2801 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2802 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2803 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2804 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2805 | } | |
2806 | } | |
2807 | ||
71461b0f AK |
2808 | if (phb) { |
2809 | /* Replace "pci" with "pci@800000020000000" */ | |
2810 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2811 | } | |
2812 | ||
c4e13492 FF |
2813 | if (vsc) { |
2814 | /* Same logic as virtio above */ | |
2815 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2816 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2817 | } | |
2818 | ||
4871dd4c TH |
2819 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2820 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2821 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2822 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2823 | } | |
2824 | ||
71461b0f AK |
2825 | return NULL; |
2826 | } | |
2827 | ||
23825581 EH |
2828 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2829 | { | |
28e02042 | 2830 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2831 | |
28e02042 | 2832 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2833 | } |
2834 | ||
2835 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2836 | { | |
28e02042 | 2837 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2838 | |
28e02042 DG |
2839 | g_free(spapr->kvm_type); |
2840 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2841 | } |
2842 | ||
f6229214 MR |
2843 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2844 | { | |
2845 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2846 | ||
2847 | return spapr->use_hotplug_event_source; | |
2848 | } | |
2849 | ||
2850 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2851 | Error **errp) | |
2852 | { | |
2853 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2854 | ||
2855 | spapr->use_hotplug_event_source = value; | |
2856 | } | |
2857 | ||
30f4b05b DG |
2858 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2859 | { | |
2860 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2861 | ||
2862 | switch (spapr->resize_hpt) { | |
2863 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2864 | return g_strdup("default"); | |
2865 | case SPAPR_RESIZE_HPT_DISABLED: | |
2866 | return g_strdup("disabled"); | |
2867 | case SPAPR_RESIZE_HPT_ENABLED: | |
2868 | return g_strdup("enabled"); | |
2869 | case SPAPR_RESIZE_HPT_REQUIRED: | |
2870 | return g_strdup("required"); | |
2871 | } | |
2872 | g_assert_not_reached(); | |
2873 | } | |
2874 | ||
2875 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
2876 | { | |
2877 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2878 | ||
2879 | if (strcmp(value, "default") == 0) { | |
2880 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
2881 | } else if (strcmp(value, "disabled") == 0) { | |
2882 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2883 | } else if (strcmp(value, "enabled") == 0) { | |
2884 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
2885 | } else if (strcmp(value, "required") == 0) { | |
2886 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
2887 | } else { | |
2888 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
2889 | } | |
2890 | } | |
2891 | ||
fa98fbfc SB |
2892 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
2893 | void *opaque, Error **errp) | |
2894 | { | |
2895 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2896 | } | |
2897 | ||
2898 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, | |
2899 | void *opaque, Error **errp) | |
2900 | { | |
2901 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2902 | } | |
2903 | ||
bcb5ce08 | 2904 | static void spapr_instance_init(Object *obj) |
23825581 | 2905 | { |
715c5407 DG |
2906 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2907 | ||
2908 | spapr->htab_fd = -1; | |
f6229214 | 2909 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2910 | object_property_add_str(obj, "kvm-type", |
2911 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2912 | object_property_set_description(obj, "kvm-type", |
2913 | "Specifies the KVM virtualization mode (HV, PR)", | |
2914 | NULL); | |
f6229214 MR |
2915 | object_property_add_bool(obj, "modern-hotplug-events", |
2916 | spapr_get_modern_hotplug_events, | |
2917 | spapr_set_modern_hotplug_events, | |
2918 | NULL); | |
2919 | object_property_set_description(obj, "modern-hotplug-events", | |
2920 | "Use dedicated hotplug event mechanism in" | |
2921 | " place of standard EPOW events when possible" | |
2922 | " (required for memory hot-unplug support)", | |
2923 | NULL); | |
7843c0d6 DG |
2924 | |
2925 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, | |
2926 | "Maximum permitted CPU compatibility mode", | |
2927 | &error_fatal); | |
30f4b05b DG |
2928 | |
2929 | object_property_add_str(obj, "resize-hpt", | |
2930 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
2931 | object_property_set_description(obj, "resize-hpt", | |
2932 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
2933 | NULL); | |
fa98fbfc SB |
2934 | object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, |
2935 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); | |
2936 | object_property_set_description(obj, "vsmt", | |
2937 | "Virtual SMT: KVM behaves as if this were" | |
2938 | " the host's SMT mode", &error_abort); | |
23825581 EH |
2939 | } |
2940 | ||
87bbdd9c DG |
2941 | static void spapr_machine_finalizefn(Object *obj) |
2942 | { | |
2943 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2944 | ||
2945 | g_free(spapr->kvm_type); | |
2946 | } | |
2947 | ||
1c7ad77e | 2948 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 2949 | { |
34316482 AK |
2950 | cpu_synchronize_state(cs); |
2951 | ppc_cpu_do_system_reset(cs); | |
2952 | } | |
2953 | ||
2954 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2955 | { | |
2956 | CPUState *cs; | |
2957 | ||
2958 | CPU_FOREACH(cs) { | |
1c7ad77e | 2959 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
2960 | } |
2961 | } | |
2962 | ||
79b78a6b MR |
2963 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2964 | uint32_t node, bool dedicated_hp_event_source, | |
2965 | Error **errp) | |
c20d332a BR |
2966 | { |
2967 | sPAPRDRConnector *drc; | |
c20d332a BR |
2968 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
2969 | int i, fdt_offset, fdt_size; | |
2970 | void *fdt; | |
79b78a6b | 2971 | uint64_t addr = addr_start; |
94fd9cba | 2972 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 2973 | Error *local_err = NULL; |
c20d332a | 2974 | |
c20d332a | 2975 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
2976 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2977 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
2978 | g_assert(drc); |
2979 | ||
2980 | fdt = create_device_tree(&fdt_size); | |
2981 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2982 | SPAPR_MEMORY_BLOCK_SIZE); | |
2983 | ||
160bb678 GK |
2984 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
2985 | if (local_err) { | |
2986 | while (addr > addr_start) { | |
2987 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
2988 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
2989 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 2990 | spapr_drc_detach(drc); |
160bb678 GK |
2991 | } |
2992 | g_free(fdt); | |
2993 | error_propagate(errp, local_err); | |
2994 | return; | |
2995 | } | |
94fd9cba LV |
2996 | if (!hotplugged) { |
2997 | spapr_drc_reset(drc); | |
2998 | } | |
c20d332a BR |
2999 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3000 | } | |
5dd5238c JD |
3001 | /* send hotplug notification to the |
3002 | * guest only in case of hotplugged memory | |
3003 | */ | |
94fd9cba | 3004 | if (hotplugged) { |
79b78a6b | 3005 | if (dedicated_hp_event_source) { |
fbf55397 DG |
3006 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3007 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
3008 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3009 | nr_lmbs, | |
0b55aa91 | 3010 | spapr_drc_index(drc)); |
79b78a6b MR |
3011 | } else { |
3012 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
3013 | nr_lmbs); | |
3014 | } | |
5dd5238c | 3015 | } |
c20d332a BR |
3016 | } |
3017 | ||
3018 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3019 | uint32_t node, Error **errp) | |
3020 | { | |
3021 | Error *local_err = NULL; | |
3022 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
3023 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3024 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3025 | MemoryRegion *mr; |
3026 | uint64_t align, size, addr; | |
3027 | ||
3028 | mr = ddc->get_memory_region(dimm, &local_err); | |
3029 | if (local_err) { | |
3030 | goto out; | |
3031 | } | |
3032 | align = memory_region_get_alignment(mr); | |
3033 | size = memory_region_size(mr); | |
df587133 | 3034 | |
d6a9b0b8 | 3035 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
3036 | if (local_err) { |
3037 | goto out; | |
3038 | } | |
3039 | ||
9ed442b8 MAL |
3040 | addr = object_property_get_uint(OBJECT(dimm), |
3041 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 3042 | if (local_err) { |
160bb678 | 3043 | goto out_unplug; |
c20d332a BR |
3044 | } |
3045 | ||
79b78a6b MR |
3046 | spapr_add_lmbs(dev, addr, size, node, |
3047 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
3048 | &local_err); |
3049 | if (local_err) { | |
3050 | goto out_unplug; | |
3051 | } | |
3052 | ||
3053 | return; | |
c20d332a | 3054 | |
160bb678 GK |
3055 | out_unplug: |
3056 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
c20d332a BR |
3057 | out: |
3058 | error_propagate(errp, local_err); | |
3059 | } | |
3060 | ||
c871bc70 LV |
3061 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3062 | Error **errp) | |
3063 | { | |
3064 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3065 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3066 | MemoryRegion *mr; |
3067 | uint64_t size; | |
c871bc70 LV |
3068 | char *mem_dev; |
3069 | ||
04790978 TH |
3070 | mr = ddc->get_memory_region(dimm, errp); |
3071 | if (!mr) { | |
3072 | return; | |
3073 | } | |
3074 | size = memory_region_size(mr); | |
3075 | ||
c871bc70 LV |
3076 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3077 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
3078 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
3079 | return; | |
3080 | } | |
3081 | ||
3082 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
3083 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
3084 | error_setg(errp, "Memory backend has bad page size. " | |
3085 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 3086 | goto out; |
c871bc70 | 3087 | } |
8a9e0e7b GK |
3088 | |
3089 | out: | |
3090 | g_free(mem_dev); | |
c871bc70 LV |
3091 | } |
3092 | ||
0cffce56 DG |
3093 | struct sPAPRDIMMState { |
3094 | PCDIMMDevice *dimm; | |
cf632463 | 3095 | uint32_t nr_lmbs; |
0cffce56 DG |
3096 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
3097 | }; | |
3098 | ||
3099 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
3100 | PCDIMMDevice *dimm) | |
3101 | { | |
3102 | sPAPRDIMMState *dimm_state = NULL; | |
3103 | ||
3104 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3105 | if (dimm_state->dimm == dimm) { | |
3106 | break; | |
3107 | } | |
3108 | } | |
3109 | return dimm_state; | |
3110 | } | |
3111 | ||
8d5981c4 BR |
3112 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, |
3113 | uint32_t nr_lmbs, | |
3114 | PCDIMMDevice *dimm) | |
0cffce56 | 3115 | { |
8d5981c4 BR |
3116 | sPAPRDIMMState *ds = NULL; |
3117 | ||
3118 | /* | |
3119 | * If this request is for a DIMM whose removal had failed earlier | |
3120 | * (due to guest's refusal to remove the LMBs), we would have this | |
3121 | * dimm already in the pending_dimm_unplugs list. In that | |
3122 | * case don't add again. | |
3123 | */ | |
3124 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3125 | if (!ds) { | |
3126 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
3127 | ds->nr_lmbs = nr_lmbs; | |
3128 | ds->dimm = dimm; | |
3129 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3130 | } | |
3131 | return ds; | |
0cffce56 DG |
3132 | } |
3133 | ||
3134 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
3135 | sPAPRDIMMState *dimm_state) | |
3136 | { | |
3137 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3138 | g_free(dimm_state); | |
3139 | } | |
cf632463 | 3140 | |
16ee9980 DHB |
3141 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
3142 | PCDIMMDevice *dimm) | |
3143 | { | |
3144 | sPAPRDRConnector *drc; | |
3145 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3146 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
16ee9980 DHB |
3147 | uint64_t size = memory_region_size(mr); |
3148 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3149 | uint32_t avail_lmbs = 0; | |
3150 | uint64_t addr_start, addr; | |
3151 | int i; | |
16ee9980 DHB |
3152 | |
3153 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3154 | &error_abort); | |
3155 | ||
3156 | addr = addr_start; | |
3157 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3158 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3159 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3160 | g_assert(drc); |
454b580a | 3161 | if (drc->dev) { |
16ee9980 DHB |
3162 | avail_lmbs++; |
3163 | } | |
3164 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3165 | } | |
3166 | ||
8d5981c4 | 3167 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3168 | } |
3169 | ||
31834723 DHB |
3170 | /* Callback to be called during DRC release. */ |
3171 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3172 | { |
765d1bdd DG |
3173 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); |
3174 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3175 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3176 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
0cffce56 | 3177 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 3178 | |
16ee9980 DHB |
3179 | /* This information will get lost if a migration occurs |
3180 | * during the unplug process. In this case recover it. */ | |
3181 | if (ds == NULL) { | |
3182 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3183 | g_assert(ds); |
454b580a DG |
3184 | /* The DRC being examined by the caller at least must be counted */ |
3185 | g_assert(ds->nr_lmbs); | |
3186 | } | |
3187 | ||
3188 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3189 | return; |
3190 | } | |
3191 | ||
cf632463 BR |
3192 | /* |
3193 | * Now that all the LMBs have been removed by the guest, call the | |
3194 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
3195 | */ | |
765d1bdd | 3196 | pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); |
cf632463 | 3197 | object_unparent(OBJECT(dev)); |
2a129767 | 3198 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3199 | } |
3200 | ||
3201 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3202 | DeviceState *dev, Error **errp) | |
3203 | { | |
0cffce56 | 3204 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3205 | Error *local_err = NULL; |
3206 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3207 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3208 | MemoryRegion *mr; |
3209 | uint32_t nr_lmbs; | |
3210 | uint64_t size, addr_start, addr; | |
0cffce56 DG |
3211 | int i; |
3212 | sPAPRDRConnector *drc; | |
04790978 TH |
3213 | |
3214 | mr = ddc->get_memory_region(dimm, &local_err); | |
3215 | if (local_err) { | |
3216 | goto out; | |
3217 | } | |
3218 | size = memory_region_size(mr); | |
3219 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3220 | ||
9ed442b8 | 3221 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3222 | &local_err); |
cf632463 BR |
3223 | if (local_err) { |
3224 | goto out; | |
3225 | } | |
3226 | ||
2a129767 DHB |
3227 | /* |
3228 | * An existing pending dimm state for this DIMM means that there is an | |
3229 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3230 | * callback to complete the job (BQL can't cover that far). In this case, | |
3231 | * bail out to avoid detaching DRCs that were already released. | |
3232 | */ | |
3233 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3234 | error_setg(&local_err, | |
3235 | "Memory unplug already in progress for device %s", | |
3236 | dev->id); | |
3237 | goto out; | |
3238 | } | |
3239 | ||
8d5981c4 | 3240 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3241 | |
3242 | addr = addr_start; | |
3243 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3244 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3245 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3246 | g_assert(drc); |
3247 | ||
a8dc47fd | 3248 | spapr_drc_detach(drc); |
0cffce56 DG |
3249 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3250 | } | |
3251 | ||
fbf55397 DG |
3252 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3253 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3254 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3255 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3256 | out: |
3257 | error_propagate(errp, local_err); | |
3258 | } | |
3259 | ||
04d0ffbd GK |
3260 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
3261 | sPAPRMachineState *spapr) | |
af81cf32 BR |
3262 | { |
3263 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3264 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 3265 | int id = spapr_get_vcpu_id(cpu); |
af81cf32 BR |
3266 | void *fdt; |
3267 | int offset, fdt_size; | |
3268 | char *nodename; | |
3269 | ||
3270 | fdt = create_device_tree(&fdt_size); | |
3271 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3272 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3273 | ||
3274 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
3275 | g_free(nodename); | |
3276 | ||
3277 | *fdt_offset = offset; | |
3278 | return fdt; | |
3279 | } | |
3280 | ||
765d1bdd DG |
3281 | /* Callback to be called during DRC release. */ |
3282 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3283 | { |
765d1bdd | 3284 | MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); |
46f7afa3 | 3285 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3286 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3287 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3288 | |
46f7afa3 GK |
3289 | if (smc->pre_2_10_has_unused_icps) { |
3290 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
46f7afa3 GK |
3291 | int i; |
3292 | ||
3293 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3294 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3295 | |
3296 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3297 | } | |
3298 | } | |
3299 | ||
07572c06 | 3300 | assert(core_slot); |
535455fd | 3301 | core_slot->cpu = NULL; |
ff9006dd IM |
3302 | object_unparent(OBJECT(dev)); |
3303 | } | |
3304 | ||
115debf2 IM |
3305 | static |
3306 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3307 | Error **errp) | |
ff9006dd | 3308 | { |
72194664 | 3309 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
535455fd IM |
3310 | int index; |
3311 | sPAPRDRConnector *drc; | |
535455fd | 3312 | CPUCore *cc = CPU_CORE(dev); |
ff9006dd | 3313 | |
535455fd IM |
3314 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3315 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3316 | cc->core_id); | |
3317 | return; | |
3318 | } | |
ff9006dd IM |
3319 | if (index == 0) { |
3320 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3321 | return; | |
3322 | } | |
3323 | ||
5d0fb150 GK |
3324 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3325 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd IM |
3326 | g_assert(drc); |
3327 | ||
a8dc47fd | 3328 | spapr_drc_detach(drc); |
ff9006dd IM |
3329 | |
3330 | spapr_hotplug_req_remove_by_index(drc); | |
3331 | } | |
3332 | ||
3333 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3334 | Error **errp) | |
3335 | { | |
3336 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3337 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3338 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3339 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3340 | CPUCore *cc = CPU_CORE(dev); | |
94ad93bd | 3341 | CPUState *cs = CPU(core->threads[0]); |
ff9006dd IM |
3342 | sPAPRDRConnector *drc; |
3343 | Error *local_err = NULL; | |
535455fd IM |
3344 | CPUArchId *core_slot; |
3345 | int index; | |
94fd9cba | 3346 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3347 | |
535455fd IM |
3348 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3349 | if (!core_slot) { | |
3350 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3351 | cc->core_id); | |
3352 | return; | |
3353 | } | |
5d0fb150 GK |
3354 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3355 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd | 3356 | |
c5514d0e | 3357 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3358 | |
ff9006dd | 3359 | if (drc) { |
e49c63d5 GK |
3360 | void *fdt; |
3361 | int fdt_offset; | |
3362 | ||
3363 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3364 | ||
5c1da812 | 3365 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3366 | if (local_err) { |
3367 | g_free(fdt); | |
ff9006dd IM |
3368 | error_propagate(errp, local_err); |
3369 | return; | |
3370 | } | |
ff9006dd | 3371 | |
94fd9cba LV |
3372 | if (hotplugged) { |
3373 | /* | |
3374 | * Send hotplug notification interrupt to the guest only | |
3375 | * in case of hotplugged CPUs. | |
3376 | */ | |
3377 | spapr_hotplug_req_add_by_index(drc); | |
3378 | } else { | |
3379 | spapr_drc_reset(drc); | |
3380 | } | |
ff9006dd | 3381 | } |
94fd9cba | 3382 | |
535455fd | 3383 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3384 | |
3385 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 GK |
3386 | int i; |
3387 | ||
3388 | for (i = 0; i < cc->nr_threads; i++) { | |
bc877283 | 3389 | cs = CPU(core->threads[i]); |
46f7afa3 GK |
3390 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3391 | } | |
3392 | } | |
ff9006dd IM |
3393 | } |
3394 | ||
3395 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3396 | Error **errp) | |
3397 | { | |
3398 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3399 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3400 | Error *local_err = NULL; |
3401 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3402 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3403 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3404 | CPUArchId *core_slot; |
3405 | int index; | |
ff9006dd | 3406 | |
c5514d0e | 3407 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3408 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3409 | goto out; | |
3410 | } | |
3411 | ||
3412 | if (strcmp(base_core_type, type)) { | |
3413 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3414 | goto out; | |
3415 | } | |
3416 | ||
3417 | if (cc->core_id % smp_threads) { | |
3418 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3419 | goto out; | |
3420 | } | |
3421 | ||
459264ef DG |
3422 | /* |
3423 | * In general we should have homogeneous threads-per-core, but old | |
3424 | * (pre hotplug support) machine types allow the last core to have | |
3425 | * reduced threads as a compatibility hack for when we allowed | |
3426 | * total vcpus not a multiple of threads-per-core. | |
3427 | */ | |
3428 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3429 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3430 | cc->nr_threads, smp_threads); |
df8658de | 3431 | goto out; |
8149e299 DG |
3432 | } |
3433 | ||
535455fd IM |
3434 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3435 | if (!core_slot) { | |
ff9006dd IM |
3436 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3437 | goto out; | |
3438 | } | |
3439 | ||
535455fd | 3440 | if (core_slot->cpu) { |
ff9006dd IM |
3441 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3442 | goto out; | |
3443 | } | |
3444 | ||
a0ceb640 | 3445 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3446 | |
ff9006dd | 3447 | out: |
ff9006dd IM |
3448 | error_propagate(errp, local_err); |
3449 | } | |
3450 | ||
c20d332a BR |
3451 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3452 | DeviceState *dev, Error **errp) | |
3453 | { | |
c86c1aff DHB |
3454 | MachineState *ms = MACHINE(hotplug_dev); |
3455 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); | |
c20d332a BR |
3456 | |
3457 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 3458 | int node; |
c20d332a BR |
3459 | |
3460 | if (!smc->dr_lmb_enabled) { | |
3461 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3462 | return; | |
3463 | } | |
9ed442b8 | 3464 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); |
c20d332a BR |
3465 | if (*errp) { |
3466 | return; | |
3467 | } | |
1a5512bb GA |
3468 | if (node < 0 || node >= MAX_NODES) { |
3469 | error_setg(errp, "Invaild node %d", node); | |
3470 | return; | |
3471 | } | |
c20d332a | 3472 | |
b556854b BR |
3473 | /* |
3474 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
3475 | * memory-less node, but instead will silently add the memory | |
3476 | * to the first node that has some memory. This causes two | |
3477 | * unexpected behaviours for the user. | |
3478 | * | |
3479 | * - Memory gets hotplugged to a different node than what the user | |
3480 | * specified. | |
3481 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
3482 | * to memory-less node, a reboot will set things accordingly | |
3483 | * and the previously hotplugged memory now ends in the right node. | |
3484 | * This appears as if some memory moved from one node to another. | |
3485 | * | |
3486 | * So until kernel starts supporting memory hotplug to memory-less | |
3487 | * nodes, just prevent such attempts upfront in QEMU. | |
3488 | */ | |
3489 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
3490 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
3491 | node); | |
3492 | return; | |
3493 | } | |
3494 | ||
c20d332a | 3495 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
3496 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3497 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3498 | } |
3499 | } | |
3500 | ||
cf632463 BR |
3501 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3502 | DeviceState *dev, Error **errp) | |
3503 | { | |
c86c1aff DHB |
3504 | sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3505 | MachineClass *mc = MACHINE_GET_CLASS(sms); | |
cf632463 BR |
3506 | |
3507 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3508 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3509 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3510 | } else { | |
3511 | /* NOTE: this means there is a window after guest reset, prior to | |
3512 | * CAS negotiation, where unplug requests will fail due to the | |
3513 | * capability not being detected yet. This is a bit different than | |
3514 | * the case with PCI unplug, where the events will be queued and | |
3515 | * eventually handled by the guest after boot | |
3516 | */ | |
3517 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3518 | } | |
6f4b5c3e | 3519 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3520 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3521 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3522 | return; | |
3523 | } | |
115debf2 | 3524 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3525 | } |
3526 | } | |
3527 | ||
94a94e4c BR |
3528 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3529 | DeviceState *dev, Error **errp) | |
3530 | { | |
c871bc70 LV |
3531 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3532 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3533 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3534 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3535 | } | |
3536 | } | |
3537 | ||
7ebaf795 BR |
3538 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3539 | DeviceState *dev) | |
c20d332a | 3540 | { |
94a94e4c BR |
3541 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3542 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3543 | return HOTPLUG_HANDLER(machine); |
3544 | } | |
3545 | return NULL; | |
3546 | } | |
3547 | ||
ea089eeb IM |
3548 | static CpuInstanceProperties |
3549 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3550 | { |
ea089eeb IM |
3551 | CPUArchId *core_slot; |
3552 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3553 | ||
3554 | /* make sure possible_cpu are intialized */ | |
3555 | mc->possible_cpu_arch_ids(machine); | |
3556 | /* get CPU core slot containing thread that matches cpu_index */ | |
3557 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3558 | assert(core_slot); | |
3559 | return core_slot->props; | |
20bb648d DG |
3560 | } |
3561 | ||
79e07936 IM |
3562 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
3563 | { | |
3564 | return idx / smp_cores % nb_numa_nodes; | |
3565 | } | |
3566 | ||
535455fd IM |
3567 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3568 | { | |
3569 | int i; | |
d342eb76 | 3570 | const char *core_type; |
535455fd IM |
3571 | int spapr_max_cores = max_cpus / smp_threads; |
3572 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3573 | ||
c5514d0e | 3574 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3575 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3576 | } | |
3577 | if (machine->possible_cpus) { | |
3578 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3579 | return machine->possible_cpus; | |
3580 | } | |
3581 | ||
d342eb76 IM |
3582 | core_type = spapr_get_cpu_core_type(machine->cpu_type); |
3583 | if (!core_type) { | |
3584 | error_report("Unable to find sPAPR CPU Core definition"); | |
3585 | exit(1); | |
3586 | } | |
3587 | ||
535455fd IM |
3588 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
3589 | sizeof(CPUArchId) * spapr_max_cores); | |
3590 | machine->possible_cpus->len = spapr_max_cores; | |
3591 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3592 | int core_id = i * smp_threads; | |
3593 | ||
d342eb76 | 3594 | machine->possible_cpus->cpus[i].type = core_type; |
f2d672c2 | 3595 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3596 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3597 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3598 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
3599 | } |
3600 | return machine->possible_cpus; | |
3601 | } | |
3602 | ||
6737d9ad | 3603 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3604 | uint64_t *buid, hwaddr *pio, |
3605 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3606 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3607 | { | |
357d1e3b DG |
3608 | /* |
3609 | * New-style PHB window placement. | |
3610 | * | |
3611 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3612 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3613 | * windows. | |
3614 | * | |
3615 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3616 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3617 | * | |
3618 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3619 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3620 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3621 | * 1TiB 64-bit MMIO windows for each PHB. | |
3622 | */ | |
6737d9ad | 3623 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3624 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3625 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3626 | int i; |
3627 | ||
357d1e3b DG |
3628 | /* Sanity check natural alignments */ |
3629 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3630 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3631 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3632 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3633 | /* Sanity check bounds */ | |
25e6a118 MT |
3634 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3635 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3636 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3637 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3638 | ||
3639 | if (index >= SPAPR_MAX_PHBS) { | |
3640 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3641 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3642 | return; |
3643 | } | |
3644 | ||
3645 | *buid = base_buid + index; | |
3646 | for (i = 0; i < n_dma; ++i) { | |
3647 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3648 | } | |
3649 | ||
357d1e3b DG |
3650 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3651 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3652 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3653 | } |
3654 | ||
7844e12b CLG |
3655 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3656 | { | |
3657 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3658 | ||
3659 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3660 | } | |
3661 | ||
3662 | static void spapr_ics_resend(XICSFabric *dev) | |
3663 | { | |
3664 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3665 | ||
3666 | ics_resend(spapr->ics); | |
3667 | } | |
3668 | ||
81210c20 | 3669 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 3670 | { |
2e886fb3 | 3671 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 3672 | |
5bc8d26d | 3673 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3674 | } |
3675 | ||
60c6823b CLG |
3676 | #define ICS_IRQ_FREE(ics, srcno) \ |
3677 | (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) | |
3678 | ||
3679 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) | |
3680 | { | |
3681 | int first, i; | |
3682 | ||
3683 | for (first = 0; first < ics->nr_irqs; first += alignnum) { | |
3684 | if (num > (ics->nr_irqs - first)) { | |
3685 | return -1; | |
3686 | } | |
3687 | for (i = first; i < first + num; ++i) { | |
3688 | if (!ICS_IRQ_FREE(ics, i)) { | |
3689 | break; | |
3690 | } | |
3691 | } | |
3692 | if (i == (first + num)) { | |
3693 | return first; | |
3694 | } | |
3695 | } | |
3696 | ||
3697 | return -1; | |
3698 | } | |
3699 | ||
9e7dc5fc CLG |
3700 | /* |
3701 | * Allocate the IRQ number and set the IRQ type, LSI or MSI | |
3702 | */ | |
3703 | static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) | |
3704 | { | |
3705 | ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); | |
3706 | } | |
3707 | ||
60c6823b CLG |
3708 | int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, |
3709 | Error **errp) | |
3710 | { | |
3711 | ICSState *ics = spapr->ics; | |
3712 | int irq; | |
3713 | ||
3714 | if (!ics) { | |
3715 | return -1; | |
3716 | } | |
3717 | if (irq_hint) { | |
3718 | if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { | |
3719 | error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); | |
3720 | return -1; | |
3721 | } | |
3722 | irq = irq_hint; | |
3723 | } else { | |
3724 | irq = ics_find_free_block(ics, 1, 1); | |
3725 | if (irq < 0) { | |
3726 | error_setg(errp, "can't allocate IRQ: no IRQ left"); | |
3727 | return -1; | |
3728 | } | |
3729 | irq += ics->offset; | |
3730 | } | |
3731 | ||
9e7dc5fc | 3732 | spapr_irq_set_lsi(spapr, irq, lsi); |
60c6823b CLG |
3733 | trace_spapr_irq_alloc(irq); |
3734 | ||
3735 | return irq; | |
3736 | } | |
3737 | ||
3738 | /* | |
3739 | * Allocate block of consecutive IRQs, and return the number of the first IRQ in | |
3740 | * the block. If align==true, aligns the first IRQ number to num. | |
3741 | */ | |
3742 | int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, | |
3743 | bool align, Error **errp) | |
3744 | { | |
3745 | ICSState *ics = spapr->ics; | |
3746 | int i, first = -1; | |
3747 | ||
3748 | if (!ics) { | |
3749 | return -1; | |
3750 | } | |
3751 | ||
3752 | /* | |
3753 | * MSIMesage::data is used for storing VIRQ so | |
3754 | * it has to be aligned to num to support multiple | |
3755 | * MSI vectors. MSI-X is not affected by this. | |
3756 | * The hint is used for the first IRQ, the rest should | |
3757 | * be allocated continuously. | |
3758 | */ | |
3759 | if (align) { | |
3760 | assert((num == 1) || (num == 2) || (num == 4) || | |
3761 | (num == 8) || (num == 16) || (num == 32)); | |
3762 | first = ics_find_free_block(ics, num, num); | |
3763 | } else { | |
3764 | first = ics_find_free_block(ics, num, 1); | |
3765 | } | |
3766 | if (first < 0) { | |
3767 | error_setg(errp, "can't find a free %d-IRQ block", num); | |
3768 | return -1; | |
3769 | } | |
3770 | ||
9e7dc5fc | 3771 | first += ics->offset; |
60c6823b | 3772 | for (i = first; i < first + num; ++i) { |
9e7dc5fc | 3773 | spapr_irq_set_lsi(spapr, i, lsi); |
60c6823b | 3774 | } |
60c6823b CLG |
3775 | |
3776 | trace_spapr_irq_alloc_block(first, num, lsi, align); | |
3777 | ||
3778 | return first; | |
3779 | } | |
3780 | ||
3781 | void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) | |
3782 | { | |
3783 | ICSState *ics = spapr->ics; | |
3784 | int srcno = irq - ics->offset; | |
3785 | int i; | |
3786 | ||
3787 | if (ics_valid_irq(ics, irq)) { | |
3788 | trace_spapr_irq_free(0, irq, num); | |
3789 | for (i = srcno; i < srcno + num; ++i) { | |
3790 | if (ICS_IRQ_FREE(ics, i)) { | |
3791 | trace_spapr_irq_free_warn(0, i + ics->offset); | |
3792 | } | |
3793 | memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); | |
3794 | } | |
3795 | } | |
3796 | } | |
3797 | ||
77183755 CLG |
3798 | qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) |
3799 | { | |
3800 | ICSState *ics = spapr->ics; | |
3801 | ||
3802 | if (ics_valid_irq(ics, irq)) { | |
3803 | return ics->qirqs[irq - ics->offset]; | |
3804 | } | |
3805 | ||
3806 | return NULL; | |
3807 | } | |
3808 | ||
6449da45 CLG |
3809 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3810 | Monitor *mon) | |
3811 | { | |
3812 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3813 | CPUState *cs; |
3814 | ||
3815 | CPU_FOREACH(cs) { | |
3816 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3817 | |
5bc8d26d | 3818 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3819 | } |
3820 | ||
3821 | ics_pic_print_info(spapr->ics, mon); | |
3822 | } | |
3823 | ||
14bb4486 | 3824 | int spapr_get_vcpu_id(PowerPCCPU *cpu) |
2e886fb3 | 3825 | { |
b1a568c1 | 3826 | return cpu->vcpu_id; |
2e886fb3 SB |
3827 | } |
3828 | ||
648edb64 GK |
3829 | void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) |
3830 | { | |
3831 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
3832 | int vcpu_id; | |
3833 | ||
5d0fb150 | 3834 | vcpu_id = spapr_vcpu_id(spapr, cpu_index); |
648edb64 GK |
3835 | |
3836 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { | |
3837 | error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); | |
3838 | error_append_hint(errp, "Adjust the number of cpus to %d " | |
3839 | "or try to raise the number of threads per core\n", | |
3840 | vcpu_id * smp_threads / spapr->vsmt); | |
3841 | return; | |
3842 | } | |
3843 | ||
3844 | cpu->vcpu_id = vcpu_id; | |
3845 | } | |
3846 | ||
2e886fb3 SB |
3847 | PowerPCCPU *spapr_find_cpu(int vcpu_id) |
3848 | { | |
3849 | CPUState *cs; | |
3850 | ||
3851 | CPU_FOREACH(cs) { | |
3852 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3853 | ||
14bb4486 | 3854 | if (spapr_get_vcpu_id(cpu) == vcpu_id) { |
2e886fb3 SB |
3855 | return cpu; |
3856 | } | |
3857 | } | |
3858 | ||
3859 | return NULL; | |
3860 | } | |
3861 | ||
29ee3247 AK |
3862 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3863 | { | |
3864 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3865 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3866 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3867 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3868 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3869 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3870 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3871 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3872 | |
0eb9054c | 3873 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3874 | |
3875 | /* | |
3876 | * We set up the default / latest behaviour here. The class_init | |
3877 | * functions for the specific versioned machine types can override | |
3878 | * these details for backwards compatibility | |
3879 | */ | |
bcb5ce08 DG |
3880 | mc->init = spapr_machine_init; |
3881 | mc->reset = spapr_machine_reset; | |
958db90c | 3882 | mc->block_default_type = IF_SCSI; |
6244bb7e | 3883 | mc->max_cpus = 1024; |
958db90c | 3884 | mc->no_parallel = 1; |
5b2128d2 | 3885 | mc->default_boot_order = ""; |
a34944fe | 3886 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 3887 | mc->kvm_type = spapr_kvm_type; |
7da79a16 | 3888 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); |
e4024630 | 3889 | mc->pci_allow_0_address = true; |
7ebaf795 | 3890 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3891 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 3892 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 3893 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 3894 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 3895 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3896 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 3897 | |
fc9f38c3 | 3898 | smc->dr_lmb_enabled = true; |
2e9c10eb | 3899 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
c5514d0e | 3900 | mc->has_hotpluggable_cpus = true; |
52b81ab5 | 3901 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 3902 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3903 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3904 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3905 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3906 | vhc->hpt_mask = spapr_hpt_mask; |
3907 | vhc->map_hptes = spapr_map_hptes; | |
3908 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3909 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3910 | vhc->get_patbe = spapr_get_patbe; |
1ec26c75 | 3911 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
7844e12b CLG |
3912 | xic->ics_get = spapr_ics_get; |
3913 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3914 | xic->icp_get = spapr_icp_get; |
6449da45 | 3915 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3916 | /* Force NUMA node memory size to be a multiple of |
3917 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3918 | * in which LMBs are represented and hot-added | |
3919 | */ | |
3920 | mc->numa_mem_align_shift = 28; | |
33face6b | 3921 | |
4e5fe368 SJS |
3922 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
3923 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; | |
3924 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; | |
8f38eaf8 | 3925 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
09114fd8 | 3926 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; |
4be8d4e7 | 3927 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; |
33face6b | 3928 | spapr_caps_add_properties(smc, &error_abort); |
29ee3247 AK |
3929 | } |
3930 | ||
3931 | static const TypeInfo spapr_machine_info = { | |
3932 | .name = TYPE_SPAPR_MACHINE, | |
3933 | .parent = TYPE_MACHINE, | |
4aee7362 | 3934 | .abstract = true, |
6ca1502e | 3935 | .instance_size = sizeof(sPAPRMachineState), |
bcb5ce08 | 3936 | .instance_init = spapr_instance_init, |
87bbdd9c | 3937 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3938 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3939 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3940 | .interfaces = (InterfaceInfo[]) { |
3941 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3942 | { TYPE_NMI }, |
c20d332a | 3943 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3944 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3945 | { TYPE_XICS_FABRIC }, |
6449da45 | 3946 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3947 | { } |
3948 | }, | |
29ee3247 AK |
3949 | }; |
3950 | ||
fccbc785 | 3951 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3952 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3953 | void *data) \ | |
3954 | { \ | |
3955 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3956 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3957 | if (latest) { \ |
3958 | mc->alias = "pseries"; \ | |
3959 | mc->is_default = 1; \ | |
3960 | } \ | |
5013c547 DG |
3961 | } \ |
3962 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
3963 | { \ | |
3964 | MachineState *machine = MACHINE(obj); \ | |
3965 | spapr_machine_##suffix##_instance_options(machine); \ | |
3966 | } \ | |
3967 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
3968 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3969 | .parent = TYPE_SPAPR_MACHINE, \ | |
3970 | .class_init = spapr_machine_##suffix##_class_init, \ | |
3971 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
3972 | }; \ | |
3973 | static void spapr_machine_register_##suffix(void) \ | |
3974 | { \ | |
3975 | type_register(&spapr_machine_##suffix##_info); \ | |
3976 | } \ | |
0e6aac87 | 3977 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3978 | |
2b615412 DG |
3979 | /* |
3980 | * pseries-2.12 | |
3981 | */ | |
3982 | static void spapr_machine_2_12_instance_options(MachineState *machine) | |
3983 | { | |
3984 | } | |
3985 | ||
3986 | static void spapr_machine_2_12_class_options(MachineClass *mc) | |
3987 | { | |
3988 | /* Defaults for the latest behaviour inherited from the base class */ | |
3989 | } | |
3990 | ||
3991 | DEFINE_SPAPR_MACHINE(2_12, "2.12", true); | |
3992 | ||
813f3cf6 SJS |
3993 | static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) |
3994 | { | |
3995 | spapr_machine_2_12_instance_options(machine); | |
3996 | } | |
3997 | ||
3998 | static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) | |
3999 | { | |
4000 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); | |
4001 | ||
4002 | spapr_machine_2_12_class_options(mc); | |
4003 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; | |
4004 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; | |
4005 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; | |
4006 | } | |
4007 | ||
4008 | DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); | |
4009 | ||
e2676b16 GK |
4010 | /* |
4011 | * pseries-2.11 | |
4012 | */ | |
2b615412 DG |
4013 | #define SPAPR_COMPAT_2_11 \ |
4014 | HW_COMPAT_2_11 | |
4015 | ||
e2676b16 GK |
4016 | static void spapr_machine_2_11_instance_options(MachineState *machine) |
4017 | { | |
2b615412 | 4018 | spapr_machine_2_12_instance_options(machine); |
e2676b16 GK |
4019 | } |
4020 | ||
4021 | static void spapr_machine_2_11_class_options(MachineClass *mc) | |
4022 | { | |
ee76a09f DG |
4023 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4024 | ||
2b615412 | 4025 | spapr_machine_2_12_class_options(mc); |
4e5fe368 | 4026 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
2b615412 | 4027 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); |
e2676b16 GK |
4028 | } |
4029 | ||
2b615412 | 4030 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 4031 | |
3fa14fbe DG |
4032 | /* |
4033 | * pseries-2.10 | |
4034 | */ | |
e2676b16 | 4035 | #define SPAPR_COMPAT_2_10 \ |
2b615412 | 4036 | HW_COMPAT_2_10 |
e2676b16 | 4037 | |
3fa14fbe DG |
4038 | static void spapr_machine_2_10_instance_options(MachineState *machine) |
4039 | { | |
2b615412 | 4040 | spapr_machine_2_11_instance_options(machine); |
3fa14fbe DG |
4041 | } |
4042 | ||
4043 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
4044 | { | |
e2676b16 GK |
4045 | spapr_machine_2_11_class_options(mc); |
4046 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); | |
3fa14fbe DG |
4047 | } |
4048 | ||
e2676b16 | 4049 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 4050 | |
fa325e6c DG |
4051 | /* |
4052 | * pseries-2.9 | |
4053 | */ | |
3fa14fbe | 4054 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
4055 | HW_COMPAT_2_9 \ |
4056 | { \ | |
4057 | .driver = TYPE_POWERPC_CPU, \ | |
4058 | .property = "pre-2.10-migration", \ | |
4059 | .value = "on", \ | |
4060 | }, \ | |
3fa14fbe | 4061 | |
fa325e6c DG |
4062 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
4063 | { | |
3fa14fbe | 4064 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
4065 | } |
4066 | ||
4067 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
4068 | { | |
46f7afa3 GK |
4069 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4070 | ||
3fa14fbe DG |
4071 | spapr_machine_2_10_class_options(mc); |
4072 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 4073 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 4074 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 4075 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
4076 | } |
4077 | ||
3fa14fbe | 4078 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 4079 | |
db800b21 DG |
4080 | /* |
4081 | * pseries-2.8 | |
4082 | */ | |
82516263 DG |
4083 | #define SPAPR_COMPAT_2_8 \ |
4084 | HW_COMPAT_2_8 \ | |
4085 | { \ | |
4086 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4087 | .property = "pcie-extended-configuration-space", \ | |
4088 | .value = "off", \ | |
4089 | }, | |
fa325e6c | 4090 | |
db800b21 DG |
4091 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
4092 | { | |
fa325e6c | 4093 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
4094 | } |
4095 | ||
4096 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
4097 | { | |
fa325e6c DG |
4098 | spapr_machine_2_9_class_options(mc); |
4099 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 4100 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
4101 | } |
4102 | ||
fa325e6c | 4103 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 4104 | |
1ea1eefc BR |
4105 | /* |
4106 | * pseries-2.7 | |
4107 | */ | |
357d1e3b DG |
4108 | #define SPAPR_COMPAT_2_7 \ |
4109 | HW_COMPAT_2_7 \ | |
4110 | { \ | |
4111 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4112 | .property = "mem_win_size", \ | |
4113 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
4114 | }, \ | |
4115 | { \ | |
4116 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4117 | .property = "mem64_win_size", \ | |
4118 | .value = "0", \ | |
146c11f1 DG |
4119 | }, \ |
4120 | { \ | |
4121 | .driver = TYPE_POWERPC_CPU, \ | |
4122 | .property = "pre-2.8-migration", \ | |
4123 | .value = "on", \ | |
5c4537bd DG |
4124 | }, \ |
4125 | { \ | |
4126 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4127 | .property = "pre-2.8-migration", \ | |
4128 | .value = "on", \ | |
357d1e3b DG |
4129 | }, |
4130 | ||
4131 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
4132 | uint64_t *buid, hwaddr *pio, | |
4133 | hwaddr *mmio32, hwaddr *mmio64, | |
4134 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
4135 | { | |
4136 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4137 | const uint64_t base_buid = 0x800000020000000ULL; | |
4138 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4139 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4140 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4141 | const uint32_t max_index = 255; | |
4142 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4143 | ||
4144 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4145 | hwaddr phb0_base, phb_base; | |
4146 | int i; | |
4147 | ||
4148 | /* Do we have hotpluggable memory? */ | |
4149 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
4150 | /* Can't just use maxram_size, because there may be an | |
4151 | * alignment gap between normal and hotpluggable memory | |
4152 | * regions */ | |
4153 | ram_top = spapr->hotplug_memory.base + | |
4154 | memory_region_size(&spapr->hotplug_memory.mr); | |
4155 | } | |
4156 | ||
4157 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4158 | ||
4159 | if (index > max_index) { | |
4160 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4161 | max_index); | |
4162 | return; | |
4163 | } | |
4164 | ||
4165 | *buid = base_buid + index; | |
4166 | for (i = 0; i < n_dma; ++i) { | |
4167 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4168 | } | |
4169 | ||
4170 | phb_base = phb0_base + index * phb_spacing; | |
4171 | *pio = phb_base + pio_offset; | |
4172 | *mmio32 = phb_base + mmio_offset; | |
4173 | /* | |
4174 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4175 | * fallback behaviour of automatically splitting a large "32-bit" | |
4176 | * window into contiguous 32-bit and 64-bit windows | |
4177 | */ | |
4178 | } | |
db800b21 | 4179 | |
1ea1eefc BR |
4180 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
4181 | { | |
f6229214 MR |
4182 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
4183 | ||
672de881 | 4184 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 4185 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
4186 | } |
4187 | ||
4188 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
4189 | { | |
3daa4a9f TH |
4190 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4191 | ||
db800b21 | 4192 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4193 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
db800b21 | 4194 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 4195 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4196 | } |
4197 | ||
db800b21 | 4198 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4199 | |
4b23699c DG |
4200 | /* |
4201 | * pseries-2.6 | |
4202 | */ | |
1ea1eefc | 4203 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
4204 | HW_COMPAT_2_6 \ |
4205 | { \ | |
4206 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4207 | .property = "ddw",\ | |
4208 | .value = stringify(off),\ | |
4209 | }, | |
1ea1eefc | 4210 | |
4b23699c DG |
4211 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
4212 | { | |
672de881 | 4213 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
4214 | } |
4215 | ||
4216 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
4217 | { | |
1ea1eefc | 4218 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4219 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 4220 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
4221 | } |
4222 | ||
1ea1eefc | 4223 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4224 | |
1c5f29bb DG |
4225 | /* |
4226 | * pseries-2.5 | |
4227 | */ | |
4b23699c | 4228 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
4229 | HW_COMPAT_2_5 \ |
4230 | { \ | |
4231 | .driver = "spapr-vlan", \ | |
4232 | .property = "use-rx-buffer-pools", \ | |
4233 | .value = "off", \ | |
4234 | }, | |
4b23699c | 4235 | |
5013c547 | 4236 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 4237 | { |
672de881 | 4238 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
4239 | } |
4240 | ||
4241 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
4242 | { | |
57040d45 TH |
4243 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4244 | ||
4b23699c | 4245 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4246 | smc->use_ohci_by_default = true; |
4b23699c | 4247 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
4248 | } |
4249 | ||
4b23699c | 4250 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4251 | |
4252 | /* | |
4253 | * pseries-2.4 | |
4254 | */ | |
80fd50f9 CH |
4255 | #define SPAPR_COMPAT_2_4 \ |
4256 | HW_COMPAT_2_4 | |
4257 | ||
5013c547 | 4258 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 4259 | { |
5013c547 DG |
4260 | spapr_machine_2_5_instance_options(machine); |
4261 | } | |
1c5f29bb | 4262 | |
5013c547 DG |
4263 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4264 | { | |
fc9f38c3 DG |
4265 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4266 | ||
4267 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4268 | smc->dr_lmb_enabled = false; |
f949b4e5 | 4269 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
4270 | } |
4271 | ||
fccbc785 | 4272 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4273 | |
4274 | /* | |
4275 | * pseries-2.3 | |
4276 | */ | |
38ff32c6 | 4277 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
4278 | HW_COMPAT_2_3 \ |
4279 | {\ | |
4280 | .driver = "spapr-pci-host-bridge",\ | |
4281 | .property = "dynamic-reconfiguration",\ | |
4282 | .value = "off",\ | |
4283 | }, | |
38ff32c6 | 4284 | |
5013c547 | 4285 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 4286 | { |
5013c547 | 4287 | spapr_machine_2_4_instance_options(machine); |
d25228e7 JW |
4288 | } |
4289 | ||
5013c547 | 4290 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4291 | { |
fc9f38c3 | 4292 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 4293 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 4294 | } |
fccbc785 | 4295 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4296 | |
1c5f29bb DG |
4297 | /* |
4298 | * pseries-2.2 | |
4299 | */ | |
4300 | ||
4301 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
4302 | HW_COMPAT_2_2 \ |
4303 | {\ | |
4304 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4305 | .property = "mem_win_size",\ | |
4306 | .value = "0x20000000",\ | |
4307 | }, | |
4308 | ||
5013c547 | 4309 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 4310 | { |
5013c547 | 4311 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 4312 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
4313 | } |
4314 | ||
5013c547 | 4315 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4316 | { |
fc9f38c3 | 4317 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 4318 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 4319 | } |
fccbc785 | 4320 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4321 | |
1c5f29bb DG |
4322 | /* |
4323 | * pseries-2.1 | |
4324 | */ | |
4325 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 4326 | HW_COMPAT_2_1 |
3dab0244 | 4327 | |
5013c547 | 4328 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 4329 | { |
5013c547 | 4330 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 4331 | } |
d25228e7 | 4332 | |
5013c547 | 4333 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4334 | { |
fc9f38c3 | 4335 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 4336 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 4337 | } |
fccbc785 | 4338 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4339 | |
29ee3247 | 4340 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4341 | { |
29ee3247 | 4342 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4343 | } |
4344 | ||
29ee3247 | 4345 | type_init(spapr_machine_register_types) |