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Revert "spapr: Fix migration of PCI host bridges from qemu-2.7"
[mirror_qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
0d75590d 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
9c17d615 29#include "sysemu/sysemu.h"
e35704ba 30#include "sysemu/numa.h"
83c9f4ca 31#include "hw/hw.h"
03dd024f 32#include "qemu/log.h"
71461b0f 33#include "hw/fw-path-provider.h"
9fdf0c29 34#include "elf.h"
1422e32d 35#include "net/net.h"
ad440b4a 36#include "sysemu/device_tree.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/cpus.h"
39#include "sysemu/kvm.h"
e97c3636 40#include "kvm_ppc.h"
ff14e817 41#include "migration/migration.h"
4be21d56 42#include "mmu-hash64.h"
3794d548 43#include "qom/cpu.h"
9fdf0c29
DG		 44
45#include "hw/boards.h"
0d09e41a 46#include "hw/ppc/ppc.h"
9fdf0c29
DG		 47#include "hw/loader.h"
48
7804c353 49#include "hw/ppc/fdt.h"
0d09e41a
PB		 50#include "hw/ppc/spapr.h"
51#include "hw/ppc/spapr_vio.h"
52#include "hw/pci-host/spapr.h"
53#include "hw/ppc/xics.h"
a2cb15b0 54#include "hw/pci/msi.h"
9fdf0c29 55
83c9f4ca 56#include "hw/pci/pci.h"
71461b0f
AK		 57#include "hw/scsi/scsi.h"
58#include "hw/virtio/virtio-scsi.h"
f61b4bed 59
022c62cb 60#include "exec/address-spaces.h"
35139a59 61#include "hw/usb.h"
1de7afc9 62#include "qemu/config-file.h"
135a129a 63#include "qemu/error-report.h"
2a6593cb 64#include "trace.h"
34316482 65#include "hw/nmi.h"
890c2b77 66
68a27b20 67#include "hw/compat.h"
f348b6d1 68#include "qemu/cutils.h"
94a94e4c 69#include "hw/ppc/spapr_cpu_core.h"
2474bfd4 70#include "qmp-commands.h"
68a27b20 71
9fdf0c29
DG		 72#include <libfdt.h>
73
4d8d5467
BH		 74/* SLOF memory layout:
75 *
76 * SLOF raw image loaded at 0, copies its romfs right below the flat
77 * device-tree, then position SLOF itself 31M below that
78 *
79 * So we set FW_OVERHEAD to 40MB which should account for all of that
80 * and more
81 *
82 * We load our kernel at 4M, leaving space for SLOF initial image
83 */
38b02bd8 84#define FDT_MAX_SIZE 0x100000
39ac8455 85#define RTAS_MAX_SIZE 0x10000
b7d1f77a 86#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 87#define FW_MAX_SIZE 0x400000
88#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 89#define FW_OVERHEAD 0x2800000
90#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 91
4d8d5467 92#define MIN_RMA_SLOF 128UL
9fdf0c29 93
0c103f8e
DG		 94#define PHANDLE_XICP 0x00001111
95
7f763a5d
DG		 96#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
c04d6cfa 98static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 99 int nr_irqs, Error **errp)
c04d6cfa 100{
34f2af3d 101 Error *err = NULL;
c04d6cfa
AL		 102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
c04d6cfa
AL		 111 return NULL;
112 }
5a3d7b23 113 return XICS_COMMON(dev);
c04d6cfa
AL		 114}
115
446f16a6 116static XICSState *xics_system_init(MachineState *machine,
1e49182d 117 int nr_servers, int nr_irqs, Error **errp)
c04d6cfa 118{
27f24582 119 XICSState *xics = NULL;
c04d6cfa 120
11ad93f6 121 if (kvm_enabled()) {
34f2af3d
MA		 122 Error *err = NULL;
123
446f16a6 124 if (machine_kernel_irqchip_allowed(machine)) {
27f24582
BH		 125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
126 &err);
11ad93f6 127 }
27f24582 128 if (machine_kernel_irqchip_required(machine) && !xics) {
b83baa60
MA		 129 error_reportf_err(err,
130 "kernel_irqchip requested but unavailable: ");
131 } else {
132 error_free(err);
11ad93f6
DG		 133 }
134 }
135
27f24582
BH		 136 if (!xics) {
137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
c04d6cfa
AL		 138 }
139
27f24582 140 return xics;
c04d6cfa
AL		 141}
142
833d4668
AK		 143static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
144 int smt_threads)
145{
146 int i, ret = 0;
147 uint32_t servers_prop[smt_threads];
148 uint32_t gservers_prop[smt_threads * 2];
149 int index = ppc_get_vcpu_dt_id(cpu);
150
6d9412ea 151 if (cpu->cpu_version) {
4bce526e 152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 153 if (ret < 0) {
154 return ret;
155 }
156 }
157
833d4668
AK		 158 /* Build interrupt servers and gservers properties */
159 for (i = 0; i < smt_threads; i++) {
160 servers_prop[i] = cpu_to_be32(index + i);
161 /* Hack, direct the group queues back to cpu 0 */
162 gservers_prop[i*2] = cpu_to_be32(index + i);
163 gservers_prop[i*2 + 1] = 0;
164 }
165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
166 servers_prop, sizeof(servers_prop));
167 if (ret < 0) {
168 return ret;
169 }
170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
171 gservers_prop, sizeof(gservers_prop));
172
173 return ret;
174}
175
0da6f3fe
BR		 176static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
177{
178 int ret = 0;
179 PowerPCCPU *cpu = POWERPC_CPU(cs);
180 int index = ppc_get_vcpu_dt_id(cpu);
181 uint32_t associativity[] = {cpu_to_be32(0x5),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(0x0),
185 cpu_to_be32(cs->numa_node),
186 cpu_to_be32(index)};
187
188 /* Advertise NUMA via ibm,associativity */
189 if (nb_numa_nodes > 1) {
190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
191 sizeof(associativity));
192 }
193
194 return ret;
195}
196
28e02042 197static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 198{
82677ed2
AK		 199 int ret = 0, offset, cpus_offset;
200 CPUState *cs;
6e806cc3
BR		 201 char cpu_model[32];
202 int smt = kvmppc_smt_threads();
7f763a5d 203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 204
82677ed2
AK		 205 CPU_FOREACH(cs) {
206 PowerPCCPU *cpu = POWERPC_CPU(cs);
207 DeviceClass *dc = DEVICE_GET_CLASS(cs);
208 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 209
0f20ba62 210 if ((index % smt) != 0) {
6e806cc3
BR		 211 continue;
212 }
213
82677ed2 214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 215
82677ed2
AK		 216 cpus_offset = fdt_path_offset(fdt, "/cpus");
217 if (cpus_offset < 0) {
218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
219 "cpus");
220 if (cpus_offset < 0) {
221 return cpus_offset;
222 }
223 }
224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 225 if (offset < 0) {
82677ed2
AK		 226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
227 if (offset < 0) {
228 return offset;
229 }
6e806cc3
BR		 230 }
231
7f763a5d
DG		 232 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
233 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 234 if (ret < 0) {
235 return ret;
236 }
833d4668 237
0da6f3fe
BR		 238 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
239 if (ret < 0) {
240 return ret;
241 }
242
82677ed2 243 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 244 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 245 if (ret < 0) {
246 return ret;
247 }
6e806cc3
BR		 248 }
249 return ret;
250}
251
b082d65a
AK		 252static hwaddr spapr_node0_size(void)
253{
fb164994
DG		 254 MachineState *machine = MACHINE(qdev_get_machine());
255
b082d65a
AK		 256 if (nb_numa_nodes) {
257 int i;
258 for (i = 0; i < nb_numa_nodes; ++i) {
259 if (numa_info[i].node_mem) {
fb164994
DG		 260 return MIN(pow2floor(numa_info[i].node_mem),
261 machine->ram_size);
b082d65a
AK		 262 }
263 }
264 }
fb164994 265 return machine->ram_size;
b082d65a
AK		 266}
267
a1d59c0f
AK		 268static void add_str(GString *s, const gchar *s1)
269{
270 g_string_append_len(s, s1, strlen(s1) + 1);
271}
7f763a5d 272
03d196b7 273static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 274 hwaddr size)
275{
276 uint32_t associativity[] = {
277 cpu_to_be32(0x4), /* length */
278 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 279 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 280 };
281 char mem_name[32];
282 uint64_t mem_reg_property[2];
283 int off;
284
285 mem_reg_property[0] = cpu_to_be64(start);
286 mem_reg_property[1] = cpu_to_be64(size);
287
288 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
289 off = fdt_add_subnode(fdt, 0, mem_name);
290 _FDT(off);
291 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
292 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
293 sizeof(mem_reg_property))));
294 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
295 sizeof(associativity))));
03d196b7 296 return off;
26a8c353
AK		 297}
298
28e02042 299static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 300{
fb164994 301 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 302 hwaddr mem_start, node_size;
303 int i, nb_nodes = nb_numa_nodes;
304 NodeInfo *nodes = numa_info;
305 NodeInfo ramnode;
306
307 /* No NUMA nodes, assume there is just one node with whole RAM */
308 if (!nb_numa_nodes) {
309 nb_nodes = 1;
fb164994 310 ramnode.node_mem = machine->ram_size;
7db8a127 311 nodes = &ramnode;
5fe269b1 312 }
7f763a5d 313
7db8a127
AK		 314 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
315 if (!nodes[i].node_mem) {
316 continue;
317 }
fb164994 318 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 319 node_size = 0;
320 } else {
7db8a127 321 node_size = nodes[i].node_mem;
fb164994
DG		 322 if (node_size > machine->ram_size - mem_start) {
323 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 324 }
325 }
7db8a127
AK		 326 if (!mem_start) {
327 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 328 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 329 mem_start += spapr->rma_size;
330 node_size -= spapr->rma_size;
331 }
6010818c
AK		 332 for ( ; node_size; ) {
333 hwaddr sizetmp = pow2floor(node_size);
334
335 /* mem_start != 0 here */
336 if (ctzl(mem_start) < ctzl(sizetmp)) {
337 sizetmp = 1ULL << ctzl(mem_start);
338 }
339
340 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
341 node_size -= sizetmp;
342 mem_start += sizetmp;
343 }
7f763a5d
DG		 344 }
345
346 return 0;
347}
348
230bf719
TH		 349/* Populate the "ibm,pa-features" property */
350static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
351{
352 uint8_t pa_features_206[] = { 6, 0,
353 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
354 uint8_t pa_features_207[] = { 24, 0,
355 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
356 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
357 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
bac3bf28 358 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
230bf719
TH		 359 uint8_t *pa_features;
360 size_t pa_size;
361
4cbec30d
TH		 362 switch (env->mmu_model) {
363 case POWERPC_MMU_2_06:
364 case POWERPC_MMU_2_06a:
230bf719
TH		 365 pa_features = pa_features_206;
366 pa_size = sizeof(pa_features_206);
4cbec30d
TH		 367 break;
368 case POWERPC_MMU_2_07:
369 case POWERPC_MMU_2_07a:
230bf719
TH		 370 pa_features = pa_features_207;
371 pa_size = sizeof(pa_features_207);
4cbec30d
TH		 372 break;
373 default:
374 return;
230bf719
TH		 375 }
376
377 if (env->ci_large_pages) {
378 /*
379 * Note: we keep CI large pages off by default because a 64K capable
380 * guest provisioned with large pages might otherwise try to map a qemu
381 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
382 * even if that qemu runs on a 4k host.
383 * We dd this bit back here if we are confident this is not an issue
384 */
385 pa_features[3] |= 0x20;
386 }
bac3bf28
TH		 387 if (kvmppc_has_cap_htm() && pa_size > 24) {
388 pa_features[24] |= 0x80; /* Transactional memory support */
389 }
230bf719
TH		 390
391 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
392}
393
0da6f3fe
BR		 394static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
395 sPAPRMachineState *spapr)
396{
397 PowerPCCPU *cpu = POWERPC_CPU(cs);
398 CPUPPCState *env = &cpu->env;
399 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
400 int index = ppc_get_vcpu_dt_id(cpu);
401 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
402 0xffffffff, 0xffffffff};
afd10a0f
BR		 403 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
404 : SPAPR_TIMEBASE_FREQ;
0da6f3fe
BR		 405 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
406 uint32_t page_sizes_prop[64];
407 size_t page_sizes_prop_size;
22419c2a 408 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe 409 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
af81cf32
BR		 410 sPAPRDRConnector *drc;
411 sPAPRDRConnectorClass *drck;
412 int drc_index;
413
414 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
415 if (drc) {
416 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
417 drc_index = drck->get_index(drc);
418 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
419 }
0da6f3fe
BR		 420
421 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
422 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
423
424 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
425 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
426 env->dcache_line_size)));
427 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
428 env->dcache_line_size)));
429 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
430 env->icache_line_size)));
431 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
432 env->icache_line_size)));
433
434 if (pcc->l1_dcache_size) {
435 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
436 pcc->l1_dcache_size)));
437 } else {
ce9863b7 438 error_report("Warning: Unknown L1 dcache size for cpu");
0da6f3fe
BR		 439 }
440 if (pcc->l1_icache_size) {
441 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
442 pcc->l1_icache_size)));
443 } else {
ce9863b7 444 error_report("Warning: Unknown L1 icache size for cpu");
0da6f3fe
BR		 445 }
446
447 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
448 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
fd5da5c4 449 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
0da6f3fe
BR		 450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
451 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
452 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
453
454 if (env->spr_cb[SPR_PURR].oea_read) {
455 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
456 }
457
458 if (env->mmu_model & POWERPC_MMU_1TSEG) {
459 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
460 segs, sizeof(segs))));
461 }
462
463 /* Advertise VMX/VSX (vector extensions) if available
464 * 0 / no property == no vector extensions
465 * 1 == VMX / Altivec available
466 * 2 == VSX available */
467 if (env->insns_flags & PPC_ALTIVEC) {
468 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
469
470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
471 }
472
473 /* Advertise DFP (Decimal Floating Point) if available
474 * 0 / no property == no DFP
475 * 1 == DFP available */
476 if (env->insns_flags2 & PPC2_DFP) {
477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
478 }
479
3654fa95 480 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
0da6f3fe
BR		 481 sizeof(page_sizes_prop));
482 if (page_sizes_prop_size) {
483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
484 page_sizes_prop, page_sizes_prop_size)));
485 }
486
230bf719 487 spapr_populate_pa_features(env, fdt, offset);
90da0d5a 488
0da6f3fe 489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 490 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 491
492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
493 pft_size_prop, sizeof(pft_size_prop))));
494
495 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
496
497 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
498 ppc_get_compat_smt_threads(cpu)));
499}
500
501static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
502{
503 CPUState *cs;
504 int cpus_offset;
505 char *nodename;
506 int smt = kvmppc_smt_threads();
507
508 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
509 _FDT(cpus_offset);
510 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
511 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
512
513 /*
514 * We walk the CPUs in reverse order to ensure that CPU DT nodes
515 * created by fdt_add_subnode() end up in the right order in FDT
516 * for the guest kernel the enumerate the CPUs correctly.
517 */
518 CPU_FOREACH_REVERSE(cs) {
519 PowerPCCPU *cpu = POWERPC_CPU(cs);
520 int index = ppc_get_vcpu_dt_id(cpu);
521 DeviceClass *dc = DEVICE_GET_CLASS(cs);
522 int offset;
523
524 if ((index % smt) != 0) {
525 continue;
526 }
527
528 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
529 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
530 g_free(nodename);
531 _FDT(offset);
532 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
533 }
534
535}
536
03d196b7
BR		 537/*
538 * Adds ibm,dynamic-reconfiguration-memory node.
539 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
540 * of this device tree node.
541 */
542static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
543{
544 MachineState *machine = MACHINE(spapr);
545 int ret, i, offset;
546 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
547 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
d0e5a8f2
BR		 548 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
549 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
550 memory_region_size(&spapr->hotplug_memory.mr)) /
551 lmb_size;
03d196b7 552 uint32_t *int_buf, *cur_index, buf_len;
6663864e 553 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 554
16c25aef 555 /*
d0e5a8f2 556 * Don't create the node if there is no hotpluggable memory
16c25aef 557 */
d0e5a8f2 558 if (machine->ram_size == machine->maxram_size) {
16c25aef
BR		 559 return 0;
560 }
561
ef001f06
TH		 562 /*
563 * Allocate enough buffer size to fit in ibm,dynamic-memory
564 * or ibm,associativity-lookup-arrays
565 */
566 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
567 * sizeof(uint32_t);
03d196b7
BR		 568 cur_index = int_buf = g_malloc0(buf_len);
569
570 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
571
572 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
573 sizeof(prop_lmb_size));
574 if (ret < 0) {
575 goto out;
576 }
577
578 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
579 if (ret < 0) {
580 goto out;
581 }
582
583 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
584 if (ret < 0) {
585 goto out;
586 }
587
588 /* ibm,dynamic-memory */
589 int_buf[0] = cpu_to_be32(nr_lmbs);
590 cur_index++;
591 for (i = 0; i < nr_lmbs; i++) {
d0e5a8f2 592 uint64_t addr = i * lmb_size;
03d196b7
BR		 593 uint32_t *dynamic_memory = cur_index;
594
d0e5a8f2
BR		 595 if (i >= hotplug_lmb_start) {
596 sPAPRDRConnector *drc;
597 sPAPRDRConnectorClass *drck;
598
599 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
600 g_assert(drc);
601 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
602
603 dynamic_memory[0] = cpu_to_be32(addr >> 32);
604 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
605 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
606 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
607 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
608 if (memory_region_present(get_system_memory(), addr)) {
609 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
610 } else {
611 dynamic_memory[5] = cpu_to_be32(0);
612 }
03d196b7 613 } else {
d0e5a8f2
BR		 614 /*
615 * LMB information for RMA, boot time RAM and gap b/n RAM and
616 * hotplug memory region -- all these are marked as reserved
617 * and as having no valid DRC.
618 */
619 dynamic_memory[0] = cpu_to_be32(addr >> 32);
620 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
621 dynamic_memory[2] = cpu_to_be32(0);
622 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
623 dynamic_memory[4] = cpu_to_be32(-1);
624 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
625 SPAPR_LMB_FLAGS_DRC_INVALID);
03d196b7
BR		 626 }
627
628 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
629 }
630 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
631 if (ret < 0) {
632 goto out;
633 }
634
635 /* ibm,associativity-lookup-arrays */
636 cur_index = int_buf;
6663864e 637 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 638 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
639 cur_index += 2;
6663864e 640 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 641 uint32_t associativity[] = {
642 cpu_to_be32(0x0),
643 cpu_to_be32(0x0),
644 cpu_to_be32(0x0),
645 cpu_to_be32(i)
646 };
647 memcpy(cur_index, associativity, sizeof(associativity));
648 cur_index += 4;
649 }
650 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
651 (cur_index - int_buf) * sizeof(uint32_t));
652out:
653 g_free(int_buf);
654 return ret;
655}
656
6787d27b
MR		 657static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
658 sPAPROptionVector *ov5_updates)
659{
660 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
417ece33 661 int ret = 0, offset;
6787d27b
MR		 662
663 /* Generate ibm,dynamic-reconfiguration-memory node if required */
664 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
665 g_assert(smc->dr_lmb_enabled);
666 ret = spapr_populate_drconf_memory(spapr, fdt);
417ece33
MR		 667 if (ret) {
668 goto out;
669 }
6787d27b
MR		 670 }
671
417ece33
MR		 672 offset = fdt_path_offset(fdt, "/chosen");
673 if (offset < 0) {
674 offset = fdt_add_subnode(fdt, 0, "chosen");
675 if (offset < 0) {
676 return offset;
677 }
678 }
679 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
680 "ibm,architecture-vec-5");
681
682out:
6787d27b
MR		 683 return ret;
684}
685
03d196b7
BR		 686int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
687 target_ulong addr, target_ulong size,
6787d27b
MR		 688 bool cpu_update,
689 sPAPROptionVector *ov5_updates)
03d196b7
BR		 690{
691 void *fdt, *fdt_skel;
692 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
03d196b7
BR		 693
694 size -= sizeof(hdr);
695
696 /* Create sceleton */
697 fdt_skel = g_malloc0(size);
698 _FDT((fdt_create(fdt_skel, size)));
699 _FDT((fdt_begin_node(fdt_skel, "")));
700 _FDT((fdt_end_node(fdt_skel)));
701 _FDT((fdt_finish(fdt_skel)));
702 fdt = g_malloc0(size);
703 _FDT((fdt_open_into(fdt_skel, fdt, size)));
704 g_free(fdt_skel);
705
706 /* Fixup cpu nodes */
707 if (cpu_update) {
708 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
709 }
710
6787d27b
MR		 711 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
712 return -1;
03d196b7
BR		 713 }
714
715 /* Pack resulting tree */
716 _FDT((fdt_pack(fdt)));
717
718 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
719 trace_spapr_cas_failed(size);
720 return -1;
721 }
722
723 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
724 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
725 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
726 g_free(fdt);
727
728 return 0;
729}
730
3f5dabce
DG		 731static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
732{
733 int rtas;
734 GString *hypertas = g_string_sized_new(256);
735 GString *qemu_hypertas = g_string_sized_new(256);
736 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
737 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
738 memory_region_size(&spapr->hotplug_memory.mr);
739 uint32_t lrdr_capacity[] = {
740 cpu_to_be32(max_hotplug_addr >> 32),
741 cpu_to_be32(max_hotplug_addr & 0xffffffff),
742 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
743 cpu_to_be32(max_cpus / smp_threads),
744 };
745
746 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
747
748 /* hypertas */
749 add_str(hypertas, "hcall-pft");
750 add_str(hypertas, "hcall-term");
751 add_str(hypertas, "hcall-dabr");
752 add_str(hypertas, "hcall-interrupt");
753 add_str(hypertas, "hcall-tce");
754 add_str(hypertas, "hcall-vio");
755 add_str(hypertas, "hcall-splpar");
756 add_str(hypertas, "hcall-bulk");
757 add_str(hypertas, "hcall-set-mode");
758 add_str(hypertas, "hcall-sprg0");
759 add_str(hypertas, "hcall-copy");
760 add_str(hypertas, "hcall-debug");
761 add_str(qemu_hypertas, "hcall-memop1");
762
763 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
764 add_str(hypertas, "hcall-multi-tce");
765 }
766 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
767 hypertas->str, hypertas->len));
768 g_string_free(hypertas, TRUE);
769 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
770 qemu_hypertas->str, qemu_hypertas->len));
771 g_string_free(qemu_hypertas, TRUE);
772
773 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
774 refpoints, sizeof(refpoints)));
775
776 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
777 RTAS_ERROR_LOG_MAX));
778 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
779 RTAS_EVENT_SCAN_RATE));
780
781 if (msi_nonbroken) {
782 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
783 }
784
785 /*
786 * According to PAPR, rtas ibm,os-term does not guarantee a return
787 * back to the guest cpu.
788 *
789 * While an additional ibm,extended-os-term property indicates
790 * that rtas call return will always occur. Set this property.
791 */
792 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
793
794 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
795 lrdr_capacity, sizeof(lrdr_capacity)));
796
797 spapr_dt_rtas_tokens(fdt, rtas);
798}
799
7c866c6a
DG		 800static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
801{
802 MachineState *machine = MACHINE(spapr);
803 int chosen;
804 const char *boot_device = machine->boot_order;
805 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
806 size_t cb = 0;
807 char *bootlist = get_boot_devices_list(&cb, true);
7c866c6a
DG		 808
809 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
810
7c866c6a
DG		 811 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
812 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
813 spapr->initrd_base));
814 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
815 spapr->initrd_base + spapr->initrd_size));
816
817 if (spapr->kernel_size) {
818 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
819 cpu_to_be64(spapr->kernel_size) };
820
821 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
822 &kprop, sizeof(kprop)));
823 if (spapr->kernel_le) {
824 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
825 }
826 }
827 if (boot_menu) {
828 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
829 }
830 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
831 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
832 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
833
834 if (cb && bootlist) {
835 int i;
836
837 for (i = 0; i < cb; i++) {
838 if (bootlist[i] == '\n') {
839 bootlist[i] = ' ';
840 }
841 }
842 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
843 }
844
845 if (boot_device && strlen(boot_device)) {
846 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
847 }
848
849 if (!spapr->has_graphics && stdout_path) {
850 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
851 }
852
853 g_free(stdout_path);
854 g_free(bootlist);
855}
856
fca5f2dc
DG		 857static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
858{
859 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
860 * KVM to work under pHyp with some guest co-operation */
861 int hypervisor;
862 uint8_t hypercall[16];
863
864 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
865 /* indicate KVM hypercall interface */
866 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
867 if (kvmppc_has_cap_fixup_hcalls()) {
868 /*
869 * Older KVM versions with older guest kernels were broken
870 * with the magic page, don't allow the guest to map it.
871 */
872 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
873 sizeof(hypercall))) {
874 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
875 hypercall, sizeof(hypercall)));
876 }
877 }
878}
879
997b6cfc
DG		 880static void *spapr_build_fdt(sPAPRMachineState *spapr,
881 hwaddr rtas_addr,
882 hwaddr rtas_size)
a3467baa 883{
5b2128d2 884 MachineState *machine = MACHINE(qdev_get_machine());
3c0c47e3 885 MachineClass *mc = MACHINE_GET_CLASS(machine);
c20d332a 886 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
7c866c6a 887 int ret;
a3467baa 888 void *fdt;
3384f95c 889 sPAPRPHBState *phb;
398a0bd5 890 char *buf;
a3467baa 891
398a0bd5
DG		 892 fdt = g_malloc0(FDT_MAX_SIZE);
893 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
a3467baa 894
398a0bd5
DG		 895 /* Root node */
896 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
897 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
898 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
899
900 /*
901 * Add info to guest to indentify which host is it being run on
902 * and what is the uuid of the guest
903 */
904 if (kvmppc_get_host_model(&buf)) {
905 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
906 g_free(buf);
907 }
908 if (kvmppc_get_host_serial(&buf)) {
909 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
910 g_free(buf);
911 }
912
913 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
914
915 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
916 if (qemu_uuid_set) {
917 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
918 }
919 g_free(buf);
920
921 if (qemu_get_vm_name()) {
922 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
923 qemu_get_vm_name()));
924 }
925
926 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
927 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
4040ab72 928
9b9a1908
DG		 929 /* /interrupt controller */
930 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP);
931
e8f986fc
BR		 932 ret = spapr_populate_memory(spapr, fdt);
933 if (ret < 0) {
ce9863b7 934 error_report("couldn't setup memory nodes in fdt");
e8f986fc 935 exit(1);
7f763a5d
DG		 936 }
937
bf5a6696
DG		 938 /* /vdevice */
939 spapr_dt_vdevice(spapr->vio_bus, fdt);
4040ab72 940
4d9392be
TH		 941 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
942 ret = spapr_rng_populate_dt(fdt);
943 if (ret < 0) {
ce9863b7 944 error_report("could not set up rng device in the fdt");
4d9392be
TH		 945 exit(1);
946 }
947 }
948
3384f95c 949 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 950 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
da34fed7
TH		 951 if (ret < 0) {
952 error_report("couldn't setup PCI devices in fdt");
953 exit(1);
954 }
3384f95c
DG		 955 }
956
0da6f3fe
BR		 957 /* cpus */
958 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 959
c20d332a
BR		 960 if (smc->dr_lmb_enabled) {
961 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
962 }
963
3c0c47e3 964 if (mc->query_hotpluggable_cpus) {
af81cf32
BR		 965 int offset = fdt_path_offset(fdt, "/cpus");
966 ret = spapr_drc_populate_dt(fdt, offset, NULL,
967 SPAPR_DR_CONNECTOR_TYPE_CPU);
968 if (ret < 0) {
969 error_report("Couldn't set up CPU DR device tree properties");
970 exit(1);
971 }
972 }
973
ffb1e275 974 /* /event-sources */
ffbb1705 975 spapr_dt_events(spapr, fdt);
ffb1e275 976
3f5dabce
DG		 977 /* /rtas */
978 spapr_dt_rtas(spapr, fdt);
979
7c866c6a
DG		 980 /* /chosen */
981 spapr_dt_chosen(spapr, fdt);
cf6e5223 982
fca5f2dc
DG		 983 /* /hypervisor */
984 if (kvm_enabled()) {
985 spapr_dt_hypervisor(spapr, fdt);
986 }
987
cf6e5223
DG		 988 /* Build memory reserve map */
989 if (spapr->kernel_size) {
990 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
991 }
992 if (spapr->initrd_size) {
993 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
994 }
995
6787d27b
MR		 996 /* ibm,client-architecture-support updates */
997 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
998 if (ret < 0) {
999 error_report("couldn't setup CAS properties fdt");
1000 exit(1);
1001 }
1002
997b6cfc 1003 return fdt;
9fdf0c29
DG		 1004}
1005
1006static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1007{
1008 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1009}
1010
1b14670a 1011static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 1012{
1b14670a
AF		 1013 CPUPPCState *env = &cpu->env;
1014
efcb9383
DG		 1015 if (msr_pr) {
1016 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1017 env->gpr[3] = H_PRIVILEGE;
1018 } else {
aa100fa4 1019 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 1020 }
9fdf0c29
DG		 1021}
1022
e6b8fd24
SMJ		 1023#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1024#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1025#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1026#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1027#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1028
715c5407
DG		 1029/*
1030 * Get the fd to access the kernel htab, re-opening it if necessary
1031 */
1032static int get_htab_fd(sPAPRMachineState *spapr)
1033{
1034 if (spapr->htab_fd >= 0) {
1035 return spapr->htab_fd;
1036 }
1037
1038 spapr->htab_fd = kvmppc_get_htab_fd(false);
1039 if (spapr->htab_fd < 0) {
1040 error_report("Unable to open fd for reading hash table from KVM: %s",
1041 strerror(errno));
1042 }
1043
1044 return spapr->htab_fd;
1045}
1046
1047static void close_htab_fd(sPAPRMachineState *spapr)
1048{
1049 if (spapr->htab_fd >= 0) {
1050 close(spapr->htab_fd);
1051 }
1052 spapr->htab_fd = -1;
1053}
1054
8dfe8e7f
DG		 1055static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1056{
1057 int shift;
1058
1059 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1060 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1061 * that's much more than is needed for Linux guests */
1062 shift = ctz64(pow2ceil(ramsize)) - 7;
1063 shift = MAX(shift, 18); /* Minimum architected size */
1064 shift = MIN(shift, 46); /* Maximum architected size */
1065 return shift;
1066}
1067
c5f54f3e
DG		 1068static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1069 Error **errp)
7f763a5d 1070{
c5f54f3e
DG		 1071 long rc;
1072
1073 /* Clean up any HPT info from a previous boot */
1074 g_free(spapr->htab);
1075 spapr->htab = NULL;
1076 spapr->htab_shift = 0;
1077 close_htab_fd(spapr);
1078
1079 rc = kvmppc_reset_htab(shift);
1080 if (rc < 0) {
1081 /* kernel-side HPT needed, but couldn't allocate one */
1082 error_setg_errno(errp, errno,
1083 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1084 shift);
1085 /* This is almost certainly fatal, but if the caller really
1086 * wants to carry on with shift == 0, it's welcome to try */
1087 } else if (rc > 0) {
1088 /* kernel-side HPT allocated */
1089 if (rc != shift) {
1090 error_setg(errp,
1091 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1092 shift, rc);
7735feda
BR		 1093 }
1094
7f763a5d 1095 spapr->htab_shift = shift;
c18ad9a5 1096 spapr->htab = NULL;
b817772a 1097 } else {
c5f54f3e
DG		 1098 /* kernel-side HPT not needed, allocate in userspace instead */
1099 size_t size = 1ULL << shift;
1100 int i;
b817772a 1101
c5f54f3e
DG		 1102 spapr->htab = qemu_memalign(size, size);
1103 if (!spapr->htab) {
1104 error_setg_errno(errp, errno,
1105 "Could not allocate HPT of order %d", shift);
1106 return;
7735feda
BR		 1107 }
1108
c5f54f3e
DG		 1109 memset(spapr->htab, 0, size);
1110 spapr->htab_shift = shift;
e6b8fd24 1111
c5f54f3e
DG		 1112 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1113 DIRTY_HPTE(HPTE(spapr->htab, i));
e6b8fd24 1114 }
7f763a5d 1115 }
9fdf0c29
DG		 1116}
1117
4f01a637 1118static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
9e3f9733
AG		 1119{
1120 bool matched = false;
1121
1122 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1123 matched = true;
1124 }
1125
1126 if (!matched) {
1127 error_report("Device %s is not supported by this machine yet.",
1128 qdev_fw_name(DEVICE(sbdev)));
1129 exit(1);
1130 }
9e3f9733
AG		 1131}
1132
c8787ad4 1133static void ppc_spapr_reset(void)
a3467baa 1134{
c5f54f3e
DG		 1135 MachineState *machine = MACHINE(qdev_get_machine());
1136 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
182735ef 1137 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1138 uint32_t rtas_limit;
cae172ab 1139 hwaddr rtas_addr, fdt_addr;
997b6cfc
DG		 1140 void *fdt;
1141 int rc;
259186a7 1142
9e3f9733
AG		 1143 /* Check for unknown sysbus devices */
1144 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1145
c5f54f3e
DG		 1146 /* Allocate and/or reset the hash page table */
1147 spapr_reallocate_hpt(spapr,
1148 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1149 &error_fatal);
1150
1151 /* Update the RMA size if necessary */
1152 if (spapr->vrma_adjust) {
1153 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1154 spapr->htab_shift);
1155 }
a3467baa 1156
c8787ad4 1157 qemu_devices_reset();
a3467baa 1158
b7d1f77a
BH		 1159 /*
1160 * We place the device tree and RTAS just below either the top of the RMA,
1161 * or just below 2GB, whichever is lowere, so that it can be
1162 * processed with 32-bit real mode code if necessary
1163 */
1164 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
cae172ab
DG		 1165 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1166 fdt_addr = rtas_addr - FDT_MAX_SIZE;
b7d1f77a 1167
6787d27b
MR		 1168 /* if this reset wasn't generated by CAS, we should reset our
1169 * negotiated options and start from scratch */
1170 if (!spapr->cas_reboot) {
1171 spapr_ovec_cleanup(spapr->ov5_cas);
1172 spapr->ov5_cas = spapr_ovec_new();
1173 }
1174
cae172ab 1175 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
a3467baa 1176
2cac78c1 1177 spapr_load_rtas(spapr, fdt, rtas_addr);
b7d1f77a 1178
997b6cfc
DG		 1179 rc = fdt_pack(fdt);
1180
1181 /* Should only fail if we've built a corrupted tree */
1182 assert(rc == 0);
1183
1184 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1185 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1186 fdt_totalsize(fdt), FDT_MAX_SIZE);
1187 exit(1);
1188 }
1189
1190 /* Load the fdt */
1191 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
cae172ab 1192 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
997b6cfc
DG		 1193 g_free(fdt);
1194
a3467baa 1195 /* Set up the entry state */
182735ef 1196 first_ppc_cpu = POWERPC_CPU(first_cpu);
cae172ab 1197 first_ppc_cpu->env.gpr[3] = fdt_addr;
182735ef
AF		 1198 first_ppc_cpu->env.gpr[5] = 0;
1199 first_cpu->halted = 0;
1b718907 1200 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa 1201
6787d27b 1202 spapr->cas_reboot = false;
a3467baa
DG		 1203}
1204
28e02042 1205static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1206{
2ff3de68 1207 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1208 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1209
3978b863 1210 if (dinfo) {
6231a6da
MA		 1211 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1212 &error_fatal);
639e8102
DG		 1213 }
1214
1215 qdev_init_nofail(dev);
1216
1217 spapr->nvram = (struct sPAPRNVRAM *)dev;
1218}
1219
28e02042 1220static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1221{
1222 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1223
1224 qdev_init_nofail(dev);
1225 spapr->rtc = dev;
74e5ae28
DG		 1226
1227 object_property_add_alias(qdev_get_machine(), "rtc-time",
1228 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1229}
1230
8c57b867 1231/* Returns whether we want to use VGA or not */
14c6a894 1232static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
f28359d8 1233{
8c57b867 1234 switch (vga_interface_type) {
8c57b867 1235 case VGA_NONE:
7effdaa3
MW		 1236 return false;
1237 case VGA_DEVICE:
1238 return true;
1ddcae82 1239 case VGA_STD:
b798c190 1240 case VGA_VIRTIO:
1ddcae82 1241 return pci_vga_init(pci_bus) != NULL;
8c57b867 1242 default:
14c6a894
DG		 1243 error_setg(errp,
1244 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1245 return false;
f28359d8 1246 }
f28359d8
LZ		 1247}
1248
880ae7de
DG		 1249static int spapr_post_load(void *opaque, int version_id)
1250{
28e02042 1251 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1252 int err = 0;
1253
631b22ea 1254 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1255 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1256 * So when migrating from those versions, poke the incoming offset
1257 * value into the RTC device */
1258 if (version_id < 3) {
1259 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1260 }
1261
1262 return err;
1263}
1264
1265static bool version_before_3(void *opaque, int version_id)
1266{
1267 return version_id < 3;
1268}
1269
62ef3760
MR		 1270static bool spapr_ov5_cas_needed(void *opaque)
1271{
1272 sPAPRMachineState *spapr = opaque;
1273 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1274 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1275 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1276 bool cas_needed;
1277
1278 /* Prior to the introduction of sPAPROptionVector, we had two option
1279 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1280 * Both of these options encode machine topology into the device-tree
1281 * in such a way that the now-booted OS should still be able to interact
1282 * appropriately with QEMU regardless of what options were actually
1283 * negotiatied on the source side.
1284 *
1285 * As such, we can avoid migrating the CAS-negotiated options if these
1286 * are the only options available on the current machine/platform.
1287 * Since these are the only options available for pseries-2.7 and
1288 * earlier, this allows us to maintain old->new/new->old migration
1289 * compatibility.
1290 *
1291 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1292 * via default pseries-2.8 machines and explicit command-line parameters.
1293 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1294 * of the actual CAS-negotiated values to continue working properly. For
1295 * example, availability of memory unplug depends on knowing whether
1296 * OV5_HP_EVT was negotiated via CAS.
1297 *
1298 * Thus, for any cases where the set of available CAS-negotiatable
1299 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1300 * include the CAS-negotiated options in the migration stream.
1301 */
1302 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1303 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1304
1305 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1306 * the mask itself since in the future it's possible "legacy" bits may be
1307 * removed via machine options, which could generate a false positive
1308 * that breaks migration.
1309 */
1310 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1311 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1312
1313 spapr_ovec_cleanup(ov5_mask);
1314 spapr_ovec_cleanup(ov5_legacy);
1315 spapr_ovec_cleanup(ov5_removed);
1316
1317 return cas_needed;
1318}
1319
1320static const VMStateDescription vmstate_spapr_ov5_cas = {
1321 .name = "spapr_option_vector_ov5_cas",
1322 .version_id = 1,
1323 .minimum_version_id = 1,
1324 .needed = spapr_ov5_cas_needed,
1325 .fields = (VMStateField[]) {
1326 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1327 vmstate_spapr_ovec, sPAPROptionVector),
1328 VMSTATE_END_OF_LIST()
1329 },
1330};
1331
4be21d56
DG		 1332static const VMStateDescription vmstate_spapr = {
1333 .name = "spapr",
880ae7de 1334 .version_id = 3,
4be21d56 1335 .minimum_version_id = 1,
880ae7de 1336 .post_load = spapr_post_load,
3aff6c2f 1337 .fields = (VMStateField[]) {
880ae7de
DG		 1338 /* used to be @next_irq */
1339 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1340
1341 /* RTC offset */
28e02042 1342 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1343
28e02042 1344 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1345 VMSTATE_END_OF_LIST()
1346 },
62ef3760
MR		 1347 .subsections = (const VMStateDescription*[]) {
1348 &vmstate_spapr_ov5_cas,
1349 NULL
1350 }
4be21d56
DG		 1351};
1352
4be21d56
DG		 1353static int htab_save_setup(QEMUFile *f, void *opaque)
1354{
28e02042 1355 sPAPRMachineState *spapr = opaque;
4be21d56 1356
4be21d56
DG		 1357 /* "Iteration" header */
1358 qemu_put_be32(f, spapr->htab_shift);
1359
e68cb8b4
AK		 1360 if (spapr->htab) {
1361 spapr->htab_save_index = 0;
1362 spapr->htab_first_pass = true;
1363 } else {
1364 assert(kvm_enabled());
e68cb8b4
AK		 1365 }
1366
1367
4be21d56
DG		 1368 return 0;
1369}
1370
28e02042 1371static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1372 int64_t max_ns)
1373{
378bc217 1374 bool has_timeout = max_ns != -1;
4be21d56
DG		 1375 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1376 int index = spapr->htab_save_index;
bc72ad67 1377 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1378
1379 assert(spapr->htab_first_pass);
1380
1381 do {
1382 int chunkstart;
1383
1384 /* Consume invalid HPTEs */
1385 while ((index < htabslots)
1386 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1387 index++;
1388 CLEAN_HPTE(HPTE(spapr->htab, index));
1389 }
1390
1391 /* Consume valid HPTEs */
1392 chunkstart = index;
338c25b6 1393 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1394 && HPTE_VALID(HPTE(spapr->htab, index))) {
1395 index++;
1396 CLEAN_HPTE(HPTE(spapr->htab, index));
1397 }
1398
1399 if (index > chunkstart) {
1400 int n_valid = index - chunkstart;
1401
1402 qemu_put_be32(f, chunkstart);
1403 qemu_put_be16(f, n_valid);
1404 qemu_put_be16(f, 0);
1405 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1406 HASH_PTE_SIZE_64 * n_valid);
1407
378bc217
DG		 1408 if (has_timeout &&
1409 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1410 break;
1411 }
1412 }
1413 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1414
1415 if (index >= htabslots) {
1416 assert(index == htabslots);
1417 index = 0;
1418 spapr->htab_first_pass = false;
1419 }
1420 spapr->htab_save_index = index;
1421}
1422
28e02042 1423static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1424 int64_t max_ns)
4be21d56
DG		 1425{
1426 bool final = max_ns < 0;
1427 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1428 int examined = 0, sent = 0;
1429 int index = spapr->htab_save_index;
bc72ad67 1430 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1431
1432 assert(!spapr->htab_first_pass);
1433
1434 do {
1435 int chunkstart, invalidstart;
1436
1437 /* Consume non-dirty HPTEs */
1438 while ((index < htabslots)
1439 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1440 index++;
1441 examined++;
1442 }
1443
1444 chunkstart = index;
1445 /* Consume valid dirty HPTEs */
338c25b6 1446 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1447 && HPTE_DIRTY(HPTE(spapr->htab, index))
1448 && HPTE_VALID(HPTE(spapr->htab, index))) {
1449 CLEAN_HPTE(HPTE(spapr->htab, index));
1450 index++;
1451 examined++;
1452 }
1453
1454 invalidstart = index;
1455 /* Consume invalid dirty HPTEs */
338c25b6 1456 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1457 && HPTE_DIRTY(HPTE(spapr->htab, index))
1458 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1459 CLEAN_HPTE(HPTE(spapr->htab, index));
1460 index++;
1461 examined++;
1462 }
1463
1464 if (index > chunkstart) {
1465 int n_valid = invalidstart - chunkstart;
1466 int n_invalid = index - invalidstart;
1467
1468 qemu_put_be32(f, chunkstart);
1469 qemu_put_be16(f, n_valid);
1470 qemu_put_be16(f, n_invalid);
1471 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1472 HASH_PTE_SIZE_64 * n_valid);
1473 sent += index - chunkstart;
1474
bc72ad67 1475 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1476 break;
1477 }
1478 }
1479
1480 if (examined >= htabslots) {
1481 break;
1482 }
1483
1484 if (index >= htabslots) {
1485 assert(index == htabslots);
1486 index = 0;
1487 }
1488 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1489
1490 if (index >= htabslots) {
1491 assert(index == htabslots);
1492 index = 0;
1493 }
1494
1495 spapr->htab_save_index = index;
1496
e68cb8b4 1497 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1498}
1499
e68cb8b4
AK		 1500#define MAX_ITERATION_NS 5000000 /* 5 ms */
1501#define MAX_KVM_BUF_SIZE 2048
1502
4be21d56
DG		 1503static int htab_save_iterate(QEMUFile *f, void *opaque)
1504{
28e02042 1505 sPAPRMachineState *spapr = opaque;
715c5407 1506 int fd;
e68cb8b4 1507 int rc = 0;
4be21d56
DG		 1508
1509 /* Iteration header */
1510 qemu_put_be32(f, 0);
1511
e68cb8b4
AK		 1512 if (!spapr->htab) {
1513 assert(kvm_enabled());
1514
715c5407
DG		 1515 fd = get_htab_fd(spapr);
1516 if (fd < 0) {
1517 return fd;
01a57972
SMJ		 1518 }
1519
715c5407 1520 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
e68cb8b4
AK		 1521 if (rc < 0) {
1522 return rc;
1523 }
1524 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1525 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1526 } else {
e68cb8b4 1527 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1528 }
1529
1530 /* End marker */
1531 qemu_put_be32(f, 0);
1532 qemu_put_be16(f, 0);
1533 qemu_put_be16(f, 0);
1534
e68cb8b4 1535 return rc;
4be21d56
DG		 1536}
1537
1538static int htab_save_complete(QEMUFile *f, void *opaque)
1539{
28e02042 1540 sPAPRMachineState *spapr = opaque;
715c5407 1541 int fd;
4be21d56
DG		 1542
1543 /* Iteration header */
1544 qemu_put_be32(f, 0);
1545
e68cb8b4
AK		 1546 if (!spapr->htab) {
1547 int rc;
1548
1549 assert(kvm_enabled());
1550
715c5407
DG		 1551 fd = get_htab_fd(spapr);
1552 if (fd < 0) {
1553 return fd;
01a57972
SMJ		 1554 }
1555
715c5407 1556 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
e68cb8b4
AK		 1557 if (rc < 0) {
1558 return rc;
1559 }
e68cb8b4 1560 } else {
378bc217
DG		 1561 if (spapr->htab_first_pass) {
1562 htab_save_first_pass(f, spapr, -1);
1563 }
e68cb8b4
AK		 1564 htab_save_later_pass(f, spapr, -1);
1565 }
4be21d56
DG		 1566
1567 /* End marker */
1568 qemu_put_be32(f, 0);
1569 qemu_put_be16(f, 0);
1570 qemu_put_be16(f, 0);
1571
1572 return 0;
1573}
1574
1575static int htab_load(QEMUFile *f, void *opaque, int version_id)
1576{
28e02042 1577 sPAPRMachineState *spapr = opaque;
4be21d56 1578 uint32_t section_hdr;
e68cb8b4 1579 int fd = -1;
4be21d56
DG		 1580
1581 if (version_id < 1 || version_id > 1) {
98a5d100 1582 error_report("htab_load() bad version");
4be21d56
DG		 1583 return -EINVAL;
1584 }
1585
1586 section_hdr = qemu_get_be32(f);
1587
1588 if (section_hdr) {
9897e462 1589 Error *local_err = NULL;
c5f54f3e
DG		 1590
1591 /* First section gives the htab size */
1592 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1593 if (local_err) {
1594 error_report_err(local_err);
4be21d56
DG		 1595 return -EINVAL;
1596 }
1597 return 0;
1598 }
1599
e68cb8b4
AK		 1600 if (!spapr->htab) {
1601 assert(kvm_enabled());
1602
1603 fd = kvmppc_get_htab_fd(true);
1604 if (fd < 0) {
98a5d100
DG		 1605 error_report("Unable to open fd to restore KVM hash table: %s",
1606 strerror(errno));
e68cb8b4
AK		 1607 }
1608 }
1609
4be21d56
DG		 1610 while (true) {
1611 uint32_t index;
1612 uint16_t n_valid, n_invalid;
1613
1614 index = qemu_get_be32(f);
1615 n_valid = qemu_get_be16(f);
1616 n_invalid = qemu_get_be16(f);
1617
1618 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1619 /* End of Stream */
1620 break;
1621 }
1622
e68cb8b4 1623 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1624 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1625 /* Bad index in stream */
98a5d100
DG		 1626 error_report(
1627 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1628 index, n_valid, n_invalid, spapr->htab_shift);
4be21d56
DG		 1629 return -EINVAL;
1630 }
1631
e68cb8b4
AK		 1632 if (spapr->htab) {
1633 if (n_valid) {
1634 qemu_get_buffer(f, HPTE(spapr->htab, index),
1635 HASH_PTE_SIZE_64 * n_valid);
1636 }
1637 if (n_invalid) {
1638 memset(HPTE(spapr->htab, index + n_valid), 0,
1639 HASH_PTE_SIZE_64 * n_invalid);
1640 }
1641 } else {
1642 int rc;
1643
1644 assert(fd >= 0);
1645
1646 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1647 if (rc < 0) {
1648 return rc;
1649 }
4be21d56
DG		 1650 }
1651 }
1652
e68cb8b4
AK		 1653 if (!spapr->htab) {
1654 assert(fd >= 0);
1655 close(fd);
1656 }
1657
4be21d56
DG		 1658 return 0;
1659}
1660
c573fc03
TH		 1661static void htab_cleanup(void *opaque)
1662{
1663 sPAPRMachineState *spapr = opaque;
1664
1665 close_htab_fd(spapr);
1666}
1667
4be21d56
DG		 1668static SaveVMHandlers savevm_htab_handlers = {
1669 .save_live_setup = htab_save_setup,
1670 .save_live_iterate = htab_save_iterate,
a3e06c3d 1671 .save_live_complete_precopy = htab_save_complete,
c573fc03 1672 .cleanup = htab_cleanup,
4be21d56
DG		 1673 .load_state = htab_load,
1674};
1675
5b2128d2
AG		 1676static void spapr_boot_set(void *opaque, const char *boot_device,
1677 Error **errp)
1678{
1679 MachineState *machine = MACHINE(qdev_get_machine());
1680 machine->boot_order = g_strdup(boot_device);
1681}
1682
224245bf
DG		 1683/*
1684 * Reset routine for LMB DR devices.
1685 *
1686 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1687 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1688 * when it walks all its children devices. LMB devices reset occurs
1689 * as part of spapr_ppc_reset().
1690 */
1691static void spapr_drc_reset(void *opaque)
1692{
1693 sPAPRDRConnector *drc = opaque;
1694 DeviceState *d = DEVICE(drc);
1695
1696 if (d) {
1697 device_reset(d);
1698 }
1699}
1700
1701static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1702{
1703 MachineState *machine = MACHINE(spapr);
1704 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1705 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1706 int i;
1707
1708 for (i = 0; i < nr_lmbs; i++) {
1709 sPAPRDRConnector *drc;
1710 uint64_t addr;
1711
e8f986fc 1712 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1713 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1714 addr/lmb_size);
1715 qemu_register_reset(spapr_drc_reset, drc);
1716 }
1717}
1718
1719/*
1720 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1721 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1722 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1723 */
7c150d6f 1724static void spapr_validate_node_memory(MachineState *machine, Error **errp)
224245bf
DG		 1725{
1726 int i;
1727
7c150d6f
DG		 1728 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1729 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1730 " is not aligned to %llu MiB",
1731 machine->ram_size,
1732 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1733 return;
1734 }
1735
1736 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1737 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1738 " is not aligned to %llu MiB",
1739 machine->ram_size,
1740 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1741 return;
224245bf
DG		 1742 }
1743
1744 for (i = 0; i < nb_numa_nodes; i++) {
1745 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
7c150d6f
DG		 1746 error_setg(errp,
1747 "Node %d memory size 0x%" PRIx64
1748 " is not aligned to %llu MiB",
1749 i, numa_info[i].node_mem,
1750 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1751 return;
224245bf
DG		 1752 }
1753 }
1754}
1755
9fdf0c29 1756/* pSeries LPAR / sPAPR hardware init */
3ef96221 1757static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1758{
28e02042 1759 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3c0c47e3 1760 MachineClass *mc = MACHINE_GET_CLASS(machine);
224245bf 1761 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221 1762 const char *kernel_filename = machine->kernel_filename;
3ef96221 1763 const char *initrd_filename = machine->initrd_filename;
8c9f64df 1764 PCIHostState *phb;
9fdf0c29 1765 int i;
890c2b77
AK		 1766 MemoryRegion *sysmem = get_system_memory();
1767 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1768 MemoryRegion *rma_region;
1769 void *rma = NULL;
a8170e5e 1770 hwaddr rma_alloc_size;
b082d65a 1771 hwaddr node0_size = spapr_node0_size();
b7d1f77a 1772 long load_limit, fw_size;
39ac8455 1773 char *filename;
94a94e4c
BR		 1774 int smt = kvmppc_smt_threads();
1775 int spapr_cores = smp_cpus / smp_threads;
1776 int spapr_max_cores = max_cpus / smp_threads;
1777
3c0c47e3 1778 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1779 if (smp_cpus % smp_threads) {
1780 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1781 smp_cpus, smp_threads);
1782 exit(1);
1783 }
1784 if (max_cpus % smp_threads) {
1785 error_report("max_cpus (%u) must be multiple of threads (%u)",
1786 max_cpus, smp_threads);
1787 exit(1);
1788 }
1789 }
9fdf0c29 1790
226419d6 1791 msi_nonbroken = true;
0ee2c058 1792
d43b45e2
DG		 1793 QLIST_INIT(&spapr->phbs);
1794
9fdf0c29
DG		 1795 cpu_ppc_hypercall = emulate_spapr_hypercall;
1796
354ac20a 1797 /* Allocate RMA if necessary */
658fa66b 1798 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1799
1800 if (rma_alloc_size == -1) {
730fce59 1801 error_report("Unable to create RMA");
354ac20a
DG		 1802 exit(1);
1803 }
7f763a5d 1804
c4177479 1805 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1806 spapr->rma_size = rma_alloc_size;
354ac20a 1807 } else {
c4177479 1808 spapr->rma_size = node0_size;
7f763a5d
DG		 1809
1810 /* With KVM, we don't actually know whether KVM supports an
1811 * unbounded RMA (PR KVM) or is limited by the hash table size
1812 * (HV KVM using VRMA), so we always assume the latter
1813 *
1814 * In that case, we also limit the initial allocations for RTAS
1815 * etc... to 256M since we have no way to know what the VRMA size
1816 * is going to be as it depends on the size of the hash table
1817 * isn't determined yet.
1818 */
1819 if (kvm_enabled()) {
1820 spapr->vrma_adjust = 1;
1821 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1822 }
912acdf4
BH		 1823
1824 /* Actually we don't support unbounded RMA anymore since we
1825 * added proper emulation of HV mode. The max we can get is
1826 * 16G which also happens to be what we configure for PAPR
1827 * mode so make sure we don't do anything bigger than that
1828 */
1829 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
354ac20a
DG		 1830 }
1831
c4177479 1832 if (spapr->rma_size > node0_size) {
d54e4d76
DG		 1833 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1834 spapr->rma_size);
c4177479
AK		 1835 exit(1);
1836 }
1837
b7d1f77a
BH		 1838 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1839 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1840
7b565160 1841 /* Set up Interrupt Controller before we create the VCPUs */
27f24582
BH		 1842 spapr->xics = xics_system_init(machine,
1843 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1844 XICS_IRQS_SPAPR, &error_fatal);
7b565160 1845
facdb8b6
MR		 1846 /* Set up containers for ibm,client-set-architecture negotiated options */
1847 spapr->ov5 = spapr_ovec_new();
1848 spapr->ov5_cas = spapr_ovec_new();
1849
224245bf 1850 if (smc->dr_lmb_enabled) {
facdb8b6 1851 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
7c150d6f 1852 spapr_validate_node_memory(machine, &error_fatal);
224245bf
DG		 1853 }
1854
417ece33
MR		 1855 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
1856
ffbb1705
MR		 1857 /* advertise support for dedicated HP event source to guests */
1858 if (spapr->use_hotplug_event_source) {
1859 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
1860 }
1861
9fdf0c29 1862 /* init CPUs */
19fb2c36 1863 if (machine->cpu_model == NULL) {
3daa4a9f 1864 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
9fdf0c29 1865 }
94a94e4c 1866
e703d2f7
GK		 1867 ppc_cpu_parse_features(machine->cpu_model);
1868
3c0c47e3 1869 if (mc->query_hotpluggable_cpus) {
94a94e4c
BR		 1870 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1871
4babfaf0 1872 if (type == NULL) {
caebf378
CLG		 1873 error_report("Unable to find sPAPR CPU Core definition");
1874 exit(1);
1875 }
1876
94a94e4c 1877 spapr->cores = g_new0(Object *, spapr_max_cores);
af81cf32 1878 for (i = 0; i < spapr_max_cores; i++) {
12bf2d33 1879 int core_id = i * smp_threads;
af81cf32
BR		 1880 sPAPRDRConnector *drc =
1881 spapr_dr_connector_new(OBJECT(spapr),
12bf2d33
GK		 1882 SPAPR_DR_CONNECTOR_TYPE_CPU,
1883 (core_id / smp_threads) * smt);
af81cf32
BR		 1884
1885 qemu_register_reset(spapr_drc_reset, drc);
1886
1887 if (i < spapr_cores) {
caebf378 1888 Object *core = object_new(type);
af81cf32
BR		 1889 object_property_set_int(core, smp_threads, "nr-threads",
1890 &error_fatal);
12bf2d33 1891 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
af81cf32
BR		 1892 &error_fatal);
1893 object_property_set_bool(core, true, "realized", &error_fatal);
94a94e4c 1894 }
9fdf0c29 1895 }
94a94e4c
BR		 1896 g_free(type);
1897 } else {
1898 for (i = 0; i < smp_cpus; i++) {
1899 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1900 if (cpu == NULL) {
1901 error_report("Unable to find PowerPC CPU definition");
1902 exit(1);
1903 }
1904 spapr_cpu_init(spapr, cpu, &error_fatal);
1905 }
9fdf0c29
DG		 1906 }
1907
026bfd89
DG		 1908 if (kvm_enabled()) {
1909 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1910 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1911 kvmppc_enable_set_mode_hcall();
5145ad4f
NW		 1912
1913 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
1914 kvmppc_enable_clear_ref_mod_hcalls();
026bfd89
DG		 1915 }
1916
9fdf0c29 1917 /* allocate RAM */
f92f5da1 1918 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1919 machine->ram_size);
f92f5da1 1920 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1921
658fa66b
AK		 1922 if (rma_alloc_size && rma) {
1923 rma_region = g_new(MemoryRegion, 1);
1924 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1925 rma_alloc_size, rma);
1926 vmstate_register_ram_global(rma_region);
1927 memory_region_add_subregion(sysmem, 0, rma_region);
1928 }
1929
4a1c9cf0
BR		 1930 /* initialize hotplug memory address space */
1931 if (machine->ram_size < machine->maxram_size) {
1932 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
71c9a3dd
BR		 1933 /*
1934 * Limit the number of hotpluggable memory slots to half the number
1935 * slots that KVM supports, leaving the other half for PCI and other
1936 * devices. However ensure that number of slots doesn't drop below 32.
1937 */
1938 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1939 SPAPR_MAX_RAM_SLOTS;
4a1c9cf0 1940
71c9a3dd
BR		 1941 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1942 max_memslots = SPAPR_MAX_RAM_SLOTS;
1943 }
1944 if (machine->ram_slots > max_memslots) {
d54e4d76
DG		 1945 error_report("Specified number of memory slots %"
1946 PRIu64" exceeds max supported %d",
71c9a3dd 1947 machine->ram_slots, max_memslots);
d54e4d76 1948 exit(1);
4a1c9cf0
BR		 1949 }
1950
1951 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1952 SPAPR_HOTPLUG_MEM_ALIGN);
1953 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1954 "hotplug-memory", hotplug_mem_size);
1955 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1956 &spapr->hotplug_memory.mr);
1957 }
1958
224245bf
DG		 1959 if (smc->dr_lmb_enabled) {
1960 spapr_create_lmb_dr_connectors(spapr);
1961 }
1962
39ac8455 1963 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1964 if (!filename) {
730fce59 1965 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1966 exit(1);
1967 }
b7d1f77a 1968 spapr->rtas_size = get_image_size(filename);
8afc22a2
ZJ		 1969 if (spapr->rtas_size < 0) {
1970 error_report("Could not get size of LPAR rtas '%s'", filename);
1971 exit(1);
1972 }
b7d1f77a
BH		 1973 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1974 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1975 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1976 exit(1);
1977 }
4d8d5467 1978 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1979 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1980 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1981 exit(1);
1982 }
7267c094 1983 g_free(filename);
39ac8455 1984
ffbb1705 1985 /* Set up RTAS event infrastructure */
74d042e5
DG		 1986 spapr_events_init(spapr);
1987
12f42174 1988 /* Set up the RTC RTAS interfaces */
28df36a1 1989 spapr_rtc_create(spapr);
12f42174 1990
b5cec4c5 1991 /* Set up VIO bus */
4040ab72
DG		 1992 spapr->vio_bus = spapr_vio_bus_init();
1993
277f9acf 1994 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1995 if (serial_hds[i]) {
d601fac4 1996 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1997 }
1998 }
9fdf0c29 1999
639e8102
DG		 2000 /* We always have at least the nvram device on VIO */
2001 spapr_create_nvram(spapr);
2002
3384f95c 2003 /* Set up PCI */
fa28f71b
AK		 2004 spapr_pci_rtas_init();
2005
89dfd6e1 2006 phb = spapr_create_phb(spapr, 0);
3384f95c 2007
277f9acf 2008 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 2009 NICInfo *nd = &nd_table[i];
2010
2011 if (!nd->model) {
7267c094 2012 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 2013 }
2014
2015 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 2016 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 2017 } else {
29b358f9 2018 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 2019 }
2020 }
2021
6e270446 2022 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 2023 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 2024 }
2025
f28359d8 2026 /* Graphics */
14c6a894 2027 if (spapr_vga_init(phb->bus, &error_fatal)) {
3fc5acde 2028 spapr->has_graphics = true;
c6e76503 2029 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 2030 }
2031
4ee9ced9 2032 if (machine->usb) {
57040d45
TH		 2033 if (smc->use_ohci_by_default) {
2034 pci_create_simple(phb->bus, -1, "pci-ohci");
2035 } else {
2036 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2037 }
c86580b8 2038
35139a59 2039 if (spapr->has_graphics) {
c86580b8
MA		 2040 USBBus *usb_bus = usb_bus_find(-1);
2041
2042 usb_create_simple(usb_bus, "usb-kbd");
2043 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 2044 }
2045 }
2046
7f763a5d 2047 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
d54e4d76
DG		 2048 error_report(
2049 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2050 MIN_RMA_SLOF);
4d8d5467
BH		 2051 exit(1);
2052 }
2053
9fdf0c29
DG		 2054 if (kernel_filename) {
2055 uint64_t lowaddr = 0;
2056
a19f7fb0
DG		 2057 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2058 NULL, NULL, &lowaddr, NULL, 1,
2059 PPC_ELF_MACHINE, 0, 0);
2060 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2061 spapr->kernel_size = load_elf(kernel_filename,
2062 translate_kernel_address, NULL, NULL,
2063 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2064 0, 0);
2065 spapr->kernel_le = spapr->kernel_size > 0;
16457e7f 2066 }
a19f7fb0
DG		 2067 if (spapr->kernel_size < 0) {
2068 error_report("error loading %s: %s", kernel_filename,
2069 load_elf_strerror(spapr->kernel_size));
9fdf0c29
DG		 2070 exit(1);
2071 }
2072
2073 /* load initrd */
2074 if (initrd_filename) {
4d8d5467
BH		 2075 /* Try to locate the initrd in the gap between the kernel
2076 * and the firmware. Add a bit of space just in case
2077 */
a19f7fb0
DG		 2078 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2079 + 0x1ffff) & ~0xffff;
2080 spapr->initrd_size = load_image_targphys(initrd_filename,
2081 spapr->initrd_base,
2082 load_limit
2083 - spapr->initrd_base);
2084 if (spapr->initrd_size < 0) {
d54e4d76
DG		 2085 error_report("could not load initial ram disk '%s'",
2086 initrd_filename);
9fdf0c29
DG		 2087 exit(1);
2088 }
9fdf0c29 2089 }
4d8d5467 2090 }
a3467baa 2091
8e7ea787
AF		 2092 if (bios_name == NULL) {
2093 bios_name = FW_FILE_NAME;
2094 }
2095 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 2096 if (!filename) {
68fea5a0 2097 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 2098 exit(1);
2099 }
4d8d5467 2100 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 2101 if (fw_size <= 0) {
2102 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 2103 exit(1);
2104 }
2105 g_free(filename);
4d8d5467 2106
28e02042
DG		 2107 /* FIXME: Should register things through the MachineState's qdev
2108 * interface, this is a legacy from the sPAPREnvironment structure
2109 * which predated MachineState but had a similar function */
4be21d56
DG		 2110 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2111 register_savevm_live(NULL, "spapr/htab", -1, 1,
2112 &savevm_htab_handlers, spapr);
2113
46503c2b
MR		 2114 /* used by RTAS */
2115 QTAILQ_INIT(&spapr->ccs_list);
2116 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2117
5b2128d2 2118 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 2119}
2120
135a129a
AK		 2121static int spapr_kvm_type(const char *vm_type)
2122{
2123 if (!vm_type) {
2124 return 0;
2125 }
2126
2127 if (!strcmp(vm_type, "HV")) {
2128 return 1;
2129 }
2130
2131 if (!strcmp(vm_type, "PR")) {
2132 return 2;
2133 }
2134
2135 error_report("Unknown kvm-type specified '%s'", vm_type);
2136 exit(1);
2137}
2138
71461b0f 2139/*
627b84f4 2140 * Implementation of an interface to adjust firmware path
71461b0f
AK		 2141 * for the bootindex property handling.
2142 */
2143static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2144 DeviceState *dev)
2145{
2146#define CAST(type, obj, name) \
2147 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2148 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2149 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2150
2151 if (d) {
2152 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2153 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2154 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2155
2156 if (spapr) {
2157 /*
2158 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2159 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2160 * in the top 16 bits of the 64-bit LUN
2161 */
2162 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2163 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2164 (uint64_t)id << 48);
2165 } else if (virtio) {
2166 /*
2167 * We use SRP luns of the form 01000000 | (target << 8) | lun
2168 * in the top 32 bits of the 64-bit LUN
2169 * Note: the quote above is from SLOF and it is wrong,
2170 * the actual binding is:
2171 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2172 */
2173 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2174 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2175 (uint64_t)id << 32);
2176 } else if (usb) {
2177 /*
2178 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2179 * in the top 32 bits of the 64-bit LUN
2180 */
2181 unsigned usb_port = atoi(usb->port->path);
2182 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2183 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2184 (uint64_t)id << 32);
2185 }
2186 }
2187
2188 if (phb) {
2189 /* Replace "pci" with "pci@800000020000000" */
2190 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2191 }
2192
2193 return NULL;
2194}
2195
23825581
EH		 2196static char *spapr_get_kvm_type(Object *obj, Error **errp)
2197{
28e02042 2198 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2199
28e02042 2200 return g_strdup(spapr->kvm_type);
23825581
EH		 2201}
2202
2203static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2204{
28e02042 2205 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2206
28e02042
DG		 2207 g_free(spapr->kvm_type);
2208 spapr->kvm_type = g_strdup(value);
23825581
EH		 2209}
2210
f6229214
MR		 2211static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2212{
2213 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2214
2215 return spapr->use_hotplug_event_source;
2216}
2217
2218static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2219 Error **errp)
2220{
2221 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2222
2223 spapr->use_hotplug_event_source = value;
2224}
2225
23825581
EH		 2226static void spapr_machine_initfn(Object *obj)
2227{
715c5407
DG		 2228 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2229
2230 spapr->htab_fd = -1;
f6229214 2231 spapr->use_hotplug_event_source = true;
23825581
EH		 2232 object_property_add_str(obj, "kvm-type",
2233 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2234 object_property_set_description(obj, "kvm-type",
2235 "Specifies the KVM virtualization mode (HV, PR)",
2236 NULL);
f6229214
MR		 2237 object_property_add_bool(obj, "modern-hotplug-events",
2238 spapr_get_modern_hotplug_events,
2239 spapr_set_modern_hotplug_events,
2240 NULL);
2241 object_property_set_description(obj, "modern-hotplug-events",
2242 "Use dedicated hotplug event mechanism in"
2243 " place of standard EPOW events when possible"
2244 " (required for memory hot-unplug support)",
2245 NULL);
23825581
EH		 2246}
2247
87bbdd9c
DG		 2248static void spapr_machine_finalizefn(Object *obj)
2249{
2250 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2251
2252 g_free(spapr->kvm_type);
2253}
2254
14e6fe12 2255static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
34316482 2256{
34316482
AK		 2257 cpu_synchronize_state(cs);
2258 ppc_cpu_do_system_reset(cs);
2259}
2260
2261static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2262{
2263 CPUState *cs;
2264
2265 CPU_FOREACH(cs) {
14e6fe12 2266 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
34316482
AK		 2267 }
2268}
2269
79b78a6b
MR		 2270static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2271 uint32_t node, bool dedicated_hp_event_source,
2272 Error **errp)
c20d332a
BR		 2273{
2274 sPAPRDRConnector *drc;
2275 sPAPRDRConnectorClass *drck;
2276 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2277 int i, fdt_offset, fdt_size;
2278 void *fdt;
79b78a6b 2279 uint64_t addr = addr_start;
c20d332a 2280
c20d332a
BR		 2281 for (i = 0; i < nr_lmbs; i++) {
2282 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2283 addr/SPAPR_MEMORY_BLOCK_SIZE);
2284 g_assert(drc);
2285
2286 fdt = create_device_tree(&fdt_size);
2287 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2288 SPAPR_MEMORY_BLOCK_SIZE);
2289
2290 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2291 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2292 addr += SPAPR_MEMORY_BLOCK_SIZE;
2293 }
5dd5238c
JD		 2294 /* send hotplug notification to the
2295 * guest only in case of hotplugged memory
2296 */
2297 if (dev->hotplugged) {
79b78a6b
MR		 2298 if (dedicated_hp_event_source) {
2299 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2300 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2301 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2302 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2303 nr_lmbs,
2304 drck->get_index(drc));
2305 } else {
2306 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2307 nr_lmbs);
2308 }
5dd5238c 2309 }
c20d332a
BR		 2310}
2311
2312static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2313 uint32_t node, Error **errp)
2314{
2315 Error *local_err = NULL;
2316 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2317 PCDIMMDevice *dimm = PC_DIMM(dev);
2318 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2319 MemoryRegion *mr = ddc->get_memory_region(dimm);
2320 uint64_t align = memory_region_get_alignment(mr);
2321 uint64_t size = memory_region_size(mr);
2322 uint64_t addr;
2323
2324 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2325 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2326 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2327 goto out;
2328 }
2329
d6a9b0b8 2330 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
c20d332a
BR		 2331 if (local_err) {
2332 goto out;
2333 }
2334
2335 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2336 if (local_err) {
2337 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2338 goto out;
2339 }
2340
79b78a6b
MR		 2341 spapr_add_lmbs(dev, addr, size, node,
2342 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2343 &error_abort);
c20d332a
BR		 2344
2345out:
2346 error_propagate(errp, local_err);
2347}
2348
cf632463
BR		 2349typedef struct sPAPRDIMMState {
2350 uint32_t nr_lmbs;
2351} sPAPRDIMMState;
2352
2353static void spapr_lmb_release(DeviceState *dev, void *opaque)
2354{
2355 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque;
2356 HotplugHandler *hotplug_ctrl;
2357
2358 if (--ds->nr_lmbs) {
2359 return;
2360 }
2361
2362 g_free(ds);
2363
2364 /*
2365 * Now that all the LMBs have been removed by the guest, call the
2366 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2367 */
2368 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2369 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2370}
2371
2372static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2373 Error **errp)
2374{
2375 sPAPRDRConnector *drc;
2376 sPAPRDRConnectorClass *drck;
2377 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2378 int i;
2379 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState));
2380 uint64_t addr = addr_start;
2381
2382 ds->nr_lmbs = nr_lmbs;
2383 for (i = 0; i < nr_lmbs; i++) {
2384 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2385 addr / SPAPR_MEMORY_BLOCK_SIZE);
2386 g_assert(drc);
2387
2388 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2389 drck->detach(drc, dev, spapr_lmb_release, ds, errp);
2390 addr += SPAPR_MEMORY_BLOCK_SIZE;
2391 }
2392
2393 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2394 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2395 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2396 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2397 nr_lmbs,
2398 drck->get_index(drc));
2399}
2400
2401static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2402 Error **errp)
2403{
2404 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2405 PCDIMMDevice *dimm = PC_DIMM(dev);
2406 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2407 MemoryRegion *mr = ddc->get_memory_region(dimm);
2408
2409 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2410 object_unparent(OBJECT(dev));
2411}
2412
2413static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2414 DeviceState *dev, Error **errp)
2415{
2416 Error *local_err = NULL;
2417 PCDIMMDevice *dimm = PC_DIMM(dev);
2418 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2419 MemoryRegion *mr = ddc->get_memory_region(dimm);
2420 uint64_t size = memory_region_size(mr);
2421 uint64_t addr;
2422
2423 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2424 if (local_err) {
2425 goto out;
2426 }
2427
2428 spapr_del_lmbs(dev, addr, size, &error_abort);
2429out:
2430 error_propagate(errp, local_err);
2431}
2432
af81cf32
BR		 2433void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2434 sPAPRMachineState *spapr)
2435{
2436 PowerPCCPU *cpu = POWERPC_CPU(cs);
2437 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2438 int id = ppc_get_vcpu_dt_id(cpu);
2439 void *fdt;
2440 int offset, fdt_size;
2441 char *nodename;
2442
2443 fdt = create_device_tree(&fdt_size);
2444 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2445 offset = fdt_add_subnode(fdt, 0, nodename);
2446
2447 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2448 g_free(nodename);
2449
2450 *fdt_offset = offset;
2451 return fdt;
2452}
2453
c20d332a
BR		 2454static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2455 DeviceState *dev, Error **errp)
2456{
2457 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2458
2459 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2460 int node;
c20d332a
BR		 2461
2462 if (!smc->dr_lmb_enabled) {
2463 error_setg(errp, "Memory hotplug not supported for this machine");
2464 return;
2465 }
2466 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2467 if (*errp) {
2468 return;
2469 }
1a5512bb
GA		 2470 if (node < 0 || node >= MAX_NODES) {
2471 error_setg(errp, "Invaild node %d", node);
2472 return;
2473 }
c20d332a 2474
b556854b
BR		 2475 /*
2476 * Currently PowerPC kernel doesn't allow hot-adding memory to
2477 * memory-less node, but instead will silently add the memory
2478 * to the first node that has some memory. This causes two
2479 * unexpected behaviours for the user.
2480 *
2481 * - Memory gets hotplugged to a different node than what the user
2482 * specified.
2483 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2484 * to memory-less node, a reboot will set things accordingly
2485 * and the previously hotplugged memory now ends in the right node.
2486 * This appears as if some memory moved from one node to another.
2487 *
2488 * So until kernel starts supporting memory hotplug to memory-less
2489 * nodes, just prevent such attempts upfront in QEMU.
2490 */
2491 if (nb_numa_nodes && !numa_info[node].node_mem) {
2492 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2493 node);
2494 return;
2495 }
2496
c20d332a 2497 spapr_memory_plug(hotplug_dev, dev, node, errp);
af81cf32
BR		 2498 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2499 spapr_core_plug(hotplug_dev, dev, errp);
c20d332a
BR		 2500 }
2501}
2502
2503static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2504 DeviceState *dev, Error **errp)
2505{
cf632463 2506 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
3c0c47e3 2507 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
6f4b5c3e 2508
c20d332a 2509 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
cf632463
BR		 2510 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2511 spapr_memory_unplug(hotplug_dev, dev, errp);
2512 } else {
2513 error_setg(errp, "Memory hot unplug not supported for this guest");
2514 }
2515 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2516 if (!mc->query_hotpluggable_cpus) {
2517 error_setg(errp, "CPU hot unplug not supported on this machine");
2518 return;
2519 }
2520 spapr_core_unplug(hotplug_dev, dev, errp);
2521 }
2522}
2523
2524static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
2525 DeviceState *dev, Error **errp)
2526{
2527 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
2528 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
2529
2530 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2531 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
2532 spapr_memory_unplug_request(hotplug_dev, dev, errp);
2533 } else {
2534 /* NOTE: this means there is a window after guest reset, prior to
2535 * CAS negotiation, where unplug requests will fail due to the
2536 * capability not being detected yet. This is a bit different than
2537 * the case with PCI unplug, where the events will be queued and
2538 * eventually handled by the guest after boot
2539 */
2540 error_setg(errp, "Memory hot unplug not supported for this guest");
2541 }
6f4b5c3e 2542 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3c0c47e3 2543 if (!mc->query_hotpluggable_cpus) {
6f4b5c3e
BR		 2544 error_setg(errp, "CPU hot unplug not supported on this machine");
2545 return;
2546 }
2547 spapr_core_unplug(hotplug_dev, dev, errp);
c20d332a
BR		 2548 }
2549}
2550
94a94e4c
BR		 2551static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2552 DeviceState *dev, Error **errp)
2553{
2554 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2555 spapr_core_pre_plug(hotplug_dev, dev, errp);
2556 }
2557}
2558
7ebaf795
BR		 2559static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
2560 DeviceState *dev)
c20d332a 2561{
94a94e4c
BR		 2562 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2563 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
c20d332a
BR		 2564 return HOTPLUG_HANDLER(machine);
2565 }
2566 return NULL;
2567}
2568
20bb648d
DG		 2569static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2570{
2571 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2572 * socket means much for the paravirtualized PAPR platform) */
2573 return cpu_index / smp_threads / smp_cores;
2574}
2575
2474bfd4
IM		 2576static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2577{
2578 int i;
2579 HotpluggableCPUList *head = NULL;
2580 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2581 int spapr_max_cores = max_cpus / smp_threads;
2474bfd4
IM		 2582
2583 for (i = 0; i < spapr_max_cores; i++) {
2584 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2585 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2586 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2587
2588 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2589 cpu_item->vcpus_count = smp_threads;
27393c33 2590 cpu_props->has_core_id = true;
12bf2d33 2591 cpu_props->core_id = i * smp_threads;
2474bfd4
IM		 2592 /* TODO: add 'has_node/node' here to describe
2593 to which node core belongs */
2594
2595 cpu_item->props = cpu_props;
2596 if (spapr->cores[i]) {
2597 cpu_item->has_qom_path = true;
2598 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2599 }
2600 list_item->value = cpu_item;
2601 list_item->next = head;
2602 head = list_item;
2603 }
2604 return head;
2605}
2606
6737d9ad 2607static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
daa23699
DG		 2608 uint64_t *buid, hwaddr *pio,
2609 hwaddr *mmio32, hwaddr *mmio64,
6737d9ad
DG		 2610 unsigned n_dma, uint32_t *liobns, Error **errp)
2611{
357d1e3b
DG		 2612 /*
2613 * New-style PHB window placement.
2614 *
2615 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
2616 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
2617 * windows.
2618 *
2619 * Some guest kernels can't work with MMIO windows above 1<<46
2620 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
2621 *
2622 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
2623 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
2624 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
2625 * 1TiB 64-bit MMIO windows for each PHB.
2626 */
6737d9ad 2627 const uint64_t base_buid = 0x800000020000000ULL;
357d1e3b
DG		 2628 const int max_phbs =
2629 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1;
6737d9ad
DG		 2630 int i;
2631
357d1e3b
DG		 2632 /* Sanity check natural alignments */
2633 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2634 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
2635 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
2636 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
2637 /* Sanity check bounds */
2638 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE);
2639 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE);
2efff1c0 2640
357d1e3b 2641 if (index >= max_phbs) {
6737d9ad 2642 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
357d1e3b 2643 max_phbs - 1);
6737d9ad
DG		 2644 return;
2645 }
2646
2647 *buid = base_buid + index;
2648 for (i = 0; i < n_dma; ++i) {
2649 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2650 }
2651
357d1e3b
DG		 2652 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
2653 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
2654 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
6737d9ad
DG		 2655}
2656
29ee3247
AK		 2657static void spapr_machine_class_init(ObjectClass *oc, void *data)
2658{
2659 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2660 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2661 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2662 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2663 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2664
0eb9054c 2665 mc->desc = "pSeries Logical Partition (PAPR compliant)";
fc9f38c3
DG		 2666
2667 /*
2668 * We set up the default / latest behaviour here. The class_init
2669 * functions for the specific versioned machine types can override
2670 * these details for backwards compatibility
2671 */
958db90c
MA		 2672 mc->init = ppc_spapr_init;
2673 mc->reset = ppc_spapr_reset;
2674 mc->block_default_type = IF_SCSI;
079019f2 2675 mc->max_cpus = 255;
958db90c 2676 mc->no_parallel = 1;
5b2128d2 2677 mc->default_boot_order = "";
a34944fe 2678 mc->default_ram_size = 512 * M_BYTE;
958db90c 2679 mc->kvm_type = spapr_kvm_type;
9e3f9733 2680 mc->has_dynamic_sysbus = true;
e4024630 2681 mc->pci_allow_0_address = true;
7ebaf795 2682 mc->get_hotplug_handler = spapr_get_hotplug_handler;
94a94e4c 2683 hc->pre_plug = spapr_machine_device_pre_plug;
c20d332a
BR		 2684 hc->plug = spapr_machine_device_plug;
2685 hc->unplug = spapr_machine_device_unplug;
20bb648d 2686 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
cf632463 2687 hc->unplug_request = spapr_machine_device_unplug_request;
00b4fbe2 2688
fc9f38c3 2689 smc->dr_lmb_enabled = true;
3daa4a9f 2690 smc->tcg_default_cpu = "POWER8";
3c0c47e3 2691 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
71461b0f 2692 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2693 nc->nmi_monitor_handler = spapr_nmi;
6737d9ad 2694 smc->phb_placement = spapr_phb_placement;
29ee3247
AK		 2695}
2696
2697static const TypeInfo spapr_machine_info = {
2698 .name = TYPE_SPAPR_MACHINE,
2699 .parent = TYPE_MACHINE,
4aee7362 2700 .abstract = true,
6ca1502e 2701 .instance_size = sizeof(sPAPRMachineState),
23825581 2702 .instance_init = spapr_machine_initfn,
87bbdd9c 2703 .instance_finalize = spapr_machine_finalizefn,
183930c0 2704 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2705 .class_init = spapr_machine_class_init,
71461b0f
AK		 2706 .interfaces = (InterfaceInfo[]) {
2707 { TYPE_FW_PATH_PROVIDER },
34316482 2708 { TYPE_NMI },
c20d332a 2709 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2710 { }
2711 },
29ee3247
AK		 2712};
2713
fccbc785 2714#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
5013c547
DG		 2715 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2716 void *data) \
2717 { \
2718 MachineClass *mc = MACHINE_CLASS(oc); \
2719 spapr_machine_##suffix##_class_options(mc); \
fccbc785
DG		 2720 if (latest) { \
2721 mc->alias = "pseries"; \
2722 mc->is_default = 1; \
2723 } \
5013c547
DG		 2724 } \
2725 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2726 { \
2727 MachineState *machine = MACHINE(obj); \
2728 spapr_machine_##suffix##_instance_options(machine); \
2729 } \
2730 static const TypeInfo spapr_machine_##suffix##_info = { \
2731 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2732 .parent = TYPE_SPAPR_MACHINE, \
2733 .class_init = spapr_machine_##suffix##_class_init, \
2734 .instance_init = spapr_machine_##suffix##_instance_init, \
2735 }; \
2736 static void spapr_machine_register_##suffix(void) \
2737 { \
2738 type_register(&spapr_machine_##suffix##_info); \
2739 } \
0e6aac87 2740 type_init(spapr_machine_register_##suffix)
5013c547 2741
db800b21
DG		 2742/*
2743 * pseries-2.8
2744 */
2745static void spapr_machine_2_8_instance_options(MachineState *machine)
2746{
2747}
2748
2749static void spapr_machine_2_8_class_options(MachineClass *mc)
2750{
2751 /* Defaults for the latest behaviour inherited from the base class */
2752}
2753
2754DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
2755
1ea1eefc
BR		 2756/*
2757 * pseries-2.7
2758 */
357d1e3b
DG		 2759#define SPAPR_COMPAT_2_7 \
2760 HW_COMPAT_2_7 \
2761 { \
2762 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2763 .property = "mem_win_size", \
2764 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
2765 }, \
2766 { \
2767 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
2768 .property = "mem64_win_size", \
2769 .value = "0", \
146c11f1
DG		 2770 }, \
2771 { \
2772 .driver = TYPE_POWERPC_CPU, \
2773 .property = "pre-2.8-migration", \
2774 .value = "on", \
357d1e3b
DG		 2775 },
2776
2777static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
2778 uint64_t *buid, hwaddr *pio,
2779 hwaddr *mmio32, hwaddr *mmio64,
2780 unsigned n_dma, uint32_t *liobns, Error **errp)
2781{
2782 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
2783 const uint64_t base_buid = 0x800000020000000ULL;
2784 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
2785 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
2786 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
2787 const uint32_t max_index = 255;
2788 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
2789
2790 uint64_t ram_top = MACHINE(spapr)->ram_size;
2791 hwaddr phb0_base, phb_base;
2792 int i;
2793
2794 /* Do we have hotpluggable memory? */
2795 if (MACHINE(spapr)->maxram_size > ram_top) {
2796 /* Can't just use maxram_size, because there may be an
2797 * alignment gap between normal and hotpluggable memory
2798 * regions */
2799 ram_top = spapr->hotplug_memory.base +
2800 memory_region_size(&spapr->hotplug_memory.mr);
2801 }
2802
2803 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
2804
2805 if (index > max_index) {
2806 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
2807 max_index);
2808 return;
2809 }
2810
2811 *buid = base_buid + index;
2812 for (i = 0; i < n_dma; ++i) {
2813 liobns[i] = SPAPR_PCI_LIOBN(index, i);
2814 }
2815
2816 phb_base = phb0_base + index * phb_spacing;
2817 *pio = phb_base + pio_offset;
2818 *mmio32 = phb_base + mmio_offset;
2819 /*
2820 * We don't set the 64-bit MMIO window, relying on the PHB's
2821 * fallback behaviour of automatically splitting a large "32-bit"
2822 * window into contiguous 32-bit and 64-bit windows
2823 */
2824}
db800b21 2825
1ea1eefc
BR		 2826static void spapr_machine_2_7_instance_options(MachineState *machine)
2827{
f6229214
MR		 2828 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2829
672de881 2830 spapr_machine_2_8_instance_options(machine);
f6229214 2831 spapr->use_hotplug_event_source = false;
1ea1eefc
BR		 2832}
2833
2834static void spapr_machine_2_7_class_options(MachineClass *mc)
2835{
3daa4a9f
TH		 2836 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2837
db800b21 2838 spapr_machine_2_8_class_options(mc);
3daa4a9f 2839 smc->tcg_default_cpu = "POWER7";
db800b21 2840 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
357d1e3b 2841 smc->phb_placement = phb_placement_2_7;
1ea1eefc
BR		 2842}
2843
db800b21 2844DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
1ea1eefc 2845
4b23699c
DG		 2846/*
2847 * pseries-2.6
2848 */
1ea1eefc 2849#define SPAPR_COMPAT_2_6 \
ae4de14c
AK		 2850 HW_COMPAT_2_6 \
2851 { \
2852 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2853 .property = "ddw",\
2854 .value = stringify(off),\
2855 },
1ea1eefc 2856
4b23699c
DG		 2857static void spapr_machine_2_6_instance_options(MachineState *machine)
2858{
672de881 2859 spapr_machine_2_7_instance_options(machine);
4b23699c
DG		 2860}
2861
2862static void spapr_machine_2_6_class_options(MachineClass *mc)
2863{
1ea1eefc 2864 spapr_machine_2_7_class_options(mc);
3c0c47e3 2865 mc->query_hotpluggable_cpus = NULL;
1ea1eefc 2866 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4b23699c
DG		 2867}
2868
1ea1eefc 2869DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4b23699c 2870
1c5f29bb
DG		 2871/*
2872 * pseries-2.5
2873 */
4b23699c 2874#define SPAPR_COMPAT_2_5 \
57c522f4
TH		 2875 HW_COMPAT_2_5 \
2876 { \
2877 .driver = "spapr-vlan", \
2878 .property = "use-rx-buffer-pools", \
2879 .value = "off", \
2880 },
4b23699c 2881
5013c547 2882static void spapr_machine_2_5_instance_options(MachineState *machine)
1c5f29bb 2883{
672de881 2884 spapr_machine_2_6_instance_options(machine);
5013c547
DG		 2885}
2886
2887static void spapr_machine_2_5_class_options(MachineClass *mc)
2888{
57040d45
TH		 2889 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2890
4b23699c 2891 spapr_machine_2_6_class_options(mc);
57040d45 2892 smc->use_ohci_by_default = true;
4b23699c 2893 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
1c5f29bb
DG		 2894}
2895
4b23699c 2896DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
1c5f29bb
DG		 2897
2898/*
2899 * pseries-2.4
2900 */
80fd50f9
CH		 2901#define SPAPR_COMPAT_2_4 \
2902 HW_COMPAT_2_4
2903
5013c547 2904static void spapr_machine_2_4_instance_options(MachineState *machine)
1c5f29bb 2905{
5013c547
DG		 2906 spapr_machine_2_5_instance_options(machine);
2907}
1c5f29bb 2908
5013c547
DG		 2909static void spapr_machine_2_4_class_options(MachineClass *mc)
2910{
fc9f38c3
DG		 2911 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2912
2913 spapr_machine_2_5_class_options(mc);
fc9f38c3 2914 smc->dr_lmb_enabled = false;
f949b4e5 2915 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
1c5f29bb
DG		 2916}
2917
fccbc785 2918DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
1c5f29bb
DG		 2919
2920/*
2921 * pseries-2.3
2922 */
38ff32c6 2923#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2924 HW_COMPAT_2_3 \
2925 {\
2926 .driver = "spapr-pci-host-bridge",\
2927 .property = "dynamic-reconfiguration",\
2928 .value = "off",\
2929 },
38ff32c6 2930
5013c547 2931static void spapr_machine_2_3_instance_options(MachineState *machine)
d25228e7 2932{
5013c547 2933 spapr_machine_2_4_instance_options(machine);
ff14e817 2934 savevm_skip_section_footers();
13d16814 2935 global_state_set_optional();
09b5e30d 2936 savevm_skip_configuration();
d25228e7
JW		 2937}
2938
5013c547 2939static void spapr_machine_2_3_class_options(MachineClass *mc)
6026db45 2940{
fc9f38c3 2941 spapr_machine_2_4_class_options(mc);
f949b4e5 2942 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
6026db45 2943}
fccbc785 2944DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
6026db45 2945
1c5f29bb
DG		 2946/*
2947 * pseries-2.2
2948 */
2949
2950#define SPAPR_COMPAT_2_2 \
1c5f29bb
DG		 2951 HW_COMPAT_2_2 \
2952 {\
2953 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2954 .property = "mem_win_size",\
2955 .value = "0x20000000",\
2956 },
2957
5013c547 2958static void spapr_machine_2_2_instance_options(MachineState *machine)
1c5f29bb 2959{
5013c547 2960 spapr_machine_2_3_instance_options(machine);
cba0e779 2961 machine->suppress_vmdesc = true;
1c5f29bb
DG		 2962}
2963
5013c547 2964static void spapr_machine_2_2_class_options(MachineClass *mc)
4aee7362 2965{
fc9f38c3 2966 spapr_machine_2_3_class_options(mc);
f949b4e5 2967 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4aee7362 2968}
fccbc785 2969DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4aee7362 2970
1c5f29bb
DG		 2971/*
2972 * pseries-2.1
2973 */
2974#define SPAPR_COMPAT_2_1 \
1c5f29bb 2975 HW_COMPAT_2_1
3dab0244 2976
5013c547 2977static void spapr_machine_2_1_instance_options(MachineState *machine)
1c5f29bb 2978{
5013c547 2979 spapr_machine_2_2_instance_options(machine);
1c5f29bb 2980}
d25228e7 2981
5013c547 2982static void spapr_machine_2_1_class_options(MachineClass *mc)
d25228e7 2983{
fc9f38c3 2984 spapr_machine_2_2_class_options(mc);
f949b4e5 2985 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
d25228e7 2986}
fccbc785 2987DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
fb0fc8f6 2988
29ee3247 2989static void spapr_machine_register_types(void)
9fdf0c29 2990{
29ee3247 2991 type_register_static(&spapr_machine_info);
9fdf0c29
DG		 2992}
2993
29ee3247 2994type_init(spapr_machine_register_types)
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