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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
e35704ba | 30 | #include "sysemu/numa.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
03dd024f | 32 | #include "qemu/log.h" |
71461b0f | 33 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 34 | #include "elf.h" |
1422e32d | 35 | #include "net/net.h" |
ad440b4a | 36 | #include "sysemu/device_tree.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 PB |
38 | #include "sysemu/cpus.h" |
39 | #include "sysemu/kvm.h" | |
c20d332a | 40 | #include "sysemu/device_tree.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
ff14e817 | 42 | #include "migration/migration.h" |
4be21d56 | 43 | #include "mmu-hash64.h" |
3794d548 | 44 | #include "qom/cpu.h" |
9fdf0c29 DG |
45 | |
46 | #include "hw/boards.h" | |
0d09e41a | 47 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
48 | #include "hw/loader.h" |
49 | ||
7804c353 | 50 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
51 | #include "hw/ppc/spapr.h" |
52 | #include "hw/ppc/spapr_vio.h" | |
53 | #include "hw/pci-host/spapr.h" | |
54 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 55 | #include "hw/pci/msi.h" |
9fdf0c29 | 56 | |
83c9f4ca | 57 | #include "hw/pci/pci.h" |
71461b0f AK |
58 | #include "hw/scsi/scsi.h" |
59 | #include "hw/virtio/virtio-scsi.h" | |
f61b4bed | 60 | |
022c62cb | 61 | #include "exec/address-spaces.h" |
35139a59 | 62 | #include "hw/usb.h" |
1de7afc9 | 63 | #include "qemu/config-file.h" |
135a129a | 64 | #include "qemu/error-report.h" |
2a6593cb | 65 | #include "trace.h" |
34316482 | 66 | #include "hw/nmi.h" |
890c2b77 | 67 | |
68a27b20 | 68 | #include "hw/compat.h" |
f348b6d1 | 69 | #include "qemu/cutils.h" |
94a94e4c | 70 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 71 | #include "qmp-commands.h" |
68a27b20 | 72 | |
9fdf0c29 DG |
73 | #include <libfdt.h> |
74 | ||
4d8d5467 BH |
75 | /* SLOF memory layout: |
76 | * | |
77 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
78 | * device-tree, then position SLOF itself 31M below that | |
79 | * | |
80 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
81 | * and more | |
82 | * | |
83 | * We load our kernel at 4M, leaving space for SLOF initial image | |
84 | */ | |
38b02bd8 | 85 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 86 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 87 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
88 | #define FW_MAX_SIZE 0x400000 |
89 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
90 | #define FW_OVERHEAD 0x2800000 |
91 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 92 | |
4d8d5467 | 93 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 94 | |
0c103f8e DG |
95 | #define PHANDLE_XICP 0x00001111 |
96 | ||
7f763a5d DG |
97 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
98 | ||
c04d6cfa | 99 | static XICSState *try_create_xics(const char *type, int nr_servers, |
34f2af3d | 100 | int nr_irqs, Error **errp) |
c04d6cfa | 101 | { |
34f2af3d | 102 | Error *err = NULL; |
c04d6cfa AL |
103 | DeviceState *dev; |
104 | ||
105 | dev = qdev_create(NULL, type); | |
106 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
107 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
34f2af3d MA |
108 | object_property_set_bool(OBJECT(dev), true, "realized", &err); |
109 | if (err) { | |
110 | error_propagate(errp, err); | |
111 | object_unparent(OBJECT(dev)); | |
c04d6cfa AL |
112 | return NULL; |
113 | } | |
5a3d7b23 | 114 | return XICS_COMMON(dev); |
c04d6cfa AL |
115 | } |
116 | ||
446f16a6 | 117 | static XICSState *xics_system_init(MachineState *machine, |
1e49182d | 118 | int nr_servers, int nr_irqs, Error **errp) |
c04d6cfa | 119 | { |
27f24582 | 120 | XICSState *xics = NULL; |
c04d6cfa | 121 | |
11ad93f6 | 122 | if (kvm_enabled()) { |
34f2af3d MA |
123 | Error *err = NULL; |
124 | ||
446f16a6 | 125 | if (machine_kernel_irqchip_allowed(machine)) { |
27f24582 BH |
126 | xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, |
127 | &err); | |
11ad93f6 | 128 | } |
27f24582 | 129 | if (machine_kernel_irqchip_required(machine) && !xics) { |
b83baa60 MA |
130 | error_reportf_err(err, |
131 | "kernel_irqchip requested but unavailable: "); | |
132 | } else { | |
133 | error_free(err); | |
11ad93f6 DG |
134 | } |
135 | } | |
136 | ||
27f24582 BH |
137 | if (!xics) { |
138 | xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); | |
c04d6cfa AL |
139 | } |
140 | ||
27f24582 | 141 | return xics; |
c04d6cfa AL |
142 | } |
143 | ||
833d4668 AK |
144 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
145 | int smt_threads) | |
146 | { | |
147 | int i, ret = 0; | |
148 | uint32_t servers_prop[smt_threads]; | |
149 | uint32_t gservers_prop[smt_threads * 2]; | |
150 | int index = ppc_get_vcpu_dt_id(cpu); | |
151 | ||
6d9412ea | 152 | if (cpu->cpu_version) { |
4bce526e | 153 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); |
6d9412ea AK |
154 | if (ret < 0) { |
155 | return ret; | |
156 | } | |
157 | } | |
158 | ||
833d4668 AK |
159 | /* Build interrupt servers and gservers properties */ |
160 | for (i = 0; i < smt_threads; i++) { | |
161 | servers_prop[i] = cpu_to_be32(index + i); | |
162 | /* Hack, direct the group queues back to cpu 0 */ | |
163 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
164 | gservers_prop[i*2 + 1] = 0; | |
165 | } | |
166 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
167 | servers_prop, sizeof(servers_prop)); | |
168 | if (ret < 0) { | |
169 | return ret; | |
170 | } | |
171 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
172 | gservers_prop, sizeof(gservers_prop)); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
0da6f3fe BR |
177 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) |
178 | { | |
179 | int ret = 0; | |
180 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
181 | int index = ppc_get_vcpu_dt_id(cpu); | |
182 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
183 | cpu_to_be32(0x0), | |
184 | cpu_to_be32(0x0), | |
185 | cpu_to_be32(0x0), | |
186 | cpu_to_be32(cs->numa_node), | |
187 | cpu_to_be32(index)}; | |
188 | ||
189 | /* Advertise NUMA via ibm,associativity */ | |
190 | if (nb_numa_nodes > 1) { | |
191 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
192 | sizeof(associativity)); | |
193 | } | |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
28e02042 | 198 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 199 | { |
82677ed2 AK |
200 | int ret = 0, offset, cpus_offset; |
201 | CPUState *cs; | |
6e806cc3 BR |
202 | char cpu_model[32]; |
203 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 204 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 205 | |
82677ed2 AK |
206 | CPU_FOREACH(cs) { |
207 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
208 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
209 | int index = ppc_get_vcpu_dt_id(cpu); | |
6e806cc3 | 210 | |
0f20ba62 | 211 | if ((index % smt) != 0) { |
6e806cc3 BR |
212 | continue; |
213 | } | |
214 | ||
82677ed2 | 215 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 216 | |
82677ed2 AK |
217 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
218 | if (cpus_offset < 0) { | |
219 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
220 | "cpus"); | |
221 | if (cpus_offset < 0) { | |
222 | return cpus_offset; | |
223 | } | |
224 | } | |
225 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 226 | if (offset < 0) { |
82677ed2 AK |
227 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
228 | if (offset < 0) { | |
229 | return offset; | |
230 | } | |
6e806cc3 BR |
231 | } |
232 | ||
7f763a5d DG |
233 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
234 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
235 | if (ret < 0) { |
236 | return ret; | |
237 | } | |
833d4668 | 238 | |
0da6f3fe BR |
239 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); |
240 | if (ret < 0) { | |
241 | return ret; | |
242 | } | |
243 | ||
82677ed2 | 244 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, |
2a48d993 | 245 | ppc_get_compat_smt_threads(cpu)); |
833d4668 AK |
246 | if (ret < 0) { |
247 | return ret; | |
248 | } | |
6e806cc3 BR |
249 | } |
250 | return ret; | |
251 | } | |
252 | ||
b082d65a AK |
253 | static hwaddr spapr_node0_size(void) |
254 | { | |
fb164994 DG |
255 | MachineState *machine = MACHINE(qdev_get_machine()); |
256 | ||
b082d65a AK |
257 | if (nb_numa_nodes) { |
258 | int i; | |
259 | for (i = 0; i < nb_numa_nodes; ++i) { | |
260 | if (numa_info[i].node_mem) { | |
fb164994 DG |
261 | return MIN(pow2floor(numa_info[i].node_mem), |
262 | machine->ram_size); | |
b082d65a AK |
263 | } |
264 | } | |
265 | } | |
fb164994 | 266 | return machine->ram_size; |
b082d65a AK |
267 | } |
268 | ||
a1d59c0f AK |
269 | static void add_str(GString *s, const gchar *s1) |
270 | { | |
271 | g_string_append_len(s, s1, strlen(s1) + 1); | |
272 | } | |
7f763a5d | 273 | |
03d196b7 | 274 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
275 | hwaddr size) |
276 | { | |
277 | uint32_t associativity[] = { | |
278 | cpu_to_be32(0x4), /* length */ | |
279 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 280 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
281 | }; |
282 | char mem_name[32]; | |
283 | uint64_t mem_reg_property[2]; | |
284 | int off; | |
285 | ||
286 | mem_reg_property[0] = cpu_to_be64(start); | |
287 | mem_reg_property[1] = cpu_to_be64(size); | |
288 | ||
289 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
290 | off = fdt_add_subnode(fdt, 0, mem_name); | |
291 | _FDT(off); | |
292 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
293 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
294 | sizeof(mem_reg_property)))); | |
295 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
296 | sizeof(associativity)))); | |
03d196b7 | 297 | return off; |
26a8c353 AK |
298 | } |
299 | ||
28e02042 | 300 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 301 | { |
fb164994 | 302 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
303 | hwaddr mem_start, node_size; |
304 | int i, nb_nodes = nb_numa_nodes; | |
305 | NodeInfo *nodes = numa_info; | |
306 | NodeInfo ramnode; | |
307 | ||
308 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
309 | if (!nb_numa_nodes) { | |
310 | nb_nodes = 1; | |
fb164994 | 311 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 312 | nodes = &ramnode; |
5fe269b1 | 313 | } |
7f763a5d | 314 | |
7db8a127 AK |
315 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
316 | if (!nodes[i].node_mem) { | |
317 | continue; | |
318 | } | |
fb164994 | 319 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
320 | node_size = 0; |
321 | } else { | |
7db8a127 | 322 | node_size = nodes[i].node_mem; |
fb164994 DG |
323 | if (node_size > machine->ram_size - mem_start) { |
324 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
325 | } |
326 | } | |
7db8a127 AK |
327 | if (!mem_start) { |
328 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 329 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
330 | mem_start += spapr->rma_size; |
331 | node_size -= spapr->rma_size; | |
332 | } | |
6010818c AK |
333 | for ( ; node_size; ) { |
334 | hwaddr sizetmp = pow2floor(node_size); | |
335 | ||
336 | /* mem_start != 0 here */ | |
337 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
338 | sizetmp = 1ULL << ctzl(mem_start); | |
339 | } | |
340 | ||
341 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
342 | node_size -= sizetmp; | |
343 | mem_start += sizetmp; | |
344 | } | |
7f763a5d DG |
345 | } |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
230bf719 TH |
350 | /* Populate the "ibm,pa-features" property */ |
351 | static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) | |
352 | { | |
353 | uint8_t pa_features_206[] = { 6, 0, | |
354 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
355 | uint8_t pa_features_207[] = { 24, 0, | |
356 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
357 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
358 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
bac3bf28 | 359 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; |
230bf719 TH |
360 | uint8_t *pa_features; |
361 | size_t pa_size; | |
362 | ||
4cbec30d TH |
363 | switch (env->mmu_model) { |
364 | case POWERPC_MMU_2_06: | |
365 | case POWERPC_MMU_2_06a: | |
230bf719 TH |
366 | pa_features = pa_features_206; |
367 | pa_size = sizeof(pa_features_206); | |
4cbec30d TH |
368 | break; |
369 | case POWERPC_MMU_2_07: | |
370 | case POWERPC_MMU_2_07a: | |
230bf719 TH |
371 | pa_features = pa_features_207; |
372 | pa_size = sizeof(pa_features_207); | |
4cbec30d TH |
373 | break; |
374 | default: | |
375 | return; | |
230bf719 TH |
376 | } |
377 | ||
378 | if (env->ci_large_pages) { | |
379 | /* | |
380 | * Note: we keep CI large pages off by default because a 64K capable | |
381 | * guest provisioned with large pages might otherwise try to map a qemu | |
382 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
383 | * even if that qemu runs on a 4k host. | |
384 | * We dd this bit back here if we are confident this is not an issue | |
385 | */ | |
386 | pa_features[3] |= 0x20; | |
387 | } | |
bac3bf28 TH |
388 | if (kvmppc_has_cap_htm() && pa_size > 24) { |
389 | pa_features[24] |= 0x80; /* Transactional memory support */ | |
390 | } | |
230bf719 TH |
391 | |
392 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
393 | } | |
394 | ||
0da6f3fe BR |
395 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
396 | sPAPRMachineState *spapr) | |
397 | { | |
398 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
399 | CPUPPCState *env = &cpu->env; | |
400 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
401 | int index = ppc_get_vcpu_dt_id(cpu); | |
402 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
403 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
404 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
405 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
406 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
407 | uint32_t page_sizes_prop[64]; | |
408 | size_t page_sizes_prop_size; | |
22419c2a | 409 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 410 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
af81cf32 BR |
411 | sPAPRDRConnector *drc; |
412 | sPAPRDRConnectorClass *drck; | |
413 | int drc_index; | |
414 | ||
415 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); | |
416 | if (drc) { | |
417 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
418 | drc_index = drck->get_index(drc); | |
419 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); | |
420 | } | |
0da6f3fe BR |
421 | |
422 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
423 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
424 | ||
425 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
426 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
427 | env->dcache_line_size))); | |
428 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
429 | env->dcache_line_size))); | |
430 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
431 | env->icache_line_size))); | |
432 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
433 | env->icache_line_size))); | |
434 | ||
435 | if (pcc->l1_dcache_size) { | |
436 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
437 | pcc->l1_dcache_size))); | |
438 | } else { | |
ce9863b7 | 439 | error_report("Warning: Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
440 | } |
441 | if (pcc->l1_icache_size) { | |
442 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
443 | pcc->l1_icache_size))); | |
444 | } else { | |
ce9863b7 | 445 | error_report("Warning: Unknown L1 icache size for cpu"); |
0da6f3fe BR |
446 | } |
447 | ||
448 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
449 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 450 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
451 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
452 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
453 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
454 | ||
455 | if (env->spr_cb[SPR_PURR].oea_read) { | |
456 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
457 | } | |
458 | ||
459 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
460 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
461 | segs, sizeof(segs)))); | |
462 | } | |
463 | ||
464 | /* Advertise VMX/VSX (vector extensions) if available | |
465 | * 0 / no property == no vector extensions | |
466 | * 1 == VMX / Altivec available | |
467 | * 2 == VSX available */ | |
468 | if (env->insns_flags & PPC_ALTIVEC) { | |
469 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
470 | ||
471 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
472 | } | |
473 | ||
474 | /* Advertise DFP (Decimal Floating Point) if available | |
475 | * 0 / no property == no DFP | |
476 | * 1 == DFP available */ | |
477 | if (env->insns_flags2 & PPC2_DFP) { | |
478 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
479 | } | |
480 | ||
3654fa95 | 481 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
482 | sizeof(page_sizes_prop)); |
483 | if (page_sizes_prop_size) { | |
484 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
485 | page_sizes_prop, page_sizes_prop_size))); | |
486 | } | |
487 | ||
230bf719 | 488 | spapr_populate_pa_features(env, fdt, offset); |
90da0d5a | 489 | |
0da6f3fe | 490 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 491 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
492 | |
493 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
494 | pft_size_prop, sizeof(pft_size_prop)))); | |
495 | ||
496 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); | |
497 | ||
498 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, | |
499 | ppc_get_compat_smt_threads(cpu))); | |
500 | } | |
501 | ||
502 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
503 | { | |
504 | CPUState *cs; | |
505 | int cpus_offset; | |
506 | char *nodename; | |
507 | int smt = kvmppc_smt_threads(); | |
508 | ||
509 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
510 | _FDT(cpus_offset); | |
511 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
512 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
513 | ||
514 | /* | |
515 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
516 | * created by fdt_add_subnode() end up in the right order in FDT | |
517 | * for the guest kernel the enumerate the CPUs correctly. | |
518 | */ | |
519 | CPU_FOREACH_REVERSE(cs) { | |
520 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
521 | int index = ppc_get_vcpu_dt_id(cpu); | |
522 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
523 | int offset; | |
524 | ||
525 | if ((index % smt) != 0) { | |
526 | continue; | |
527 | } | |
528 | ||
529 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
530 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
531 | g_free(nodename); | |
532 | _FDT(offset); | |
533 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
534 | } | |
535 | ||
536 | } | |
537 | ||
03d196b7 BR |
538 | /* |
539 | * Adds ibm,dynamic-reconfiguration-memory node. | |
540 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
541 | * of this device tree node. | |
542 | */ | |
543 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
544 | { | |
545 | MachineState *machine = MACHINE(spapr); | |
546 | int ret, i, offset; | |
547 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
548 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
549 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
550 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
551 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
552 | lmb_size; | |
03d196b7 | 553 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 554 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 555 | |
16c25aef | 556 | /* |
d0e5a8f2 | 557 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 558 | */ |
d0e5a8f2 | 559 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
560 | return 0; |
561 | } | |
562 | ||
ef001f06 TH |
563 | /* |
564 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
565 | * or ibm,associativity-lookup-arrays | |
566 | */ | |
567 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
568 | * sizeof(uint32_t); | |
03d196b7 BR |
569 | cur_index = int_buf = g_malloc0(buf_len); |
570 | ||
571 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
572 | ||
573 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
574 | sizeof(prop_lmb_size)); | |
575 | if (ret < 0) { | |
576 | goto out; | |
577 | } | |
578 | ||
579 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
580 | if (ret < 0) { | |
581 | goto out; | |
582 | } | |
583 | ||
584 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
585 | if (ret < 0) { | |
586 | goto out; | |
587 | } | |
588 | ||
589 | /* ibm,dynamic-memory */ | |
590 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
591 | cur_index++; | |
592 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 593 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
594 | uint32_t *dynamic_memory = cur_index; |
595 | ||
d0e5a8f2 BR |
596 | if (i >= hotplug_lmb_start) { |
597 | sPAPRDRConnector *drc; | |
598 | sPAPRDRConnectorClass *drck; | |
599 | ||
600 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); | |
601 | g_assert(drc); | |
602 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
603 | ||
604 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
605 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
606 | dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); | |
607 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
608 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
609 | if (memory_region_present(get_system_memory(), addr)) { | |
610 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
611 | } else { | |
612 | dynamic_memory[5] = cpu_to_be32(0); | |
613 | } | |
03d196b7 | 614 | } else { |
d0e5a8f2 BR |
615 | /* |
616 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
617 | * hotplug memory region -- all these are marked as reserved | |
618 | * and as having no valid DRC. | |
619 | */ | |
620 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
621 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
622 | dynamic_memory[2] = cpu_to_be32(0); | |
623 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
624 | dynamic_memory[4] = cpu_to_be32(-1); | |
625 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
626 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
627 | } |
628 | ||
629 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
630 | } | |
631 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
632 | if (ret < 0) { | |
633 | goto out; | |
634 | } | |
635 | ||
636 | /* ibm,associativity-lookup-arrays */ | |
637 | cur_index = int_buf; | |
6663864e | 638 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
639 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
640 | cur_index += 2; | |
6663864e | 641 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
642 | uint32_t associativity[] = { |
643 | cpu_to_be32(0x0), | |
644 | cpu_to_be32(0x0), | |
645 | cpu_to_be32(0x0), | |
646 | cpu_to_be32(i) | |
647 | }; | |
648 | memcpy(cur_index, associativity, sizeof(associativity)); | |
649 | cur_index += 4; | |
650 | } | |
651 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
652 | (cur_index - int_buf) * sizeof(uint32_t)); | |
653 | out: | |
654 | g_free(int_buf); | |
655 | return ret; | |
656 | } | |
657 | ||
6787d27b MR |
658 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
659 | sPAPROptionVector *ov5_updates) | |
660 | { | |
661 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 662 | int ret = 0, offset; |
6787d27b MR |
663 | |
664 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
665 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
666 | g_assert(smc->dr_lmb_enabled); | |
667 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
668 | if (ret) { |
669 | goto out; | |
670 | } | |
6787d27b MR |
671 | } |
672 | ||
417ece33 MR |
673 | offset = fdt_path_offset(fdt, "/chosen"); |
674 | if (offset < 0) { | |
675 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
676 | if (offset < 0) { | |
677 | return offset; | |
678 | } | |
679 | } | |
680 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
681 | "ibm,architecture-vec-5"); | |
682 | ||
683 | out: | |
6787d27b MR |
684 | return ret; |
685 | } | |
686 | ||
03d196b7 BR |
687 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
688 | target_ulong addr, target_ulong size, | |
6787d27b MR |
689 | bool cpu_update, |
690 | sPAPROptionVector *ov5_updates) | |
03d196b7 BR |
691 | { |
692 | void *fdt, *fdt_skel; | |
693 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 BR |
694 | |
695 | size -= sizeof(hdr); | |
696 | ||
697 | /* Create sceleton */ | |
698 | fdt_skel = g_malloc0(size); | |
699 | _FDT((fdt_create(fdt_skel, size))); | |
700 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
701 | _FDT((fdt_end_node(fdt_skel))); | |
702 | _FDT((fdt_finish(fdt_skel))); | |
703 | fdt = g_malloc0(size); | |
704 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
705 | g_free(fdt_skel); | |
706 | ||
707 | /* Fixup cpu nodes */ | |
708 | if (cpu_update) { | |
709 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); | |
710 | } | |
711 | ||
6787d27b MR |
712 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
713 | return -1; | |
03d196b7 BR |
714 | } |
715 | ||
716 | /* Pack resulting tree */ | |
717 | _FDT((fdt_pack(fdt))); | |
718 | ||
719 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
720 | trace_spapr_cas_failed(size); | |
721 | return -1; | |
722 | } | |
723 | ||
724 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
725 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
726 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
727 | g_free(fdt); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
3f5dabce DG |
732 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
733 | { | |
734 | int rtas; | |
735 | GString *hypertas = g_string_sized_new(256); | |
736 | GString *qemu_hypertas = g_string_sized_new(256); | |
737 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
738 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
739 | memory_region_size(&spapr->hotplug_memory.mr); | |
740 | uint32_t lrdr_capacity[] = { | |
741 | cpu_to_be32(max_hotplug_addr >> 32), | |
742 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
743 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
744 | cpu_to_be32(max_cpus / smp_threads), | |
745 | }; | |
746 | ||
747 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
748 | ||
749 | /* hypertas */ | |
750 | add_str(hypertas, "hcall-pft"); | |
751 | add_str(hypertas, "hcall-term"); | |
752 | add_str(hypertas, "hcall-dabr"); | |
753 | add_str(hypertas, "hcall-interrupt"); | |
754 | add_str(hypertas, "hcall-tce"); | |
755 | add_str(hypertas, "hcall-vio"); | |
756 | add_str(hypertas, "hcall-splpar"); | |
757 | add_str(hypertas, "hcall-bulk"); | |
758 | add_str(hypertas, "hcall-set-mode"); | |
759 | add_str(hypertas, "hcall-sprg0"); | |
760 | add_str(hypertas, "hcall-copy"); | |
761 | add_str(hypertas, "hcall-debug"); | |
762 | add_str(qemu_hypertas, "hcall-memop1"); | |
763 | ||
764 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
765 | add_str(hypertas, "hcall-multi-tce"); | |
766 | } | |
767 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", | |
768 | hypertas->str, hypertas->len)); | |
769 | g_string_free(hypertas, TRUE); | |
770 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
771 | qemu_hypertas->str, qemu_hypertas->len)); | |
772 | g_string_free(qemu_hypertas, TRUE); | |
773 | ||
774 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
775 | refpoints, sizeof(refpoints))); | |
776 | ||
777 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
778 | RTAS_ERROR_LOG_MAX)); | |
779 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
780 | RTAS_EVENT_SCAN_RATE)); | |
781 | ||
782 | if (msi_nonbroken) { | |
783 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
784 | } | |
785 | ||
786 | /* | |
787 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
788 | * back to the guest cpu. | |
789 | * | |
790 | * While an additional ibm,extended-os-term property indicates | |
791 | * that rtas call return will always occur. Set this property. | |
792 | */ | |
793 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
794 | ||
795 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
796 | lrdr_capacity, sizeof(lrdr_capacity))); | |
797 | ||
798 | spapr_dt_rtas_tokens(fdt, rtas); | |
799 | } | |
800 | ||
7c866c6a DG |
801 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
802 | { | |
803 | MachineState *machine = MACHINE(spapr); | |
804 | int chosen; | |
805 | const char *boot_device = machine->boot_order; | |
806 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
807 | size_t cb = 0; | |
808 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
809 | |
810 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
811 | ||
7c866c6a DG |
812 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
813 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
814 | spapr->initrd_base)); | |
815 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
816 | spapr->initrd_base + spapr->initrd_size)); | |
817 | ||
818 | if (spapr->kernel_size) { | |
819 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
820 | cpu_to_be64(spapr->kernel_size) }; | |
821 | ||
822 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
823 | &kprop, sizeof(kprop))); | |
824 | if (spapr->kernel_le) { | |
825 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
826 | } | |
827 | } | |
828 | if (boot_menu) { | |
829 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
830 | } | |
831 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
832 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
833 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
834 | ||
835 | if (cb && bootlist) { | |
836 | int i; | |
837 | ||
838 | for (i = 0; i < cb; i++) { | |
839 | if (bootlist[i] == '\n') { | |
840 | bootlist[i] = ' '; | |
841 | } | |
842 | } | |
843 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
844 | } | |
845 | ||
846 | if (boot_device && strlen(boot_device)) { | |
847 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
848 | } | |
849 | ||
850 | if (!spapr->has_graphics && stdout_path) { | |
851 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
852 | } | |
853 | ||
854 | g_free(stdout_path); | |
855 | g_free(bootlist); | |
856 | } | |
857 | ||
fca5f2dc DG |
858 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
859 | { | |
860 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
861 | * KVM to work under pHyp with some guest co-operation */ | |
862 | int hypervisor; | |
863 | uint8_t hypercall[16]; | |
864 | ||
865 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
866 | /* indicate KVM hypercall interface */ | |
867 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
868 | if (kvmppc_has_cap_fixup_hcalls()) { | |
869 | /* | |
870 | * Older KVM versions with older guest kernels were broken | |
871 | * with the magic page, don't allow the guest to map it. | |
872 | */ | |
873 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
874 | sizeof(hypercall))) { | |
875 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
876 | hypercall, sizeof(hypercall))); | |
877 | } | |
878 | } | |
879 | } | |
880 | ||
997b6cfc DG |
881 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
882 | hwaddr rtas_addr, | |
883 | hwaddr rtas_size) | |
a3467baa | 884 | { |
5b2128d2 | 885 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c0c47e3 | 886 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 887 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 888 | int ret; |
a3467baa | 889 | void *fdt; |
3384f95c | 890 | sPAPRPHBState *phb; |
398a0bd5 | 891 | char *buf; |
a3467baa | 892 | |
398a0bd5 DG |
893 | fdt = g_malloc0(FDT_MAX_SIZE); |
894 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 895 | |
398a0bd5 DG |
896 | /* Root node */ |
897 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
898 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
899 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
900 | ||
901 | /* | |
902 | * Add info to guest to indentify which host is it being run on | |
903 | * and what is the uuid of the guest | |
904 | */ | |
905 | if (kvmppc_get_host_model(&buf)) { | |
906 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
907 | g_free(buf); | |
908 | } | |
909 | if (kvmppc_get_host_serial(&buf)) { | |
910 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
911 | g_free(buf); | |
912 | } | |
913 | ||
914 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
915 | ||
916 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
917 | if (qemu_uuid_set) { | |
918 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
919 | } | |
920 | g_free(buf); | |
921 | ||
922 | if (qemu_get_vm_name()) { | |
923 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
924 | qemu_get_vm_name())); | |
925 | } | |
926 | ||
927 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
928 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 929 | |
9b9a1908 DG |
930 | /* /interrupt controller */ |
931 | spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP); | |
932 | ||
e8f986fc BR |
933 | ret = spapr_populate_memory(spapr, fdt); |
934 | if (ret < 0) { | |
ce9863b7 | 935 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 936 | exit(1); |
7f763a5d DG |
937 | } |
938 | ||
bf5a6696 DG |
939 | /* /vdevice */ |
940 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 941 | |
4d9392be TH |
942 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
943 | ret = spapr_rng_populate_dt(fdt); | |
944 | if (ret < 0) { | |
ce9863b7 | 945 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
946 | exit(1); |
947 | } | |
948 | } | |
949 | ||
3384f95c | 950 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 951 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
952 | if (ret < 0) { |
953 | error_report("couldn't setup PCI devices in fdt"); | |
954 | exit(1); | |
955 | } | |
3384f95c DG |
956 | } |
957 | ||
0da6f3fe BR |
958 | /* cpus */ |
959 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 960 | |
c20d332a BR |
961 | if (smc->dr_lmb_enabled) { |
962 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
963 | } | |
964 | ||
3c0c47e3 | 965 | if (mc->query_hotpluggable_cpus) { |
af81cf32 BR |
966 | int offset = fdt_path_offset(fdt, "/cpus"); |
967 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
968 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
969 | if (ret < 0) { | |
970 | error_report("Couldn't set up CPU DR device tree properties"); | |
971 | exit(1); | |
972 | } | |
973 | } | |
974 | ||
ffb1e275 | 975 | /* /event-sources */ |
ffbb1705 | 976 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 977 | |
3f5dabce DG |
978 | /* /rtas */ |
979 | spapr_dt_rtas(spapr, fdt); | |
980 | ||
7c866c6a DG |
981 | /* /chosen */ |
982 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 983 | |
fca5f2dc DG |
984 | /* /hypervisor */ |
985 | if (kvm_enabled()) { | |
986 | spapr_dt_hypervisor(spapr, fdt); | |
987 | } | |
988 | ||
cf6e5223 DG |
989 | /* Build memory reserve map */ |
990 | if (spapr->kernel_size) { | |
991 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
992 | } | |
993 | if (spapr->initrd_size) { | |
994 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
995 | } | |
996 | ||
6787d27b MR |
997 | /* ibm,client-architecture-support updates */ |
998 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
999 | if (ret < 0) { | |
1000 | error_report("couldn't setup CAS properties fdt"); | |
1001 | exit(1); | |
1002 | } | |
1003 | ||
997b6cfc | 1004 | return fdt; |
9fdf0c29 DG |
1005 | } |
1006 | ||
1007 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1008 | { | |
1009 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1010 | } | |
1011 | ||
1b14670a | 1012 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 1013 | { |
1b14670a AF |
1014 | CPUPPCState *env = &cpu->env; |
1015 | ||
efcb9383 DG |
1016 | if (msr_pr) { |
1017 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1018 | env->gpr[3] = H_PRIVILEGE; | |
1019 | } else { | |
aa100fa4 | 1020 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1021 | } |
9fdf0c29 DG |
1022 | } |
1023 | ||
e6b8fd24 SMJ |
1024 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1025 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1026 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1027 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1028 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1029 | ||
715c5407 DG |
1030 | /* |
1031 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1032 | */ | |
1033 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1034 | { | |
1035 | if (spapr->htab_fd >= 0) { | |
1036 | return spapr->htab_fd; | |
1037 | } | |
1038 | ||
1039 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1040 | if (spapr->htab_fd < 0) { | |
1041 | error_report("Unable to open fd for reading hash table from KVM: %s", | |
1042 | strerror(errno)); | |
1043 | } | |
1044 | ||
1045 | return spapr->htab_fd; | |
1046 | } | |
1047 | ||
1048 | static void close_htab_fd(sPAPRMachineState *spapr) | |
1049 | { | |
1050 | if (spapr->htab_fd >= 0) { | |
1051 | close(spapr->htab_fd); | |
1052 | } | |
1053 | spapr->htab_fd = -1; | |
1054 | } | |
1055 | ||
8dfe8e7f DG |
1056 | static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1057 | { | |
1058 | int shift; | |
1059 | ||
1060 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1061 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1062 | * that's much more than is needed for Linux guests */ | |
1063 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1064 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1065 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1066 | return shift; | |
1067 | } | |
1068 | ||
c5f54f3e DG |
1069 | static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1070 | Error **errp) | |
7f763a5d | 1071 | { |
c5f54f3e DG |
1072 | long rc; |
1073 | ||
1074 | /* Clean up any HPT info from a previous boot */ | |
1075 | g_free(spapr->htab); | |
1076 | spapr->htab = NULL; | |
1077 | spapr->htab_shift = 0; | |
1078 | close_htab_fd(spapr); | |
1079 | ||
1080 | rc = kvmppc_reset_htab(shift); | |
1081 | if (rc < 0) { | |
1082 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1083 | error_setg_errno(errp, errno, | |
1084 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1085 | shift); | |
1086 | /* This is almost certainly fatal, but if the caller really | |
1087 | * wants to carry on with shift == 0, it's welcome to try */ | |
1088 | } else if (rc > 0) { | |
1089 | /* kernel-side HPT allocated */ | |
1090 | if (rc != shift) { | |
1091 | error_setg(errp, | |
1092 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1093 | shift, rc); | |
7735feda BR |
1094 | } |
1095 | ||
7f763a5d | 1096 | spapr->htab_shift = shift; |
c18ad9a5 | 1097 | spapr->htab = NULL; |
b817772a | 1098 | } else { |
c5f54f3e DG |
1099 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1100 | size_t size = 1ULL << shift; | |
1101 | int i; | |
b817772a | 1102 | |
c5f54f3e DG |
1103 | spapr->htab = qemu_memalign(size, size); |
1104 | if (!spapr->htab) { | |
1105 | error_setg_errno(errp, errno, | |
1106 | "Could not allocate HPT of order %d", shift); | |
1107 | return; | |
7735feda BR |
1108 | } |
1109 | ||
c5f54f3e DG |
1110 | memset(spapr->htab, 0, size); |
1111 | spapr->htab_shift = shift; | |
e6b8fd24 | 1112 | |
c5f54f3e DG |
1113 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1114 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1115 | } |
7f763a5d | 1116 | } |
9fdf0c29 DG |
1117 | } |
1118 | ||
4f01a637 | 1119 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1120 | { |
1121 | bool matched = false; | |
1122 | ||
1123 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1124 | matched = true; | |
1125 | } | |
1126 | ||
1127 | if (!matched) { | |
1128 | error_report("Device %s is not supported by this machine yet.", | |
1129 | qdev_fw_name(DEVICE(sbdev))); | |
1130 | exit(1); | |
1131 | } | |
9e3f9733 AG |
1132 | } |
1133 | ||
c8787ad4 | 1134 | static void ppc_spapr_reset(void) |
a3467baa | 1135 | { |
c5f54f3e DG |
1136 | MachineState *machine = MACHINE(qdev_get_machine()); |
1137 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1138 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1139 | uint32_t rtas_limit; |
cae172ab | 1140 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1141 | void *fdt; |
1142 | int rc; | |
259186a7 | 1143 | |
9e3f9733 AG |
1144 | /* Check for unknown sysbus devices */ |
1145 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1146 | ||
c5f54f3e DG |
1147 | /* Allocate and/or reset the hash page table */ |
1148 | spapr_reallocate_hpt(spapr, | |
1149 | spapr_hpt_shift_for_ramsize(machine->maxram_size), | |
1150 | &error_fatal); | |
1151 | ||
1152 | /* Update the RMA size if necessary */ | |
1153 | if (spapr->vrma_adjust) { | |
1154 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), | |
1155 | spapr->htab_shift); | |
1156 | } | |
a3467baa | 1157 | |
c8787ad4 | 1158 | qemu_devices_reset(); |
a3467baa | 1159 | |
b7d1f77a BH |
1160 | /* |
1161 | * We place the device tree and RTAS just below either the top of the RMA, | |
1162 | * or just below 2GB, whichever is lowere, so that it can be | |
1163 | * processed with 32-bit real mode code if necessary | |
1164 | */ | |
1165 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1166 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1167 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1168 | |
6787d27b MR |
1169 | /* if this reset wasn't generated by CAS, we should reset our |
1170 | * negotiated options and start from scratch */ | |
1171 | if (!spapr->cas_reboot) { | |
1172 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1173 | spapr->ov5_cas = spapr_ovec_new(); | |
1174 | } | |
1175 | ||
cae172ab | 1176 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1177 | |
2cac78c1 | 1178 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1179 | |
997b6cfc DG |
1180 | rc = fdt_pack(fdt); |
1181 | ||
1182 | /* Should only fail if we've built a corrupted tree */ | |
1183 | assert(rc == 0); | |
1184 | ||
1185 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1186 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1187 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1188 | exit(1); | |
1189 | } | |
1190 | ||
1191 | /* Load the fdt */ | |
1192 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1193 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1194 | g_free(fdt); |
1195 | ||
a3467baa | 1196 | /* Set up the entry state */ |
182735ef | 1197 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
cae172ab | 1198 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1199 | first_ppc_cpu->env.gpr[5] = 0; |
1200 | first_cpu->halted = 0; | |
1b718907 | 1201 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1202 | |
6787d27b | 1203 | spapr->cas_reboot = false; |
a3467baa DG |
1204 | } |
1205 | ||
28e02042 | 1206 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1207 | { |
2ff3de68 | 1208 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1209 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1210 | |
3978b863 | 1211 | if (dinfo) { |
6231a6da MA |
1212 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1213 | &error_fatal); | |
639e8102 DG |
1214 | } |
1215 | ||
1216 | qdev_init_nofail(dev); | |
1217 | ||
1218 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1219 | } | |
1220 | ||
28e02042 | 1221 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 DG |
1222 | { |
1223 | DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); | |
1224 | ||
1225 | qdev_init_nofail(dev); | |
1226 | spapr->rtc = dev; | |
74e5ae28 DG |
1227 | |
1228 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
1229 | OBJECT(spapr->rtc), "date", NULL); | |
28df36a1 DG |
1230 | } |
1231 | ||
8c57b867 | 1232 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1233 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1234 | { |
8c57b867 | 1235 | switch (vga_interface_type) { |
8c57b867 | 1236 | case VGA_NONE: |
7effdaa3 MW |
1237 | return false; |
1238 | case VGA_DEVICE: | |
1239 | return true; | |
1ddcae82 | 1240 | case VGA_STD: |
b798c190 | 1241 | case VGA_VIRTIO: |
1ddcae82 | 1242 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1243 | default: |
14c6a894 DG |
1244 | error_setg(errp, |
1245 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1246 | return false; | |
f28359d8 | 1247 | } |
f28359d8 LZ |
1248 | } |
1249 | ||
880ae7de DG |
1250 | static int spapr_post_load(void *opaque, int version_id) |
1251 | { | |
28e02042 | 1252 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1253 | int err = 0; |
1254 | ||
631b22ea | 1255 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1256 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1257 | * So when migrating from those versions, poke the incoming offset | |
1258 | * value into the RTC device */ | |
1259 | if (version_id < 3) { | |
1260 | err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); | |
1261 | } | |
1262 | ||
1263 | return err; | |
1264 | } | |
1265 | ||
1266 | static bool version_before_3(void *opaque, int version_id) | |
1267 | { | |
1268 | return version_id < 3; | |
1269 | } | |
1270 | ||
4be21d56 DG |
1271 | static const VMStateDescription vmstate_spapr = { |
1272 | .name = "spapr", | |
880ae7de | 1273 | .version_id = 3, |
4be21d56 | 1274 | .minimum_version_id = 1, |
880ae7de | 1275 | .post_load = spapr_post_load, |
3aff6c2f | 1276 | .fields = (VMStateField[]) { |
880ae7de DG |
1277 | /* used to be @next_irq */ |
1278 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1279 | |
1280 | /* RTC offset */ | |
28e02042 | 1281 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1282 | |
28e02042 | 1283 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1284 | VMSTATE_END_OF_LIST() |
1285 | }, | |
1286 | }; | |
1287 | ||
4be21d56 DG |
1288 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1289 | { | |
28e02042 | 1290 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1291 | |
4be21d56 DG |
1292 | /* "Iteration" header */ |
1293 | qemu_put_be32(f, spapr->htab_shift); | |
1294 | ||
e68cb8b4 AK |
1295 | if (spapr->htab) { |
1296 | spapr->htab_save_index = 0; | |
1297 | spapr->htab_first_pass = true; | |
1298 | } else { | |
1299 | assert(kvm_enabled()); | |
e68cb8b4 AK |
1300 | } |
1301 | ||
1302 | ||
4be21d56 DG |
1303 | return 0; |
1304 | } | |
1305 | ||
28e02042 | 1306 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1307 | int64_t max_ns) |
1308 | { | |
378bc217 | 1309 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1310 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1311 | int index = spapr->htab_save_index; | |
bc72ad67 | 1312 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1313 | |
1314 | assert(spapr->htab_first_pass); | |
1315 | ||
1316 | do { | |
1317 | int chunkstart; | |
1318 | ||
1319 | /* Consume invalid HPTEs */ | |
1320 | while ((index < htabslots) | |
1321 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1322 | index++; | |
1323 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1324 | } | |
1325 | ||
1326 | /* Consume valid HPTEs */ | |
1327 | chunkstart = index; | |
338c25b6 | 1328 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1329 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
1330 | index++; | |
1331 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1332 | } | |
1333 | ||
1334 | if (index > chunkstart) { | |
1335 | int n_valid = index - chunkstart; | |
1336 | ||
1337 | qemu_put_be32(f, chunkstart); | |
1338 | qemu_put_be16(f, n_valid); | |
1339 | qemu_put_be16(f, 0); | |
1340 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1341 | HASH_PTE_SIZE_64 * n_valid); | |
1342 | ||
378bc217 DG |
1343 | if (has_timeout && |
1344 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1345 | break; |
1346 | } | |
1347 | } | |
1348 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1349 | ||
1350 | if (index >= htabslots) { | |
1351 | assert(index == htabslots); | |
1352 | index = 0; | |
1353 | spapr->htab_first_pass = false; | |
1354 | } | |
1355 | spapr->htab_save_index = index; | |
1356 | } | |
1357 | ||
28e02042 | 1358 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1359 | int64_t max_ns) |
4be21d56 DG |
1360 | { |
1361 | bool final = max_ns < 0; | |
1362 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1363 | int examined = 0, sent = 0; | |
1364 | int index = spapr->htab_save_index; | |
bc72ad67 | 1365 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1366 | |
1367 | assert(!spapr->htab_first_pass); | |
1368 | ||
1369 | do { | |
1370 | int chunkstart, invalidstart; | |
1371 | ||
1372 | /* Consume non-dirty HPTEs */ | |
1373 | while ((index < htabslots) | |
1374 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1375 | index++; | |
1376 | examined++; | |
1377 | } | |
1378 | ||
1379 | chunkstart = index; | |
1380 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1381 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1382 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1383 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1384 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1385 | index++; | |
1386 | examined++; | |
1387 | } | |
1388 | ||
1389 | invalidstart = index; | |
1390 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1391 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1392 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1393 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1394 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1395 | index++; | |
1396 | examined++; | |
1397 | } | |
1398 | ||
1399 | if (index > chunkstart) { | |
1400 | int n_valid = invalidstart - chunkstart; | |
1401 | int n_invalid = index - invalidstart; | |
1402 | ||
1403 | qemu_put_be32(f, chunkstart); | |
1404 | qemu_put_be16(f, n_valid); | |
1405 | qemu_put_be16(f, n_invalid); | |
1406 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1407 | HASH_PTE_SIZE_64 * n_valid); | |
1408 | sent += index - chunkstart; | |
1409 | ||
bc72ad67 | 1410 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1411 | break; |
1412 | } | |
1413 | } | |
1414 | ||
1415 | if (examined >= htabslots) { | |
1416 | break; | |
1417 | } | |
1418 | ||
1419 | if (index >= htabslots) { | |
1420 | assert(index == htabslots); | |
1421 | index = 0; | |
1422 | } | |
1423 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1424 | ||
1425 | if (index >= htabslots) { | |
1426 | assert(index == htabslots); | |
1427 | index = 0; | |
1428 | } | |
1429 | ||
1430 | spapr->htab_save_index = index; | |
1431 | ||
e68cb8b4 | 1432 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1433 | } |
1434 | ||
e68cb8b4 AK |
1435 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1436 | #define MAX_KVM_BUF_SIZE 2048 | |
1437 | ||
4be21d56 DG |
1438 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1439 | { | |
28e02042 | 1440 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1441 | int fd; |
e68cb8b4 | 1442 | int rc = 0; |
4be21d56 DG |
1443 | |
1444 | /* Iteration header */ | |
1445 | qemu_put_be32(f, 0); | |
1446 | ||
e68cb8b4 AK |
1447 | if (!spapr->htab) { |
1448 | assert(kvm_enabled()); | |
1449 | ||
715c5407 DG |
1450 | fd = get_htab_fd(spapr); |
1451 | if (fd < 0) { | |
1452 | return fd; | |
01a57972 SMJ |
1453 | } |
1454 | ||
715c5407 | 1455 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1456 | if (rc < 0) { |
1457 | return rc; | |
1458 | } | |
1459 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1460 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1461 | } else { | |
e68cb8b4 | 1462 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1463 | } |
1464 | ||
1465 | /* End marker */ | |
1466 | qemu_put_be32(f, 0); | |
1467 | qemu_put_be16(f, 0); | |
1468 | qemu_put_be16(f, 0); | |
1469 | ||
e68cb8b4 | 1470 | return rc; |
4be21d56 DG |
1471 | } |
1472 | ||
1473 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1474 | { | |
28e02042 | 1475 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1476 | int fd; |
4be21d56 DG |
1477 | |
1478 | /* Iteration header */ | |
1479 | qemu_put_be32(f, 0); | |
1480 | ||
e68cb8b4 AK |
1481 | if (!spapr->htab) { |
1482 | int rc; | |
1483 | ||
1484 | assert(kvm_enabled()); | |
1485 | ||
715c5407 DG |
1486 | fd = get_htab_fd(spapr); |
1487 | if (fd < 0) { | |
1488 | return fd; | |
01a57972 SMJ |
1489 | } |
1490 | ||
715c5407 | 1491 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1492 | if (rc < 0) { |
1493 | return rc; | |
1494 | } | |
e68cb8b4 | 1495 | } else { |
378bc217 DG |
1496 | if (spapr->htab_first_pass) { |
1497 | htab_save_first_pass(f, spapr, -1); | |
1498 | } | |
e68cb8b4 AK |
1499 | htab_save_later_pass(f, spapr, -1); |
1500 | } | |
4be21d56 DG |
1501 | |
1502 | /* End marker */ | |
1503 | qemu_put_be32(f, 0); | |
1504 | qemu_put_be16(f, 0); | |
1505 | qemu_put_be16(f, 0); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1511 | { | |
28e02042 | 1512 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1513 | uint32_t section_hdr; |
e68cb8b4 | 1514 | int fd = -1; |
4be21d56 DG |
1515 | |
1516 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 1517 | error_report("htab_load() bad version"); |
4be21d56 DG |
1518 | return -EINVAL; |
1519 | } | |
1520 | ||
1521 | section_hdr = qemu_get_be32(f); | |
1522 | ||
1523 | if (section_hdr) { | |
9897e462 | 1524 | Error *local_err = NULL; |
c5f54f3e DG |
1525 | |
1526 | /* First section gives the htab size */ | |
1527 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
1528 | if (local_err) { | |
1529 | error_report_err(local_err); | |
4be21d56 DG |
1530 | return -EINVAL; |
1531 | } | |
1532 | return 0; | |
1533 | } | |
1534 | ||
e68cb8b4 AK |
1535 | if (!spapr->htab) { |
1536 | assert(kvm_enabled()); | |
1537 | ||
1538 | fd = kvmppc_get_htab_fd(true); | |
1539 | if (fd < 0) { | |
98a5d100 DG |
1540 | error_report("Unable to open fd to restore KVM hash table: %s", |
1541 | strerror(errno)); | |
e68cb8b4 AK |
1542 | } |
1543 | } | |
1544 | ||
4be21d56 DG |
1545 | while (true) { |
1546 | uint32_t index; | |
1547 | uint16_t n_valid, n_invalid; | |
1548 | ||
1549 | index = qemu_get_be32(f); | |
1550 | n_valid = qemu_get_be16(f); | |
1551 | n_invalid = qemu_get_be16(f); | |
1552 | ||
1553 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1554 | /* End of Stream */ | |
1555 | break; | |
1556 | } | |
1557 | ||
e68cb8b4 | 1558 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1559 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1560 | /* Bad index in stream */ | |
98a5d100 DG |
1561 | error_report( |
1562 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
1563 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
1564 | return -EINVAL; |
1565 | } | |
1566 | ||
e68cb8b4 AK |
1567 | if (spapr->htab) { |
1568 | if (n_valid) { | |
1569 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1570 | HASH_PTE_SIZE_64 * n_valid); | |
1571 | } | |
1572 | if (n_invalid) { | |
1573 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1574 | HASH_PTE_SIZE_64 * n_invalid); | |
1575 | } | |
1576 | } else { | |
1577 | int rc; | |
1578 | ||
1579 | assert(fd >= 0); | |
1580 | ||
1581 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1582 | if (rc < 0) { | |
1583 | return rc; | |
1584 | } | |
4be21d56 DG |
1585 | } |
1586 | } | |
1587 | ||
e68cb8b4 AK |
1588 | if (!spapr->htab) { |
1589 | assert(fd >= 0); | |
1590 | close(fd); | |
1591 | } | |
1592 | ||
4be21d56 DG |
1593 | return 0; |
1594 | } | |
1595 | ||
c573fc03 TH |
1596 | static void htab_cleanup(void *opaque) |
1597 | { | |
1598 | sPAPRMachineState *spapr = opaque; | |
1599 | ||
1600 | close_htab_fd(spapr); | |
1601 | } | |
1602 | ||
4be21d56 DG |
1603 | static SaveVMHandlers savevm_htab_handlers = { |
1604 | .save_live_setup = htab_save_setup, | |
1605 | .save_live_iterate = htab_save_iterate, | |
a3e06c3d | 1606 | .save_live_complete_precopy = htab_save_complete, |
c573fc03 | 1607 | .cleanup = htab_cleanup, |
4be21d56 DG |
1608 | .load_state = htab_load, |
1609 | }; | |
1610 | ||
5b2128d2 AG |
1611 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1612 | Error **errp) | |
1613 | { | |
1614 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1615 | machine->boot_order = g_strdup(boot_device); | |
1616 | } | |
1617 | ||
224245bf DG |
1618 | /* |
1619 | * Reset routine for LMB DR devices. | |
1620 | * | |
1621 | * Unlike PCI DR devices, LMB DR devices explicitly register this reset | |
1622 | * routine. Reset for PCI DR devices will be handled by PHB reset routine | |
1623 | * when it walks all its children devices. LMB devices reset occurs | |
1624 | * as part of spapr_ppc_reset(). | |
1625 | */ | |
1626 | static void spapr_drc_reset(void *opaque) | |
1627 | { | |
1628 | sPAPRDRConnector *drc = opaque; | |
1629 | DeviceState *d = DEVICE(drc); | |
1630 | ||
1631 | if (d) { | |
1632 | device_reset(d); | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) | |
1637 | { | |
1638 | MachineState *machine = MACHINE(spapr); | |
1639 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 1640 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
1641 | int i; |
1642 | ||
1643 | for (i = 0; i < nr_lmbs; i++) { | |
1644 | sPAPRDRConnector *drc; | |
1645 | uint64_t addr; | |
1646 | ||
e8f986fc | 1647 | addr = i * lmb_size + spapr->hotplug_memory.base; |
224245bf DG |
1648 | drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, |
1649 | addr/lmb_size); | |
1650 | qemu_register_reset(spapr_drc_reset, drc); | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | /* | |
1655 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
1656 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
1657 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
1658 | */ | |
7c150d6f | 1659 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
1660 | { |
1661 | int i; | |
1662 | ||
7c150d6f DG |
1663 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
1664 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
1665 | " is not aligned to %llu MiB", | |
1666 | machine->ram_size, | |
1667 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1668 | return; | |
1669 | } | |
1670 | ||
1671 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
1672 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
1673 | " is not aligned to %llu MiB", | |
1674 | machine->ram_size, | |
1675 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1676 | return; | |
224245bf DG |
1677 | } |
1678 | ||
1679 | for (i = 0; i < nb_numa_nodes; i++) { | |
1680 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
1681 | error_setg(errp, |
1682 | "Node %d memory size 0x%" PRIx64 | |
1683 | " is not aligned to %llu MiB", | |
1684 | i, numa_info[i].node_mem, | |
1685 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1686 | return; | |
224245bf DG |
1687 | } |
1688 | } | |
1689 | } | |
1690 | ||
9fdf0c29 | 1691 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 1692 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 1693 | { |
28e02042 | 1694 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3c0c47e3 | 1695 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
224245bf | 1696 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 1697 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 1698 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 1699 | PCIHostState *phb; |
9fdf0c29 | 1700 | int i; |
890c2b77 AK |
1701 | MemoryRegion *sysmem = get_system_memory(); |
1702 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
1703 | MemoryRegion *rma_region; |
1704 | void *rma = NULL; | |
a8170e5e | 1705 | hwaddr rma_alloc_size; |
b082d65a | 1706 | hwaddr node0_size = spapr_node0_size(); |
b7d1f77a | 1707 | long load_limit, fw_size; |
39ac8455 | 1708 | char *filename; |
94a94e4c BR |
1709 | int smt = kvmppc_smt_threads(); |
1710 | int spapr_cores = smp_cpus / smp_threads; | |
1711 | int spapr_max_cores = max_cpus / smp_threads; | |
1712 | ||
3c0c47e3 | 1713 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1714 | if (smp_cpus % smp_threads) { |
1715 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
1716 | smp_cpus, smp_threads); | |
1717 | exit(1); | |
1718 | } | |
1719 | if (max_cpus % smp_threads) { | |
1720 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
1721 | max_cpus, smp_threads); | |
1722 | exit(1); | |
1723 | } | |
1724 | } | |
9fdf0c29 | 1725 | |
226419d6 | 1726 | msi_nonbroken = true; |
0ee2c058 | 1727 | |
d43b45e2 DG |
1728 | QLIST_INIT(&spapr->phbs); |
1729 | ||
9fdf0c29 DG |
1730 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1731 | ||
354ac20a | 1732 | /* Allocate RMA if necessary */ |
658fa66b | 1733 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
1734 | |
1735 | if (rma_alloc_size == -1) { | |
730fce59 | 1736 | error_report("Unable to create RMA"); |
354ac20a DG |
1737 | exit(1); |
1738 | } | |
7f763a5d | 1739 | |
c4177479 | 1740 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1741 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1742 | } else { |
c4177479 | 1743 | spapr->rma_size = node0_size; |
7f763a5d DG |
1744 | |
1745 | /* With KVM, we don't actually know whether KVM supports an | |
1746 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1747 | * (HV KVM using VRMA), so we always assume the latter | |
1748 | * | |
1749 | * In that case, we also limit the initial allocations for RTAS | |
1750 | * etc... to 256M since we have no way to know what the VRMA size | |
1751 | * is going to be as it depends on the size of the hash table | |
1752 | * isn't determined yet. | |
1753 | */ | |
1754 | if (kvm_enabled()) { | |
1755 | spapr->vrma_adjust = 1; | |
1756 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1757 | } | |
912acdf4 BH |
1758 | |
1759 | /* Actually we don't support unbounded RMA anymore since we | |
1760 | * added proper emulation of HV mode. The max we can get is | |
1761 | * 16G which also happens to be what we configure for PAPR | |
1762 | * mode so make sure we don't do anything bigger than that | |
1763 | */ | |
1764 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
1765 | } |
1766 | ||
c4177479 | 1767 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
1768 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
1769 | spapr->rma_size); | |
c4177479 AK |
1770 | exit(1); |
1771 | } | |
1772 | ||
b7d1f77a BH |
1773 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
1774 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 1775 | |
7b565160 | 1776 | /* Set up Interrupt Controller before we create the VCPUs */ |
27f24582 BH |
1777 | spapr->xics = xics_system_init(machine, |
1778 | DIV_ROUND_UP(max_cpus * smt, smp_threads), | |
1779 | XICS_IRQS_SPAPR, &error_fatal); | |
7b565160 | 1780 | |
facdb8b6 MR |
1781 | /* Set up containers for ibm,client-set-architecture negotiated options */ |
1782 | spapr->ov5 = spapr_ovec_new(); | |
1783 | spapr->ov5_cas = spapr_ovec_new(); | |
1784 | ||
224245bf | 1785 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 1786 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 1787 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
1788 | } |
1789 | ||
417ece33 MR |
1790 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
1791 | ||
ffbb1705 MR |
1792 | /* advertise support for dedicated HP event source to guests */ |
1793 | if (spapr->use_hotplug_event_source) { | |
1794 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
1795 | } | |
1796 | ||
9fdf0c29 | 1797 | /* init CPUs */ |
19fb2c36 | 1798 | if (machine->cpu_model == NULL) { |
3daa4a9f | 1799 | machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; |
9fdf0c29 | 1800 | } |
94a94e4c | 1801 | |
e703d2f7 GK |
1802 | ppc_cpu_parse_features(machine->cpu_model); |
1803 | ||
3c0c47e3 | 1804 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1805 | char *type = spapr_get_cpu_core_type(machine->cpu_model); |
1806 | ||
4babfaf0 | 1807 | if (type == NULL) { |
caebf378 CLG |
1808 | error_report("Unable to find sPAPR CPU Core definition"); |
1809 | exit(1); | |
1810 | } | |
1811 | ||
94a94e4c | 1812 | spapr->cores = g_new0(Object *, spapr_max_cores); |
af81cf32 | 1813 | for (i = 0; i < spapr_max_cores; i++) { |
12bf2d33 | 1814 | int core_id = i * smp_threads; |
af81cf32 BR |
1815 | sPAPRDRConnector *drc = |
1816 | spapr_dr_connector_new(OBJECT(spapr), | |
12bf2d33 GK |
1817 | SPAPR_DR_CONNECTOR_TYPE_CPU, |
1818 | (core_id / smp_threads) * smt); | |
af81cf32 BR |
1819 | |
1820 | qemu_register_reset(spapr_drc_reset, drc); | |
1821 | ||
1822 | if (i < spapr_cores) { | |
caebf378 | 1823 | Object *core = object_new(type); |
af81cf32 BR |
1824 | object_property_set_int(core, smp_threads, "nr-threads", |
1825 | &error_fatal); | |
12bf2d33 | 1826 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, |
af81cf32 BR |
1827 | &error_fatal); |
1828 | object_property_set_bool(core, true, "realized", &error_fatal); | |
94a94e4c | 1829 | } |
9fdf0c29 | 1830 | } |
94a94e4c BR |
1831 | g_free(type); |
1832 | } else { | |
1833 | for (i = 0; i < smp_cpus; i++) { | |
1834 | PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); | |
1835 | if (cpu == NULL) { | |
1836 | error_report("Unable to find PowerPC CPU definition"); | |
1837 | exit(1); | |
1838 | } | |
1839 | spapr_cpu_init(spapr, cpu, &error_fatal); | |
1840 | } | |
9fdf0c29 DG |
1841 | } |
1842 | ||
026bfd89 DG |
1843 | if (kvm_enabled()) { |
1844 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
1845 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 1846 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
1847 | |
1848 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
1849 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
1850 | } |
1851 | ||
9fdf0c29 | 1852 | /* allocate RAM */ |
f92f5da1 | 1853 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 1854 | machine->ram_size); |
f92f5da1 | 1855 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 1856 | |
658fa66b AK |
1857 | if (rma_alloc_size && rma) { |
1858 | rma_region = g_new(MemoryRegion, 1); | |
1859 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
1860 | rma_alloc_size, rma); | |
1861 | vmstate_register_ram_global(rma_region); | |
1862 | memory_region_add_subregion(sysmem, 0, rma_region); | |
1863 | } | |
1864 | ||
4a1c9cf0 BR |
1865 | /* initialize hotplug memory address space */ |
1866 | if (machine->ram_size < machine->maxram_size) { | |
1867 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
1868 | /* |
1869 | * Limit the number of hotpluggable memory slots to half the number | |
1870 | * slots that KVM supports, leaving the other half for PCI and other | |
1871 | * devices. However ensure that number of slots doesn't drop below 32. | |
1872 | */ | |
1873 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
1874 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 1875 | |
71c9a3dd BR |
1876 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
1877 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
1878 | } | |
1879 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
1880 | error_report("Specified number of memory slots %" |
1881 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 1882 | machine->ram_slots, max_memslots); |
d54e4d76 | 1883 | exit(1); |
4a1c9cf0 BR |
1884 | } |
1885 | ||
1886 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
1887 | SPAPR_HOTPLUG_MEM_ALIGN); | |
1888 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
1889 | "hotplug-memory", hotplug_mem_size); | |
1890 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
1891 | &spapr->hotplug_memory.mr); | |
1892 | } | |
1893 | ||
224245bf DG |
1894 | if (smc->dr_lmb_enabled) { |
1895 | spapr_create_lmb_dr_connectors(spapr); | |
1896 | } | |
1897 | ||
39ac8455 | 1898 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 1899 | if (!filename) { |
730fce59 | 1900 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
1901 | exit(1); |
1902 | } | |
b7d1f77a | 1903 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
1904 | if (spapr->rtas_size < 0) { |
1905 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
1906 | exit(1); | |
1907 | } | |
b7d1f77a BH |
1908 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
1909 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 1910 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
1911 | exit(1); |
1912 | } | |
4d8d5467 | 1913 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
1914 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
1915 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
1916 | exit(1); |
1917 | } | |
7267c094 | 1918 | g_free(filename); |
39ac8455 | 1919 | |
ffbb1705 | 1920 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
1921 | spapr_events_init(spapr); |
1922 | ||
12f42174 | 1923 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 1924 | spapr_rtc_create(spapr); |
12f42174 | 1925 | |
b5cec4c5 | 1926 | /* Set up VIO bus */ |
4040ab72 DG |
1927 | spapr->vio_bus = spapr_vio_bus_init(); |
1928 | ||
277f9acf | 1929 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1930 | if (serial_hds[i]) { |
d601fac4 | 1931 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1932 | } |
1933 | } | |
9fdf0c29 | 1934 | |
639e8102 DG |
1935 | /* We always have at least the nvram device on VIO */ |
1936 | spapr_create_nvram(spapr); | |
1937 | ||
3384f95c | 1938 | /* Set up PCI */ |
fa28f71b AK |
1939 | spapr_pci_rtas_init(); |
1940 | ||
89dfd6e1 | 1941 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1942 | |
277f9acf | 1943 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1944 | NICInfo *nd = &nd_table[i]; |
1945 | ||
1946 | if (!nd->model) { | |
7267c094 | 1947 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1948 | } |
1949 | ||
1950 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1951 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1952 | } else { |
29b358f9 | 1953 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1954 | } |
1955 | } | |
1956 | ||
6e270446 | 1957 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1958 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1959 | } |
1960 | ||
f28359d8 | 1961 | /* Graphics */ |
14c6a894 | 1962 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 1963 | spapr->has_graphics = true; |
c6e76503 | 1964 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
1965 | } |
1966 | ||
4ee9ced9 | 1967 | if (machine->usb) { |
57040d45 TH |
1968 | if (smc->use_ohci_by_default) { |
1969 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
1970 | } else { | |
1971 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
1972 | } | |
c86580b8 | 1973 | |
35139a59 | 1974 | if (spapr->has_graphics) { |
c86580b8 MA |
1975 | USBBus *usb_bus = usb_bus_find(-1); |
1976 | ||
1977 | usb_create_simple(usb_bus, "usb-kbd"); | |
1978 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
1979 | } |
1980 | } | |
1981 | ||
7f763a5d | 1982 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
1983 | error_report( |
1984 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
1985 | MIN_RMA_SLOF); | |
4d8d5467 BH |
1986 | exit(1); |
1987 | } | |
1988 | ||
9fdf0c29 DG |
1989 | if (kernel_filename) { |
1990 | uint64_t lowaddr = 0; | |
1991 | ||
a19f7fb0 DG |
1992 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
1993 | NULL, NULL, &lowaddr, NULL, 1, | |
1994 | PPC_ELF_MACHINE, 0, 0); | |
1995 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
1996 | spapr->kernel_size = load_elf(kernel_filename, | |
1997 | translate_kernel_address, NULL, NULL, | |
1998 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
1999 | 0, 0); | |
2000 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2001 | } |
a19f7fb0 DG |
2002 | if (spapr->kernel_size < 0) { |
2003 | error_report("error loading %s: %s", kernel_filename, | |
2004 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2005 | exit(1); |
2006 | } | |
2007 | ||
2008 | /* load initrd */ | |
2009 | if (initrd_filename) { | |
4d8d5467 BH |
2010 | /* Try to locate the initrd in the gap between the kernel |
2011 | * and the firmware. Add a bit of space just in case | |
2012 | */ | |
a19f7fb0 DG |
2013 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2014 | + 0x1ffff) & ~0xffff; | |
2015 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2016 | spapr->initrd_base, | |
2017 | load_limit | |
2018 | - spapr->initrd_base); | |
2019 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2020 | error_report("could not load initial ram disk '%s'", |
2021 | initrd_filename); | |
9fdf0c29 DG |
2022 | exit(1); |
2023 | } | |
9fdf0c29 | 2024 | } |
4d8d5467 | 2025 | } |
a3467baa | 2026 | |
8e7ea787 AF |
2027 | if (bios_name == NULL) { |
2028 | bios_name = FW_FILE_NAME; | |
2029 | } | |
2030 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2031 | if (!filename) { |
68fea5a0 | 2032 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2033 | exit(1); |
2034 | } | |
4d8d5467 | 2035 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2036 | if (fw_size <= 0) { |
2037 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2038 | exit(1); |
2039 | } | |
2040 | g_free(filename); | |
4d8d5467 | 2041 | |
28e02042 DG |
2042 | /* FIXME: Should register things through the MachineState's qdev |
2043 | * interface, this is a legacy from the sPAPREnvironment structure | |
2044 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2045 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2046 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2047 | &savevm_htab_handlers, spapr); | |
2048 | ||
46503c2b MR |
2049 | /* used by RTAS */ |
2050 | QTAILQ_INIT(&spapr->ccs_list); | |
2051 | qemu_register_reset(spapr_ccs_reset_hook, spapr); | |
2052 | ||
5b2128d2 | 2053 | qemu_register_boot_set(spapr_boot_set, spapr); |
9fdf0c29 DG |
2054 | } |
2055 | ||
135a129a AK |
2056 | static int spapr_kvm_type(const char *vm_type) |
2057 | { | |
2058 | if (!vm_type) { | |
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | if (!strcmp(vm_type, "HV")) { | |
2063 | return 1; | |
2064 | } | |
2065 | ||
2066 | if (!strcmp(vm_type, "PR")) { | |
2067 | return 2; | |
2068 | } | |
2069 | ||
2070 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2071 | exit(1); | |
2072 | } | |
2073 | ||
71461b0f | 2074 | /* |
627b84f4 | 2075 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2076 | * for the bootindex property handling. |
2077 | */ | |
2078 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2079 | DeviceState *dev) | |
2080 | { | |
2081 | #define CAST(type, obj, name) \ | |
2082 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2083 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2084 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
2085 | ||
2086 | if (d) { | |
2087 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2088 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2089 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2090 | ||
2091 | if (spapr) { | |
2092 | /* | |
2093 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2094 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2095 | * in the top 16 bits of the 64-bit LUN | |
2096 | */ | |
2097 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2098 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2099 | (uint64_t)id << 48); | |
2100 | } else if (virtio) { | |
2101 | /* | |
2102 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2103 | * in the top 32 bits of the 64-bit LUN | |
2104 | * Note: the quote above is from SLOF and it is wrong, | |
2105 | * the actual binding is: | |
2106 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2107 | */ | |
2108 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2109 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2110 | (uint64_t)id << 32); | |
2111 | } else if (usb) { | |
2112 | /* | |
2113 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2114 | * in the top 32 bits of the 64-bit LUN | |
2115 | */ | |
2116 | unsigned usb_port = atoi(usb->port->path); | |
2117 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2118 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2119 | (uint64_t)id << 32); | |
2120 | } | |
2121 | } | |
2122 | ||
2123 | if (phb) { | |
2124 | /* Replace "pci" with "pci@800000020000000" */ | |
2125 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2126 | } | |
2127 | ||
2128 | return NULL; | |
2129 | } | |
2130 | ||
23825581 EH |
2131 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2132 | { | |
28e02042 | 2133 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2134 | |
28e02042 | 2135 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2136 | } |
2137 | ||
2138 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2139 | { | |
28e02042 | 2140 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2141 | |
28e02042 DG |
2142 | g_free(spapr->kvm_type); |
2143 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2144 | } |
2145 | ||
f6229214 MR |
2146 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2147 | { | |
2148 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2149 | ||
2150 | return spapr->use_hotplug_event_source; | |
2151 | } | |
2152 | ||
2153 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2154 | Error **errp) | |
2155 | { | |
2156 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2157 | ||
2158 | spapr->use_hotplug_event_source = value; | |
2159 | } | |
2160 | ||
23825581 EH |
2161 | static void spapr_machine_initfn(Object *obj) |
2162 | { | |
715c5407 DG |
2163 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2164 | ||
2165 | spapr->htab_fd = -1; | |
f6229214 | 2166 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2167 | object_property_add_str(obj, "kvm-type", |
2168 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2169 | object_property_set_description(obj, "kvm-type", |
2170 | "Specifies the KVM virtualization mode (HV, PR)", | |
2171 | NULL); | |
f6229214 MR |
2172 | object_property_add_bool(obj, "modern-hotplug-events", |
2173 | spapr_get_modern_hotplug_events, | |
2174 | spapr_set_modern_hotplug_events, | |
2175 | NULL); | |
2176 | object_property_set_description(obj, "modern-hotplug-events", | |
2177 | "Use dedicated hotplug event mechanism in" | |
2178 | " place of standard EPOW events when possible" | |
2179 | " (required for memory hot-unplug support)", | |
2180 | NULL); | |
23825581 EH |
2181 | } |
2182 | ||
87bbdd9c DG |
2183 | static void spapr_machine_finalizefn(Object *obj) |
2184 | { | |
2185 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2186 | ||
2187 | g_free(spapr->kvm_type); | |
2188 | } | |
2189 | ||
e0eeb4a2 | 2190 | static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg) |
34316482 | 2191 | { |
34316482 AK |
2192 | cpu_synchronize_state(cs); |
2193 | ppc_cpu_do_system_reset(cs); | |
2194 | } | |
2195 | ||
2196 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2197 | { | |
2198 | CPUState *cs; | |
2199 | ||
2200 | CPU_FOREACH(cs) { | |
e0eeb4a2 | 2201 | async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL); |
34316482 AK |
2202 | } |
2203 | } | |
2204 | ||
79b78a6b MR |
2205 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2206 | uint32_t node, bool dedicated_hp_event_source, | |
2207 | Error **errp) | |
c20d332a BR |
2208 | { |
2209 | sPAPRDRConnector *drc; | |
2210 | sPAPRDRConnectorClass *drck; | |
2211 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; | |
2212 | int i, fdt_offset, fdt_size; | |
2213 | void *fdt; | |
79b78a6b | 2214 | uint64_t addr = addr_start; |
c20d332a | 2215 | |
c20d332a BR |
2216 | for (i = 0; i < nr_lmbs; i++) { |
2217 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2218 | addr/SPAPR_MEMORY_BLOCK_SIZE); | |
2219 | g_assert(drc); | |
2220 | ||
2221 | fdt = create_device_tree(&fdt_size); | |
2222 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2223 | SPAPR_MEMORY_BLOCK_SIZE); | |
2224 | ||
2225 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2226 | drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); | |
c20d332a BR |
2227 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2228 | } | |
5dd5238c JD |
2229 | /* send hotplug notification to the |
2230 | * guest only in case of hotplugged memory | |
2231 | */ | |
2232 | if (dev->hotplugged) { | |
79b78a6b MR |
2233 | if (dedicated_hp_event_source) { |
2234 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2235 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
2236 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2237 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2238 | nr_lmbs, | |
2239 | drck->get_index(drc)); | |
2240 | } else { | |
2241 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2242 | nr_lmbs); | |
2243 | } | |
5dd5238c | 2244 | } |
c20d332a BR |
2245 | } |
2246 | ||
2247 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2248 | uint32_t node, Error **errp) | |
2249 | { | |
2250 | Error *local_err = NULL; | |
2251 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2252 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2253 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2254 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2255 | uint64_t align = memory_region_get_alignment(mr); | |
2256 | uint64_t size = memory_region_size(mr); | |
2257 | uint64_t addr; | |
2258 | ||
2259 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2260 | error_setg(&local_err, "Hotplugged memory size must be a multiple of " | |
2261 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
2262 | goto out; | |
2263 | } | |
2264 | ||
d6a9b0b8 | 2265 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2266 | if (local_err) { |
2267 | goto out; | |
2268 | } | |
2269 | ||
2270 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2271 | if (local_err) { | |
2272 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2273 | goto out; | |
2274 | } | |
2275 | ||
79b78a6b MR |
2276 | spapr_add_lmbs(dev, addr, size, node, |
2277 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
2278 | &error_abort); | |
c20d332a BR |
2279 | |
2280 | out: | |
2281 | error_propagate(errp, local_err); | |
2282 | } | |
2283 | ||
cf632463 BR |
2284 | typedef struct sPAPRDIMMState { |
2285 | uint32_t nr_lmbs; | |
2286 | } sPAPRDIMMState; | |
2287 | ||
2288 | static void spapr_lmb_release(DeviceState *dev, void *opaque) | |
2289 | { | |
2290 | sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; | |
2291 | HotplugHandler *hotplug_ctrl; | |
2292 | ||
2293 | if (--ds->nr_lmbs) { | |
2294 | return; | |
2295 | } | |
2296 | ||
2297 | g_free(ds); | |
2298 | ||
2299 | /* | |
2300 | * Now that all the LMBs have been removed by the guest, call the | |
2301 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
2302 | */ | |
2303 | hotplug_ctrl = qdev_get_hotplug_handler(dev); | |
2304 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
2305 | } | |
2306 | ||
2307 | static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, | |
2308 | Error **errp) | |
2309 | { | |
2310 | sPAPRDRConnector *drc; | |
2311 | sPAPRDRConnectorClass *drck; | |
2312 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
2313 | int i; | |
2314 | sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
2315 | uint64_t addr = addr_start; | |
2316 | ||
2317 | ds->nr_lmbs = nr_lmbs; | |
2318 | for (i = 0; i < nr_lmbs; i++) { | |
2319 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2320 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
2321 | g_assert(drc); | |
2322 | ||
2323 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2324 | drck->detach(drc, dev, spapr_lmb_release, ds, errp); | |
2325 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
2326 | } | |
2327 | ||
2328 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2329 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
2330 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2331 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2332 | nr_lmbs, | |
2333 | drck->get_index(drc)); | |
2334 | } | |
2335 | ||
2336 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2337 | Error **errp) | |
2338 | { | |
2339 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2340 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2341 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2342 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2343 | ||
2344 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2345 | object_unparent(OBJECT(dev)); | |
2346 | } | |
2347 | ||
2348 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
2349 | DeviceState *dev, Error **errp) | |
2350 | { | |
2351 | Error *local_err = NULL; | |
2352 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2353 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2354 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2355 | uint64_t size = memory_region_size(mr); | |
2356 | uint64_t addr; | |
2357 | ||
2358 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2359 | if (local_err) { | |
2360 | goto out; | |
2361 | } | |
2362 | ||
2363 | spapr_del_lmbs(dev, addr, size, &error_abort); | |
2364 | out: | |
2365 | error_propagate(errp, local_err); | |
2366 | } | |
2367 | ||
af81cf32 BR |
2368 | void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
2369 | sPAPRMachineState *spapr) | |
2370 | { | |
2371 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2372 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2373 | int id = ppc_get_vcpu_dt_id(cpu); | |
2374 | void *fdt; | |
2375 | int offset, fdt_size; | |
2376 | char *nodename; | |
2377 | ||
2378 | fdt = create_device_tree(&fdt_size); | |
2379 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
2380 | offset = fdt_add_subnode(fdt, 0, nodename); | |
2381 | ||
2382 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
2383 | g_free(nodename); | |
2384 | ||
2385 | *fdt_offset = offset; | |
2386 | return fdt; | |
2387 | } | |
2388 | ||
c20d332a BR |
2389 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
2390 | DeviceState *dev, Error **errp) | |
2391 | { | |
2392 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
2393 | ||
2394 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 2395 | int node; |
c20d332a BR |
2396 | |
2397 | if (!smc->dr_lmb_enabled) { | |
2398 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
2399 | return; | |
2400 | } | |
2401 | node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); | |
2402 | if (*errp) { | |
2403 | return; | |
2404 | } | |
1a5512bb GA |
2405 | if (node < 0 || node >= MAX_NODES) { |
2406 | error_setg(errp, "Invaild node %d", node); | |
2407 | return; | |
2408 | } | |
c20d332a | 2409 | |
b556854b BR |
2410 | /* |
2411 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
2412 | * memory-less node, but instead will silently add the memory | |
2413 | * to the first node that has some memory. This causes two | |
2414 | * unexpected behaviours for the user. | |
2415 | * | |
2416 | * - Memory gets hotplugged to a different node than what the user | |
2417 | * specified. | |
2418 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
2419 | * to memory-less node, a reboot will set things accordingly | |
2420 | * and the previously hotplugged memory now ends in the right node. | |
2421 | * This appears as if some memory moved from one node to another. | |
2422 | * | |
2423 | * So until kernel starts supporting memory hotplug to memory-less | |
2424 | * nodes, just prevent such attempts upfront in QEMU. | |
2425 | */ | |
2426 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
2427 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
2428 | node); | |
2429 | return; | |
2430 | } | |
2431 | ||
c20d332a | 2432 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
2433 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
2434 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
2435 | } |
2436 | } | |
2437 | ||
2438 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, | |
2439 | DeviceState *dev, Error **errp) | |
2440 | { | |
cf632463 | 2441 | sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); |
3c0c47e3 | 2442 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
6f4b5c3e | 2443 | |
c20d332a | 2444 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
cf632463 BR |
2445 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { |
2446 | spapr_memory_unplug(hotplug_dev, dev, errp); | |
2447 | } else { | |
2448 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
2449 | } | |
2450 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
2451 | if (!mc->query_hotpluggable_cpus) { | |
2452 | error_setg(errp, "CPU hot unplug not supported on this machine"); | |
2453 | return; | |
2454 | } | |
2455 | spapr_core_unplug(hotplug_dev, dev, errp); | |
2456 | } | |
2457 | } | |
2458 | ||
2459 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, | |
2460 | DeviceState *dev, Error **errp) | |
2461 | { | |
2462 | sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); | |
2463 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | |
2464 | ||
2465 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2466 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
2467 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
2468 | } else { | |
2469 | /* NOTE: this means there is a window after guest reset, prior to | |
2470 | * CAS negotiation, where unplug requests will fail due to the | |
2471 | * capability not being detected yet. This is a bit different than | |
2472 | * the case with PCI unplug, where the events will be queued and | |
2473 | * eventually handled by the guest after boot | |
2474 | */ | |
2475 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
2476 | } | |
6f4b5c3e | 2477 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3c0c47e3 | 2478 | if (!mc->query_hotpluggable_cpus) { |
6f4b5c3e BR |
2479 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
2480 | return; | |
2481 | } | |
2482 | spapr_core_unplug(hotplug_dev, dev, errp); | |
c20d332a BR |
2483 | } |
2484 | } | |
2485 | ||
94a94e4c BR |
2486 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
2487 | DeviceState *dev, Error **errp) | |
2488 | { | |
2489 | if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
2490 | spapr_core_pre_plug(hotplug_dev, dev, errp); | |
2491 | } | |
2492 | } | |
2493 | ||
7ebaf795 BR |
2494 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
2495 | DeviceState *dev) | |
c20d332a | 2496 | { |
94a94e4c BR |
2497 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2498 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
2499 | return HOTPLUG_HANDLER(machine); |
2500 | } | |
2501 | return NULL; | |
2502 | } | |
2503 | ||
20bb648d DG |
2504 | static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) |
2505 | { | |
2506 | /* Allocate to NUMA nodes on a "socket" basis (not that concept of | |
2507 | * socket means much for the paravirtualized PAPR platform) */ | |
2508 | return cpu_index / smp_threads / smp_cores; | |
2509 | } | |
2510 | ||
2474bfd4 IM |
2511 | static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) |
2512 | { | |
2513 | int i; | |
2514 | HotpluggableCPUList *head = NULL; | |
2515 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
2516 | int spapr_max_cores = max_cpus / smp_threads; | |
2474bfd4 IM |
2517 | |
2518 | for (i = 0; i < spapr_max_cores; i++) { | |
2519 | HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); | |
2520 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); | |
2521 | CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); | |
2522 | ||
2523 | cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); | |
2524 | cpu_item->vcpus_count = smp_threads; | |
27393c33 | 2525 | cpu_props->has_core_id = true; |
12bf2d33 | 2526 | cpu_props->core_id = i * smp_threads; |
2474bfd4 IM |
2527 | /* TODO: add 'has_node/node' here to describe |
2528 | to which node core belongs */ | |
2529 | ||
2530 | cpu_item->props = cpu_props; | |
2531 | if (spapr->cores[i]) { | |
2532 | cpu_item->has_qom_path = true; | |
2533 | cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); | |
2534 | } | |
2535 | list_item->value = cpu_item; | |
2536 | list_item->next = head; | |
2537 | head = list_item; | |
2538 | } | |
2539 | return head; | |
2540 | } | |
2541 | ||
6737d9ad | 2542 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
2543 | uint64_t *buid, hwaddr *pio, |
2544 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
2545 | unsigned n_dma, uint32_t *liobns, Error **errp) |
2546 | { | |
357d1e3b DG |
2547 | /* |
2548 | * New-style PHB window placement. | |
2549 | * | |
2550 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
2551 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
2552 | * windows. | |
2553 | * | |
2554 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
2555 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
2556 | * | |
2557 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
2558 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
2559 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
2560 | * 1TiB 64-bit MMIO windows for each PHB. | |
2561 | */ | |
6737d9ad | 2562 | const uint64_t base_buid = 0x800000020000000ULL; |
357d1e3b DG |
2563 | const int max_phbs = |
2564 | (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1; | |
6737d9ad DG |
2565 | int i; |
2566 | ||
357d1e3b DG |
2567 | /* Sanity check natural alignments */ |
2568 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
2569 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
2570 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
2571 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
2572 | /* Sanity check bounds */ | |
2573 | QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE); | |
2574 | QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE); | |
2efff1c0 | 2575 | |
357d1e3b | 2576 | if (index >= max_phbs) { |
6737d9ad | 2577 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", |
357d1e3b | 2578 | max_phbs - 1); |
6737d9ad DG |
2579 | return; |
2580 | } | |
2581 | ||
2582 | *buid = base_buid + index; | |
2583 | for (i = 0; i < n_dma; ++i) { | |
2584 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
2585 | } | |
2586 | ||
357d1e3b DG |
2587 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
2588 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
2589 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
2590 | } |
2591 | ||
29ee3247 AK |
2592 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
2593 | { | |
2594 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 2595 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 2596 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 2597 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 2598 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
958db90c | 2599 | |
0eb9054c | 2600 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
2601 | |
2602 | /* | |
2603 | * We set up the default / latest behaviour here. The class_init | |
2604 | * functions for the specific versioned machine types can override | |
2605 | * these details for backwards compatibility | |
2606 | */ | |
958db90c MA |
2607 | mc->init = ppc_spapr_init; |
2608 | mc->reset = ppc_spapr_reset; | |
2609 | mc->block_default_type = IF_SCSI; | |
079019f2 | 2610 | mc->max_cpus = 255; |
958db90c | 2611 | mc->no_parallel = 1; |
5b2128d2 | 2612 | mc->default_boot_order = ""; |
a34944fe | 2613 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 2614 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 2615 | mc->has_dynamic_sysbus = true; |
e4024630 | 2616 | mc->pci_allow_0_address = true; |
7ebaf795 | 2617 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 2618 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a BR |
2619 | hc->plug = spapr_machine_device_plug; |
2620 | hc->unplug = spapr_machine_device_unplug; | |
20bb648d | 2621 | mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; |
cf632463 | 2622 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 2623 | |
fc9f38c3 | 2624 | smc->dr_lmb_enabled = true; |
3daa4a9f | 2625 | smc->tcg_default_cpu = "POWER8"; |
3c0c47e3 | 2626 | mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; |
71461b0f | 2627 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 2628 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 2629 | smc->phb_placement = spapr_phb_placement; |
29ee3247 AK |
2630 | } |
2631 | ||
2632 | static const TypeInfo spapr_machine_info = { | |
2633 | .name = TYPE_SPAPR_MACHINE, | |
2634 | .parent = TYPE_MACHINE, | |
4aee7362 | 2635 | .abstract = true, |
6ca1502e | 2636 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 2637 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 2638 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 2639 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 2640 | .class_init = spapr_machine_class_init, |
71461b0f AK |
2641 | .interfaces = (InterfaceInfo[]) { |
2642 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 2643 | { TYPE_NMI }, |
c20d332a | 2644 | { TYPE_HOTPLUG_HANDLER }, |
71461b0f AK |
2645 | { } |
2646 | }, | |
29ee3247 AK |
2647 | }; |
2648 | ||
fccbc785 | 2649 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
2650 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
2651 | void *data) \ | |
2652 | { \ | |
2653 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
2654 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
2655 | if (latest) { \ |
2656 | mc->alias = "pseries"; \ | |
2657 | mc->is_default = 1; \ | |
2658 | } \ | |
5013c547 DG |
2659 | } \ |
2660 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
2661 | { \ | |
2662 | MachineState *machine = MACHINE(obj); \ | |
2663 | spapr_machine_##suffix##_instance_options(machine); \ | |
2664 | } \ | |
2665 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
2666 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
2667 | .parent = TYPE_SPAPR_MACHINE, \ | |
2668 | .class_init = spapr_machine_##suffix##_class_init, \ | |
2669 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
2670 | }; \ | |
2671 | static void spapr_machine_register_##suffix(void) \ | |
2672 | { \ | |
2673 | type_register(&spapr_machine_##suffix##_info); \ | |
2674 | } \ | |
0e6aac87 | 2675 | type_init(spapr_machine_register_##suffix) |
5013c547 | 2676 | |
db800b21 DG |
2677 | /* |
2678 | * pseries-2.8 | |
2679 | */ | |
2680 | static void spapr_machine_2_8_instance_options(MachineState *machine) | |
2681 | { | |
2682 | } | |
2683 | ||
2684 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
2685 | { | |
2686 | /* Defaults for the latest behaviour inherited from the base class */ | |
2687 | } | |
2688 | ||
2689 | DEFINE_SPAPR_MACHINE(2_8, "2.8", true); | |
2690 | ||
1ea1eefc BR |
2691 | /* |
2692 | * pseries-2.7 | |
2693 | */ | |
357d1e3b DG |
2694 | #define SPAPR_COMPAT_2_7 \ |
2695 | HW_COMPAT_2_7 \ | |
2696 | { \ | |
2697 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
2698 | .property = "mem_win_size", \ | |
2699 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
2700 | }, \ | |
2701 | { \ | |
2702 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
2703 | .property = "mem64_win_size", \ | |
2704 | .value = "0", \ | |
2705 | }, | |
2706 | ||
2707 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
2708 | uint64_t *buid, hwaddr *pio, | |
2709 | hwaddr *mmio32, hwaddr *mmio64, | |
2710 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
2711 | { | |
2712 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
2713 | const uint64_t base_buid = 0x800000020000000ULL; | |
2714 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
2715 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
2716 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
2717 | const uint32_t max_index = 255; | |
2718 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
2719 | ||
2720 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
2721 | hwaddr phb0_base, phb_base; | |
2722 | int i; | |
2723 | ||
2724 | /* Do we have hotpluggable memory? */ | |
2725 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
2726 | /* Can't just use maxram_size, because there may be an | |
2727 | * alignment gap between normal and hotpluggable memory | |
2728 | * regions */ | |
2729 | ram_top = spapr->hotplug_memory.base + | |
2730 | memory_region_size(&spapr->hotplug_memory.mr); | |
2731 | } | |
2732 | ||
2733 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
2734 | ||
2735 | if (index > max_index) { | |
2736 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
2737 | max_index); | |
2738 | return; | |
2739 | } | |
2740 | ||
2741 | *buid = base_buid + index; | |
2742 | for (i = 0; i < n_dma; ++i) { | |
2743 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
2744 | } | |
2745 | ||
2746 | phb_base = phb0_base + index * phb_spacing; | |
2747 | *pio = phb_base + pio_offset; | |
2748 | *mmio32 = phb_base + mmio_offset; | |
2749 | /* | |
2750 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
2751 | * fallback behaviour of automatically splitting a large "32-bit" | |
2752 | * window into contiguous 32-bit and 64-bit windows | |
2753 | */ | |
2754 | } | |
db800b21 | 2755 | |
1ea1eefc BR |
2756 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
2757 | { | |
f6229214 MR |
2758 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
2759 | ||
672de881 | 2760 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 2761 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
2762 | } |
2763 | ||
2764 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
2765 | { | |
3daa4a9f TH |
2766 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2767 | ||
db800b21 | 2768 | spapr_machine_2_8_class_options(mc); |
3daa4a9f | 2769 | smc->tcg_default_cpu = "POWER7"; |
db800b21 | 2770 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 2771 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
2772 | } |
2773 | ||
db800b21 | 2774 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 2775 | |
4b23699c DG |
2776 | /* |
2777 | * pseries-2.6 | |
2778 | */ | |
1ea1eefc | 2779 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
2780 | HW_COMPAT_2_6 \ |
2781 | { \ | |
2782 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2783 | .property = "ddw",\ | |
2784 | .value = stringify(off),\ | |
2785 | }, | |
1ea1eefc | 2786 | |
4b23699c DG |
2787 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
2788 | { | |
672de881 | 2789 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
2790 | } |
2791 | ||
2792 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
2793 | { | |
1ea1eefc | 2794 | spapr_machine_2_7_class_options(mc); |
3c0c47e3 | 2795 | mc->query_hotpluggable_cpus = NULL; |
1ea1eefc | 2796 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
2797 | } |
2798 | ||
1ea1eefc | 2799 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 2800 | |
1c5f29bb DG |
2801 | /* |
2802 | * pseries-2.5 | |
2803 | */ | |
4b23699c | 2804 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
2805 | HW_COMPAT_2_5 \ |
2806 | { \ | |
2807 | .driver = "spapr-vlan", \ | |
2808 | .property = "use-rx-buffer-pools", \ | |
2809 | .value = "off", \ | |
2810 | }, | |
4b23699c | 2811 | |
5013c547 | 2812 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 2813 | { |
672de881 | 2814 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
2815 | } |
2816 | ||
2817 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
2818 | { | |
57040d45 TH |
2819 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2820 | ||
4b23699c | 2821 | spapr_machine_2_6_class_options(mc); |
57040d45 | 2822 | smc->use_ohci_by_default = true; |
4b23699c | 2823 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
2824 | } |
2825 | ||
4b23699c | 2826 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
2827 | |
2828 | /* | |
2829 | * pseries-2.4 | |
2830 | */ | |
80fd50f9 CH |
2831 | #define SPAPR_COMPAT_2_4 \ |
2832 | HW_COMPAT_2_4 | |
2833 | ||
5013c547 | 2834 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 2835 | { |
5013c547 DG |
2836 | spapr_machine_2_5_instance_options(machine); |
2837 | } | |
1c5f29bb | 2838 | |
5013c547 DG |
2839 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
2840 | { | |
fc9f38c3 DG |
2841 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2842 | ||
2843 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 2844 | smc->dr_lmb_enabled = false; |
f949b4e5 | 2845 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
2846 | } |
2847 | ||
fccbc785 | 2848 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
2849 | |
2850 | /* | |
2851 | * pseries-2.3 | |
2852 | */ | |
38ff32c6 | 2853 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
2854 | HW_COMPAT_2_3 \ |
2855 | {\ | |
2856 | .driver = "spapr-pci-host-bridge",\ | |
2857 | .property = "dynamic-reconfiguration",\ | |
2858 | .value = "off",\ | |
2859 | }, | |
38ff32c6 | 2860 | |
5013c547 | 2861 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 2862 | { |
5013c547 | 2863 | spapr_machine_2_4_instance_options(machine); |
ff14e817 | 2864 | savevm_skip_section_footers(); |
13d16814 | 2865 | global_state_set_optional(); |
09b5e30d | 2866 | savevm_skip_configuration(); |
d25228e7 JW |
2867 | } |
2868 | ||
5013c547 | 2869 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 2870 | { |
fc9f38c3 | 2871 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 2872 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 2873 | } |
fccbc785 | 2874 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 2875 | |
1c5f29bb DG |
2876 | /* |
2877 | * pseries-2.2 | |
2878 | */ | |
2879 | ||
2880 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
2881 | HW_COMPAT_2_2 \ |
2882 | {\ | |
2883 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2884 | .property = "mem_win_size",\ | |
2885 | .value = "0x20000000",\ | |
2886 | }, | |
2887 | ||
5013c547 | 2888 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 2889 | { |
5013c547 | 2890 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 2891 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
2892 | } |
2893 | ||
5013c547 | 2894 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 2895 | { |
fc9f38c3 | 2896 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 2897 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 2898 | } |
fccbc785 | 2899 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 2900 | |
1c5f29bb DG |
2901 | /* |
2902 | * pseries-2.1 | |
2903 | */ | |
2904 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 2905 | HW_COMPAT_2_1 |
3dab0244 | 2906 | |
5013c547 | 2907 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 2908 | { |
5013c547 | 2909 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 2910 | } |
d25228e7 | 2911 | |
5013c547 | 2912 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 2913 | { |
fc9f38c3 | 2914 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 2915 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 2916 | } |
fccbc785 | 2917 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 2918 | |
29ee3247 | 2919 | static void spapr_machine_register_types(void) |
9fdf0c29 | 2920 | { |
29ee3247 | 2921 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
2922 | } |
2923 | ||
29ee3247 | 2924 | type_init(spapr_machine_register_types) |