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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151021' into staging
[mirror_qemu.git] / hw / ppc / spapr.c
CommitLineData
9fdf0c29
DG		 1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
9c17d615 27#include "sysemu/sysemu.h"
e35704ba 28#include "sysemu/numa.h"
83c9f4ca 29#include "hw/hw.h"
71461b0f 30#include "hw/fw-path-provider.h"
9fdf0c29 31#include "elf.h"
1422e32d 32#include "net/net.h"
ad440b4a 33#include "sysemu/device_tree.h"
fa1d36df 34#include "sysemu/block-backend.h"
9c17d615
PB		 35#include "sysemu/cpus.h"
36#include "sysemu/kvm.h"
c20d332a 37#include "sysemu/device_tree.h"
e97c3636 38#include "kvm_ppc.h"
ff14e817 39#include "migration/migration.h"
4be21d56 40#include "mmu-hash64.h"
3794d548 41#include "qom/cpu.h"
9fdf0c29
DG		 42
43#include "hw/boards.h"
0d09e41a 44#include "hw/ppc/ppc.h"
9fdf0c29
DG		 45#include "hw/loader.h"
46
0d09e41a
PB		 47#include "hw/ppc/spapr.h"
48#include "hw/ppc/spapr_vio.h"
49#include "hw/pci-host/spapr.h"
50#include "hw/ppc/xics.h"
a2cb15b0 51#include "hw/pci/msi.h"
9fdf0c29 52
83c9f4ca 53#include "hw/pci/pci.h"
71461b0f
AK		 54#include "hw/scsi/scsi.h"
55#include "hw/virtio/virtio-scsi.h"
f61b4bed 56
022c62cb 57#include "exec/address-spaces.h"
35139a59 58#include "hw/usb.h"
1de7afc9 59#include "qemu/config-file.h"
135a129a 60#include "qemu/error-report.h"
2a6593cb 61#include "trace.h"
34316482 62#include "hw/nmi.h"
890c2b77 63
68a27b20 64#include "hw/compat.h"
224245bf 65#include "qemu-common.h"
68a27b20 66
9fdf0c29
DG		 67#include <libfdt.h>
68
4d8d5467
BH		 69/* SLOF memory layout:
70 *
71 * SLOF raw image loaded at 0, copies its romfs right below the flat
72 * device-tree, then position SLOF itself 31M below that
73 *
74 * So we set FW_OVERHEAD to 40MB which should account for all of that
75 * and more
76 *
77 * We load our kernel at 4M, leaving space for SLOF initial image
78 */
38b02bd8 79#define FDT_MAX_SIZE 0x100000
39ac8455 80#define RTAS_MAX_SIZE 0x10000
b7d1f77a 81#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
a9f8ad8f
DG		 82#define FW_MAX_SIZE 0x400000
83#define FW_FILE_NAME "slof.bin"
4d8d5467
BH		 84#define FW_OVERHEAD 0x2800000
85#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 86
4d8d5467 87#define MIN_RMA_SLOF 128UL
9fdf0c29
DG		 88
89#define TIMEBASE_FREQ 512000000ULL
90
0c103f8e
DG		 91#define PHANDLE_XICP 0x00001111
92
7f763a5d
DG		 93#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
94
c04d6cfa 95static XICSState *try_create_xics(const char *type, int nr_servers,
34f2af3d 96 int nr_irqs, Error **errp)
c04d6cfa 97{
34f2af3d 98 Error *err = NULL;
c04d6cfa
AL		 99 DeviceState *dev;
100
101 dev = qdev_create(NULL, type);
102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
34f2af3d
MA		 104 object_property_set_bool(OBJECT(dev), true, "realized", &err);
105 if (err) {
106 error_propagate(errp, err);
107 object_unparent(OBJECT(dev));
c04d6cfa
AL		 108 return NULL;
109 }
5a3d7b23 110 return XICS_COMMON(dev);
c04d6cfa
AL		 111}
112
446f16a6
MA		 113static XICSState *xics_system_init(MachineState *machine,
114 int nr_servers, int nr_irqs)
c04d6cfa
AL		 115{
116 XICSState *icp = NULL;
117
11ad93f6 118 if (kvm_enabled()) {
34f2af3d
MA		 119 Error *err = NULL;
120
446f16a6 121 if (machine_kernel_irqchip_allowed(machine)) {
34f2af3d 122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
11ad93f6 123 }
446f16a6 124 if (machine_kernel_irqchip_required(machine) && !icp) {
34f2af3d
MA		 125 error_report("kernel_irqchip requested but unavailable: %s",
126 error_get_pretty(err));
11ad93f6
DG		 127 }
128 }
129
130 if (!icp) {
34f2af3d 131 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort);
c04d6cfa
AL		 132 }
133
134 return icp;
135}
136
833d4668
AK		 137static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
138 int smt_threads)
139{
140 int i, ret = 0;
141 uint32_t servers_prop[smt_threads];
142 uint32_t gservers_prop[smt_threads * 2];
143 int index = ppc_get_vcpu_dt_id(cpu);
144
6d9412ea 145 if (cpu->cpu_version) {
4bce526e 146 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
6d9412ea
AK		 147 if (ret < 0) {
148 return ret;
149 }
150 }
151
833d4668
AK		 152 /* Build interrupt servers and gservers properties */
153 for (i = 0; i < smt_threads; i++) {
154 servers_prop[i] = cpu_to_be32(index + i);
155 /* Hack, direct the group queues back to cpu 0 */
156 gservers_prop[i*2] = cpu_to_be32(index + i);
157 gservers_prop[i*2 + 1] = 0;
158 }
159 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
160 servers_prop, sizeof(servers_prop));
161 if (ret < 0) {
162 return ret;
163 }
164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
165 gservers_prop, sizeof(gservers_prop));
166
167 return ret;
168}
169
0da6f3fe
BR		 170static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
171{
172 int ret = 0;
173 PowerPCCPU *cpu = POWERPC_CPU(cs);
174 int index = ppc_get_vcpu_dt_id(cpu);
175 uint32_t associativity[] = {cpu_to_be32(0x5),
176 cpu_to_be32(0x0),
177 cpu_to_be32(0x0),
178 cpu_to_be32(0x0),
179 cpu_to_be32(cs->numa_node),
180 cpu_to_be32(index)};
181
182 /* Advertise NUMA via ibm,associativity */
183 if (nb_numa_nodes > 1) {
184 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
185 sizeof(associativity));
186 }
187
188 return ret;
189}
190
28e02042 191static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
6e806cc3 192{
82677ed2
AK		 193 int ret = 0, offset, cpus_offset;
194 CPUState *cs;
6e806cc3
BR		 195 char cpu_model[32];
196 int smt = kvmppc_smt_threads();
7f763a5d 197 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
6e806cc3 198
82677ed2
AK		 199 CPU_FOREACH(cs) {
200 PowerPCCPU *cpu = POWERPC_CPU(cs);
201 DeviceClass *dc = DEVICE_GET_CLASS(cs);
202 int index = ppc_get_vcpu_dt_id(cpu);
6e806cc3 203
0f20ba62 204 if ((index % smt) != 0) {
6e806cc3
BR		 205 continue;
206 }
207
82677ed2 208 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
6e806cc3 209
82677ed2
AK		 210 cpus_offset = fdt_path_offset(fdt, "/cpus");
211 if (cpus_offset < 0) {
212 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
213 "cpus");
214 if (cpus_offset < 0) {
215 return cpus_offset;
216 }
217 }
218 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
6e806cc3 219 if (offset < 0) {
82677ed2
AK		 220 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
221 if (offset < 0) {
222 return offset;
223 }
6e806cc3
BR		 224 }
225
7f763a5d
DG		 226 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
227 pft_size_prop, sizeof(pft_size_prop));
6e806cc3
BR		 228 if (ret < 0) {
229 return ret;
230 }
833d4668 231
0da6f3fe
BR		 232 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
233 if (ret < 0) {
234 return ret;
235 }
236
82677ed2 237 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
2a48d993 238 ppc_get_compat_smt_threads(cpu));
833d4668
AK		 239 if (ret < 0) {
240 return ret;
241 }
6e806cc3
BR		 242 }
243 return ret;
244}
245
5af9873d
BH		 246
247static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
248 size_t maxsize)
249{
250 size_t maxcells = maxsize / sizeof(uint32_t);
251 int i, j, count;
252 uint32_t *p = prop;
253
254 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
255 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
256
257 if (!sps->page_shift) {
258 break;
259 }
260 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
261 if (sps->enc[count].page_shift == 0) {
262 break;
263 }
264 }
265 if ((p - prop) >= (maxcells - 3 - count * 2)) {
266 break;
267 }
268 *(p++) = cpu_to_be32(sps->page_shift);
269 *(p++) = cpu_to_be32(sps->slb_enc);
270 *(p++) = cpu_to_be32(count);
271 for (j = 0; j < count; j++) {
272 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
273 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
274 }
275 }
276
277 return (p - prop) * sizeof(uint32_t);
278}
279
b082d65a
AK		 280static hwaddr spapr_node0_size(void)
281{
fb164994
DG		 282 MachineState *machine = MACHINE(qdev_get_machine());
283
b082d65a
AK		 284 if (nb_numa_nodes) {
285 int i;
286 for (i = 0; i < nb_numa_nodes; ++i) {
287 if (numa_info[i].node_mem) {
fb164994
DG		 288 return MIN(pow2floor(numa_info[i].node_mem),
289 machine->ram_size);
b082d65a
AK		 290 }
291 }
292 }
fb164994 293 return machine->ram_size;
b082d65a
AK		 294}
295
7f763a5d
DG		 296#define _FDT(exp) \
297 do { \
298 int ret = (exp); \
299 if (ret < 0) { \
300 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
301 #exp, fdt_strerror(ret)); \
302 exit(1); \
303 } \
304 } while (0)
305
a1d59c0f
AK		 306static void add_str(GString *s, const gchar *s1)
307{
308 g_string_append_len(s, s1, strlen(s1) + 1);
309}
7f763a5d 310
3bbf37f2 311static void *spapr_create_fdt_skel(hwaddr initrd_base,
a8170e5e
AK		 312 hwaddr initrd_size,
313 hwaddr kernel_size,
16457e7f 314 bool little_endian,
74d042e5
DG		 315 const char *kernel_cmdline,
316 uint32_t epow_irq)
9fdf0c29
DG		 317{
318 void *fdt;
9fdf0c29
DG		 319 uint32_t start_prop = cpu_to_be32(initrd_base);
320 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
a1d59c0f
AK		 321 GString *hypertas = g_string_sized_new(256);
322 GString *qemu_hypertas = g_string_sized_new(256);
7f763a5d 323 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
9e734e3d 324 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
6e806cc3 325 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
ef951443 326 char *buf;
9fdf0c29 327
a1d59c0f
AK		 328 add_str(hypertas, "hcall-pft");
329 add_str(hypertas, "hcall-term");
330 add_str(hypertas, "hcall-dabr");
331 add_str(hypertas, "hcall-interrupt");
332 add_str(hypertas, "hcall-tce");
333 add_str(hypertas, "hcall-vio");
334 add_str(hypertas, "hcall-splpar");
335 add_str(hypertas, "hcall-bulk");
336 add_str(hypertas, "hcall-set-mode");
337 add_str(qemu_hypertas, "hcall-memop1");
338
7267c094 339 fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29
DG		 340 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
341
4d8d5467
BH		 342 if (kernel_size) {
343 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
344 }
345 if (initrd_size) {
346 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
347 }
9fdf0c29
DG		 348 _FDT((fdt_finish_reservemap(fdt)));
349
350 /* Root node */
351 _FDT((fdt_begin_node(fdt, "")));
352 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 353 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
d63919c9 354 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
9fdf0c29 355
ef951443
ND		 356 /*
357 * Add info to guest to indentify which host is it being run on
358 * and what is the uuid of the guest
359 */
360 if (kvmppc_get_host_model(&buf)) {
361 _FDT((fdt_property_string(fdt, "host-model", buf)));
362 g_free(buf);
363 }
364 if (kvmppc_get_host_serial(&buf)) {
365 _FDT((fdt_property_string(fdt, "host-serial", buf)));
366 g_free(buf);
367 }
368
369 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
370 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
371 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
372 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
373 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
374 qemu_uuid[14], qemu_uuid[15]);
375
376 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
377 g_free(buf);
378
2c1aaa81
SB		 379 if (qemu_get_vm_name()) {
380 _FDT((fdt_property_string(fdt, "ibm,partition-name",
381 qemu_get_vm_name())));
382 }
383
9fdf0c29
DG		 384 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
385 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
386
387 /* /chosen */
388 _FDT((fdt_begin_node(fdt, "chosen")));
389
6e806cc3
BR		 390 /* Set Form1_affinity */
391 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
392
9fdf0c29
DG		 393 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
394 _FDT((fdt_property(fdt, "linux,initrd-start",
395 &start_prop, sizeof(start_prop))));
396 _FDT((fdt_property(fdt, "linux,initrd-end",
397 &end_prop, sizeof(end_prop))));
4d8d5467
BH		 398 if (kernel_size) {
399 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
400 cpu_to_be64(kernel_size) };
9fdf0c29 401
4d8d5467 402 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
16457e7f
BH		 403 if (little_endian) {
404 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
405 }
4d8d5467 406 }
cc84c0f3
AS		 407 if (boot_menu) {
408 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
409 }
f28359d8
LZ		 410 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
411 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
412 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 413
9fdf0c29
DG		 414 _FDT((fdt_end_node(fdt)));
415
f43e3525
DG		 416 /* RTAS */
417 _FDT((fdt_begin_node(fdt, "rtas")));
418
da95324e
AK		 419 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
420 add_str(hypertas, "hcall-multi-tce");
421 }
a1d59c0f
AK		 422 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
423 hypertas->len)));
424 g_string_free(hypertas, TRUE);
425 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
426 qemu_hypertas->len)));
427 g_string_free(qemu_hypertas, TRUE);
f43e3525 428
6e806cc3
BR		 429 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
430 refpoints, sizeof(refpoints))));
431
74d042e5 432 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
79853e18
TD		 433 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
434 RTAS_EVENT_SCAN_RATE)));
74d042e5 435
a95f9922
SB		 436 if (msi_supported) {
437 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
438 }
439
2e14072f 440 /*
9d632f5f 441 * According to PAPR, rtas ibm,os-term does not guarantee a return
2e14072f
ND		 442 * back to the guest cpu.
443 *
444 * While an additional ibm,extended-os-term property indicates that
445 * rtas call return will always occur. Set this property.
446 */
447 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
448
f43e3525
DG		 449 _FDT((fdt_end_node(fdt)));
450
b5cec4c5 451 /* interrupt controller */
9dfef5aa 452 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG		 453
454 _FDT((fdt_property_string(fdt, "device_type",
455 "PowerPC-External-Interrupt-Presentation")));
456 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG		 457 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
458 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
459 interrupt_server_ranges_prop,
460 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG		 461 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
462 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
463 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG		 464
465 _FDT((fdt_end_node(fdt)));
466
4040ab72
DG		 467 /* vdevice */
468 _FDT((fdt_begin_node(fdt, "vdevice")));
469
470 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
471 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
472 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
473 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG		 474 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
475 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG		 476
477 _FDT((fdt_end_node(fdt)));
478
74d042e5
DG		 479 /* event-sources */
480 spapr_events_fdt_skel(fdt, epow_irq);
481
f7d69146
AG		 482 /* /hypervisor node */
483 if (kvm_enabled()) {
484 uint8_t hypercall[16];
485
486 /* indicate KVM hypercall interface */
487 _FDT((fdt_begin_node(fdt, "hypervisor")));
488 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
489 if (kvmppc_has_cap_fixup_hcalls()) {
490 /*
491 * Older KVM versions with older guest kernels were broken with the
492 * magic page, don't allow the guest to map it.
493 */
494 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
495 sizeof(hypercall));
496 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
497 sizeof(hypercall))));
498 }
499 _FDT((fdt_end_node(fdt)));
500 }
501
9fdf0c29
DG		 502 _FDT((fdt_end_node(fdt))); /* close root node */
503 _FDT((fdt_finish(fdt)));
504
a3467baa
DG		 505 return fdt;
506}
507
03d196b7 508static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
26a8c353
AK		 509 hwaddr size)
510{
511 uint32_t associativity[] = {
512 cpu_to_be32(0x4), /* length */
513 cpu_to_be32(0x0), cpu_to_be32(0x0),
c3b4f589 514 cpu_to_be32(0x0), cpu_to_be32(nodeid)
26a8c353
AK		 515 };
516 char mem_name[32];
517 uint64_t mem_reg_property[2];
518 int off;
519
520 mem_reg_property[0] = cpu_to_be64(start);
521 mem_reg_property[1] = cpu_to_be64(size);
522
523 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
524 off = fdt_add_subnode(fdt, 0, mem_name);
525 _FDT(off);
526 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
527 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
528 sizeof(mem_reg_property))));
529 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
530 sizeof(associativity))));
03d196b7 531 return off;
26a8c353
AK		 532}
533
28e02042 534static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
7f763a5d 535{
fb164994 536 MachineState *machine = MACHINE(spapr);
7db8a127
AK		 537 hwaddr mem_start, node_size;
538 int i, nb_nodes = nb_numa_nodes;
539 NodeInfo *nodes = numa_info;
540 NodeInfo ramnode;
541
542 /* No NUMA nodes, assume there is just one node with whole RAM */
543 if (!nb_numa_nodes) {
544 nb_nodes = 1;
fb164994 545 ramnode.node_mem = machine->ram_size;
7db8a127 546 nodes = &ramnode;
5fe269b1 547 }
7f763a5d 548
7db8a127
AK		 549 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
550 if (!nodes[i].node_mem) {
551 continue;
552 }
fb164994 553 if (mem_start >= machine->ram_size) {
5fe269b1
PM		 554 node_size = 0;
555 } else {
7db8a127 556 node_size = nodes[i].node_mem;
fb164994
DG		 557 if (node_size > machine->ram_size - mem_start) {
558 node_size = machine->ram_size - mem_start;
5fe269b1
PM		 559 }
560 }
7db8a127
AK		 561 if (!mem_start) {
562 /* ppc_spapr_init() checks for rma_size <= node0_size already */
e8f986fc 563 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
7db8a127
AK		 564 mem_start += spapr->rma_size;
565 node_size -= spapr->rma_size;
566 }
6010818c
AK		 567 for ( ; node_size; ) {
568 hwaddr sizetmp = pow2floor(node_size);
569
570 /* mem_start != 0 here */
571 if (ctzl(mem_start) < ctzl(sizetmp)) {
572 sizetmp = 1ULL << ctzl(mem_start);
573 }
574
575 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
576 node_size -= sizetmp;
577 mem_start += sizetmp;
578 }
7f763a5d
DG		 579 }
580
581 return 0;
582}
583
0da6f3fe
BR		 584static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
585 sPAPRMachineState *spapr)
586{
587 PowerPCCPU *cpu = POWERPC_CPU(cs);
588 CPUPPCState *env = &cpu->env;
589 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
590 int index = ppc_get_vcpu_dt_id(cpu);
591 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
592 0xffffffff, 0xffffffff};
593 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
594 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
595 uint32_t page_sizes_prop[64];
596 size_t page_sizes_prop_size;
22419c2a 597 uint32_t vcpus_per_socket = smp_threads * smp_cores;
0da6f3fe
BR		 598 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
599
600 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
601 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
602
603 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
604 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
605 env->dcache_line_size)));
606 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
607 env->dcache_line_size)));
608 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
609 env->icache_line_size)));
610 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
611 env->icache_line_size)));
612
613 if (pcc->l1_dcache_size) {
614 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
615 pcc->l1_dcache_size)));
616 } else {
617 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
618 }
619 if (pcc->l1_icache_size) {
620 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
621 pcc->l1_icache_size)));
622 } else {
623 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
624 }
625
626 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
627 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
628 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
629 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
630 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
631
632 if (env->spr_cb[SPR_PURR].oea_read) {
633 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
634 }
635
636 if (env->mmu_model & POWERPC_MMU_1TSEG) {
637 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
638 segs, sizeof(segs))));
639 }
640
641 /* Advertise VMX/VSX (vector extensions) if available
642 * 0 / no property == no vector extensions
643 * 1 == VMX / Altivec available
644 * 2 == VSX available */
645 if (env->insns_flags & PPC_ALTIVEC) {
646 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
647
648 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
649 }
650
651 /* Advertise DFP (Decimal Floating Point) if available
652 * 0 / no property == no DFP
653 * 1 == DFP available */
654 if (env->insns_flags2 & PPC2_DFP) {
655 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
656 }
657
658 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
659 sizeof(page_sizes_prop));
660 if (page_sizes_prop_size) {
661 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
662 page_sizes_prop, page_sizes_prop_size)));
663 }
664
665 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
22419c2a 666 cs->cpu_index / vcpus_per_socket)));
0da6f3fe
BR		 667
668 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
669 pft_size_prop, sizeof(pft_size_prop))));
670
671 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
672
673 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
674 ppc_get_compat_smt_threads(cpu)));
675}
676
677static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
678{
679 CPUState *cs;
680 int cpus_offset;
681 char *nodename;
682 int smt = kvmppc_smt_threads();
683
684 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
685 _FDT(cpus_offset);
686 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
687 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
688
689 /*
690 * We walk the CPUs in reverse order to ensure that CPU DT nodes
691 * created by fdt_add_subnode() end up in the right order in FDT
692 * for the guest kernel the enumerate the CPUs correctly.
693 */
694 CPU_FOREACH_REVERSE(cs) {
695 PowerPCCPU *cpu = POWERPC_CPU(cs);
696 int index = ppc_get_vcpu_dt_id(cpu);
697 DeviceClass *dc = DEVICE_GET_CLASS(cs);
698 int offset;
699
700 if ((index % smt) != 0) {
701 continue;
702 }
703
704 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
705 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
706 g_free(nodename);
707 _FDT(offset);
708 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
709 }
710
711}
712
03d196b7
BR		 713/*
714 * Adds ibm,dynamic-reconfiguration-memory node.
715 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
716 * of this device tree node.
717 */
718static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
719{
720 MachineState *machine = MACHINE(spapr);
721 int ret, i, offset;
722 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
723 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
e8f986fc 724 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
03d196b7 725 uint32_t *int_buf, *cur_index, buf_len;
6663864e 726 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
03d196b7 727
ef001f06
TH		 728 /*
729 * Allocate enough buffer size to fit in ibm,dynamic-memory
730 * or ibm,associativity-lookup-arrays
731 */
732 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
733 * sizeof(uint32_t);
03d196b7
BR		 734 cur_index = int_buf = g_malloc0(buf_len);
735
736 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
737
738 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
739 sizeof(prop_lmb_size));
740 if (ret < 0) {
741 goto out;
742 }
743
744 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
745 if (ret < 0) {
746 goto out;
747 }
748
749 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
750 if (ret < 0) {
751 goto out;
752 }
753
754 /* ibm,dynamic-memory */
755 int_buf[0] = cpu_to_be32(nr_lmbs);
756 cur_index++;
757 for (i = 0; i < nr_lmbs; i++) {
758 sPAPRDRConnector *drc;
759 sPAPRDRConnectorClass *drck;
e8f986fc 760 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
03d196b7
BR		 761 uint32_t *dynamic_memory = cur_index;
762
03d196b7
BR		 763 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
764 addr/lmb_size);
765 g_assert(drc);
766 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
767
768 dynamic_memory[0] = cpu_to_be32(addr >> 32);
769 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
770 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
771 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
772 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
773 if (addr < machine->ram_size ||
774 memory_region_present(get_system_memory(), addr)) {
775 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
776 } else {
777 dynamic_memory[5] = cpu_to_be32(0);
778 }
779
780 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
781 }
782 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
783 if (ret < 0) {
784 goto out;
785 }
786
787 /* ibm,associativity-lookup-arrays */
788 cur_index = int_buf;
6663864e 789 int_buf[0] = cpu_to_be32(nr_nodes);
03d196b7
BR		 790 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
791 cur_index += 2;
6663864e 792 for (i = 0; i < nr_nodes; i++) {
03d196b7
BR		 793 uint32_t associativity[] = {
794 cpu_to_be32(0x0),
795 cpu_to_be32(0x0),
796 cpu_to_be32(0x0),
797 cpu_to_be32(i)
798 };
799 memcpy(cur_index, associativity, sizeof(associativity));
800 cur_index += 4;
801 }
802 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
803 (cur_index - int_buf) * sizeof(uint32_t));
804out:
805 g_free(int_buf);
806 return ret;
807}
808
809int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
810 target_ulong addr, target_ulong size,
811 bool cpu_update, bool memory_update)
812{
813 void *fdt, *fdt_skel;
814 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
815 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
816
817 size -= sizeof(hdr);
818
819 /* Create sceleton */
820 fdt_skel = g_malloc0(size);
821 _FDT((fdt_create(fdt_skel, size)));
822 _FDT((fdt_begin_node(fdt_skel, "")));
823 _FDT((fdt_end_node(fdt_skel)));
824 _FDT((fdt_finish(fdt_skel)));
825 fdt = g_malloc0(size);
826 _FDT((fdt_open_into(fdt_skel, fdt, size)));
827 g_free(fdt_skel);
828
829 /* Fixup cpu nodes */
830 if (cpu_update) {
831 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
832 }
833
834 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */
835 if (memory_update && smc->dr_lmb_enabled) {
836 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
03d196b7
BR		 837 }
838
839 /* Pack resulting tree */
840 _FDT((fdt_pack(fdt)));
841
842 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
843 trace_spapr_cas_failed(size);
844 return -1;
845 }
846
847 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
848 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
849 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
850 g_free(fdt);
851
852 return 0;
853}
854
28e02042 855static void spapr_finalize_fdt(sPAPRMachineState *spapr,
a8170e5e
AK		 856 hwaddr fdt_addr,
857 hwaddr rtas_addr,
858 hwaddr rtas_size)
a3467baa 859{
5b2128d2 860 MachineState *machine = MACHINE(qdev_get_machine());
c20d332a 861 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
5b2128d2 862 const char *boot_device = machine->boot_order;
71461b0f
AK		 863 int ret, i;
864 size_t cb = 0;
865 char *bootlist;
a3467baa 866 void *fdt;
3384f95c 867 sPAPRPHBState *phb;
a3467baa 868
7267c094 869 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG		 870
871 /* open out the base tree into a temp buffer for the final tweaks */
872 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 873
e8f986fc
BR		 874 ret = spapr_populate_memory(spapr, fdt);
875 if (ret < 0) {
876 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
877 exit(1);
7f763a5d
DG		 878 }
879
4040ab72
DG		 880 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
881 if (ret < 0) {
882 fprintf(stderr, "couldn't setup vio devices in fdt\n");
883 exit(1);
884 }
885
4d9392be
TH		 886 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
887 ret = spapr_rng_populate_dt(fdt);
888 if (ret < 0) {
889 fprintf(stderr, "could not set up rng device in the fdt\n");
890 exit(1);
891 }
892 }
893
3384f95c 894 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 895 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
3384f95c
DG		 896 }
897
898 if (ret < 0) {
899 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
900 exit(1);
901 }
902
39ac8455
DG		 903 /* RTAS */
904 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
905 if (ret < 0) {
906 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
907 }
908
0da6f3fe
BR		 909 /* cpus */
910 spapr_populate_cpus_dt_node(fdt, spapr);
6e806cc3 911
71461b0f
AK		 912 bootlist = get_boot_devices_list(&cb, true);
913 if (cb && bootlist) {
914 int offset = fdt_path_offset(fdt, "/chosen");
915 if (offset < 0) {
916 exit(1);
917 }
918 for (i = 0; i < cb; i++) {
919 if (bootlist[i] == '\n') {
920 bootlist[i] = ' ';
921 }
922
923 }
924 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
925 }
926
5b2128d2
AG		 927 if (boot_device && strlen(boot_device)) {
928 int offset = fdt_path_offset(fdt, "/chosen");
929
930 if (offset < 0) {
931 exit(1);
932 }
933 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
934 }
935
3fc5acde 936 if (!spapr->has_graphics) {
f28359d8
LZ		 937 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
938 }
68f3a94c 939
c20d332a
BR		 940 if (smc->dr_lmb_enabled) {
941 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
942 }
943
4040ab72
DG		 944 _FDT((fdt_pack(fdt)));
945
4d8d5467 946 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
730fce59
TH		 947 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
948 fdt_totalsize(fdt), FDT_MAX_SIZE);
4d8d5467
BH		 949 exit(1);
950 }
951
ad440b4a 952 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
a3467baa 953 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 954
a21a7a70 955 g_free(bootlist);
7267c094 956 g_free(fdt);
9fdf0c29
DG		 957}
958
959static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
960{
961 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
962}
963
1b14670a 964static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 965{
1b14670a
AF		 966 CPUPPCState *env = &cpu->env;
967
efcb9383
DG		 968 if (msr_pr) {
969 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
970 env->gpr[3] = H_PRIVILEGE;
971 } else {
aa100fa4 972 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 973 }
9fdf0c29
DG		 974}
975
e6b8fd24
SMJ		 976#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
977#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
978#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
979#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
980#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
981
28e02042 982static void spapr_reset_htab(sPAPRMachineState *spapr)
7f763a5d
DG		 983{
984 long shift;
e6b8fd24 985 int index;
7f763a5d
DG		 986
987 /* allocate hash page table. For now we always make this 16mb,
988 * later we should probably make it scale to the size of guest
989 * RAM */
990
991 shift = kvmppc_reset_htab(spapr->htab_shift);
992
993 if (shift > 0) {
994 /* Kernel handles htab, we don't need to allocate one */
995 spapr->htab_shift = shift;
7c43bca0 996 kvmppc_kern_htab = true;
01a57972
SMJ		 997
998 /* Tell readers to update their file descriptor */
999 if (spapr->htab_fd >= 0) {
1000 spapr->htab_fd_stale = true;
1001 }
7f763a5d
DG		 1002 } else {
1003 if (!spapr->htab) {
1004 /* Allocate an htab if we don't yet have one */
1005 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
1006 }
1007
1008 /* And clear it */
1009 memset(spapr->htab, 0, HTAB_SIZE(spapr));
e6b8fd24
SMJ		 1010
1011 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
1012 DIRTY_HPTE(HPTE(spapr->htab, index));
1013 }
7f763a5d
DG		 1014 }
1015
1016 /* Update the RMA size if necessary */
1017 if (spapr->vrma_adjust) {
b082d65a
AK		 1018 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1019 spapr->htab_shift);
7f763a5d 1020 }
9fdf0c29
DG		 1021}
1022
9e3f9733
AG		 1023static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1024{
1025 bool matched = false;
1026
1027 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1028 matched = true;
1029 }
1030
1031 if (!matched) {
1032 error_report("Device %s is not supported by this machine yet.",
1033 qdev_fw_name(DEVICE(sbdev)));
1034 exit(1);
1035 }
1036
1037 return 0;
1038}
1039
01a57972
SMJ		 1040/*
1041 * A guest reset will cause spapr->htab_fd to become stale if being used.
1042 * Reopen the file descriptor to make sure the whole HTAB is properly read.
1043 */
28e02042 1044static int spapr_check_htab_fd(sPAPRMachineState *spapr)
01a57972
SMJ		 1045{
1046 int rc = 0;
1047
1048 if (spapr->htab_fd_stale) {
1049 close(spapr->htab_fd);
1050 spapr->htab_fd = kvmppc_get_htab_fd(false);
1051 if (spapr->htab_fd < 0) {
1052 error_report("Unable to open fd for reading hash table from KVM: "
730fce59 1053 "%s", strerror(errno));
01a57972
SMJ		 1054 rc = -1;
1055 }
1056 spapr->htab_fd_stale = false;
1057 }
1058
1059 return rc;
1060}
1061
c8787ad4 1062static void ppc_spapr_reset(void)
a3467baa 1063{
28e02042 1064 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
182735ef 1065 PowerPCCPU *first_ppc_cpu;
b7d1f77a 1066 uint32_t rtas_limit;
259186a7 1067
9e3f9733
AG		 1068 /* Check for unknown sysbus devices */
1069 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1070
7f763a5d
DG		 1071 /* Reset the hash table & recalc the RMA */
1072 spapr_reset_htab(spapr);
a3467baa 1073
c8787ad4 1074 qemu_devices_reset();
a3467baa 1075
b7d1f77a
BH		 1076 /*
1077 * We place the device tree and RTAS just below either the top of the RMA,
1078 * or just below 2GB, whichever is lowere, so that it can be
1079 * processed with 32-bit real mode code if necessary
1080 */
1081 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1082 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1083 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1084
a3467baa
DG		 1085 /* Load the fdt */
1086 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1087 spapr->rtas_size);
1088
b7d1f77a
BH		 1089 /* Copy RTAS over */
1090 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1091 spapr->rtas_size);
1092
a3467baa 1093 /* Set up the entry state */
182735ef
AF		 1094 first_ppc_cpu = POWERPC_CPU(first_cpu);
1095 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1096 first_ppc_cpu->env.gpr[5] = 0;
1097 first_cpu->halted = 0;
1b718907 1098 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
a3467baa
DG		 1099
1100}
1101
1bba0dc9
AF		 1102static void spapr_cpu_reset(void *opaque)
1103{
28e02042 1104 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
5b2038e0 1105 PowerPCCPU *cpu = opaque;
259186a7 1106 CPUState *cs = CPU(cpu);
048706d9 1107 CPUPPCState *env = &cpu->env;
1bba0dc9 1108
259186a7 1109 cpu_reset(cs);
048706d9
DG		 1110
1111 /* All CPUs start halted. CPU0 is unhalted from the machine level
1112 * reset code and the rest are explicitly started up by the guest
1113 * using an RTAS call */
259186a7 1114 cs->halted = 1;
048706d9
DG		 1115
1116 env->spr[SPR_HIOR] = 0;
7f763a5d 1117
4be21d56 1118 env->external_htab = (uint8_t *)spapr->htab;
5736245c
AK		 1119 if (kvm_enabled() && !env->external_htab) {
1120 /*
1121 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
1122 * functions do the right thing.
1123 */
1124 env->external_htab = (void *)1;
1125 }
7f763a5d 1126 env->htab_base = -1;
f3c75d42
AK		 1127 /*
1128 * htab_mask is the mask used to normalize hash value to PTEG index.
1129 * htab_shift is log2 of hash table size.
1130 * We have 8 hpte per group, and each hpte is 16 bytes.
1131 * ie have 128 bytes per hpte entry.
1132 */
28e02042 1133 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1;
ec4936e1 1134 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
7f763a5d 1135 (spapr->htab_shift - 18);
1bba0dc9
AF		 1136}
1137
28e02042 1138static void spapr_create_nvram(sPAPRMachineState *spapr)
639e8102 1139{
2ff3de68 1140 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
3978b863 1141 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
639e8102 1142
3978b863 1143 if (dinfo) {
4be74634 1144 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo));
639e8102
DG		 1145 }
1146
1147 qdev_init_nofail(dev);
1148
1149 spapr->nvram = (struct sPAPRNVRAM *)dev;
1150}
1151
28e02042 1152static void spapr_rtc_create(sPAPRMachineState *spapr)
28df36a1
DG		 1153{
1154 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1155
1156 qdev_init_nofail(dev);
1157 spapr->rtc = dev;
74e5ae28
DG		 1158
1159 object_property_add_alias(qdev_get_machine(), "rtc-time",
1160 OBJECT(spapr->rtc), "date", NULL);
28df36a1
DG		 1161}
1162
8c57b867 1163/* Returns whether we want to use VGA or not */
f28359d8
LZ		 1164static int spapr_vga_init(PCIBus *pci_bus)
1165{
8c57b867 1166 switch (vga_interface_type) {
8c57b867 1167 case VGA_NONE:
7effdaa3
MW		 1168 return false;
1169 case VGA_DEVICE:
1170 return true;
1ddcae82 1171 case VGA_STD:
b798c190 1172 case VGA_VIRTIO:
1ddcae82 1173 return pci_vga_init(pci_bus) != NULL;
8c57b867 1174 default:
f28359d8
LZ		 1175 fprintf(stderr, "This vga model is not supported,"
1176 "currently it only supports -vga std\n");
8c57b867 1177 exit(0);
f28359d8 1178 }
f28359d8
LZ		 1179}
1180
880ae7de
DG		 1181static int spapr_post_load(void *opaque, int version_id)
1182{
28e02042 1183 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
880ae7de
DG		 1184 int err = 0;
1185
631b22ea 1186 /* In earlier versions, there was no separate qdev for the PAPR
880ae7de
DG		 1187 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1188 * So when migrating from those versions, poke the incoming offset
1189 * value into the RTC device */
1190 if (version_id < 3) {
1191 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1192 }
1193
1194 return err;
1195}
1196
1197static bool version_before_3(void *opaque, int version_id)
1198{
1199 return version_id < 3;
1200}
1201
4be21d56
DG		 1202static const VMStateDescription vmstate_spapr = {
1203 .name = "spapr",
880ae7de 1204 .version_id = 3,
4be21d56 1205 .minimum_version_id = 1,
880ae7de 1206 .post_load = spapr_post_load,
3aff6c2f 1207 .fields = (VMStateField[]) {
880ae7de
DG		 1208 /* used to be @next_irq */
1209 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
4be21d56
DG		 1210
1211 /* RTC offset */
28e02042 1212 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
880ae7de 1213
28e02042 1214 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
4be21d56
DG		 1215 VMSTATE_END_OF_LIST()
1216 },
1217};
1218
4be21d56
DG		 1219static int htab_save_setup(QEMUFile *f, void *opaque)
1220{
28e02042 1221 sPAPRMachineState *spapr = opaque;
4be21d56 1222
4be21d56
DG		 1223 /* "Iteration" header */
1224 qemu_put_be32(f, spapr->htab_shift);
1225
e68cb8b4
AK		 1226 if (spapr->htab) {
1227 spapr->htab_save_index = 0;
1228 spapr->htab_first_pass = true;
1229 } else {
1230 assert(kvm_enabled());
1231
1232 spapr->htab_fd = kvmppc_get_htab_fd(false);
01a57972 1233 spapr->htab_fd_stale = false;
e68cb8b4
AK		 1234 if (spapr->htab_fd < 0) {
1235 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
1236 strerror(errno));
1237 return -1;
1238 }
1239 }
1240
1241
4be21d56
DG		 1242 return 0;
1243}
1244
28e02042 1245static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
4be21d56
DG		 1246 int64_t max_ns)
1247{
1248 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1249 int index = spapr->htab_save_index;
bc72ad67 1250 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1251
1252 assert(spapr->htab_first_pass);
1253
1254 do {
1255 int chunkstart;
1256
1257 /* Consume invalid HPTEs */
1258 while ((index < htabslots)
1259 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1260 index++;
1261 CLEAN_HPTE(HPTE(spapr->htab, index));
1262 }
1263
1264 /* Consume valid HPTEs */
1265 chunkstart = index;
338c25b6 1266 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1267 && HPTE_VALID(HPTE(spapr->htab, index))) {
1268 index++;
1269 CLEAN_HPTE(HPTE(spapr->htab, index));
1270 }
1271
1272 if (index > chunkstart) {
1273 int n_valid = index - chunkstart;
1274
1275 qemu_put_be32(f, chunkstart);
1276 qemu_put_be16(f, n_valid);
1277 qemu_put_be16(f, 0);
1278 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1279 HASH_PTE_SIZE_64 * n_valid);
1280
bc72ad67 1281 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1282 break;
1283 }
1284 }
1285 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1286
1287 if (index >= htabslots) {
1288 assert(index == htabslots);
1289 index = 0;
1290 spapr->htab_first_pass = false;
1291 }
1292 spapr->htab_save_index = index;
1293}
1294
28e02042 1295static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
e68cb8b4 1296 int64_t max_ns)
4be21d56
DG		 1297{
1298 bool final = max_ns < 0;
1299 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1300 int examined = 0, sent = 0;
1301 int index = spapr->htab_save_index;
bc72ad67 1302 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
4be21d56
DG		 1303
1304 assert(!spapr->htab_first_pass);
1305
1306 do {
1307 int chunkstart, invalidstart;
1308
1309 /* Consume non-dirty HPTEs */
1310 while ((index < htabslots)
1311 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1312 index++;
1313 examined++;
1314 }
1315
1316 chunkstart = index;
1317 /* Consume valid dirty HPTEs */
338c25b6 1318 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
4be21d56
DG		 1319 && HPTE_DIRTY(HPTE(spapr->htab, index))
1320 && HPTE_VALID(HPTE(spapr->htab, index))) {
1321 CLEAN_HPTE(HPTE(spapr->htab, index));
1322 index++;
1323 examined++;
1324 }
1325
1326 invalidstart = index;
1327 /* Consume invalid dirty HPTEs */
338c25b6 1328 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
4be21d56
DG		 1329 && HPTE_DIRTY(HPTE(spapr->htab, index))
1330 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1331 CLEAN_HPTE(HPTE(spapr->htab, index));
1332 index++;
1333 examined++;
1334 }
1335
1336 if (index > chunkstart) {
1337 int n_valid = invalidstart - chunkstart;
1338 int n_invalid = index - invalidstart;
1339
1340 qemu_put_be32(f, chunkstart);
1341 qemu_put_be16(f, n_valid);
1342 qemu_put_be16(f, n_invalid);
1343 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1344 HASH_PTE_SIZE_64 * n_valid);
1345 sent += index - chunkstart;
1346
bc72ad67 1347 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
4be21d56
DG		 1348 break;
1349 }
1350 }
1351
1352 if (examined >= htabslots) {
1353 break;
1354 }
1355
1356 if (index >= htabslots) {
1357 assert(index == htabslots);
1358 index = 0;
1359 }
1360 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1361
1362 if (index >= htabslots) {
1363 assert(index == htabslots);
1364 index = 0;
1365 }
1366
1367 spapr->htab_save_index = index;
1368
e68cb8b4 1369 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
4be21d56
DG		 1370}
1371
e68cb8b4
AK		 1372#define MAX_ITERATION_NS 5000000 /* 5 ms */
1373#define MAX_KVM_BUF_SIZE 2048
1374
4be21d56
DG		 1375static int htab_save_iterate(QEMUFile *f, void *opaque)
1376{
28e02042 1377 sPAPRMachineState *spapr = opaque;
e68cb8b4 1378 int rc = 0;
4be21d56
DG		 1379
1380 /* Iteration header */
1381 qemu_put_be32(f, 0);
1382
e68cb8b4
AK		 1383 if (!spapr->htab) {
1384 assert(kvm_enabled());
1385
01a57972
SMJ		 1386 rc = spapr_check_htab_fd(spapr);
1387 if (rc < 0) {
1388 return rc;
1389 }
1390
e68cb8b4
AK		 1391 rc = kvmppc_save_htab(f, spapr->htab_fd,
1392 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1393 if (rc < 0) {
1394 return rc;
1395 }
1396 } else if (spapr->htab_first_pass) {
4be21d56
DG		 1397 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1398 } else {
e68cb8b4 1399 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
4be21d56
DG		 1400 }
1401
1402 /* End marker */
1403 qemu_put_be32(f, 0);
1404 qemu_put_be16(f, 0);
1405 qemu_put_be16(f, 0);
1406
e68cb8b4 1407 return rc;
4be21d56
DG		 1408}
1409
1410static int htab_save_complete(QEMUFile *f, void *opaque)
1411{
28e02042 1412 sPAPRMachineState *spapr = opaque;
4be21d56
DG		 1413
1414 /* Iteration header */
1415 qemu_put_be32(f, 0);
1416
e68cb8b4
AK		 1417 if (!spapr->htab) {
1418 int rc;
1419
1420 assert(kvm_enabled());
1421
01a57972
SMJ		 1422 rc = spapr_check_htab_fd(spapr);
1423 if (rc < 0) {
1424 return rc;
1425 }
1426
e68cb8b4
AK		 1427 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
1428 if (rc < 0) {
1429 return rc;
1430 }
1431 close(spapr->htab_fd);
1432 spapr->htab_fd = -1;
1433 } else {
1434 htab_save_later_pass(f, spapr, -1);
1435 }
4be21d56
DG		 1436
1437 /* End marker */
1438 qemu_put_be32(f, 0);
1439 qemu_put_be16(f, 0);
1440 qemu_put_be16(f, 0);
1441
1442 return 0;
1443}
1444
1445static int htab_load(QEMUFile *f, void *opaque, int version_id)
1446{
28e02042 1447 sPAPRMachineState *spapr = opaque;
4be21d56 1448 uint32_t section_hdr;
e68cb8b4 1449 int fd = -1;
4be21d56
DG		 1450
1451 if (version_id < 1 || version_id > 1) {
1452 fprintf(stderr, "htab_load() bad version\n");
1453 return -EINVAL;
1454 }
1455
1456 section_hdr = qemu_get_be32(f);
1457
1458 if (section_hdr) {
1459 /* First section, just the hash shift */
1460 if (spapr->htab_shift != section_hdr) {
613e7a76
BR		 1461 error_report("htab_shift mismatch: source %d target %d",
1462 section_hdr, spapr->htab_shift);
4be21d56
DG		 1463 return -EINVAL;
1464 }
1465 return 0;
1466 }
1467
e68cb8b4
AK		 1468 if (!spapr->htab) {
1469 assert(kvm_enabled());
1470
1471 fd = kvmppc_get_htab_fd(true);
1472 if (fd < 0) {
1473 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
1474 strerror(errno));
1475 }
1476 }
1477
4be21d56
DG		 1478 while (true) {
1479 uint32_t index;
1480 uint16_t n_valid, n_invalid;
1481
1482 index = qemu_get_be32(f);
1483 n_valid = qemu_get_be16(f);
1484 n_invalid = qemu_get_be16(f);
1485
1486 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1487 /* End of Stream */
1488 break;
1489 }
1490
e68cb8b4 1491 if ((index + n_valid + n_invalid) >
4be21d56
DG		 1492 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1493 /* Bad index in stream */
1494 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
e68cb8b4
AK		 1495 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
1496 spapr->htab_shift);
4be21d56
DG		 1497 return -EINVAL;
1498 }
1499
e68cb8b4
AK		 1500 if (spapr->htab) {
1501 if (n_valid) {
1502 qemu_get_buffer(f, HPTE(spapr->htab, index),
1503 HASH_PTE_SIZE_64 * n_valid);
1504 }
1505 if (n_invalid) {
1506 memset(HPTE(spapr->htab, index + n_valid), 0,
1507 HASH_PTE_SIZE_64 * n_invalid);
1508 }
1509 } else {
1510 int rc;
1511
1512 assert(fd >= 0);
1513
1514 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1515 if (rc < 0) {
1516 return rc;
1517 }
4be21d56
DG		 1518 }
1519 }
1520
e68cb8b4
AK		 1521 if (!spapr->htab) {
1522 assert(fd >= 0);
1523 close(fd);
1524 }
1525
4be21d56
DG		 1526 return 0;
1527}
1528
1529static SaveVMHandlers savevm_htab_handlers = {
1530 .save_live_setup = htab_save_setup,
1531 .save_live_iterate = htab_save_iterate,
1532 .save_live_complete = htab_save_complete,
1533 .load_state = htab_load,
1534};
1535
5b2128d2
AG		 1536static void spapr_boot_set(void *opaque, const char *boot_device,
1537 Error **errp)
1538{
1539 MachineState *machine = MACHINE(qdev_get_machine());
1540 machine->boot_order = g_strdup(boot_device);
1541}
1542
bab99ea0
BR		 1543static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
1544{
1545 CPUPPCState *env = &cpu->env;
1546
1547 /* Set time-base frequency to 512 MHz */
1548 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1549
1550 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1551 * MSR[IP] should never be set.
1552 */
1553 env->msr_mask &= ~(1 << 6);
1554
1555 /* Tell KVM that we're in PAPR mode */
1556 if (kvm_enabled()) {
1557 kvmppc_set_papr(cpu);
1558 }
1559
1560 if (cpu->max_compat) {
1561 if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
1562 exit(1);
1563 }
1564 }
1565
1566 xics_cpu_setup(spapr->icp, cpu);
1567
1568 qemu_register_reset(spapr_cpu_reset, cpu);
1569}
1570
224245bf
DG		 1571/*
1572 * Reset routine for LMB DR devices.
1573 *
1574 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1575 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1576 * when it walks all its children devices. LMB devices reset occurs
1577 * as part of spapr_ppc_reset().
1578 */
1579static void spapr_drc_reset(void *opaque)
1580{
1581 sPAPRDRConnector *drc = opaque;
1582 DeviceState *d = DEVICE(drc);
1583
1584 if (d) {
1585 device_reset(d);
1586 }
1587}
1588
1589static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1590{
1591 MachineState *machine = MACHINE(spapr);
1592 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
e8f986fc 1593 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
224245bf
DG		 1594 int i;
1595
1596 for (i = 0; i < nr_lmbs; i++) {
1597 sPAPRDRConnector *drc;
1598 uint64_t addr;
1599
e8f986fc 1600 addr = i * lmb_size + spapr->hotplug_memory.base;
224245bf
DG		 1601 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1602 addr/lmb_size);
1603 qemu_register_reset(spapr_drc_reset, drc);
1604 }
1605}
1606
1607/*
1608 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1609 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1610 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1611 */
1612static void spapr_validate_node_memory(MachineState *machine)
1613{
1614 int i;
1615
1616 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE ||
1617 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1618 error_report("Can't support memory configuration where RAM size "
1619 "0x" RAM_ADDR_FMT " or maxmem size "
1620 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB",
1621 machine->ram_size, machine->maxram_size,
1622 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1623 exit(EXIT_FAILURE);
1624 }
1625
1626 for (i = 0; i < nb_numa_nodes; i++) {
1627 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1628 error_report("Can't support memory configuration where memory size"
1629 " %" PRIx64 " of node %d isn't aligned to %llu MB",
1630 numa_info[i].node_mem, i,
1631 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1632 exit(EXIT_FAILURE);
1633 }
1634 }
1635}
1636
9fdf0c29 1637/* pSeries LPAR / sPAPR hardware init */
3ef96221 1638static void ppc_spapr_init(MachineState *machine)
9fdf0c29 1639{
28e02042 1640 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
224245bf 1641 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
3ef96221
MA		 1642 const char *kernel_filename = machine->kernel_filename;
1643 const char *kernel_cmdline = machine->kernel_cmdline;
1644 const char *initrd_filename = machine->initrd_filename;
05769733 1645 PowerPCCPU *cpu;
8c9f64df 1646 PCIHostState *phb;
9fdf0c29 1647 int i;
890c2b77
AK		 1648 MemoryRegion *sysmem = get_system_memory();
1649 MemoryRegion *ram = g_new(MemoryRegion, 1);
658fa66b
AK		 1650 MemoryRegion *rma_region;
1651 void *rma = NULL;
a8170e5e 1652 hwaddr rma_alloc_size;
b082d65a 1653 hwaddr node0_size = spapr_node0_size();
4d8d5467
BH		 1654 uint32_t initrd_base = 0;
1655 long kernel_size = 0, initrd_size = 0;
b7d1f77a 1656 long load_limit, fw_size;
16457e7f 1657 bool kernel_le = false;
39ac8455 1658 char *filename;
9fdf0c29 1659
0ee2c058
AK		 1660 msi_supported = true;
1661
d43b45e2
DG		 1662 QLIST_INIT(&spapr->phbs);
1663
9fdf0c29
DG		 1664 cpu_ppc_hypercall = emulate_spapr_hypercall;
1665
354ac20a 1666 /* Allocate RMA if necessary */
658fa66b 1667 rma_alloc_size = kvmppc_alloc_rma(&rma);
354ac20a
DG		 1668
1669 if (rma_alloc_size == -1) {
730fce59 1670 error_report("Unable to create RMA");
354ac20a
DG		 1671 exit(1);
1672 }
7f763a5d 1673
c4177479 1674 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
7f763a5d 1675 spapr->rma_size = rma_alloc_size;
354ac20a 1676 } else {
c4177479 1677 spapr->rma_size = node0_size;
7f763a5d
DG		 1678
1679 /* With KVM, we don't actually know whether KVM supports an
1680 * unbounded RMA (PR KVM) or is limited by the hash table size
1681 * (HV KVM using VRMA), so we always assume the latter
1682 *
1683 * In that case, we also limit the initial allocations for RTAS
1684 * etc... to 256M since we have no way to know what the VRMA size
1685 * is going to be as it depends on the size of the hash table
1686 * isn't determined yet.
1687 */
1688 if (kvm_enabled()) {
1689 spapr->vrma_adjust = 1;
1690 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1691 }
354ac20a
DG		 1692 }
1693
c4177479
AK		 1694 if (spapr->rma_size > node0_size) {
1695 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
1696 spapr->rma_size);
1697 exit(1);
1698 }
1699
b7d1f77a
BH		 1700 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1701 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
9fdf0c29 1702
382be75d
DG		 1703 /* We aim for a hash table of size 1/128 the size of RAM. The
1704 * normal rule of thumb is 1/64 the size of RAM, but that's much
1705 * more than needed for the Linux guests we support. */
1706 spapr->htab_shift = 18; /* Minimum architected size */
1707 while (spapr->htab_shift <= 46) {
ce881f77 1708 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) {
382be75d
DG		 1709 break;
1710 }
1711 spapr->htab_shift++;
1712 }
7f763a5d 1713
7b565160 1714 /* Set up Interrupt Controller before we create the VCPUs */
446f16a6 1715 spapr->icp = xics_system_init(machine,
9e734e3d 1716 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
f303f117 1717 smp_threads),
7b565160 1718 XICS_IRQS);
7b565160 1719
224245bf
DG		 1720 if (smc->dr_lmb_enabled) {
1721 spapr_validate_node_memory(machine);
1722 }
1723
9fdf0c29 1724 /* init CPUs */
19fb2c36
BR		 1725 if (machine->cpu_model == NULL) {
1726 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29
DG		 1727 }
1728 for (i = 0; i < smp_cpus; i++) {
19fb2c36 1729 cpu = cpu_ppc_init(machine->cpu_model);
05769733 1730 if (cpu == NULL) {
9fdf0c29
DG		 1731 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
1732 exit(1);
1733 }
bab99ea0 1734 spapr_cpu_init(spapr, cpu);
9fdf0c29
DG		 1735 }
1736
026bfd89
DG		 1737 if (kvm_enabled()) {
1738 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1739 kvmppc_enable_logical_ci_hcalls();
ef9971dd 1740 kvmppc_enable_set_mode_hcall();
026bfd89
DG		 1741 }
1742
9fdf0c29 1743 /* allocate RAM */
f92f5da1 1744 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
fb164994 1745 machine->ram_size);
f92f5da1 1746 memory_region_add_subregion(sysmem, 0, ram);
9fdf0c29 1747
658fa66b
AK		 1748 if (rma_alloc_size && rma) {
1749 rma_region = g_new(MemoryRegion, 1);
1750 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1751 rma_alloc_size, rma);
1752 vmstate_register_ram_global(rma_region);
1753 memory_region_add_subregion(sysmem, 0, rma_region);
1754 }
1755
4a1c9cf0
BR		 1756 /* initialize hotplug memory address space */
1757 if (machine->ram_size < machine->maxram_size) {
1758 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1759
1760 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
19a35c9e
BR		 1761 error_report("Specified number of memory slots %"PRIu64" exceeds max supported %d\n",
1762 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
4a1c9cf0
BR		 1763 exit(EXIT_FAILURE);
1764 }
1765
1766 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1767 SPAPR_HOTPLUG_MEM_ALIGN);
1768 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1769 "hotplug-memory", hotplug_mem_size);
1770 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1771 &spapr->hotplug_memory.mr);
1772 }
1773
224245bf
DG		 1774 if (smc->dr_lmb_enabled) {
1775 spapr_create_lmb_dr_connectors(spapr);
1776 }
1777
39ac8455 1778 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
4c56440d 1779 if (!filename) {
730fce59 1780 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
4c56440d
SW		 1781 exit(1);
1782 }
b7d1f77a
BH		 1783 spapr->rtas_size = get_image_size(filename);
1784 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1785 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
730fce59 1786 error_report("Could not load LPAR rtas '%s'", filename);
39ac8455
DG		 1787 exit(1);
1788 }
4d8d5467 1789 if (spapr->rtas_size > RTAS_MAX_SIZE) {
730fce59
TH		 1790 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1791 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
4d8d5467
BH		 1792 exit(1);
1793 }
7267c094 1794 g_free(filename);
39ac8455 1795
74d042e5
DG		 1796 /* Set up EPOW events infrastructure */
1797 spapr_events_init(spapr);
1798
12f42174 1799 /* Set up the RTC RTAS interfaces */
28df36a1 1800 spapr_rtc_create(spapr);
12f42174 1801
b5cec4c5 1802 /* Set up VIO bus */
4040ab72
DG		 1803 spapr->vio_bus = spapr_vio_bus_init();
1804
277f9acf 1805 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 1806 if (serial_hds[i]) {
d601fac4 1807 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG		 1808 }
1809 }
9fdf0c29 1810
639e8102
DG		 1811 /* We always have at least the nvram device on VIO */
1812 spapr_create_nvram(spapr);
1813
3384f95c 1814 /* Set up PCI */
fa28f71b
AK		 1815 spapr_pci_rtas_init();
1816
89dfd6e1 1817 phb = spapr_create_phb(spapr, 0);
3384f95c 1818
277f9acf 1819 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG		 1820 NICInfo *nd = &nd_table[i];
1821
1822 if (!nd->model) {
7267c094 1823 nd->model = g_strdup("ibmveth");
8d90ad90
DG		 1824 }
1825
1826 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 1827 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 1828 } else {
29b358f9 1829 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
8d90ad90
DG		 1830 }
1831 }
1832
6e270446 1833 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 1834 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH		 1835 }
1836
f28359d8 1837 /* Graphics */
8c9f64df 1838 if (spapr_vga_init(phb->bus)) {
3fc5acde 1839 spapr->has_graphics = true;
c6e76503 1840 machine->usb |= defaults_enabled() && !machine->usb_disabled;
f28359d8
LZ		 1841 }
1842
4ee9ced9 1843 if (machine->usb) {
8c9f64df 1844 pci_create_simple(phb->bus, -1, "pci-ohci");
c86580b8 1845
35139a59 1846 if (spapr->has_graphics) {
c86580b8
MA		 1847 USBBus *usb_bus = usb_bus_find(-1);
1848
1849 usb_create_simple(usb_bus, "usb-kbd");
1850 usb_create_simple(usb_bus, "usb-mouse");
35139a59
DG		 1851 }
1852 }
1853
7f763a5d 1854 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
4d8d5467
BH		 1855 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
1856 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
1857 exit(1);
1858 }
1859
9fdf0c29
DG		 1860 if (kernel_filename) {
1861 uint64_t lowaddr = 0;
1862
9fdf0c29 1863 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
4ecd4d16 1864 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
3b66da82 1865 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
16457e7f
BH		 1866 kernel_size = load_elf(kernel_filename,
1867 translate_kernel_address, NULL,
4ecd4d16 1868 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0);
16457e7f
BH		 1869 kernel_le = kernel_size > 0;
1870 }
9fdf0c29 1871 if (kernel_size < 0) {
3b66da82
AK		 1872 fprintf(stderr, "qemu: error loading %s: %s\n",
1873 kernel_filename, load_elf_strerror(kernel_size));
9fdf0c29
DG		 1874 exit(1);
1875 }
1876
1877 /* load initrd */
1878 if (initrd_filename) {
4d8d5467
BH		 1879 /* Try to locate the initrd in the gap between the kernel
1880 * and the firmware. Add a bit of space just in case
1881 */
1882 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 1883 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 1884 load_limit - initrd_base);
9fdf0c29
DG		 1885 if (initrd_size < 0) {
1886 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1887 initrd_filename);
1888 exit(1);
1889 }
1890 } else {
1891 initrd_base = 0;
1892 initrd_size = 0;
1893 }
4d8d5467 1894 }
a3467baa 1895
8e7ea787
AF		 1896 if (bios_name == NULL) {
1897 bios_name = FW_FILE_NAME;
1898 }
1899 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
4c56440d 1900 if (!filename) {
68fea5a0 1901 error_report("Could not find LPAR firmware '%s'", bios_name);
4c56440d
SW		 1902 exit(1);
1903 }
4d8d5467 1904 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
68fea5a0
TH		 1905 if (fw_size <= 0) {
1906 error_report("Could not load LPAR firmware '%s'", filename);
4d8d5467
BH		 1907 exit(1);
1908 }
1909 g_free(filename);
4d8d5467 1910
28e02042
DG		 1911 /* FIXME: Should register things through the MachineState's qdev
1912 * interface, this is a legacy from the sPAPREnvironment structure
1913 * which predated MachineState but had a similar function */
4be21d56
DG		 1914 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1915 register_savevm_live(NULL, "spapr/htab", -1, 1,
1916 &savevm_htab_handlers, spapr);
1917
9fdf0c29 1918 /* Prepare the device tree */
3bbf37f2 1919 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
16457e7f 1920 kernel_size, kernel_le,
31fe14d1
NF		 1921 kernel_cmdline,
1922 spapr->check_exception_irq);
a3467baa 1923 assert(spapr->fdt_skel != NULL);
5b2128d2 1924
46503c2b
MR		 1925 /* used by RTAS */
1926 QTAILQ_INIT(&spapr->ccs_list);
1927 qemu_register_reset(spapr_ccs_reset_hook, spapr);
1928
5b2128d2 1929 qemu_register_boot_set(spapr_boot_set, spapr);
9fdf0c29
DG		 1930}
1931
135a129a
AK		 1932static int spapr_kvm_type(const char *vm_type)
1933{
1934 if (!vm_type) {
1935 return 0;
1936 }
1937
1938 if (!strcmp(vm_type, "HV")) {
1939 return 1;
1940 }
1941
1942 if (!strcmp(vm_type, "PR")) {
1943 return 2;
1944 }
1945
1946 error_report("Unknown kvm-type specified '%s'", vm_type);
1947 exit(1);
1948}
1949
71461b0f 1950/*
627b84f4 1951 * Implementation of an interface to adjust firmware path
71461b0f
AK		 1952 * for the bootindex property handling.
1953 */
1954static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
1955 DeviceState *dev)
1956{
1957#define CAST(type, obj, name) \
1958 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1959 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
1960 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
1961
1962 if (d) {
1963 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
1964 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
1965 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
1966
1967 if (spapr) {
1968 /*
1969 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1970 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1971 * in the top 16 bits of the 64-bit LUN
1972 */
1973 unsigned id = 0x8000 | (d->id << 8) | d->lun;
1974 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1975 (uint64_t)id << 48);
1976 } else if (virtio) {
1977 /*
1978 * We use SRP luns of the form 01000000 | (target << 8) | lun
1979 * in the top 32 bits of the 64-bit LUN
1980 * Note: the quote above is from SLOF and it is wrong,
1981 * the actual binding is:
1982 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1983 */
1984 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
1985 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1986 (uint64_t)id << 32);
1987 } else if (usb) {
1988 /*
1989 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1990 * in the top 32 bits of the 64-bit LUN
1991 */
1992 unsigned usb_port = atoi(usb->port->path);
1993 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
1994 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
1995 (uint64_t)id << 32);
1996 }
1997 }
1998
1999 if (phb) {
2000 /* Replace "pci" with "pci@800000020000000" */
2001 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2002 }
2003
2004 return NULL;
2005}
2006
23825581
EH		 2007static char *spapr_get_kvm_type(Object *obj, Error **errp)
2008{
28e02042 2009 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2010
28e02042 2011 return g_strdup(spapr->kvm_type);
23825581
EH		 2012}
2013
2014static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2015{
28e02042 2016 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
23825581 2017
28e02042
DG		 2018 g_free(spapr->kvm_type);
2019 spapr->kvm_type = g_strdup(value);
23825581
EH		 2020}
2021
2022static void spapr_machine_initfn(Object *obj)
2023{
2024 object_property_add_str(obj, "kvm-type",
2025 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
49d2e648
MA		 2026 object_property_set_description(obj, "kvm-type",
2027 "Specifies the KVM virtualization mode (HV, PR)",
2028 NULL);
23825581
EH		 2029}
2030
34316482
AK		 2031static void ppc_cpu_do_nmi_on_cpu(void *arg)
2032{
2033 CPUState *cs = arg;
2034
2035 cpu_synchronize_state(cs);
2036 ppc_cpu_do_system_reset(cs);
2037}
2038
2039static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2040{
2041 CPUState *cs;
2042
2043 CPU_FOREACH(cs) {
2044 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2045 }
2046}
2047
c20d332a
BR		 2048static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2049 uint32_t node, Error **errp)
2050{
2051 sPAPRDRConnector *drc;
2052 sPAPRDRConnectorClass *drck;
2053 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2054 int i, fdt_offset, fdt_size;
2055 void *fdt;
2056
2057 /*
2058 * Check for DRC connectors and send hotplug notification to the
2059 * guest only in case of hotplugged memory. This allows cold plugged
2060 * memory to be specified at boot time.
2061 */
2062 if (!dev->hotplugged) {
2063 return;
2064 }
2065
2066 for (i = 0; i < nr_lmbs; i++) {
2067 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2068 addr/SPAPR_MEMORY_BLOCK_SIZE);
2069 g_assert(drc);
2070
2071 fdt = create_device_tree(&fdt_size);
2072 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2073 SPAPR_MEMORY_BLOCK_SIZE);
2074
2075 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2076 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
c20d332a
BR		 2077 addr += SPAPR_MEMORY_BLOCK_SIZE;
2078 }
0a417869 2079 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
c20d332a
BR		 2080}
2081
2082static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2083 uint32_t node, Error **errp)
2084{
2085 Error *local_err = NULL;
2086 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2087 PCDIMMDevice *dimm = PC_DIMM(dev);
2088 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2089 MemoryRegion *mr = ddc->get_memory_region(dimm);
2090 uint64_t align = memory_region_get_alignment(mr);
2091 uint64_t size = memory_region_size(mr);
2092 uint64_t addr;
2093
2094 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2095 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2096 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2097 goto out;
2098 }
2099
df0acded 2100 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, false, &local_err);
c20d332a
BR		 2101 if (local_err) {
2102 goto out;
2103 }
2104
2105 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2106 if (local_err) {
2107 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2108 goto out;
2109 }
2110
2111 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2112
2113out:
2114 error_propagate(errp, local_err);
2115}
2116
2117static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2118 DeviceState *dev, Error **errp)
2119{
2120 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2121
2122 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
b556854b 2123 int node;
c20d332a
BR		 2124
2125 if (!smc->dr_lmb_enabled) {
2126 error_setg(errp, "Memory hotplug not supported for this machine");
2127 return;
2128 }
2129 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2130 if (*errp) {
2131 return;
2132 }
2133
b556854b
BR		 2134 /*
2135 * Currently PowerPC kernel doesn't allow hot-adding memory to
2136 * memory-less node, but instead will silently add the memory
2137 * to the first node that has some memory. This causes two
2138 * unexpected behaviours for the user.
2139 *
2140 * - Memory gets hotplugged to a different node than what the user
2141 * specified.
2142 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2143 * to memory-less node, a reboot will set things accordingly
2144 * and the previously hotplugged memory now ends in the right node.
2145 * This appears as if some memory moved from one node to another.
2146 *
2147 * So until kernel starts supporting memory hotplug to memory-less
2148 * nodes, just prevent such attempts upfront in QEMU.
2149 */
2150 if (nb_numa_nodes && !numa_info[node].node_mem) {
2151 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2152 node);
2153 return;
2154 }
2155
c20d332a
BR		 2156 spapr_memory_plug(hotplug_dev, dev, node, errp);
2157 }
2158}
2159
2160static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2161 DeviceState *dev, Error **errp)
2162{
2163 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2164 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2165 }
2166}
2167
2168static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2169 DeviceState *dev)
2170{
2171 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2172 return HOTPLUG_HANDLER(machine);
2173 }
2174 return NULL;
2175}
2176
20bb648d
DG		 2177static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2178{
2179 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2180 * socket means much for the paravirtualized PAPR platform) */
2181 return cpu_index / smp_threads / smp_cores;
2182}
2183
29ee3247
AK		 2184static void spapr_machine_class_init(ObjectClass *oc, void *data)
2185{
2186 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2187 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
71461b0f 2188 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
34316482 2189 NMIClass *nc = NMI_CLASS(oc);
c20d332a 2190 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
958db90c 2191
958db90c
MA		 2192 mc->init = ppc_spapr_init;
2193 mc->reset = ppc_spapr_reset;
2194 mc->block_default_type = IF_SCSI;
38b02bd8 2195 mc->max_cpus = MAX_CPUMASK_BITS;
958db90c 2196 mc->no_parallel = 1;
5b2128d2 2197 mc->default_boot_order = "";
a34944fe 2198 mc->default_ram_size = 512 * M_BYTE;
958db90c 2199 mc->kvm_type = spapr_kvm_type;
9e3f9733 2200 mc->has_dynamic_sysbus = true;
e4024630 2201 mc->pci_allow_0_address = true;
c20d332a
BR		 2202 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2203 hc->plug = spapr_machine_device_plug;
2204 hc->unplug = spapr_machine_device_unplug;
20bb648d 2205 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
00b4fbe2 2206
224245bf 2207 smc->dr_lmb_enabled = false;
71461b0f 2208 fwc->get_dev_path = spapr_get_fw_dev_path;
34316482 2209 nc->nmi_monitor_handler = spapr_nmi;
29ee3247
AK		 2210}
2211
2212static const TypeInfo spapr_machine_info = {
2213 .name = TYPE_SPAPR_MACHINE,
2214 .parent = TYPE_MACHINE,
4aee7362 2215 .abstract = true,
6ca1502e 2216 .instance_size = sizeof(sPAPRMachineState),
23825581 2217 .instance_init = spapr_machine_initfn,
183930c0 2218 .class_size = sizeof(sPAPRMachineClass),
29ee3247 2219 .class_init = spapr_machine_class_init,
71461b0f
AK		 2220 .interfaces = (InterfaceInfo[]) {
2221 { TYPE_FW_PATH_PROVIDER },
34316482 2222 { TYPE_NMI },
c20d332a 2223 { TYPE_HOTPLUG_HANDLER },
71461b0f
AK		 2224 { }
2225 },
29ee3247
AK		 2226};
2227
38ff32c6 2228#define SPAPR_COMPAT_2_3 \
7619c7b0
MR		 2229 HW_COMPAT_2_3 \
2230 {\
2231 .driver = "spapr-pci-host-bridge",\
2232 .property = "dynamic-reconfiguration",\
2233 .value = "off",\
2234 },
38ff32c6 2235
b194df47 2236#define SPAPR_COMPAT_2_2 \
38ff32c6 2237 SPAPR_COMPAT_2_3 \
4dfd8eaa 2238 HW_COMPAT_2_2 \
b194df47
AK		 2239 {\
2240 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2241 .property = "mem_win_size",\
2242 .value = "0x20000000",\
dd754baf 2243 },
b194df47
AK		 2244
2245#define SPAPR_COMPAT_2_1 \
4dfd8eaa
EH		 2246 SPAPR_COMPAT_2_2 \
2247 HW_COMPAT_2_1
b194df47 2248
d25228e7
JW		 2249static void spapr_compat_2_3(Object *obj)
2250{
ff14e817 2251 savevm_skip_section_footers();
13d16814 2252 global_state_set_optional();
d25228e7
JW		 2253}
2254
b0e966d0
JW		 2255static void spapr_compat_2_2(Object *obj)
2256{
d25228e7 2257 spapr_compat_2_3(obj);
b0e966d0
JW		 2258}
2259
2260static void spapr_compat_2_1(Object *obj)
2261{
2262 spapr_compat_2_2(obj);
2263}
2264
d25228e7
JW		 2265static void spapr_machine_2_3_instance_init(Object *obj)
2266{
2267 spapr_compat_2_3(obj);
2268 spapr_machine_initfn(obj);
2269}
2270
b0e966d0
JW		 2271static void spapr_machine_2_2_instance_init(Object *obj)
2272{
2273 spapr_compat_2_2(obj);
2274 spapr_machine_initfn(obj);
2275}
2276
2277static void spapr_machine_2_1_instance_init(Object *obj)
2278{
2279 spapr_compat_2_1(obj);
2280 spapr_machine_initfn(obj);
2281}
2282
6026db45
AK		 2283static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data)
2284{
2285 MachineClass *mc = MACHINE_CLASS(oc);
68a27b20 2286 static GlobalProperty compat_props[] = {
dd754baf 2287 SPAPR_COMPAT_2_1
68a27b20
MT		 2288 { /* end of list */ }
2289 };
6026db45 2290
6026db45 2291 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1";
68a27b20 2292 mc->compat_props = compat_props;
6026db45
AK		 2293}
2294
2295static const TypeInfo spapr_machine_2_1_info = {
b9f072d0 2296 .name = MACHINE_TYPE_NAME("pseries-2.1"),
6026db45
AK		 2297 .parent = TYPE_SPAPR_MACHINE,
2298 .class_init = spapr_machine_2_1_class_init,
b0e966d0 2299 .instance_init = spapr_machine_2_1_instance_init,
6026db45
AK		 2300};
2301
4aee7362
DG		 2302static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data)
2303{
b194df47 2304 static GlobalProperty compat_props[] = {
dd754baf 2305 SPAPR_COMPAT_2_2
b194df47
AK		 2306 { /* end of list */ }
2307 };
4aee7362
DG		 2308 MachineClass *mc = MACHINE_CLASS(oc);
2309
4aee7362 2310 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2";
b194df47 2311 mc->compat_props = compat_props;
4aee7362
DG		 2312}
2313
2314static const TypeInfo spapr_machine_2_2_info = {
b9f072d0 2315 .name = MACHINE_TYPE_NAME("pseries-2.2"),
4aee7362
DG		 2316 .parent = TYPE_SPAPR_MACHINE,
2317 .class_init = spapr_machine_2_2_class_init,
b0e966d0 2318 .instance_init = spapr_machine_2_2_instance_init,
4aee7362
DG		 2319};
2320
3dab0244
AK		 2321static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data)
2322{
a1a45612 2323 static GlobalProperty compat_props[] = {
7619c7b0 2324 SPAPR_COMPAT_2_3
a1a45612
DG		 2325 { /* end of list */ }
2326 };
3dab0244
AK		 2327 MachineClass *mc = MACHINE_CLASS(oc);
2328
3dab0244 2329 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3";
a1a45612 2330 mc->compat_props = compat_props;
3dab0244
AK		 2331}
2332
2333static const TypeInfo spapr_machine_2_3_info = {
b9f072d0 2334 .name = MACHINE_TYPE_NAME("pseries-2.3"),
3dab0244
AK		 2335 .parent = TYPE_SPAPR_MACHINE,
2336 .class_init = spapr_machine_2_3_class_init,
d25228e7
JW		 2337 .instance_init = spapr_machine_2_3_instance_init,
2338};
2339
2340static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data)
2341{
2342 MachineClass *mc = MACHINE_CLASS(oc);
2343
d25228e7
JW		 2344 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4";
2345 mc->alias = "pseries";
fb0fc8f6 2346 mc->is_default = 0;
d25228e7
JW		 2347}
2348
2349static const TypeInfo spapr_machine_2_4_info = {
b9f072d0 2350 .name = MACHINE_TYPE_NAME("pseries-2.4"),
d25228e7
JW		 2351 .parent = TYPE_SPAPR_MACHINE,
2352 .class_init = spapr_machine_2_4_class_init,
3dab0244
AK		 2353};
2354
fb0fc8f6
DG		 2355static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data)
2356{
2357 MachineClass *mc = MACHINE_CLASS(oc);
224245bf 2358 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
fb0fc8f6
DG		 2359
2360 mc->name = "pseries-2.5";
2361 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5";
2362 mc->alias = "pseries";
2363 mc->is_default = 1;
224245bf 2364 smc->dr_lmb_enabled = true;
fb0fc8f6
DG		 2365}
2366
2367static const TypeInfo spapr_machine_2_5_info = {
2368 .name = MACHINE_TYPE_NAME("pseries-2.5"),
2369 .parent = TYPE_SPAPR_MACHINE,
2370 .class_init = spapr_machine_2_5_class_init,
2371};
2372
29ee3247 2373static void spapr_machine_register_types(void)
9fdf0c29 2374{
29ee3247 2375 type_register_static(&spapr_machine_info);
6026db45 2376 type_register_static(&spapr_machine_2_1_info);
4aee7362 2377 type_register_static(&spapr_machine_2_2_info);
3dab0244 2378 type_register_static(&spapr_machine_2_3_info);
d25228e7 2379 type_register_static(&spapr_machine_2_4_info);
fb0fc8f6 2380 type_register_static(&spapr_machine_2_5_info);
9fdf0c29
DG		 2381}
2382
29ee3247 2383type_init(spapr_machine_register_types)
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