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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
9fdf0c29 | 29 | #include "elf.h" |
1422e32d | 30 | #include "net/net.h" |
9c17d615 PB |
31 | #include "sysemu/blockdev.h" |
32 | #include "sysemu/cpus.h" | |
33 | #include "sysemu/kvm.h" | |
e97c3636 | 34 | #include "kvm_ppc.h" |
4be21d56 | 35 | #include "mmu-hash64.h" |
9fdf0c29 DG |
36 | |
37 | #include "hw/boards.h" | |
0d09e41a | 38 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
39 | #include "hw/loader.h" |
40 | ||
0d09e41a PB |
41 | #include "hw/ppc/spapr.h" |
42 | #include "hw/ppc/spapr_vio.h" | |
43 | #include "hw/pci-host/spapr.h" | |
44 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 45 | #include "hw/pci/msi.h" |
9fdf0c29 | 46 | |
83c9f4ca | 47 | #include "hw/pci/pci.h" |
f61b4bed | 48 | |
022c62cb | 49 | #include "exec/address-spaces.h" |
35139a59 | 50 | #include "hw/usb.h" |
1de7afc9 | 51 | #include "qemu/config-file.h" |
135a129a | 52 | #include "qemu/error-report.h" |
890c2b77 | 53 | |
9fdf0c29 DG |
54 | #include <libfdt.h> |
55 | ||
4d8d5467 BH |
56 | /* SLOF memory layout: |
57 | * | |
58 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
59 | * device-tree, then position SLOF itself 31M below that | |
60 | * | |
61 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
62 | * and more | |
63 | * | |
64 | * We load our kernel at 4M, leaving space for SLOF initial image | |
65 | */ | |
3bf6eedd | 66 | #define FDT_MAX_SIZE 0x40000 |
39ac8455 | 67 | #define RTAS_MAX_SIZE 0x10000 |
a9f8ad8f DG |
68 | #define FW_MAX_SIZE 0x400000 |
69 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
70 | #define FW_OVERHEAD 0x2800000 |
71 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 72 | |
4d8d5467 | 73 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 DG |
74 | |
75 | #define TIMEBASE_FREQ 512000000ULL | |
76 | ||
41019fec | 77 | #define MAX_CPUS 256 |
4d8d5467 | 78 | #define XICS_IRQS 1024 |
9fdf0c29 | 79 | |
0c103f8e DG |
80 | #define PHANDLE_XICP 0x00001111 |
81 | ||
7f763a5d DG |
82 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
83 | ||
9fdf0c29 DG |
84 | sPAPREnvironment *spapr; |
85 | ||
ff9d2afa | 86 | int spapr_allocate_irq(int hint, bool lsi) |
e6c866d4 | 87 | { |
a307d594 | 88 | int irq; |
e6c866d4 DG |
89 | |
90 | if (hint) { | |
91 | irq = hint; | |
f1c2dc7c AK |
92 | if (hint >= spapr->next_irq) { |
93 | spapr->next_irq = hint + 1; | |
94 | } | |
e6c866d4 DG |
95 | /* FIXME: we should probably check for collisions somehow */ |
96 | } else { | |
97 | irq = spapr->next_irq++; | |
98 | } | |
99 | ||
a307d594 AK |
100 | /* Configure irq type */ |
101 | if (!xics_get_qirq(spapr->icp, irq)) { | |
102 | return 0; | |
e6c866d4 DG |
103 | } |
104 | ||
ff9d2afa | 105 | xics_set_irq_type(spapr->icp, irq, lsi); |
e6c866d4 | 106 | |
a307d594 | 107 | return irq; |
e6c866d4 DG |
108 | } |
109 | ||
f1c2dc7c AK |
110 | /* |
111 | * Allocate block of consequtive IRQs, returns a number of the first. | |
112 | * If msi==true, aligns the first IRQ number to num. | |
113 | */ | |
114 | int spapr_allocate_irq_block(int num, bool lsi, bool msi) | |
f4b9523b AK |
115 | { |
116 | int first = -1; | |
f1c2dc7c AK |
117 | int i, hint = 0; |
118 | ||
119 | /* | |
120 | * MSIMesage::data is used for storing VIRQ so | |
121 | * it has to be aligned to num to support multiple | |
122 | * MSI vectors. MSI-X is not affected by this. | |
123 | * The hint is used for the first IRQ, the rest should | |
73f395fa | 124 | * be allocated continuously. |
f1c2dc7c AK |
125 | */ |
126 | if (msi) { | |
127 | assert((num == 1) || (num == 2) || (num == 4) || | |
128 | (num == 8) || (num == 16) || (num == 32)); | |
129 | hint = (spapr->next_irq + num - 1) & ~(num - 1); | |
130 | } | |
f4b9523b AK |
131 | |
132 | for (i = 0; i < num; ++i) { | |
133 | int irq; | |
134 | ||
f1c2dc7c | 135 | irq = spapr_allocate_irq(hint, lsi); |
f4b9523b AK |
136 | if (!irq) { |
137 | return -1; | |
138 | } | |
139 | ||
140 | if (0 == i) { | |
141 | first = irq; | |
f1c2dc7c | 142 | hint = 0; |
f4b9523b AK |
143 | } |
144 | ||
145 | /* If the above doesn't create a consecutive block then that's | |
146 | * an internal bug */ | |
147 | assert(irq == (first + i)); | |
148 | } | |
149 | ||
150 | return first; | |
151 | } | |
152 | ||
c04d6cfa AL |
153 | static XICSState *try_create_xics(const char *type, int nr_servers, |
154 | int nr_irqs) | |
155 | { | |
156 | DeviceState *dev; | |
157 | ||
158 | dev = qdev_create(NULL, type); | |
159 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
160 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
161 | if (qdev_init(dev) < 0) { | |
162 | return NULL; | |
163 | } | |
164 | ||
5a3d7b23 | 165 | return XICS_COMMON(dev); |
c04d6cfa AL |
166 | } |
167 | ||
168 | static XICSState *xics_system_init(int nr_servers, int nr_irqs) | |
169 | { | |
170 | XICSState *icp = NULL; | |
171 | ||
11ad93f6 DG |
172 | if (kvm_enabled()) { |
173 | QemuOpts *machine_opts = qemu_get_machine_opts(); | |
174 | bool irqchip_allowed = qemu_opt_get_bool(machine_opts, | |
175 | "kernel_irqchip", true); | |
176 | bool irqchip_required = qemu_opt_get_bool(machine_opts, | |
177 | "kernel_irqchip", false); | |
178 | if (irqchip_allowed) { | |
179 | icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); | |
180 | } | |
181 | ||
182 | if (irqchip_required && !icp) { | |
183 | perror("Failed to create in-kernel XICS\n"); | |
184 | abort(); | |
185 | } | |
186 | } | |
187 | ||
188 | if (!icp) { | |
189 | icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); | |
190 | } | |
191 | ||
c04d6cfa AL |
192 | if (!icp) { |
193 | perror("Failed to create XICS\n"); | |
194 | abort(); | |
195 | } | |
196 | ||
197 | return icp; | |
198 | } | |
199 | ||
7f763a5d | 200 | static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) |
6e806cc3 BR |
201 | { |
202 | int ret = 0, offset; | |
1b1ed8dc | 203 | CPUState *cpu; |
6e806cc3 BR |
204 | char cpu_model[32]; |
205 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 206 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 207 | |
bdc44640 | 208 | CPU_FOREACH(cpu) { |
3bbf37f2 | 209 | DeviceClass *dc = DEVICE_GET_CLASS(cpu); |
0f20ba62 | 210 | int index = ppc_get_vcpu_dt_id(POWERPC_CPU(cpu)); |
6e806cc3 BR |
211 | uint32_t associativity[] = {cpu_to_be32(0x5), |
212 | cpu_to_be32(0x0), | |
213 | cpu_to_be32(0x0), | |
214 | cpu_to_be32(0x0), | |
1b1ed8dc | 215 | cpu_to_be32(cpu->numa_node), |
0f20ba62 | 216 | cpu_to_be32(index)}; |
6e806cc3 | 217 | |
0f20ba62 | 218 | if ((index % smt) != 0) { |
6e806cc3 BR |
219 | continue; |
220 | } | |
221 | ||
3bbf37f2 | 222 | snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name, |
0f20ba62 | 223 | index); |
6e806cc3 BR |
224 | |
225 | offset = fdt_path_offset(fdt, cpu_model); | |
226 | if (offset < 0) { | |
227 | return offset; | |
228 | } | |
229 | ||
7f763a5d DG |
230 | if (nb_numa_nodes > 1) { |
231 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
232 | sizeof(associativity)); | |
233 | if (ret < 0) { | |
234 | return ret; | |
235 | } | |
236 | } | |
237 | ||
238 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", | |
239 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
240 | if (ret < 0) { |
241 | return ret; | |
242 | } | |
243 | } | |
244 | return ret; | |
245 | } | |
246 | ||
5af9873d BH |
247 | |
248 | static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, | |
249 | size_t maxsize) | |
250 | { | |
251 | size_t maxcells = maxsize / sizeof(uint32_t); | |
252 | int i, j, count; | |
253 | uint32_t *p = prop; | |
254 | ||
255 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
256 | struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
257 | ||
258 | if (!sps->page_shift) { | |
259 | break; | |
260 | } | |
261 | for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { | |
262 | if (sps->enc[count].page_shift == 0) { | |
263 | break; | |
264 | } | |
265 | } | |
266 | if ((p - prop) >= (maxcells - 3 - count * 2)) { | |
267 | break; | |
268 | } | |
269 | *(p++) = cpu_to_be32(sps->page_shift); | |
270 | *(p++) = cpu_to_be32(sps->slb_enc); | |
271 | *(p++) = cpu_to_be32(count); | |
272 | for (j = 0; j < count; j++) { | |
273 | *(p++) = cpu_to_be32(sps->enc[j].page_shift); | |
274 | *(p++) = cpu_to_be32(sps->enc[j].pte_enc); | |
275 | } | |
276 | } | |
277 | ||
278 | return (p - prop) * sizeof(uint32_t); | |
279 | } | |
280 | ||
7f763a5d DG |
281 | #define _FDT(exp) \ |
282 | do { \ | |
283 | int ret = (exp); \ | |
284 | if (ret < 0) { \ | |
285 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
286 | #exp, fdt_strerror(ret)); \ | |
287 | exit(1); \ | |
288 | } \ | |
289 | } while (0) | |
290 | ||
291 | ||
3bbf37f2 | 292 | static void *spapr_create_fdt_skel(hwaddr initrd_base, |
a8170e5e AK |
293 | hwaddr initrd_size, |
294 | hwaddr kernel_size, | |
16457e7f | 295 | bool little_endian, |
a3467baa | 296 | const char *boot_device, |
74d042e5 DG |
297 | const char *kernel_cmdline, |
298 | uint32_t epow_irq) | |
9fdf0c29 DG |
299 | { |
300 | void *fdt; | |
182735ef | 301 | CPUState *cs; |
9fdf0c29 DG |
302 | uint32_t start_prop = cpu_to_be32(initrd_base); |
303 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
ee86dfee | 304 | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
42561bf2 | 305 | "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk\0hcall-set-mode"; |
c73e3771 | 306 | char qemu_hypertas_prop[] = "hcall-memop1"; |
7f763a5d | 307 | uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
b5cec4c5 | 308 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; |
7f763a5d | 309 | int i, smt = kvmppc_smt_threads(); |
6e806cc3 | 310 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
9fdf0c29 | 311 | |
7267c094 | 312 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
313 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
314 | ||
4d8d5467 BH |
315 | if (kernel_size) { |
316 | _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); | |
317 | } | |
318 | if (initrd_size) { | |
319 | _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); | |
320 | } | |
9fdf0c29 DG |
321 | _FDT((fdt_finish_reservemap(fdt))); |
322 | ||
323 | /* Root node */ | |
324 | _FDT((fdt_begin_node(fdt, ""))); | |
325 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 326 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 327 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 DG |
328 | |
329 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
330 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
331 | ||
332 | /* /chosen */ | |
333 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
334 | ||
6e806cc3 BR |
335 | /* Set Form1_affinity */ |
336 | _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); | |
337 | ||
9fdf0c29 DG |
338 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); |
339 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
340 | &start_prop, sizeof(start_prop)))); | |
341 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
342 | &end_prop, sizeof(end_prop)))); | |
4d8d5467 BH |
343 | if (kernel_size) { |
344 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
345 | cpu_to_be64(kernel_size) }; | |
9fdf0c29 | 346 | |
4d8d5467 | 347 | _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
16457e7f BH |
348 | if (little_endian) { |
349 | _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); | |
350 | } | |
4d8d5467 | 351 | } |
2c9ee029 AS |
352 | if (boot_device) { |
353 | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); | |
354 | } | |
f28359d8 LZ |
355 | _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); |
356 | _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); | |
357 | _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); | |
3384f95c | 358 | |
9fdf0c29 DG |
359 | _FDT((fdt_end_node(fdt))); |
360 | ||
9fdf0c29 DG |
361 | /* cpus */ |
362 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
363 | ||
364 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
365 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
366 | ||
bdc44640 | 367 | CPU_FOREACH(cs) { |
182735ef AF |
368 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
369 | CPUPPCState *env = &cpu->env; | |
3bbf37f2 | 370 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
182735ef | 371 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); |
0f20ba62 | 372 | int index = ppc_get_vcpu_dt_id(cpu); |
e97c3636 DG |
373 | uint32_t servers_prop[smp_threads]; |
374 | uint32_t gservers_prop[smp_threads * 2]; | |
9fdf0c29 DG |
375 | char *nodename; |
376 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
377 | 0xffffffff, 0xffffffff}; | |
0a8b2938 AG |
378 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
379 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; | |
5af9873d BH |
380 | uint32_t page_sizes_prop[64]; |
381 | size_t page_sizes_prop_size; | |
9fdf0c29 | 382 | |
e97c3636 DG |
383 | if ((index % smt) != 0) { |
384 | continue; | |
385 | } | |
386 | ||
3bbf37f2 | 387 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); |
9fdf0c29 DG |
388 | |
389 | _FDT((fdt_begin_node(fdt, nodename))); | |
390 | ||
4ecf8aa5 | 391 | g_free(nodename); |
9fdf0c29 | 392 | |
c7a5c0c9 | 393 | _FDT((fdt_property_cell(fdt, "reg", index))); |
9fdf0c29 DG |
394 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
395 | ||
396 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
0cbad81f | 397 | _FDT((fdt_property_cell(fdt, "d-cache-block-size", |
9fdf0c29 | 398 | env->dcache_line_size))); |
0cbad81f DG |
399 | _FDT((fdt_property_cell(fdt, "d-cache-line-size", |
400 | env->dcache_line_size))); | |
401 | _FDT((fdt_property_cell(fdt, "i-cache-block-size", | |
402 | env->icache_line_size))); | |
403 | _FDT((fdt_property_cell(fdt, "i-cache-line-size", | |
9fdf0c29 | 404 | env->icache_line_size))); |
0cbad81f DG |
405 | |
406 | if (pcc->l1_dcache_size) { | |
407 | _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); | |
408 | } else { | |
409 | fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); | |
410 | } | |
411 | if (pcc->l1_icache_size) { | |
412 | _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); | |
413 | } else { | |
414 | fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); | |
415 | } | |
416 | ||
0a8b2938 AG |
417 | _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); |
418 | _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); | |
9fdf0c29 DG |
419 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); |
420 | _FDT((fdt_property_string(fdt, "status", "okay"))); | |
421 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
e97c3636 DG |
422 | |
423 | /* Build interrupt servers and gservers properties */ | |
424 | for (i = 0; i < smp_threads; i++) { | |
425 | servers_prop[i] = cpu_to_be32(index + i); | |
426 | /* Hack, direct the group queues back to cpu 0 */ | |
427 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
428 | gservers_prop[i*2 + 1] = 0; | |
429 | } | |
430 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", | |
431 | servers_prop, sizeof(servers_prop)))); | |
b5cec4c5 | 432 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", |
e97c3636 | 433 | gservers_prop, sizeof(gservers_prop)))); |
9fdf0c29 | 434 | |
dcb861cb AK |
435 | if (env->spr_cb[SPR_PURR].oea_read) { |
436 | _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); | |
437 | } | |
438 | ||
c7a5c0c9 | 439 | if (env->mmu_model & POWERPC_MMU_1TSEG) { |
9fdf0c29 DG |
440 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", |
441 | segs, sizeof(segs)))); | |
442 | } | |
443 | ||
6659394f DG |
444 | /* Advertise VMX/VSX (vector extensions) if available |
445 | * 0 / no property == no vector extensions | |
446 | * 1 == VMX / Altivec available | |
447 | * 2 == VSX available */ | |
a7342588 DG |
448 | if (env->insns_flags & PPC_ALTIVEC) { |
449 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
450 | ||
6659394f DG |
451 | _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); |
452 | } | |
453 | ||
454 | /* Advertise DFP (Decimal Floating Point) if available | |
455 | * 0 / no property == no DFP | |
456 | * 1 == DFP available */ | |
a7342588 DG |
457 | if (env->insns_flags2 & PPC2_DFP) { |
458 | _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); | |
6659394f DG |
459 | } |
460 | ||
5af9873d BH |
461 | page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, |
462 | sizeof(page_sizes_prop)); | |
463 | if (page_sizes_prop_size) { | |
464 | _FDT((fdt_property(fdt, "ibm,segment-page-sizes", | |
465 | page_sizes_prop, page_sizes_prop_size))); | |
466 | } | |
467 | ||
9fdf0c29 DG |
468 | _FDT((fdt_end_node(fdt))); |
469 | } | |
470 | ||
9fdf0c29 DG |
471 | _FDT((fdt_end_node(fdt))); |
472 | ||
f43e3525 DG |
473 | /* RTAS */ |
474 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
475 | ||
476 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, | |
477 | sizeof(hypertas_prop)))); | |
c73e3771 BH |
478 | _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, |
479 | sizeof(qemu_hypertas_prop)))); | |
f43e3525 | 480 | |
6e806cc3 BR |
481 | _FDT((fdt_property(fdt, "ibm,associativity-reference-points", |
482 | refpoints, sizeof(refpoints)))); | |
483 | ||
74d042e5 DG |
484 | _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); |
485 | ||
f43e3525 DG |
486 | _FDT((fdt_end_node(fdt))); |
487 | ||
b5cec4c5 | 488 | /* interrupt controller */ |
9dfef5aa | 489 | _FDT((fdt_begin_node(fdt, "interrupt-controller"))); |
b5cec4c5 DG |
490 | |
491 | _FDT((fdt_property_string(fdt, "device_type", | |
492 | "PowerPC-External-Interrupt-Presentation"))); | |
493 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
b5cec4c5 DG |
494 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
495 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
496 | interrupt_server_ranges_prop, | |
497 | sizeof(interrupt_server_ranges_prop)))); | |
0c103f8e DG |
498 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
499 | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); | |
500 | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); | |
b5cec4c5 DG |
501 | |
502 | _FDT((fdt_end_node(fdt))); | |
503 | ||
4040ab72 DG |
504 | /* vdevice */ |
505 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
506 | ||
507 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
508 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
509 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
510 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
511 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
512 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
513 | |
514 | _FDT((fdt_end_node(fdt))); | |
515 | ||
74d042e5 DG |
516 | /* event-sources */ |
517 | spapr_events_fdt_skel(fdt, epow_irq); | |
518 | ||
9fdf0c29 DG |
519 | _FDT((fdt_end_node(fdt))); /* close root node */ |
520 | _FDT((fdt_finish(fdt))); | |
521 | ||
a3467baa DG |
522 | return fdt; |
523 | } | |
524 | ||
7f763a5d DG |
525 | static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) |
526 | { | |
527 | uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), | |
528 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
529 | cpu_to_be32(0x0)}; | |
530 | char mem_name[32]; | |
5fe269b1 | 531 | hwaddr node0_size, mem_start, node_size; |
7f763a5d DG |
532 | uint64_t mem_reg_property[2]; |
533 | int i, off; | |
534 | ||
535 | /* memory node(s) */ | |
5fe269b1 PM |
536 | if (nb_numa_nodes > 1 && node_mem[0] < ram_size) { |
537 | node0_size = node_mem[0]; | |
538 | } else { | |
539 | node0_size = ram_size; | |
540 | } | |
7f763a5d DG |
541 | |
542 | /* RMA */ | |
543 | mem_reg_property[0] = 0; | |
544 | mem_reg_property[1] = cpu_to_be64(spapr->rma_size); | |
545 | off = fdt_add_subnode(fdt, 0, "memory@0"); | |
546 | _FDT(off); | |
547 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
548 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
549 | sizeof(mem_reg_property)))); | |
550 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
551 | sizeof(associativity)))); | |
552 | ||
553 | /* RAM: Node 0 */ | |
554 | if (node0_size > spapr->rma_size) { | |
555 | mem_reg_property[0] = cpu_to_be64(spapr->rma_size); | |
556 | mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); | |
557 | ||
558 | sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); | |
559 | off = fdt_add_subnode(fdt, 0, mem_name); | |
560 | _FDT(off); | |
561 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
562 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
563 | sizeof(mem_reg_property)))); | |
564 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
565 | sizeof(associativity)))); | |
566 | } | |
567 | ||
568 | /* RAM: Node 1 and beyond */ | |
569 | mem_start = node0_size; | |
570 | for (i = 1; i < nb_numa_nodes; i++) { | |
571 | mem_reg_property[0] = cpu_to_be64(mem_start); | |
5fe269b1 PM |
572 | if (mem_start >= ram_size) { |
573 | node_size = 0; | |
574 | } else { | |
575 | node_size = node_mem[i]; | |
576 | if (node_size > ram_size - mem_start) { | |
577 | node_size = ram_size - mem_start; | |
578 | } | |
579 | } | |
580 | mem_reg_property[1] = cpu_to_be64(node_size); | |
7f763a5d DG |
581 | associativity[3] = associativity[4] = cpu_to_be32(i); |
582 | sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); | |
583 | off = fdt_add_subnode(fdt, 0, mem_name); | |
584 | _FDT(off); | |
585 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
586 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
587 | sizeof(mem_reg_property)))); | |
588 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
589 | sizeof(associativity)))); | |
5fe269b1 | 590 | mem_start += node_size; |
7f763a5d DG |
591 | } |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
a3467baa | 596 | static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
a8170e5e AK |
597 | hwaddr fdt_addr, |
598 | hwaddr rtas_addr, | |
599 | hwaddr rtas_size) | |
a3467baa DG |
600 | { |
601 | int ret; | |
602 | void *fdt; | |
3384f95c | 603 | sPAPRPHBState *phb; |
a3467baa | 604 | |
7267c094 | 605 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
606 | |
607 | /* open out the base tree into a temp buffer for the final tweaks */ | |
608 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 609 | |
7f763a5d DG |
610 | ret = spapr_populate_memory(spapr, fdt); |
611 | if (ret < 0) { | |
612 | fprintf(stderr, "couldn't setup memory nodes in fdt\n"); | |
613 | exit(1); | |
614 | } | |
615 | ||
4040ab72 DG |
616 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
617 | if (ret < 0) { | |
618 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
619 | exit(1); | |
620 | } | |
621 | ||
3384f95c | 622 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 623 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
3384f95c DG |
624 | } |
625 | ||
626 | if (ret < 0) { | |
627 | fprintf(stderr, "couldn't setup PCI devices in fdt\n"); | |
628 | exit(1); | |
629 | } | |
630 | ||
39ac8455 DG |
631 | /* RTAS */ |
632 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
633 | if (ret < 0) { | |
634 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
635 | } | |
636 | ||
6e806cc3 | 637 | /* Advertise NUMA via ibm,associativity */ |
7f763a5d DG |
638 | ret = spapr_fixup_cpu_dt(fdt, spapr); |
639 | if (ret < 0) { | |
640 | fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); | |
6e806cc3 BR |
641 | } |
642 | ||
3fc5acde | 643 | if (!spapr->has_graphics) { |
f28359d8 LZ |
644 | spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
645 | } | |
68f3a94c | 646 | |
4040ab72 DG |
647 | _FDT((fdt_pack(fdt))); |
648 | ||
4d8d5467 BH |
649 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
650 | hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", | |
651 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
652 | exit(1); | |
653 | } | |
654 | ||
a3467baa | 655 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 656 | |
7267c094 | 657 | g_free(fdt); |
9fdf0c29 DG |
658 | } |
659 | ||
660 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
661 | { | |
662 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
663 | } | |
664 | ||
1b14670a | 665 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 666 | { |
1b14670a AF |
667 | CPUPPCState *env = &cpu->env; |
668 | ||
efcb9383 DG |
669 | if (msr_pr) { |
670 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
671 | env->gpr[3] = H_PRIVILEGE; | |
672 | } else { | |
aa100fa4 | 673 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 674 | } |
9fdf0c29 DG |
675 | } |
676 | ||
7f763a5d DG |
677 | static void spapr_reset_htab(sPAPREnvironment *spapr) |
678 | { | |
679 | long shift; | |
680 | ||
681 | /* allocate hash page table. For now we always make this 16mb, | |
682 | * later we should probably make it scale to the size of guest | |
683 | * RAM */ | |
684 | ||
685 | shift = kvmppc_reset_htab(spapr->htab_shift); | |
686 | ||
687 | if (shift > 0) { | |
688 | /* Kernel handles htab, we don't need to allocate one */ | |
689 | spapr->htab_shift = shift; | |
7c43bca0 | 690 | kvmppc_kern_htab = true; |
7f763a5d DG |
691 | } else { |
692 | if (!spapr->htab) { | |
693 | /* Allocate an htab if we don't yet have one */ | |
694 | spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); | |
695 | } | |
696 | ||
697 | /* And clear it */ | |
698 | memset(spapr->htab, 0, HTAB_SIZE(spapr)); | |
699 | } | |
700 | ||
701 | /* Update the RMA size if necessary */ | |
702 | if (spapr->vrma_adjust) { | |
c4177479 AK |
703 | hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; |
704 | spapr->rma_size = kvmppc_rma_size(node0_size, spapr->htab_shift); | |
7f763a5d | 705 | } |
9fdf0c29 DG |
706 | } |
707 | ||
c8787ad4 | 708 | static void ppc_spapr_reset(void) |
a3467baa | 709 | { |
182735ef | 710 | PowerPCCPU *first_ppc_cpu; |
259186a7 | 711 | |
7f763a5d DG |
712 | /* Reset the hash table & recalc the RMA */ |
713 | spapr_reset_htab(spapr); | |
a3467baa | 714 | |
c8787ad4 | 715 | qemu_devices_reset(); |
a3467baa DG |
716 | |
717 | /* Load the fdt */ | |
718 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
719 | spapr->rtas_size); | |
720 | ||
721 | /* Set up the entry state */ | |
182735ef AF |
722 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
723 | first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; | |
724 | first_ppc_cpu->env.gpr[5] = 0; | |
725 | first_cpu->halted = 0; | |
726 | first_ppc_cpu->env.nip = spapr->entry_point; | |
a3467baa DG |
727 | |
728 | } | |
729 | ||
1bba0dc9 AF |
730 | static void spapr_cpu_reset(void *opaque) |
731 | { | |
5b2038e0 | 732 | PowerPCCPU *cpu = opaque; |
259186a7 | 733 | CPUState *cs = CPU(cpu); |
048706d9 | 734 | CPUPPCState *env = &cpu->env; |
1bba0dc9 | 735 | |
259186a7 | 736 | cpu_reset(cs); |
048706d9 DG |
737 | |
738 | /* All CPUs start halted. CPU0 is unhalted from the machine level | |
739 | * reset code and the rest are explicitly started up by the guest | |
740 | * using an RTAS call */ | |
259186a7 | 741 | cs->halted = 1; |
048706d9 DG |
742 | |
743 | env->spr[SPR_HIOR] = 0; | |
7f763a5d | 744 | |
4be21d56 | 745 | env->external_htab = (uint8_t *)spapr->htab; |
5736245c AK |
746 | if (kvm_enabled() && !env->external_htab) { |
747 | /* | |
748 | * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* | |
749 | * functions do the right thing. | |
750 | */ | |
751 | env->external_htab = (void *)1; | |
752 | } | |
7f763a5d | 753 | env->htab_base = -1; |
f3c75d42 AK |
754 | /* |
755 | * htab_mask is the mask used to normalize hash value to PTEG index. | |
756 | * htab_shift is log2 of hash table size. | |
757 | * We have 8 hpte per group, and each hpte is 16 bytes. | |
758 | * ie have 128 bytes per hpte entry. | |
759 | */ | |
760 | env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; | |
ec4936e1 | 761 | env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | |
7f763a5d | 762 | (spapr->htab_shift - 18); |
1bba0dc9 AF |
763 | } |
764 | ||
639e8102 DG |
765 | static void spapr_create_nvram(sPAPREnvironment *spapr) |
766 | { | |
2ff3de68 | 767 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 768 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 769 | |
3978b863 PB |
770 | if (dinfo) { |
771 | qdev_prop_set_drive_nofail(dev, "drive", dinfo->bdrv); | |
639e8102 DG |
772 | } |
773 | ||
774 | qdev_init_nofail(dev); | |
775 | ||
776 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
777 | } | |
778 | ||
8c57b867 | 779 | /* Returns whether we want to use VGA or not */ |
f28359d8 LZ |
780 | static int spapr_vga_init(PCIBus *pci_bus) |
781 | { | |
8c57b867 | 782 | switch (vga_interface_type) { |
8c57b867 | 783 | case VGA_NONE: |
1ddcae82 AJ |
784 | case VGA_STD: |
785 | return pci_vga_init(pci_bus) != NULL; | |
8c57b867 | 786 | default: |
f28359d8 LZ |
787 | fprintf(stderr, "This vga model is not supported," |
788 | "currently it only supports -vga std\n"); | |
8c57b867 AG |
789 | exit(0); |
790 | break; | |
f28359d8 | 791 | } |
f28359d8 LZ |
792 | } |
793 | ||
4be21d56 DG |
794 | static const VMStateDescription vmstate_spapr = { |
795 | .name = "spapr", | |
796 | .version_id = 1, | |
797 | .minimum_version_id = 1, | |
798 | .minimum_version_id_old = 1, | |
799 | .fields = (VMStateField []) { | |
800 | VMSTATE_UINT32(next_irq, sPAPREnvironment), | |
801 | ||
802 | /* RTC offset */ | |
803 | VMSTATE_UINT64(rtc_offset, sPAPREnvironment), | |
804 | ||
805 | VMSTATE_END_OF_LIST() | |
806 | }, | |
807 | }; | |
808 | ||
809 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) | |
810 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
811 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
812 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
813 | ||
814 | static int htab_save_setup(QEMUFile *f, void *opaque) | |
815 | { | |
816 | sPAPREnvironment *spapr = opaque; | |
817 | ||
4be21d56 DG |
818 | /* "Iteration" header */ |
819 | qemu_put_be32(f, spapr->htab_shift); | |
820 | ||
e68cb8b4 AK |
821 | if (spapr->htab) { |
822 | spapr->htab_save_index = 0; | |
823 | spapr->htab_first_pass = true; | |
824 | } else { | |
825 | assert(kvm_enabled()); | |
826 | ||
827 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
828 | if (spapr->htab_fd < 0) { | |
829 | fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", | |
830 | strerror(errno)); | |
831 | return -1; | |
832 | } | |
833 | } | |
834 | ||
835 | ||
4be21d56 DG |
836 | return 0; |
837 | } | |
838 | ||
4be21d56 DG |
839 | static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, |
840 | int64_t max_ns) | |
841 | { | |
842 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
843 | int index = spapr->htab_save_index; | |
bc72ad67 | 844 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
845 | |
846 | assert(spapr->htab_first_pass); | |
847 | ||
848 | do { | |
849 | int chunkstart; | |
850 | ||
851 | /* Consume invalid HPTEs */ | |
852 | while ((index < htabslots) | |
853 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
854 | index++; | |
855 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
856 | } | |
857 | ||
858 | /* Consume valid HPTEs */ | |
859 | chunkstart = index; | |
860 | while ((index < htabslots) | |
861 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
862 | index++; | |
863 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
864 | } | |
865 | ||
866 | if (index > chunkstart) { | |
867 | int n_valid = index - chunkstart; | |
868 | ||
869 | qemu_put_be32(f, chunkstart); | |
870 | qemu_put_be16(f, n_valid); | |
871 | qemu_put_be16(f, 0); | |
872 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
873 | HASH_PTE_SIZE_64 * n_valid); | |
874 | ||
bc72ad67 | 875 | if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
876 | break; |
877 | } | |
878 | } | |
879 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
880 | ||
881 | if (index >= htabslots) { | |
882 | assert(index == htabslots); | |
883 | index = 0; | |
884 | spapr->htab_first_pass = false; | |
885 | } | |
886 | spapr->htab_save_index = index; | |
887 | } | |
888 | ||
e68cb8b4 AK |
889 | static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, |
890 | int64_t max_ns) | |
4be21d56 DG |
891 | { |
892 | bool final = max_ns < 0; | |
893 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
894 | int examined = 0, sent = 0; | |
895 | int index = spapr->htab_save_index; | |
bc72ad67 | 896 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
897 | |
898 | assert(!spapr->htab_first_pass); | |
899 | ||
900 | do { | |
901 | int chunkstart, invalidstart; | |
902 | ||
903 | /* Consume non-dirty HPTEs */ | |
904 | while ((index < htabslots) | |
905 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
906 | index++; | |
907 | examined++; | |
908 | } | |
909 | ||
910 | chunkstart = index; | |
911 | /* Consume valid dirty HPTEs */ | |
912 | while ((index < htabslots) | |
913 | && HPTE_DIRTY(HPTE(spapr->htab, index)) | |
914 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
915 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
916 | index++; | |
917 | examined++; | |
918 | } | |
919 | ||
920 | invalidstart = index; | |
921 | /* Consume invalid dirty HPTEs */ | |
922 | while ((index < htabslots) | |
923 | && HPTE_DIRTY(HPTE(spapr->htab, index)) | |
924 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
925 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
926 | index++; | |
927 | examined++; | |
928 | } | |
929 | ||
930 | if (index > chunkstart) { | |
931 | int n_valid = invalidstart - chunkstart; | |
932 | int n_invalid = index - invalidstart; | |
933 | ||
934 | qemu_put_be32(f, chunkstart); | |
935 | qemu_put_be16(f, n_valid); | |
936 | qemu_put_be16(f, n_invalid); | |
937 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
938 | HASH_PTE_SIZE_64 * n_valid); | |
939 | sent += index - chunkstart; | |
940 | ||
bc72ad67 | 941 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
942 | break; |
943 | } | |
944 | } | |
945 | ||
946 | if (examined >= htabslots) { | |
947 | break; | |
948 | } | |
949 | ||
950 | if (index >= htabslots) { | |
951 | assert(index == htabslots); | |
952 | index = 0; | |
953 | } | |
954 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
955 | ||
956 | if (index >= htabslots) { | |
957 | assert(index == htabslots); | |
958 | index = 0; | |
959 | } | |
960 | ||
961 | spapr->htab_save_index = index; | |
962 | ||
e68cb8b4 | 963 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
964 | } |
965 | ||
e68cb8b4 AK |
966 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
967 | #define MAX_KVM_BUF_SIZE 2048 | |
968 | ||
4be21d56 DG |
969 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
970 | { | |
971 | sPAPREnvironment *spapr = opaque; | |
e68cb8b4 | 972 | int rc = 0; |
4be21d56 DG |
973 | |
974 | /* Iteration header */ | |
975 | qemu_put_be32(f, 0); | |
976 | ||
e68cb8b4 AK |
977 | if (!spapr->htab) { |
978 | assert(kvm_enabled()); | |
979 | ||
980 | rc = kvmppc_save_htab(f, spapr->htab_fd, | |
981 | MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); | |
982 | if (rc < 0) { | |
983 | return rc; | |
984 | } | |
985 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
986 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
987 | } else { | |
e68cb8b4 | 988 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
989 | } |
990 | ||
991 | /* End marker */ | |
992 | qemu_put_be32(f, 0); | |
993 | qemu_put_be16(f, 0); | |
994 | qemu_put_be16(f, 0); | |
995 | ||
e68cb8b4 | 996 | return rc; |
4be21d56 DG |
997 | } |
998 | ||
999 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1000 | { | |
1001 | sPAPREnvironment *spapr = opaque; | |
1002 | ||
1003 | /* Iteration header */ | |
1004 | qemu_put_be32(f, 0); | |
1005 | ||
e68cb8b4 AK |
1006 | if (!spapr->htab) { |
1007 | int rc; | |
1008 | ||
1009 | assert(kvm_enabled()); | |
1010 | ||
1011 | rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); | |
1012 | if (rc < 0) { | |
1013 | return rc; | |
1014 | } | |
1015 | close(spapr->htab_fd); | |
1016 | spapr->htab_fd = -1; | |
1017 | } else { | |
1018 | htab_save_later_pass(f, spapr, -1); | |
1019 | } | |
4be21d56 DG |
1020 | |
1021 | /* End marker */ | |
1022 | qemu_put_be32(f, 0); | |
1023 | qemu_put_be16(f, 0); | |
1024 | qemu_put_be16(f, 0); | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1030 | { | |
1031 | sPAPREnvironment *spapr = opaque; | |
1032 | uint32_t section_hdr; | |
e68cb8b4 | 1033 | int fd = -1; |
4be21d56 DG |
1034 | |
1035 | if (version_id < 1 || version_id > 1) { | |
1036 | fprintf(stderr, "htab_load() bad version\n"); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | section_hdr = qemu_get_be32(f); | |
1041 | ||
1042 | if (section_hdr) { | |
1043 | /* First section, just the hash shift */ | |
1044 | if (spapr->htab_shift != section_hdr) { | |
1045 | return -EINVAL; | |
1046 | } | |
1047 | return 0; | |
1048 | } | |
1049 | ||
e68cb8b4 AK |
1050 | if (!spapr->htab) { |
1051 | assert(kvm_enabled()); | |
1052 | ||
1053 | fd = kvmppc_get_htab_fd(true); | |
1054 | if (fd < 0) { | |
1055 | fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", | |
1056 | strerror(errno)); | |
1057 | } | |
1058 | } | |
1059 | ||
4be21d56 DG |
1060 | while (true) { |
1061 | uint32_t index; | |
1062 | uint16_t n_valid, n_invalid; | |
1063 | ||
1064 | index = qemu_get_be32(f); | |
1065 | n_valid = qemu_get_be16(f); | |
1066 | n_invalid = qemu_get_be16(f); | |
1067 | ||
1068 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1069 | /* End of Stream */ | |
1070 | break; | |
1071 | } | |
1072 | ||
e68cb8b4 | 1073 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1074 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1075 | /* Bad index in stream */ | |
1076 | fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " | |
e68cb8b4 AK |
1077 | "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, |
1078 | spapr->htab_shift); | |
4be21d56 DG |
1079 | return -EINVAL; |
1080 | } | |
1081 | ||
e68cb8b4 AK |
1082 | if (spapr->htab) { |
1083 | if (n_valid) { | |
1084 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1085 | HASH_PTE_SIZE_64 * n_valid); | |
1086 | } | |
1087 | if (n_invalid) { | |
1088 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1089 | HASH_PTE_SIZE_64 * n_invalid); | |
1090 | } | |
1091 | } else { | |
1092 | int rc; | |
1093 | ||
1094 | assert(fd >= 0); | |
1095 | ||
1096 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1097 | if (rc < 0) { | |
1098 | return rc; | |
1099 | } | |
4be21d56 DG |
1100 | } |
1101 | } | |
1102 | ||
e68cb8b4 AK |
1103 | if (!spapr->htab) { |
1104 | assert(fd >= 0); | |
1105 | close(fd); | |
1106 | } | |
1107 | ||
4be21d56 DG |
1108 | return 0; |
1109 | } | |
1110 | ||
1111 | static SaveVMHandlers savevm_htab_handlers = { | |
1112 | .save_live_setup = htab_save_setup, | |
1113 | .save_live_iterate = htab_save_iterate, | |
1114 | .save_live_complete = htab_save_complete, | |
1115 | .load_state = htab_load, | |
1116 | }; | |
1117 | ||
9fdf0c29 | 1118 | /* pSeries LPAR / sPAPR hardware init */ |
5f072e1f | 1119 | static void ppc_spapr_init(QEMUMachineInitArgs *args) |
9fdf0c29 | 1120 | { |
5f072e1f EH |
1121 | ram_addr_t ram_size = args->ram_size; |
1122 | const char *cpu_model = args->cpu_model; | |
1123 | const char *kernel_filename = args->kernel_filename; | |
1124 | const char *kernel_cmdline = args->kernel_cmdline; | |
1125 | const char *initrd_filename = args->initrd_filename; | |
c1654732 | 1126 | const char *boot_device = args->boot_order; |
05769733 | 1127 | PowerPCCPU *cpu; |
e2684c0b | 1128 | CPUPPCState *env; |
8c9f64df | 1129 | PCIHostState *phb; |
9fdf0c29 | 1130 | int i; |
890c2b77 AK |
1131 | MemoryRegion *sysmem = get_system_memory(); |
1132 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
a8170e5e | 1133 | hwaddr rma_alloc_size; |
c4177479 | 1134 | hwaddr node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; |
4d8d5467 BH |
1135 | uint32_t initrd_base = 0; |
1136 | long kernel_size = 0, initrd_size = 0; | |
1137 | long load_limit, rtas_limit, fw_size; | |
16457e7f | 1138 | bool kernel_le = false; |
39ac8455 | 1139 | char *filename; |
9fdf0c29 | 1140 | |
0ee2c058 AK |
1141 | msi_supported = true; |
1142 | ||
d43b45e2 DG |
1143 | spapr = g_malloc0(sizeof(*spapr)); |
1144 | QLIST_INIT(&spapr->phbs); | |
1145 | ||
9fdf0c29 DG |
1146 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1147 | ||
354ac20a DG |
1148 | /* Allocate RMA if necessary */ |
1149 | rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); | |
1150 | ||
1151 | if (rma_alloc_size == -1) { | |
1152 | hw_error("qemu: Unable to create RMA\n"); | |
1153 | exit(1); | |
1154 | } | |
7f763a5d | 1155 | |
c4177479 | 1156 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1157 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1158 | } else { |
c4177479 | 1159 | spapr->rma_size = node0_size; |
7f763a5d DG |
1160 | |
1161 | /* With KVM, we don't actually know whether KVM supports an | |
1162 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1163 | * (HV KVM using VRMA), so we always assume the latter | |
1164 | * | |
1165 | * In that case, we also limit the initial allocations for RTAS | |
1166 | * etc... to 256M since we have no way to know what the VRMA size | |
1167 | * is going to be as it depends on the size of the hash table | |
1168 | * isn't determined yet. | |
1169 | */ | |
1170 | if (kvm_enabled()) { | |
1171 | spapr->vrma_adjust = 1; | |
1172 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1173 | } | |
354ac20a DG |
1174 | } |
1175 | ||
c4177479 AK |
1176 | if (spapr->rma_size > node0_size) { |
1177 | fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", | |
1178 | spapr->rma_size); | |
1179 | exit(1); | |
1180 | } | |
1181 | ||
4d8d5467 | 1182 | /* We place the device tree and RTAS just below either the top of the RMA, |
354ac20a DG |
1183 | * or just below 2GB, whichever is lowere, so that it can be |
1184 | * processed with 32-bit real mode code if necessary */ | |
7f763a5d | 1185 | rtas_limit = MIN(spapr->rma_size, 0x80000000); |
4d8d5467 BH |
1186 | spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1187 | spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; | |
1188 | load_limit = spapr->fdt_addr - FW_OVERHEAD; | |
9fdf0c29 | 1189 | |
382be75d DG |
1190 | /* We aim for a hash table of size 1/128 the size of RAM. The |
1191 | * normal rule of thumb is 1/64 the size of RAM, but that's much | |
1192 | * more than needed for the Linux guests we support. */ | |
1193 | spapr->htab_shift = 18; /* Minimum architected size */ | |
1194 | while (spapr->htab_shift <= 46) { | |
1195 | if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { | |
1196 | break; | |
1197 | } | |
1198 | spapr->htab_shift++; | |
1199 | } | |
7f763a5d | 1200 | |
7b565160 DG |
1201 | /* Set up Interrupt Controller before we create the VCPUs */ |
1202 | spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, | |
1203 | XICS_IRQS); | |
1204 | spapr->next_irq = XICS_IRQ_BASE; | |
1205 | ||
9fdf0c29 DG |
1206 | /* init CPUs */ |
1207 | if (cpu_model == NULL) { | |
6b7a2cf6 | 1208 | cpu_model = kvm_enabled() ? "host" : "POWER7"; |
9fdf0c29 DG |
1209 | } |
1210 | for (i = 0; i < smp_cpus; i++) { | |
05769733 AF |
1211 | cpu = cpu_ppc_init(cpu_model); |
1212 | if (cpu == NULL) { | |
9fdf0c29 DG |
1213 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
1214 | exit(1); | |
1215 | } | |
05769733 AF |
1216 | env = &cpu->env; |
1217 | ||
9fdf0c29 DG |
1218 | /* Set time-base frequency to 512 MHz */ |
1219 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
9fdf0c29 | 1220 | |
2cf3eb6d FC |
1221 | /* PAPR always has exception vectors in RAM not ROM. To ensure this, |
1222 | * MSR[IP] should never be set. | |
1223 | */ | |
1224 | env->msr_mask &= ~(1 << 6); | |
048706d9 DG |
1225 | |
1226 | /* Tell KVM that we're in PAPR mode */ | |
1227 | if (kvm_enabled()) { | |
1bc22652 | 1228 | kvmppc_set_papr(cpu); |
048706d9 DG |
1229 | } |
1230 | ||
24408a7d AK |
1231 | xics_cpu_setup(spapr->icp, cpu); |
1232 | ||
048706d9 | 1233 | qemu_register_reset(spapr_cpu_reset, cpu); |
9fdf0c29 DG |
1234 | } |
1235 | ||
1236 | /* allocate RAM */ | |
f73a2575 | 1237 | spapr->ram_limit = ram_size; |
354ac20a DG |
1238 | if (spapr->ram_limit > rma_alloc_size) { |
1239 | ram_addr_t nonrma_base = rma_alloc_size; | |
1240 | ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; | |
1241 | ||
2c9b15ca | 1242 | memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); |
c5705a77 | 1243 | vmstate_register_ram_global(ram); |
354ac20a DG |
1244 | memory_region_add_subregion(sysmem, nonrma_base, ram); |
1245 | } | |
9fdf0c29 | 1246 | |
39ac8455 | 1247 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
a3467baa | 1248 | spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
4d8d5467 | 1249 | rtas_limit - spapr->rtas_addr); |
a3467baa | 1250 | if (spapr->rtas_size < 0) { |
39ac8455 DG |
1251 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); |
1252 | exit(1); | |
1253 | } | |
4d8d5467 BH |
1254 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
1255 | hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", | |
1256 | spapr->rtas_size, RTAS_MAX_SIZE); | |
1257 | exit(1); | |
1258 | } | |
7267c094 | 1259 | g_free(filename); |
39ac8455 | 1260 | |
74d042e5 DG |
1261 | /* Set up EPOW events infrastructure */ |
1262 | spapr_events_init(spapr); | |
1263 | ||
b5cec4c5 | 1264 | /* Set up VIO bus */ |
4040ab72 DG |
1265 | spapr->vio_bus = spapr_vio_bus_init(); |
1266 | ||
277f9acf | 1267 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1268 | if (serial_hds[i]) { |
d601fac4 | 1269 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1270 | } |
1271 | } | |
9fdf0c29 | 1272 | |
639e8102 DG |
1273 | /* We always have at least the nvram device on VIO */ |
1274 | spapr_create_nvram(spapr); | |
1275 | ||
3384f95c | 1276 | /* Set up PCI */ |
f1c2dc7c | 1277 | spapr_pci_msi_init(spapr, SPAPR_PCI_MSI_WINDOW); |
fa28f71b AK |
1278 | spapr_pci_rtas_init(); |
1279 | ||
89dfd6e1 | 1280 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1281 | |
277f9acf | 1282 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1283 | NICInfo *nd = &nd_table[i]; |
1284 | ||
1285 | if (!nd->model) { | |
7267c094 | 1286 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1287 | } |
1288 | ||
1289 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1290 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1291 | } else { |
29b358f9 | 1292 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1293 | } |
1294 | } | |
1295 | ||
6e270446 | 1296 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1297 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1298 | } |
1299 | ||
f28359d8 | 1300 | /* Graphics */ |
8c9f64df | 1301 | if (spapr_vga_init(phb->bus)) { |
3fc5acde | 1302 | spapr->has_graphics = true; |
f28359d8 LZ |
1303 | } |
1304 | ||
094b287f | 1305 | if (usb_enabled(spapr->has_graphics)) { |
8c9f64df | 1306 | pci_create_simple(phb->bus, -1, "pci-ohci"); |
35139a59 DG |
1307 | if (spapr->has_graphics) { |
1308 | usbdevice_create("keyboard"); | |
1309 | usbdevice_create("mouse"); | |
1310 | } | |
1311 | } | |
1312 | ||
7f763a5d | 1313 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
4d8d5467 BH |
1314 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " |
1315 | "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); | |
1316 | exit(1); | |
1317 | } | |
1318 | ||
9fdf0c29 DG |
1319 | if (kernel_filename) { |
1320 | uint64_t lowaddr = 0; | |
1321 | ||
9fdf0c29 DG |
1322 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
1323 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
3b66da82 | 1324 | if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { |
16457e7f BH |
1325 | kernel_size = load_elf(kernel_filename, |
1326 | translate_kernel_address, NULL, | |
1327 | NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); | |
1328 | kernel_le = kernel_size > 0; | |
1329 | } | |
9fdf0c29 | 1330 | if (kernel_size < 0) { |
3b66da82 AK |
1331 | fprintf(stderr, "qemu: error loading %s: %s\n", |
1332 | kernel_filename, load_elf_strerror(kernel_size)); | |
9fdf0c29 DG |
1333 | exit(1); |
1334 | } | |
1335 | ||
1336 | /* load initrd */ | |
1337 | if (initrd_filename) { | |
4d8d5467 BH |
1338 | /* Try to locate the initrd in the gap between the kernel |
1339 | * and the firmware. Add a bit of space just in case | |
1340 | */ | |
1341 | initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; | |
9fdf0c29 | 1342 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
4d8d5467 | 1343 | load_limit - initrd_base); |
9fdf0c29 DG |
1344 | if (initrd_size < 0) { |
1345 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
1346 | initrd_filename); | |
1347 | exit(1); | |
1348 | } | |
1349 | } else { | |
1350 | initrd_base = 0; | |
1351 | initrd_size = 0; | |
1352 | } | |
4d8d5467 | 1353 | } |
a3467baa | 1354 | |
8e7ea787 AF |
1355 | if (bios_name == NULL) { |
1356 | bios_name = FW_FILE_NAME; | |
1357 | } | |
1358 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4d8d5467 BH |
1359 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
1360 | if (fw_size < 0) { | |
1361 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
1362 | exit(1); | |
1363 | } | |
1364 | g_free(filename); | |
4d8d5467 BH |
1365 | |
1366 | spapr->entry_point = 0x100; | |
1367 | ||
4be21d56 DG |
1368 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
1369 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
1370 | &savevm_htab_handlers, spapr); | |
1371 | ||
9fdf0c29 | 1372 | /* Prepare the device tree */ |
3bbf37f2 | 1373 | spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, |
16457e7f | 1374 | kernel_size, kernel_le, |
74d042e5 DG |
1375 | boot_device, kernel_cmdline, |
1376 | spapr->epow_irq); | |
a3467baa | 1377 | assert(spapr->fdt_skel != NULL); |
9fdf0c29 DG |
1378 | } |
1379 | ||
135a129a AK |
1380 | static int spapr_kvm_type(const char *vm_type) |
1381 | { | |
1382 | if (!vm_type) { | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | if (!strcmp(vm_type, "HV")) { | |
1387 | return 1; | |
1388 | } | |
1389 | ||
1390 | if (!strcmp(vm_type, "PR")) { | |
1391 | return 2; | |
1392 | } | |
1393 | ||
1394 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
1395 | exit(1); | |
1396 | } | |
1397 | ||
9fdf0c29 DG |
1398 | static QEMUMachine spapr_machine = { |
1399 | .name = "pseries", | |
1400 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
159f8286 | 1401 | .is_default = 1, |
9fdf0c29 | 1402 | .init = ppc_spapr_init, |
c8787ad4 | 1403 | .reset = ppc_spapr_reset, |
2d0d2837 | 1404 | .block_default_type = IF_SCSI, |
9fdf0c29 | 1405 | .max_cpus = MAX_CPUS, |
9fdf0c29 | 1406 | .no_parallel = 1, |
c1654732 | 1407 | .default_boot_order = NULL, |
135a129a | 1408 | .kvm_type = spapr_kvm_type, |
9fdf0c29 DG |
1409 | }; |
1410 | ||
1411 | static void spapr_machine_init(void) | |
1412 | { | |
1413 | qemu_register_machine(&spapr_machine); | |
1414 | } | |
1415 | ||
1416 | machine_init(spapr_machine_init); |