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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
9fdf0c29 | 29 | #include "elf.h" |
1422e32d | 30 | #include "net/net.h" |
9c17d615 PB |
31 | #include "sysemu/blockdev.h" |
32 | #include "sysemu/cpus.h" | |
33 | #include "sysemu/kvm.h" | |
e97c3636 | 34 | #include "kvm_ppc.h" |
4be21d56 | 35 | #include "mmu-hash64.h" |
9fdf0c29 DG |
36 | |
37 | #include "hw/boards.h" | |
0d09e41a | 38 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
39 | #include "hw/loader.h" |
40 | ||
0d09e41a PB |
41 | #include "hw/ppc/spapr.h" |
42 | #include "hw/ppc/spapr_vio.h" | |
43 | #include "hw/pci-host/spapr.h" | |
44 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 45 | #include "hw/pci/msi.h" |
9fdf0c29 | 46 | |
83c9f4ca | 47 | #include "hw/pci/pci.h" |
f61b4bed | 48 | |
022c62cb | 49 | #include "exec/address-spaces.h" |
35139a59 | 50 | #include "hw/usb.h" |
1de7afc9 | 51 | #include "qemu/config-file.h" |
890c2b77 | 52 | |
9fdf0c29 DG |
53 | #include <libfdt.h> |
54 | ||
4d8d5467 BH |
55 | /* SLOF memory layout: |
56 | * | |
57 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
58 | * device-tree, then position SLOF itself 31M below that | |
59 | * | |
60 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
61 | * and more | |
62 | * | |
63 | * We load our kernel at 4M, leaving space for SLOF initial image | |
64 | */ | |
9fdf0c29 | 65 | #define FDT_MAX_SIZE 0x10000 |
39ac8455 | 66 | #define RTAS_MAX_SIZE 0x10000 |
a9f8ad8f DG |
67 | #define FW_MAX_SIZE 0x400000 |
68 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
69 | #define FW_OVERHEAD 0x2800000 |
70 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 71 | |
4d8d5467 | 72 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 DG |
73 | |
74 | #define TIMEBASE_FREQ 512000000ULL | |
75 | ||
41019fec | 76 | #define MAX_CPUS 256 |
4d8d5467 | 77 | #define XICS_IRQS 1024 |
9fdf0c29 | 78 | |
0c103f8e DG |
79 | #define PHANDLE_XICP 0x00001111 |
80 | ||
7f763a5d DG |
81 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
82 | ||
9fdf0c29 DG |
83 | sPAPREnvironment *spapr; |
84 | ||
ff9d2afa | 85 | int spapr_allocate_irq(int hint, bool lsi) |
e6c866d4 | 86 | { |
a307d594 | 87 | int irq; |
e6c866d4 DG |
88 | |
89 | if (hint) { | |
90 | irq = hint; | |
91 | /* FIXME: we should probably check for collisions somehow */ | |
92 | } else { | |
93 | irq = spapr->next_irq++; | |
94 | } | |
95 | ||
a307d594 AK |
96 | /* Configure irq type */ |
97 | if (!xics_get_qirq(spapr->icp, irq)) { | |
98 | return 0; | |
e6c866d4 DG |
99 | } |
100 | ||
ff9d2afa | 101 | xics_set_irq_type(spapr->icp, irq, lsi); |
e6c866d4 | 102 | |
a307d594 | 103 | return irq; |
e6c866d4 DG |
104 | } |
105 | ||
f4b9523b | 106 | /* Allocate block of consequtive IRQs, returns a number of the first */ |
ff9d2afa | 107 | int spapr_allocate_irq_block(int num, bool lsi) |
f4b9523b AK |
108 | { |
109 | int first = -1; | |
110 | int i; | |
111 | ||
112 | for (i = 0; i < num; ++i) { | |
113 | int irq; | |
114 | ||
ff9d2afa | 115 | irq = spapr_allocate_irq(0, lsi); |
f4b9523b AK |
116 | if (!irq) { |
117 | return -1; | |
118 | } | |
119 | ||
120 | if (0 == i) { | |
121 | first = irq; | |
122 | } | |
123 | ||
124 | /* If the above doesn't create a consecutive block then that's | |
125 | * an internal bug */ | |
126 | assert(irq == (first + i)); | |
127 | } | |
128 | ||
129 | return first; | |
130 | } | |
131 | ||
7f763a5d | 132 | static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) |
6e806cc3 BR |
133 | { |
134 | int ret = 0, offset; | |
1b1ed8dc | 135 | CPUState *cpu; |
6e806cc3 BR |
136 | char cpu_model[32]; |
137 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 138 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 BR |
139 | |
140 | assert(spapr->cpu_model); | |
141 | ||
182735ef | 142 | for (cpu = first_cpu; cpu != NULL; cpu = cpu->next_cpu) { |
6e806cc3 BR |
143 | uint32_t associativity[] = {cpu_to_be32(0x5), |
144 | cpu_to_be32(0x0), | |
145 | cpu_to_be32(0x0), | |
146 | cpu_to_be32(0x0), | |
1b1ed8dc | 147 | cpu_to_be32(cpu->numa_node), |
55e5c285 | 148 | cpu_to_be32(cpu->cpu_index)}; |
6e806cc3 | 149 | |
55e5c285 | 150 | if ((cpu->cpu_index % smt) != 0) { |
6e806cc3 BR |
151 | continue; |
152 | } | |
153 | ||
154 | snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, | |
55e5c285 | 155 | cpu->cpu_index); |
6e806cc3 BR |
156 | |
157 | offset = fdt_path_offset(fdt, cpu_model); | |
158 | if (offset < 0) { | |
159 | return offset; | |
160 | } | |
161 | ||
7f763a5d DG |
162 | if (nb_numa_nodes > 1) { |
163 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
164 | sizeof(associativity)); | |
165 | if (ret < 0) { | |
166 | return ret; | |
167 | } | |
168 | } | |
169 | ||
170 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", | |
171 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
172 | if (ret < 0) { |
173 | return ret; | |
174 | } | |
175 | } | |
176 | return ret; | |
177 | } | |
178 | ||
5af9873d BH |
179 | |
180 | static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, | |
181 | size_t maxsize) | |
182 | { | |
183 | size_t maxcells = maxsize / sizeof(uint32_t); | |
184 | int i, j, count; | |
185 | uint32_t *p = prop; | |
186 | ||
187 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
188 | struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
189 | ||
190 | if (!sps->page_shift) { | |
191 | break; | |
192 | } | |
193 | for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { | |
194 | if (sps->enc[count].page_shift == 0) { | |
195 | break; | |
196 | } | |
197 | } | |
198 | if ((p - prop) >= (maxcells - 3 - count * 2)) { | |
199 | break; | |
200 | } | |
201 | *(p++) = cpu_to_be32(sps->page_shift); | |
202 | *(p++) = cpu_to_be32(sps->slb_enc); | |
203 | *(p++) = cpu_to_be32(count); | |
204 | for (j = 0; j < count; j++) { | |
205 | *(p++) = cpu_to_be32(sps->enc[j].page_shift); | |
206 | *(p++) = cpu_to_be32(sps->enc[j].pte_enc); | |
207 | } | |
208 | } | |
209 | ||
210 | return (p - prop) * sizeof(uint32_t); | |
211 | } | |
212 | ||
7f763a5d DG |
213 | #define _FDT(exp) \ |
214 | do { \ | |
215 | int ret = (exp); \ | |
216 | if (ret < 0) { \ | |
217 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
218 | #exp, fdt_strerror(ret)); \ | |
219 | exit(1); \ | |
220 | } \ | |
221 | } while (0) | |
222 | ||
223 | ||
a3467baa | 224 | static void *spapr_create_fdt_skel(const char *cpu_model, |
a8170e5e AK |
225 | hwaddr initrd_base, |
226 | hwaddr initrd_size, | |
227 | hwaddr kernel_size, | |
a3467baa | 228 | const char *boot_device, |
74d042e5 DG |
229 | const char *kernel_cmdline, |
230 | uint32_t epow_irq) | |
9fdf0c29 DG |
231 | { |
232 | void *fdt; | |
182735ef | 233 | CPUState *cs; |
9fdf0c29 DG |
234 | uint32_t start_prop = cpu_to_be32(initrd_base); |
235 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
ee86dfee | 236 | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
a3d0abae | 237 | "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk"; |
c73e3771 | 238 | char qemu_hypertas_prop[] = "hcall-memop1"; |
7f763a5d | 239 | uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
b5cec4c5 | 240 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; |
9fdf0c29 | 241 | char *modelname; |
7f763a5d | 242 | int i, smt = kvmppc_smt_threads(); |
6e806cc3 | 243 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
9fdf0c29 | 244 | |
7267c094 | 245 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
246 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
247 | ||
4d8d5467 BH |
248 | if (kernel_size) { |
249 | _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); | |
250 | } | |
251 | if (initrd_size) { | |
252 | _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); | |
253 | } | |
9fdf0c29 DG |
254 | _FDT((fdt_finish_reservemap(fdt))); |
255 | ||
256 | /* Root node */ | |
257 | _FDT((fdt_begin_node(fdt, ""))); | |
258 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 259 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 260 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 DG |
261 | |
262 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
263 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
264 | ||
265 | /* /chosen */ | |
266 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
267 | ||
6e806cc3 BR |
268 | /* Set Form1_affinity */ |
269 | _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); | |
270 | ||
9fdf0c29 DG |
271 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); |
272 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
273 | &start_prop, sizeof(start_prop)))); | |
274 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
275 | &end_prop, sizeof(end_prop)))); | |
4d8d5467 BH |
276 | if (kernel_size) { |
277 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
278 | cpu_to_be64(kernel_size) }; | |
9fdf0c29 | 279 | |
4d8d5467 BH |
280 | _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
281 | } | |
2c9ee029 AS |
282 | if (boot_device) { |
283 | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); | |
284 | } | |
f28359d8 LZ |
285 | _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); |
286 | _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); | |
287 | _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); | |
3384f95c | 288 | |
9fdf0c29 DG |
289 | _FDT((fdt_end_node(fdt))); |
290 | ||
9fdf0c29 DG |
291 | /* cpus */ |
292 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
293 | ||
294 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
295 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
296 | ||
7267c094 | 297 | modelname = g_strdup(cpu_model); |
9fdf0c29 DG |
298 | |
299 | for (i = 0; i < strlen(modelname); i++) { | |
300 | modelname[i] = toupper(modelname[i]); | |
301 | } | |
302 | ||
6e806cc3 BR |
303 | /* This is needed during FDT finalization */ |
304 | spapr->cpu_model = g_strdup(modelname); | |
305 | ||
182735ef AF |
306 | for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { |
307 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
308 | CPUPPCState *env = &cpu->env; | |
309 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
310 | int index = cs->cpu_index; | |
e97c3636 DG |
311 | uint32_t servers_prop[smp_threads]; |
312 | uint32_t gservers_prop[smp_threads * 2]; | |
9fdf0c29 DG |
313 | char *nodename; |
314 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
315 | 0xffffffff, 0xffffffff}; | |
0a8b2938 AG |
316 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
317 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; | |
5af9873d BH |
318 | uint32_t page_sizes_prop[64]; |
319 | size_t page_sizes_prop_size; | |
9fdf0c29 | 320 | |
e97c3636 DG |
321 | if ((index % smt) != 0) { |
322 | continue; | |
323 | } | |
324 | ||
4ecf8aa5 | 325 | nodename = g_strdup_printf("%s@%x", modelname, index); |
9fdf0c29 DG |
326 | |
327 | _FDT((fdt_begin_node(fdt, nodename))); | |
328 | ||
4ecf8aa5 | 329 | g_free(nodename); |
9fdf0c29 | 330 | |
c7a5c0c9 | 331 | _FDT((fdt_property_cell(fdt, "reg", index))); |
9fdf0c29 DG |
332 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
333 | ||
334 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
0cbad81f | 335 | _FDT((fdt_property_cell(fdt, "d-cache-block-size", |
9fdf0c29 | 336 | env->dcache_line_size))); |
0cbad81f DG |
337 | _FDT((fdt_property_cell(fdt, "d-cache-line-size", |
338 | env->dcache_line_size))); | |
339 | _FDT((fdt_property_cell(fdt, "i-cache-block-size", | |
340 | env->icache_line_size))); | |
341 | _FDT((fdt_property_cell(fdt, "i-cache-line-size", | |
9fdf0c29 | 342 | env->icache_line_size))); |
0cbad81f DG |
343 | |
344 | if (pcc->l1_dcache_size) { | |
345 | _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); | |
346 | } else { | |
347 | fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); | |
348 | } | |
349 | if (pcc->l1_icache_size) { | |
350 | _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); | |
351 | } else { | |
352 | fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); | |
353 | } | |
354 | ||
0a8b2938 AG |
355 | _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); |
356 | _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); | |
9fdf0c29 DG |
357 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); |
358 | _FDT((fdt_property_string(fdt, "status", "okay"))); | |
359 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
e97c3636 DG |
360 | |
361 | /* Build interrupt servers and gservers properties */ | |
362 | for (i = 0; i < smp_threads; i++) { | |
363 | servers_prop[i] = cpu_to_be32(index + i); | |
364 | /* Hack, direct the group queues back to cpu 0 */ | |
365 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
366 | gservers_prop[i*2 + 1] = 0; | |
367 | } | |
368 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s", | |
369 | servers_prop, sizeof(servers_prop)))); | |
b5cec4c5 | 370 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", |
e97c3636 | 371 | gservers_prop, sizeof(gservers_prop)))); |
9fdf0c29 | 372 | |
c7a5c0c9 | 373 | if (env->mmu_model & POWERPC_MMU_1TSEG) { |
9fdf0c29 DG |
374 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", |
375 | segs, sizeof(segs)))); | |
376 | } | |
377 | ||
6659394f DG |
378 | /* Advertise VMX/VSX (vector extensions) if available |
379 | * 0 / no property == no vector extensions | |
380 | * 1 == VMX / Altivec available | |
381 | * 2 == VSX available */ | |
a7342588 DG |
382 | if (env->insns_flags & PPC_ALTIVEC) { |
383 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
384 | ||
6659394f DG |
385 | _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); |
386 | } | |
387 | ||
388 | /* Advertise DFP (Decimal Floating Point) if available | |
389 | * 0 / no property == no DFP | |
390 | * 1 == DFP available */ | |
a7342588 DG |
391 | if (env->insns_flags2 & PPC2_DFP) { |
392 | _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); | |
6659394f DG |
393 | } |
394 | ||
5af9873d BH |
395 | page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, |
396 | sizeof(page_sizes_prop)); | |
397 | if (page_sizes_prop_size) { | |
398 | _FDT((fdt_property(fdt, "ibm,segment-page-sizes", | |
399 | page_sizes_prop, page_sizes_prop_size))); | |
400 | } | |
401 | ||
9fdf0c29 DG |
402 | _FDT((fdt_end_node(fdt))); |
403 | } | |
404 | ||
7267c094 | 405 | g_free(modelname); |
9fdf0c29 DG |
406 | |
407 | _FDT((fdt_end_node(fdt))); | |
408 | ||
f43e3525 DG |
409 | /* RTAS */ |
410 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
411 | ||
412 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, | |
413 | sizeof(hypertas_prop)))); | |
c73e3771 BH |
414 | _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop, |
415 | sizeof(qemu_hypertas_prop)))); | |
f43e3525 | 416 | |
6e806cc3 BR |
417 | _FDT((fdt_property(fdt, "ibm,associativity-reference-points", |
418 | refpoints, sizeof(refpoints)))); | |
419 | ||
74d042e5 DG |
420 | _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); |
421 | ||
f43e3525 DG |
422 | _FDT((fdt_end_node(fdt))); |
423 | ||
b5cec4c5 | 424 | /* interrupt controller */ |
9dfef5aa | 425 | _FDT((fdt_begin_node(fdt, "interrupt-controller"))); |
b5cec4c5 DG |
426 | |
427 | _FDT((fdt_property_string(fdt, "device_type", | |
428 | "PowerPC-External-Interrupt-Presentation"))); | |
429 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
b5cec4c5 DG |
430 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
431 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
432 | interrupt_server_ranges_prop, | |
433 | sizeof(interrupt_server_ranges_prop)))); | |
0c103f8e DG |
434 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
435 | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); | |
436 | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); | |
b5cec4c5 DG |
437 | |
438 | _FDT((fdt_end_node(fdt))); | |
439 | ||
4040ab72 DG |
440 | /* vdevice */ |
441 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
442 | ||
443 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
444 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
445 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
446 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
447 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
448 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
449 | |
450 | _FDT((fdt_end_node(fdt))); | |
451 | ||
74d042e5 DG |
452 | /* event-sources */ |
453 | spapr_events_fdt_skel(fdt, epow_irq); | |
454 | ||
9fdf0c29 DG |
455 | _FDT((fdt_end_node(fdt))); /* close root node */ |
456 | _FDT((fdt_finish(fdt))); | |
457 | ||
a3467baa DG |
458 | return fdt; |
459 | } | |
460 | ||
7f763a5d DG |
461 | static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) |
462 | { | |
463 | uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0), | |
464 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
465 | cpu_to_be32(0x0)}; | |
466 | char mem_name[32]; | |
a8170e5e | 467 | hwaddr node0_size, mem_start; |
7f763a5d DG |
468 | uint64_t mem_reg_property[2]; |
469 | int i, off; | |
470 | ||
471 | /* memory node(s) */ | |
472 | node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; | |
473 | if (spapr->rma_size > node0_size) { | |
474 | spapr->rma_size = node0_size; | |
475 | } | |
476 | ||
477 | /* RMA */ | |
478 | mem_reg_property[0] = 0; | |
479 | mem_reg_property[1] = cpu_to_be64(spapr->rma_size); | |
480 | off = fdt_add_subnode(fdt, 0, "memory@0"); | |
481 | _FDT(off); | |
482 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
483 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
484 | sizeof(mem_reg_property)))); | |
485 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
486 | sizeof(associativity)))); | |
487 | ||
488 | /* RAM: Node 0 */ | |
489 | if (node0_size > spapr->rma_size) { | |
490 | mem_reg_property[0] = cpu_to_be64(spapr->rma_size); | |
491 | mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size); | |
492 | ||
493 | sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size); | |
494 | off = fdt_add_subnode(fdt, 0, mem_name); | |
495 | _FDT(off); | |
496 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
497 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
498 | sizeof(mem_reg_property)))); | |
499 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
500 | sizeof(associativity)))); | |
501 | } | |
502 | ||
503 | /* RAM: Node 1 and beyond */ | |
504 | mem_start = node0_size; | |
505 | for (i = 1; i < nb_numa_nodes; i++) { | |
506 | mem_reg_property[0] = cpu_to_be64(mem_start); | |
507 | mem_reg_property[1] = cpu_to_be64(node_mem[i]); | |
508 | associativity[3] = associativity[4] = cpu_to_be32(i); | |
509 | sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start); | |
510 | off = fdt_add_subnode(fdt, 0, mem_name); | |
511 | _FDT(off); | |
512 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
513 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
514 | sizeof(mem_reg_property)))); | |
515 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
516 | sizeof(associativity)))); | |
517 | mem_start += node_mem[i]; | |
518 | } | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
a3467baa | 523 | static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
a8170e5e AK |
524 | hwaddr fdt_addr, |
525 | hwaddr rtas_addr, | |
526 | hwaddr rtas_size) | |
a3467baa DG |
527 | { |
528 | int ret; | |
529 | void *fdt; | |
3384f95c | 530 | sPAPRPHBState *phb; |
a3467baa | 531 | |
7267c094 | 532 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
533 | |
534 | /* open out the base tree into a temp buffer for the final tweaks */ | |
535 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 536 | |
7f763a5d DG |
537 | ret = spapr_populate_memory(spapr, fdt); |
538 | if (ret < 0) { | |
539 | fprintf(stderr, "couldn't setup memory nodes in fdt\n"); | |
540 | exit(1); | |
541 | } | |
542 | ||
4040ab72 DG |
543 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
544 | if (ret < 0) { | |
545 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
546 | exit(1); | |
547 | } | |
548 | ||
3384f95c | 549 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 550 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
3384f95c DG |
551 | } |
552 | ||
553 | if (ret < 0) { | |
554 | fprintf(stderr, "couldn't setup PCI devices in fdt\n"); | |
555 | exit(1); | |
556 | } | |
557 | ||
39ac8455 DG |
558 | /* RTAS */ |
559 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
560 | if (ret < 0) { | |
561 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
562 | } | |
563 | ||
6e806cc3 | 564 | /* Advertise NUMA via ibm,associativity */ |
7f763a5d DG |
565 | ret = spapr_fixup_cpu_dt(fdt, spapr); |
566 | if (ret < 0) { | |
567 | fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); | |
6e806cc3 BR |
568 | } |
569 | ||
3fc5acde | 570 | if (!spapr->has_graphics) { |
f28359d8 LZ |
571 | spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
572 | } | |
68f3a94c | 573 | |
4040ab72 DG |
574 | _FDT((fdt_pack(fdt))); |
575 | ||
4d8d5467 BH |
576 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
577 | hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", | |
578 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
579 | exit(1); | |
580 | } | |
581 | ||
a3467baa | 582 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 583 | |
7267c094 | 584 | g_free(fdt); |
9fdf0c29 DG |
585 | } |
586 | ||
587 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
588 | { | |
589 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
590 | } | |
591 | ||
1b14670a | 592 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 593 | { |
1b14670a AF |
594 | CPUPPCState *env = &cpu->env; |
595 | ||
efcb9383 DG |
596 | if (msr_pr) { |
597 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
598 | env->gpr[3] = H_PRIVILEGE; | |
599 | } else { | |
aa100fa4 | 600 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 601 | } |
9fdf0c29 DG |
602 | } |
603 | ||
7f763a5d DG |
604 | static void spapr_reset_htab(sPAPREnvironment *spapr) |
605 | { | |
606 | long shift; | |
607 | ||
608 | /* allocate hash page table. For now we always make this 16mb, | |
609 | * later we should probably make it scale to the size of guest | |
610 | * RAM */ | |
611 | ||
612 | shift = kvmppc_reset_htab(spapr->htab_shift); | |
613 | ||
614 | if (shift > 0) { | |
615 | /* Kernel handles htab, we don't need to allocate one */ | |
616 | spapr->htab_shift = shift; | |
617 | } else { | |
618 | if (!spapr->htab) { | |
619 | /* Allocate an htab if we don't yet have one */ | |
620 | spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); | |
621 | } | |
622 | ||
623 | /* And clear it */ | |
624 | memset(spapr->htab, 0, HTAB_SIZE(spapr)); | |
625 | } | |
626 | ||
627 | /* Update the RMA size if necessary */ | |
628 | if (spapr->vrma_adjust) { | |
629 | spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift); | |
630 | } | |
9fdf0c29 DG |
631 | } |
632 | ||
c8787ad4 | 633 | static void ppc_spapr_reset(void) |
a3467baa | 634 | { |
182735ef | 635 | PowerPCCPU *first_ppc_cpu; |
259186a7 | 636 | |
7f763a5d DG |
637 | /* Reset the hash table & recalc the RMA */ |
638 | spapr_reset_htab(spapr); | |
a3467baa | 639 | |
c8787ad4 | 640 | qemu_devices_reset(); |
a3467baa DG |
641 | |
642 | /* Load the fdt */ | |
643 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
644 | spapr->rtas_size); | |
645 | ||
646 | /* Set up the entry state */ | |
182735ef AF |
647 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
648 | first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; | |
649 | first_ppc_cpu->env.gpr[5] = 0; | |
650 | first_cpu->halted = 0; | |
651 | first_ppc_cpu->env.nip = spapr->entry_point; | |
a3467baa DG |
652 | |
653 | } | |
654 | ||
1bba0dc9 AF |
655 | static void spapr_cpu_reset(void *opaque) |
656 | { | |
5b2038e0 | 657 | PowerPCCPU *cpu = opaque; |
259186a7 | 658 | CPUState *cs = CPU(cpu); |
048706d9 | 659 | CPUPPCState *env = &cpu->env; |
1bba0dc9 | 660 | |
259186a7 | 661 | cpu_reset(cs); |
048706d9 DG |
662 | |
663 | /* All CPUs start halted. CPU0 is unhalted from the machine level | |
664 | * reset code and the rest are explicitly started up by the guest | |
665 | * using an RTAS call */ | |
259186a7 | 666 | cs->halted = 1; |
048706d9 DG |
667 | |
668 | env->spr[SPR_HIOR] = 0; | |
7f763a5d | 669 | |
4be21d56 | 670 | env->external_htab = (uint8_t *)spapr->htab; |
7f763a5d DG |
671 | env->htab_base = -1; |
672 | env->htab_mask = HTAB_SIZE(spapr) - 1; | |
ec4936e1 | 673 | env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | |
7f763a5d | 674 | (spapr->htab_shift - 18); |
1bba0dc9 AF |
675 | } |
676 | ||
639e8102 DG |
677 | static void spapr_create_nvram(sPAPREnvironment *spapr) |
678 | { | |
2ff3de68 MA |
679 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
680 | const char *drivename = qemu_opt_get(qemu_get_machine_opts(), "nvram"); | |
639e8102 | 681 | |
2ff3de68 MA |
682 | if (drivename) { |
683 | BlockDriverState *bs; | |
639e8102 | 684 | |
2ff3de68 MA |
685 | bs = bdrv_find(drivename); |
686 | if (!bs) { | |
687 | fprintf(stderr, "No such block device \"%s\" for nvram\n", | |
688 | drivename); | |
689 | exit(1); | |
639e8102 | 690 | } |
2ff3de68 | 691 | qdev_prop_set_drive_nofail(dev, "drive", bs); |
639e8102 DG |
692 | } |
693 | ||
694 | qdev_init_nofail(dev); | |
695 | ||
696 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
697 | } | |
698 | ||
8c57b867 | 699 | /* Returns whether we want to use VGA or not */ |
f28359d8 LZ |
700 | static int spapr_vga_init(PCIBus *pci_bus) |
701 | { | |
8c57b867 | 702 | switch (vga_interface_type) { |
8c57b867 | 703 | case VGA_NONE: |
1ddcae82 AJ |
704 | case VGA_STD: |
705 | return pci_vga_init(pci_bus) != NULL; | |
8c57b867 | 706 | default: |
f28359d8 LZ |
707 | fprintf(stderr, "This vga model is not supported," |
708 | "currently it only supports -vga std\n"); | |
8c57b867 AG |
709 | exit(0); |
710 | break; | |
f28359d8 | 711 | } |
f28359d8 LZ |
712 | } |
713 | ||
4be21d56 DG |
714 | static const VMStateDescription vmstate_spapr = { |
715 | .name = "spapr", | |
716 | .version_id = 1, | |
717 | .minimum_version_id = 1, | |
718 | .minimum_version_id_old = 1, | |
719 | .fields = (VMStateField []) { | |
720 | VMSTATE_UINT32(next_irq, sPAPREnvironment), | |
721 | ||
722 | /* RTC offset */ | |
723 | VMSTATE_UINT64(rtc_offset, sPAPREnvironment), | |
724 | ||
725 | VMSTATE_END_OF_LIST() | |
726 | }, | |
727 | }; | |
728 | ||
729 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) | |
730 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
731 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
732 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
733 | ||
734 | static int htab_save_setup(QEMUFile *f, void *opaque) | |
735 | { | |
736 | sPAPREnvironment *spapr = opaque; | |
737 | ||
4be21d56 DG |
738 | /* "Iteration" header */ |
739 | qemu_put_be32(f, spapr->htab_shift); | |
740 | ||
e68cb8b4 AK |
741 | if (spapr->htab) { |
742 | spapr->htab_save_index = 0; | |
743 | spapr->htab_first_pass = true; | |
744 | } else { | |
745 | assert(kvm_enabled()); | |
746 | ||
747 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
748 | if (spapr->htab_fd < 0) { | |
749 | fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", | |
750 | strerror(errno)); | |
751 | return -1; | |
752 | } | |
753 | } | |
754 | ||
755 | ||
4be21d56 DG |
756 | return 0; |
757 | } | |
758 | ||
4be21d56 DG |
759 | static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, |
760 | int64_t max_ns) | |
761 | { | |
762 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
763 | int index = spapr->htab_save_index; | |
764 | int64_t starttime = qemu_get_clock_ns(rt_clock); | |
765 | ||
766 | assert(spapr->htab_first_pass); | |
767 | ||
768 | do { | |
769 | int chunkstart; | |
770 | ||
771 | /* Consume invalid HPTEs */ | |
772 | while ((index < htabslots) | |
773 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
774 | index++; | |
775 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
776 | } | |
777 | ||
778 | /* Consume valid HPTEs */ | |
779 | chunkstart = index; | |
780 | while ((index < htabslots) | |
781 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
782 | index++; | |
783 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
784 | } | |
785 | ||
786 | if (index > chunkstart) { | |
787 | int n_valid = index - chunkstart; | |
788 | ||
789 | qemu_put_be32(f, chunkstart); | |
790 | qemu_put_be16(f, n_valid); | |
791 | qemu_put_be16(f, 0); | |
792 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
793 | HASH_PTE_SIZE_64 * n_valid); | |
794 | ||
795 | if ((qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { | |
796 | break; | |
797 | } | |
798 | } | |
799 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
800 | ||
801 | if (index >= htabslots) { | |
802 | assert(index == htabslots); | |
803 | index = 0; | |
804 | spapr->htab_first_pass = false; | |
805 | } | |
806 | spapr->htab_save_index = index; | |
807 | } | |
808 | ||
e68cb8b4 AK |
809 | static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, |
810 | int64_t max_ns) | |
4be21d56 DG |
811 | { |
812 | bool final = max_ns < 0; | |
813 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
814 | int examined = 0, sent = 0; | |
815 | int index = spapr->htab_save_index; | |
816 | int64_t starttime = qemu_get_clock_ns(rt_clock); | |
817 | ||
818 | assert(!spapr->htab_first_pass); | |
819 | ||
820 | do { | |
821 | int chunkstart, invalidstart; | |
822 | ||
823 | /* Consume non-dirty HPTEs */ | |
824 | while ((index < htabslots) | |
825 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
826 | index++; | |
827 | examined++; | |
828 | } | |
829 | ||
830 | chunkstart = index; | |
831 | /* Consume valid dirty HPTEs */ | |
832 | while ((index < htabslots) | |
833 | && HPTE_DIRTY(HPTE(spapr->htab, index)) | |
834 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
835 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
836 | index++; | |
837 | examined++; | |
838 | } | |
839 | ||
840 | invalidstart = index; | |
841 | /* Consume invalid dirty HPTEs */ | |
842 | while ((index < htabslots) | |
843 | && HPTE_DIRTY(HPTE(spapr->htab, index)) | |
844 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
845 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
846 | index++; | |
847 | examined++; | |
848 | } | |
849 | ||
850 | if (index > chunkstart) { | |
851 | int n_valid = invalidstart - chunkstart; | |
852 | int n_invalid = index - invalidstart; | |
853 | ||
854 | qemu_put_be32(f, chunkstart); | |
855 | qemu_put_be16(f, n_valid); | |
856 | qemu_put_be16(f, n_invalid); | |
857 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
858 | HASH_PTE_SIZE_64 * n_valid); | |
859 | sent += index - chunkstart; | |
860 | ||
861 | if (!final && (qemu_get_clock_ns(rt_clock) - starttime) > max_ns) { | |
862 | break; | |
863 | } | |
864 | } | |
865 | ||
866 | if (examined >= htabslots) { | |
867 | break; | |
868 | } | |
869 | ||
870 | if (index >= htabslots) { | |
871 | assert(index == htabslots); | |
872 | index = 0; | |
873 | } | |
874 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
875 | ||
876 | if (index >= htabslots) { | |
877 | assert(index == htabslots); | |
878 | index = 0; | |
879 | } | |
880 | ||
881 | spapr->htab_save_index = index; | |
882 | ||
e68cb8b4 | 883 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
884 | } |
885 | ||
e68cb8b4 AK |
886 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
887 | #define MAX_KVM_BUF_SIZE 2048 | |
888 | ||
4be21d56 DG |
889 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
890 | { | |
891 | sPAPREnvironment *spapr = opaque; | |
e68cb8b4 | 892 | int rc = 0; |
4be21d56 DG |
893 | |
894 | /* Iteration header */ | |
895 | qemu_put_be32(f, 0); | |
896 | ||
e68cb8b4 AK |
897 | if (!spapr->htab) { |
898 | assert(kvm_enabled()); | |
899 | ||
900 | rc = kvmppc_save_htab(f, spapr->htab_fd, | |
901 | MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); | |
902 | if (rc < 0) { | |
903 | return rc; | |
904 | } | |
905 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
906 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
907 | } else { | |
e68cb8b4 | 908 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
909 | } |
910 | ||
911 | /* End marker */ | |
912 | qemu_put_be32(f, 0); | |
913 | qemu_put_be16(f, 0); | |
914 | qemu_put_be16(f, 0); | |
915 | ||
e68cb8b4 | 916 | return rc; |
4be21d56 DG |
917 | } |
918 | ||
919 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
920 | { | |
921 | sPAPREnvironment *spapr = opaque; | |
922 | ||
923 | /* Iteration header */ | |
924 | qemu_put_be32(f, 0); | |
925 | ||
e68cb8b4 AK |
926 | if (!spapr->htab) { |
927 | int rc; | |
928 | ||
929 | assert(kvm_enabled()); | |
930 | ||
931 | rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); | |
932 | if (rc < 0) { | |
933 | return rc; | |
934 | } | |
935 | close(spapr->htab_fd); | |
936 | spapr->htab_fd = -1; | |
937 | } else { | |
938 | htab_save_later_pass(f, spapr, -1); | |
939 | } | |
4be21d56 DG |
940 | |
941 | /* End marker */ | |
942 | qemu_put_be32(f, 0); | |
943 | qemu_put_be16(f, 0); | |
944 | qemu_put_be16(f, 0); | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
950 | { | |
951 | sPAPREnvironment *spapr = opaque; | |
952 | uint32_t section_hdr; | |
e68cb8b4 | 953 | int fd = -1; |
4be21d56 DG |
954 | |
955 | if (version_id < 1 || version_id > 1) { | |
956 | fprintf(stderr, "htab_load() bad version\n"); | |
957 | return -EINVAL; | |
958 | } | |
959 | ||
960 | section_hdr = qemu_get_be32(f); | |
961 | ||
962 | if (section_hdr) { | |
963 | /* First section, just the hash shift */ | |
964 | if (spapr->htab_shift != section_hdr) { | |
965 | return -EINVAL; | |
966 | } | |
967 | return 0; | |
968 | } | |
969 | ||
e68cb8b4 AK |
970 | if (!spapr->htab) { |
971 | assert(kvm_enabled()); | |
972 | ||
973 | fd = kvmppc_get_htab_fd(true); | |
974 | if (fd < 0) { | |
975 | fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", | |
976 | strerror(errno)); | |
977 | } | |
978 | } | |
979 | ||
4be21d56 DG |
980 | while (true) { |
981 | uint32_t index; | |
982 | uint16_t n_valid, n_invalid; | |
983 | ||
984 | index = qemu_get_be32(f); | |
985 | n_valid = qemu_get_be16(f); | |
986 | n_invalid = qemu_get_be16(f); | |
987 | ||
988 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
989 | /* End of Stream */ | |
990 | break; | |
991 | } | |
992 | ||
e68cb8b4 | 993 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
994 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
995 | /* Bad index in stream */ | |
996 | fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " | |
e68cb8b4 AK |
997 | "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, |
998 | spapr->htab_shift); | |
4be21d56 DG |
999 | return -EINVAL; |
1000 | } | |
1001 | ||
e68cb8b4 AK |
1002 | if (spapr->htab) { |
1003 | if (n_valid) { | |
1004 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1005 | HASH_PTE_SIZE_64 * n_valid); | |
1006 | } | |
1007 | if (n_invalid) { | |
1008 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1009 | HASH_PTE_SIZE_64 * n_invalid); | |
1010 | } | |
1011 | } else { | |
1012 | int rc; | |
1013 | ||
1014 | assert(fd >= 0); | |
1015 | ||
1016 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1017 | if (rc < 0) { | |
1018 | return rc; | |
1019 | } | |
4be21d56 DG |
1020 | } |
1021 | } | |
1022 | ||
e68cb8b4 AK |
1023 | if (!spapr->htab) { |
1024 | assert(fd >= 0); | |
1025 | close(fd); | |
1026 | } | |
1027 | ||
4be21d56 DG |
1028 | return 0; |
1029 | } | |
1030 | ||
1031 | static SaveVMHandlers savevm_htab_handlers = { | |
1032 | .save_live_setup = htab_save_setup, | |
1033 | .save_live_iterate = htab_save_iterate, | |
1034 | .save_live_complete = htab_save_complete, | |
1035 | .load_state = htab_load, | |
1036 | }; | |
1037 | ||
9fdf0c29 | 1038 | /* pSeries LPAR / sPAPR hardware init */ |
5f072e1f | 1039 | static void ppc_spapr_init(QEMUMachineInitArgs *args) |
9fdf0c29 | 1040 | { |
5f072e1f EH |
1041 | ram_addr_t ram_size = args->ram_size; |
1042 | const char *cpu_model = args->cpu_model; | |
1043 | const char *kernel_filename = args->kernel_filename; | |
1044 | const char *kernel_cmdline = args->kernel_cmdline; | |
1045 | const char *initrd_filename = args->initrd_filename; | |
1046 | const char *boot_device = args->boot_device; | |
05769733 | 1047 | PowerPCCPU *cpu; |
e2684c0b | 1048 | CPUPPCState *env; |
8c9f64df | 1049 | PCIHostState *phb; |
9fdf0c29 | 1050 | int i; |
890c2b77 AK |
1051 | MemoryRegion *sysmem = get_system_memory(); |
1052 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
a8170e5e | 1053 | hwaddr rma_alloc_size; |
4d8d5467 BH |
1054 | uint32_t initrd_base = 0; |
1055 | long kernel_size = 0, initrd_size = 0; | |
1056 | long load_limit, rtas_limit, fw_size; | |
39ac8455 | 1057 | char *filename; |
9fdf0c29 | 1058 | |
0ee2c058 AK |
1059 | msi_supported = true; |
1060 | ||
d43b45e2 DG |
1061 | spapr = g_malloc0(sizeof(*spapr)); |
1062 | QLIST_INIT(&spapr->phbs); | |
1063 | ||
9fdf0c29 DG |
1064 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1065 | ||
354ac20a DG |
1066 | /* Allocate RMA if necessary */ |
1067 | rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem); | |
1068 | ||
1069 | if (rma_alloc_size == -1) { | |
1070 | hw_error("qemu: Unable to create RMA\n"); | |
1071 | exit(1); | |
1072 | } | |
7f763a5d | 1073 | |
354ac20a | 1074 | if (rma_alloc_size && (rma_alloc_size < ram_size)) { |
7f763a5d | 1075 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1076 | } else { |
7f763a5d DG |
1077 | spapr->rma_size = ram_size; |
1078 | ||
1079 | /* With KVM, we don't actually know whether KVM supports an | |
1080 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1081 | * (HV KVM using VRMA), so we always assume the latter | |
1082 | * | |
1083 | * In that case, we also limit the initial allocations for RTAS | |
1084 | * etc... to 256M since we have no way to know what the VRMA size | |
1085 | * is going to be as it depends on the size of the hash table | |
1086 | * isn't determined yet. | |
1087 | */ | |
1088 | if (kvm_enabled()) { | |
1089 | spapr->vrma_adjust = 1; | |
1090 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1091 | } | |
354ac20a DG |
1092 | } |
1093 | ||
4d8d5467 | 1094 | /* We place the device tree and RTAS just below either the top of the RMA, |
354ac20a DG |
1095 | * or just below 2GB, whichever is lowere, so that it can be |
1096 | * processed with 32-bit real mode code if necessary */ | |
7f763a5d | 1097 | rtas_limit = MIN(spapr->rma_size, 0x80000000); |
4d8d5467 BH |
1098 | spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1099 | spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; | |
1100 | load_limit = spapr->fdt_addr - FW_OVERHEAD; | |
9fdf0c29 | 1101 | |
382be75d DG |
1102 | /* We aim for a hash table of size 1/128 the size of RAM. The |
1103 | * normal rule of thumb is 1/64 the size of RAM, but that's much | |
1104 | * more than needed for the Linux guests we support. */ | |
1105 | spapr->htab_shift = 18; /* Minimum architected size */ | |
1106 | while (spapr->htab_shift <= 46) { | |
1107 | if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { | |
1108 | break; | |
1109 | } | |
1110 | spapr->htab_shift++; | |
1111 | } | |
7f763a5d | 1112 | |
7b565160 DG |
1113 | /* Set up Interrupt Controller before we create the VCPUs */ |
1114 | spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, | |
1115 | XICS_IRQS); | |
1116 | spapr->next_irq = XICS_IRQ_BASE; | |
1117 | ||
9fdf0c29 DG |
1118 | /* init CPUs */ |
1119 | if (cpu_model == NULL) { | |
6b7a2cf6 | 1120 | cpu_model = kvm_enabled() ? "host" : "POWER7"; |
9fdf0c29 DG |
1121 | } |
1122 | for (i = 0; i < smp_cpus; i++) { | |
05769733 AF |
1123 | cpu = cpu_ppc_init(cpu_model); |
1124 | if (cpu == NULL) { | |
9fdf0c29 DG |
1125 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
1126 | exit(1); | |
1127 | } | |
05769733 AF |
1128 | env = &cpu->env; |
1129 | ||
7b565160 DG |
1130 | xics_cpu_setup(spapr->icp, cpu); |
1131 | ||
9fdf0c29 DG |
1132 | /* Set time-base frequency to 512 MHz */ |
1133 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
9fdf0c29 | 1134 | |
2cf3eb6d FC |
1135 | /* PAPR always has exception vectors in RAM not ROM. To ensure this, |
1136 | * MSR[IP] should never be set. | |
1137 | */ | |
1138 | env->msr_mask &= ~(1 << 6); | |
048706d9 DG |
1139 | |
1140 | /* Tell KVM that we're in PAPR mode */ | |
1141 | if (kvm_enabled()) { | |
1bc22652 | 1142 | kvmppc_set_papr(cpu); |
048706d9 DG |
1143 | } |
1144 | ||
1145 | qemu_register_reset(spapr_cpu_reset, cpu); | |
9fdf0c29 DG |
1146 | } |
1147 | ||
1148 | /* allocate RAM */ | |
f73a2575 | 1149 | spapr->ram_limit = ram_size; |
354ac20a DG |
1150 | if (spapr->ram_limit > rma_alloc_size) { |
1151 | ram_addr_t nonrma_base = rma_alloc_size; | |
1152 | ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size; | |
1153 | ||
2c9b15ca | 1154 | memory_region_init_ram(ram, NULL, "ppc_spapr.ram", nonrma_size); |
c5705a77 | 1155 | vmstate_register_ram_global(ram); |
354ac20a DG |
1156 | memory_region_add_subregion(sysmem, nonrma_base, ram); |
1157 | } | |
9fdf0c29 | 1158 | |
39ac8455 | 1159 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
a3467baa | 1160 | spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
4d8d5467 | 1161 | rtas_limit - spapr->rtas_addr); |
a3467baa | 1162 | if (spapr->rtas_size < 0) { |
39ac8455 DG |
1163 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); |
1164 | exit(1); | |
1165 | } | |
4d8d5467 BH |
1166 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
1167 | hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n", | |
1168 | spapr->rtas_size, RTAS_MAX_SIZE); | |
1169 | exit(1); | |
1170 | } | |
7267c094 | 1171 | g_free(filename); |
39ac8455 | 1172 | |
74d042e5 DG |
1173 | /* Set up EPOW events infrastructure */ |
1174 | spapr_events_init(spapr); | |
1175 | ||
b5cec4c5 | 1176 | /* Set up VIO bus */ |
4040ab72 DG |
1177 | spapr->vio_bus = spapr_vio_bus_init(); |
1178 | ||
277f9acf | 1179 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1180 | if (serial_hds[i]) { |
d601fac4 | 1181 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1182 | } |
1183 | } | |
9fdf0c29 | 1184 | |
639e8102 DG |
1185 | /* We always have at least the nvram device on VIO */ |
1186 | spapr_create_nvram(spapr); | |
1187 | ||
3384f95c | 1188 | /* Set up PCI */ |
fa28f71b AK |
1189 | spapr_pci_rtas_init(); |
1190 | ||
89dfd6e1 | 1191 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1192 | |
277f9acf | 1193 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1194 | NICInfo *nd = &nd_table[i]; |
1195 | ||
1196 | if (!nd->model) { | |
7267c094 | 1197 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1198 | } |
1199 | ||
1200 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1201 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1202 | } else { |
29b358f9 | 1203 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1204 | } |
1205 | } | |
1206 | ||
6e270446 | 1207 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1208 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1209 | } |
1210 | ||
f28359d8 | 1211 | /* Graphics */ |
8c9f64df | 1212 | if (spapr_vga_init(phb->bus)) { |
3fc5acde | 1213 | spapr->has_graphics = true; |
f28359d8 LZ |
1214 | } |
1215 | ||
094b287f | 1216 | if (usb_enabled(spapr->has_graphics)) { |
8c9f64df | 1217 | pci_create_simple(phb->bus, -1, "pci-ohci"); |
35139a59 DG |
1218 | if (spapr->has_graphics) { |
1219 | usbdevice_create("keyboard"); | |
1220 | usbdevice_create("mouse"); | |
1221 | } | |
1222 | } | |
1223 | ||
7f763a5d | 1224 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
4d8d5467 BH |
1225 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " |
1226 | "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); | |
1227 | exit(1); | |
1228 | } | |
1229 | ||
9fdf0c29 DG |
1230 | if (kernel_filename) { |
1231 | uint64_t lowaddr = 0; | |
1232 | ||
9fdf0c29 DG |
1233 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
1234 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
1235 | if (kernel_size < 0) { | |
a3467baa DG |
1236 | kernel_size = load_image_targphys(kernel_filename, |
1237 | KERNEL_LOAD_ADDR, | |
4d8d5467 | 1238 | load_limit - KERNEL_LOAD_ADDR); |
9fdf0c29 DG |
1239 | } |
1240 | if (kernel_size < 0) { | |
1241 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
1242 | kernel_filename); | |
1243 | exit(1); | |
1244 | } | |
1245 | ||
1246 | /* load initrd */ | |
1247 | if (initrd_filename) { | |
4d8d5467 BH |
1248 | /* Try to locate the initrd in the gap between the kernel |
1249 | * and the firmware. Add a bit of space just in case | |
1250 | */ | |
1251 | initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; | |
9fdf0c29 | 1252 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
4d8d5467 | 1253 | load_limit - initrd_base); |
9fdf0c29 DG |
1254 | if (initrd_size < 0) { |
1255 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
1256 | initrd_filename); | |
1257 | exit(1); | |
1258 | } | |
1259 | } else { | |
1260 | initrd_base = 0; | |
1261 | initrd_size = 0; | |
1262 | } | |
4d8d5467 | 1263 | } |
a3467baa | 1264 | |
8e7ea787 AF |
1265 | if (bios_name == NULL) { |
1266 | bios_name = FW_FILE_NAME; | |
1267 | } | |
1268 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4d8d5467 BH |
1269 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
1270 | if (fw_size < 0) { | |
1271 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
1272 | exit(1); | |
1273 | } | |
1274 | g_free(filename); | |
4d8d5467 BH |
1275 | |
1276 | spapr->entry_point = 0x100; | |
1277 | ||
4be21d56 DG |
1278 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
1279 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
1280 | &savevm_htab_handlers, spapr); | |
1281 | ||
9fdf0c29 | 1282 | /* Prepare the device tree */ |
7f763a5d | 1283 | spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
a3467baa | 1284 | initrd_base, initrd_size, |
4d8d5467 | 1285 | kernel_size, |
74d042e5 DG |
1286 | boot_device, kernel_cmdline, |
1287 | spapr->epow_irq); | |
a3467baa | 1288 | assert(spapr->fdt_skel != NULL); |
9fdf0c29 DG |
1289 | } |
1290 | ||
1291 | static QEMUMachine spapr_machine = { | |
1292 | .name = "pseries", | |
1293 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
159f8286 | 1294 | .is_default = 1, |
9fdf0c29 | 1295 | .init = ppc_spapr_init, |
c8787ad4 | 1296 | .reset = ppc_spapr_reset, |
2d0d2837 | 1297 | .block_default_type = IF_SCSI, |
9fdf0c29 | 1298 | .max_cpus = MAX_CPUS, |
9fdf0c29 | 1299 | .no_parallel = 1, |
2c9ee029 | 1300 | .boot_order = NULL, |
9fdf0c29 DG |
1301 | }; |
1302 | ||
1303 | static void spapr_machine_init(void) | |
1304 | { | |
1305 | qemu_register_machine(&spapr_machine); | |
1306 | } | |
1307 | ||
1308 | machine_init(spapr_machine_init); |