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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
fa98fbfc | 29 | #include "qapi/visitor.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
e35704ba | 31 | #include "sysemu/numa.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
03dd024f | 33 | #include "qemu/log.h" |
71461b0f | 34 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 35 | #include "elf.h" |
1422e32d | 36 | #include "net/net.h" |
ad440b4a | 37 | #include "sysemu/device_tree.h" |
fa1d36df | 38 | #include "sysemu/block-backend.h" |
9c17d615 | 39 | #include "sysemu/cpus.h" |
b3946626 | 40 | #include "sysemu/hw_accel.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
c4b63b7c | 42 | #include "migration/misc.h" |
84a899de | 43 | #include "migration/global_state.h" |
f2a8f0a6 | 44 | #include "migration/register.h" |
4be21d56 | 45 | #include "mmu-hash64.h" |
b4db5413 | 46 | #include "mmu-book3s-v3.h" |
7abd43ba | 47 | #include "cpu-models.h" |
3794d548 | 48 | #include "qom/cpu.h" |
9fdf0c29 DG |
49 | |
50 | #include "hw/boards.h" | |
0d09e41a | 51 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
52 | #include "hw/loader.h" |
53 | ||
7804c353 | 54 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
55 | #include "hw/ppc/spapr.h" |
56 | #include "hw/ppc/spapr_vio.h" | |
57 | #include "hw/pci-host/spapr.h" | |
58 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 59 | #include "hw/pci/msi.h" |
9fdf0c29 | 60 | |
83c9f4ca | 61 | #include "hw/pci/pci.h" |
71461b0f AK |
62 | #include "hw/scsi/scsi.h" |
63 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 64 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 65 | |
022c62cb | 66 | #include "exec/address-spaces.h" |
35139a59 | 67 | #include "hw/usb.h" |
1de7afc9 | 68 | #include "qemu/config-file.h" |
135a129a | 69 | #include "qemu/error-report.h" |
2a6593cb | 70 | #include "trace.h" |
34316482 | 71 | #include "hw/nmi.h" |
6449da45 | 72 | #include "hw/intc/intc.h" |
890c2b77 | 73 | |
68a27b20 | 74 | #include "hw/compat.h" |
f348b6d1 | 75 | #include "qemu/cutils.h" |
94a94e4c | 76 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 77 | #include "qmp-commands.h" |
68a27b20 | 78 | |
9fdf0c29 DG |
79 | #include <libfdt.h> |
80 | ||
4d8d5467 BH |
81 | /* SLOF memory layout: |
82 | * | |
83 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
84 | * device-tree, then position SLOF itself 31M below that | |
85 | * | |
86 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
87 | * and more | |
88 | * | |
89 | * We load our kernel at 4M, leaving space for SLOF initial image | |
90 | */ | |
38b02bd8 | 91 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 92 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 93 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
94 | #define FW_MAX_SIZE 0x400000 |
95 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
96 | #define FW_OVERHEAD 0x2800000 |
97 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 98 | |
4d8d5467 | 99 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 100 | |
0c103f8e DG |
101 | #define PHANDLE_XICP 0x00001111 |
102 | ||
71cd4dac CLG |
103 | static ICSState *spapr_ics_create(sPAPRMachineState *spapr, |
104 | const char *type_ics, | |
105 | int nr_irqs, Error **errp) | |
c04d6cfa | 106 | { |
175d2aa0 | 107 | Error *local_err = NULL; |
71cd4dac | 108 | Object *obj; |
4e4169f7 | 109 | |
71cd4dac | 110 | obj = object_new(type_ics); |
175d2aa0 | 111 | object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); |
ad265631 GK |
112 | object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), |
113 | &error_abort); | |
175d2aa0 GK |
114 | object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); |
115 | if (local_err) { | |
116 | goto error; | |
117 | } | |
71cd4dac | 118 | object_property_set_bool(obj, true, "realized", &local_err); |
175d2aa0 GK |
119 | if (local_err) { |
120 | goto error; | |
4e4169f7 | 121 | } |
4e4169f7 | 122 | |
71cd4dac | 123 | return ICS_SIMPLE(obj); |
175d2aa0 GK |
124 | |
125 | error: | |
126 | error_propagate(errp, local_err); | |
127 | return NULL; | |
c04d6cfa AL |
128 | } |
129 | ||
46f7afa3 GK |
130 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
131 | { | |
132 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
133 | * and newer QEMUs don't even have them. In both cases, we don't want | |
134 | * to send anything on the wire. | |
135 | */ | |
136 | return false; | |
137 | } | |
138 | ||
139 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
140 | .name = "icp/server", | |
141 | .version_id = 1, | |
142 | .minimum_version_id = 1, | |
143 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
144 | .fields = (VMStateField[]) { | |
145 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
146 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
147 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
148 | VMSTATE_END_OF_LIST() | |
149 | }, | |
150 | }; | |
151 | ||
152 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
153 | { | |
154 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
155 | (void *)(uintptr_t) i); | |
156 | } | |
157 | ||
158 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
159 | { | |
160 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
161 | (void *)(uintptr_t) i); | |
162 | } | |
163 | ||
164 | static inline int xics_max_server_number(void) | |
165 | { | |
166 | return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); | |
167 | } | |
168 | ||
71cd4dac | 169 | static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) |
c04d6cfa | 170 | { |
71cd4dac | 171 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
46f7afa3 | 172 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
c04d6cfa | 173 | |
11ad93f6 | 174 | if (kvm_enabled()) { |
2192a930 | 175 | if (machine_kernel_irqchip_allowed(machine) && |
71cd4dac CLG |
176 | !xics_kvm_init(spapr, errp)) { |
177 | spapr->icp_type = TYPE_KVM_ICP; | |
3d85885a | 178 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); |
11ad93f6 | 179 | } |
71cd4dac | 180 | if (machine_kernel_irqchip_required(machine) && !spapr->ics) { |
3d85885a GK |
181 | error_prepend(errp, "kernel_irqchip requested but unavailable: "); |
182 | return; | |
11ad93f6 DG |
183 | } |
184 | } | |
185 | ||
71cd4dac | 186 | if (!spapr->ics) { |
f63ebfe0 | 187 | xics_spapr_init(spapr); |
71cd4dac CLG |
188 | spapr->icp_type = TYPE_ICP; |
189 | spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); | |
3d85885a GK |
190 | if (!spapr->ics) { |
191 | return; | |
192 | } | |
c04d6cfa | 193 | } |
46f7afa3 GK |
194 | |
195 | if (smc->pre_2_10_has_unused_icps) { | |
196 | int i; | |
197 | ||
198 | for (i = 0; i < xics_max_server_number(); i++) { | |
199 | /* Dummy entries get deregistered when real ICPState objects | |
200 | * are registered during CPU core hotplug. | |
201 | */ | |
202 | pre_2_10_vmstate_register_dummy_icp(i); | |
203 | } | |
204 | } | |
c04d6cfa AL |
205 | } |
206 | ||
833d4668 AK |
207 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
208 | int smt_threads) | |
209 | { | |
210 | int i, ret = 0; | |
211 | uint32_t servers_prop[smt_threads]; | |
212 | uint32_t gservers_prop[smt_threads * 2]; | |
2e886fb3 | 213 | int index = spapr_vcpu_id(cpu); |
833d4668 | 214 | |
d6e166c0 DG |
215 | if (cpu->compat_pvr) { |
216 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
217 | if (ret < 0) { |
218 | return ret; | |
219 | } | |
220 | } | |
221 | ||
833d4668 AK |
222 | /* Build interrupt servers and gservers properties */ |
223 | for (i = 0; i < smt_threads; i++) { | |
224 | servers_prop[i] = cpu_to_be32(index + i); | |
225 | /* Hack, direct the group queues back to cpu 0 */ | |
226 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
227 | gservers_prop[i*2 + 1] = 0; | |
228 | } | |
229 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
230 | servers_prop, sizeof(servers_prop)); | |
231 | if (ret < 0) { | |
232 | return ret; | |
233 | } | |
234 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
235 | gservers_prop, sizeof(gservers_prop)); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
99861ecb | 240 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 241 | { |
2e886fb3 | 242 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
243 | uint32_t associativity[] = {cpu_to_be32(0x5), |
244 | cpu_to_be32(0x0), | |
245 | cpu_to_be32(0x0), | |
246 | cpu_to_be32(0x0), | |
15f8b142 | 247 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
248 | cpu_to_be32(index)}; |
249 | ||
250 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 251 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 252 | sizeof(associativity)); |
0da6f3fe BR |
253 | } |
254 | ||
86d5771a | 255 | /* Populate the "ibm,pa-features" property */ |
ee76a09f DG |
256 | static void spapr_populate_pa_features(sPAPRMachineState *spapr, |
257 | PowerPCCPU *cpu, | |
258 | void *fdt, int offset, | |
7abd43ba | 259 | bool legacy_guest) |
86d5771a | 260 | { |
7abd43ba | 261 | CPUPPCState *env = &cpu->env; |
86d5771a SB |
262 | uint8_t pa_features_206[] = { 6, 0, |
263 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
264 | uint8_t pa_features_207[] = { 24, 0, | |
265 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
266 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
267 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
268 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
269 | uint8_t pa_features_300[] = { 66, 0, |
270 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
271 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
272 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
273 | /* 6: DS207 */ | |
274 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
275 | /* 16: Vector */ | |
86d5771a | 276 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 277 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 278 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
279 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
280 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
281 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
282 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
283 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
284 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
285 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
286 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
287 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
288 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
289 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
290 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
291 | /* 60: NM atomic, 62: RNG */ | |
292 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
293 | }; | |
7abd43ba | 294 | uint8_t *pa_features = NULL; |
86d5771a SB |
295 | size_t pa_size; |
296 | ||
7abd43ba | 297 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
298 | pa_features = pa_features_206; |
299 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
300 | } |
301 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
302 | pa_features = pa_features_207; |
303 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
304 | } |
305 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
306 | pa_features = pa_features_300; |
307 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
308 | } |
309 | if (!pa_features) { | |
86d5771a SB |
310 | return; |
311 | } | |
312 | ||
313 | if (env->ci_large_pages) { | |
314 | /* | |
315 | * Note: we keep CI large pages off by default because a 64K capable | |
316 | * guest provisioned with large pages might otherwise try to map a qemu | |
317 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
318 | * even if that qemu runs on a 4k host. | |
319 | * We dd this bit back here if we are confident this is not an issue | |
320 | */ | |
321 | pa_features[3] |= 0x20; | |
322 | } | |
ee76a09f | 323 | if (spapr_has_cap(spapr, SPAPR_CAP_HTM) && pa_size > 24) { |
86d5771a SB |
324 | pa_features[24] |= 0x80; /* Transactional memory support */ |
325 | } | |
e957f6a9 SB |
326 | if (legacy_guest && pa_size > 40) { |
327 | /* Workaround for broken kernels that attempt (guest) radix | |
328 | * mode when they can't handle it, if they see the radix bit set | |
329 | * in pa-features. So hide it from them. */ | |
330 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
331 | } | |
86d5771a SB |
332 | |
333 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
334 | } | |
335 | ||
28e02042 | 336 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 337 | { |
82677ed2 AK |
338 | int ret = 0, offset, cpus_offset; |
339 | CPUState *cs; | |
6e806cc3 BR |
340 | char cpu_model[32]; |
341 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 342 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 343 | |
82677ed2 AK |
344 | CPU_FOREACH(cs) { |
345 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
346 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2e886fb3 | 347 | int index = spapr_vcpu_id(cpu); |
12dbeb16 | 348 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
6e806cc3 | 349 | |
0f20ba62 | 350 | if ((index % smt) != 0) { |
6e806cc3 BR |
351 | continue; |
352 | } | |
353 | ||
82677ed2 | 354 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 355 | |
82677ed2 AK |
356 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
357 | if (cpus_offset < 0) { | |
a4f3885c | 358 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
82677ed2 AK |
359 | if (cpus_offset < 0) { |
360 | return cpus_offset; | |
361 | } | |
362 | } | |
363 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 364 | if (offset < 0) { |
82677ed2 AK |
365 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
366 | if (offset < 0) { | |
367 | return offset; | |
368 | } | |
6e806cc3 BR |
369 | } |
370 | ||
7f763a5d DG |
371 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
372 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
373 | if (ret < 0) { |
374 | return ret; | |
375 | } | |
833d4668 | 376 | |
99861ecb IM |
377 | if (nb_numa_nodes > 1) { |
378 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
379 | if (ret < 0) { | |
380 | return ret; | |
381 | } | |
0da6f3fe BR |
382 | } |
383 | ||
12dbeb16 | 384 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
385 | if (ret < 0) { |
386 | return ret; | |
387 | } | |
e957f6a9 | 388 | |
ee76a09f DG |
389 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
390 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
391 | } |
392 | return ret; | |
393 | } | |
394 | ||
c86c1aff | 395 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a AK |
396 | { |
397 | if (nb_numa_nodes) { | |
398 | int i; | |
399 | for (i = 0; i < nb_numa_nodes; ++i) { | |
400 | if (numa_info[i].node_mem) { | |
fb164994 DG |
401 | return MIN(pow2floor(numa_info[i].node_mem), |
402 | machine->ram_size); | |
b082d65a AK |
403 | } |
404 | } | |
405 | } | |
fb164994 | 406 | return machine->ram_size; |
b082d65a AK |
407 | } |
408 | ||
a1d59c0f AK |
409 | static void add_str(GString *s, const gchar *s1) |
410 | { | |
411 | g_string_append_len(s, s1, strlen(s1) + 1); | |
412 | } | |
7f763a5d | 413 | |
03d196b7 | 414 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
415 | hwaddr size) |
416 | { | |
417 | uint32_t associativity[] = { | |
418 | cpu_to_be32(0x4), /* length */ | |
419 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 420 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
421 | }; |
422 | char mem_name[32]; | |
423 | uint64_t mem_reg_property[2]; | |
424 | int off; | |
425 | ||
426 | mem_reg_property[0] = cpu_to_be64(start); | |
427 | mem_reg_property[1] = cpu_to_be64(size); | |
428 | ||
429 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
430 | off = fdt_add_subnode(fdt, 0, mem_name); | |
431 | _FDT(off); | |
432 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
433 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
434 | sizeof(mem_reg_property)))); | |
435 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
436 | sizeof(associativity)))); | |
03d196b7 | 437 | return off; |
26a8c353 AK |
438 | } |
439 | ||
28e02042 | 440 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 441 | { |
fb164994 | 442 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
443 | hwaddr mem_start, node_size; |
444 | int i, nb_nodes = nb_numa_nodes; | |
445 | NodeInfo *nodes = numa_info; | |
446 | NodeInfo ramnode; | |
447 | ||
448 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
449 | if (!nb_numa_nodes) { | |
450 | nb_nodes = 1; | |
fb164994 | 451 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 452 | nodes = &ramnode; |
5fe269b1 | 453 | } |
7f763a5d | 454 | |
7db8a127 AK |
455 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
456 | if (!nodes[i].node_mem) { | |
457 | continue; | |
458 | } | |
fb164994 | 459 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
460 | node_size = 0; |
461 | } else { | |
7db8a127 | 462 | node_size = nodes[i].node_mem; |
fb164994 DG |
463 | if (node_size > machine->ram_size - mem_start) { |
464 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
465 | } |
466 | } | |
7db8a127 AK |
467 | if (!mem_start) { |
468 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 469 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
470 | mem_start += spapr->rma_size; |
471 | node_size -= spapr->rma_size; | |
472 | } | |
6010818c AK |
473 | for ( ; node_size; ) { |
474 | hwaddr sizetmp = pow2floor(node_size); | |
475 | ||
476 | /* mem_start != 0 here */ | |
477 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
478 | sizetmp = 1ULL << ctzl(mem_start); | |
479 | } | |
480 | ||
481 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
482 | node_size -= sizetmp; | |
483 | mem_start += sizetmp; | |
484 | } | |
7f763a5d DG |
485 | } |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
0da6f3fe BR |
490 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
491 | sPAPRMachineState *spapr) | |
492 | { | |
493 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
494 | CPUPPCState *env = &cpu->env; | |
495 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
2e886fb3 | 496 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
497 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
498 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
499 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
500 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
501 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
502 | uint32_t page_sizes_prop[64]; | |
503 | size_t page_sizes_prop_size; | |
22419c2a | 504 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 505 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
12dbeb16 | 506 | int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); |
af81cf32 | 507 | sPAPRDRConnector *drc; |
af81cf32 | 508 | int drc_index; |
c64abd1f SB |
509 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
510 | int i; | |
af81cf32 | 511 | |
fbf55397 | 512 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 513 | if (drc) { |
0b55aa91 | 514 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
515 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
516 | } | |
0da6f3fe BR |
517 | |
518 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
519 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
520 | ||
521 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
522 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
523 | env->dcache_line_size))); | |
524 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
525 | env->dcache_line_size))); | |
526 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
527 | env->icache_line_size))); | |
528 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
529 | env->icache_line_size))); | |
530 | ||
531 | if (pcc->l1_dcache_size) { | |
532 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
533 | pcc->l1_dcache_size))); | |
534 | } else { | |
3dc6f869 | 535 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
536 | } |
537 | if (pcc->l1_icache_size) { | |
538 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
539 | pcc->l1_icache_size))); | |
540 | } else { | |
3dc6f869 | 541 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
542 | } |
543 | ||
544 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
545 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 546 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
547 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
548 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
549 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
550 | ||
551 | if (env->spr_cb[SPR_PURR].oea_read) { | |
552 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
553 | } | |
554 | ||
555 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
556 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
557 | segs, sizeof(segs)))); | |
558 | } | |
559 | ||
560 | /* Advertise VMX/VSX (vector extensions) if available | |
561 | * 0 / no property == no vector extensions | |
562 | * 1 == VMX / Altivec available | |
563 | * 2 == VSX available */ | |
564 | if (env->insns_flags & PPC_ALTIVEC) { | |
565 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
566 | ||
567 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
568 | } | |
569 | ||
570 | /* Advertise DFP (Decimal Floating Point) if available | |
571 | * 0 / no property == no DFP | |
572 | * 1 == DFP available */ | |
573 | if (env->insns_flags2 & PPC2_DFP) { | |
574 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
575 | } | |
576 | ||
3654fa95 | 577 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
578 | sizeof(page_sizes_prop)); |
579 | if (page_sizes_prop_size) { | |
580 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
581 | page_sizes_prop, page_sizes_prop_size))); | |
582 | } | |
583 | ||
ee76a09f | 584 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
90da0d5a | 585 | |
0da6f3fe | 586 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 587 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
588 | |
589 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
590 | pft_size_prop, sizeof(pft_size_prop)))); | |
591 | ||
99861ecb IM |
592 | if (nb_numa_nodes > 1) { |
593 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
594 | } | |
0da6f3fe | 595 | |
12dbeb16 | 596 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
597 | |
598 | if (pcc->radix_page_info) { | |
599 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
600 | radix_AP_encodings[i] = | |
601 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
602 | } | |
603 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
604 | radix_AP_encodings, | |
605 | pcc->radix_page_info->count * | |
606 | sizeof(radix_AP_encodings[0])))); | |
607 | } | |
0da6f3fe BR |
608 | } |
609 | ||
610 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
611 | { | |
612 | CPUState *cs; | |
613 | int cpus_offset; | |
614 | char *nodename; | |
615 | int smt = kvmppc_smt_threads(); | |
616 | ||
617 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
618 | _FDT(cpus_offset); | |
619 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
620 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
621 | ||
622 | /* | |
623 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
624 | * created by fdt_add_subnode() end up in the right order in FDT | |
625 | * for the guest kernel the enumerate the CPUs correctly. | |
626 | */ | |
627 | CPU_FOREACH_REVERSE(cs) { | |
628 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2e886fb3 | 629 | int index = spapr_vcpu_id(cpu); |
0da6f3fe BR |
630 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
631 | int offset; | |
632 | ||
633 | if ((index % smt) != 0) { | |
634 | continue; | |
635 | } | |
636 | ||
637 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
638 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
639 | g_free(nodename); | |
640 | _FDT(offset); | |
641 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
642 | } | |
643 | ||
644 | } | |
645 | ||
f47bd1c8 IM |
646 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
647 | { | |
648 | MemoryDeviceInfoList *info; | |
649 | ||
650 | for (info = list; info; info = info->next) { | |
651 | MemoryDeviceInfo *value = info->value; | |
652 | ||
653 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
654 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
655 | ||
656 | if (pcdimm_info->addr >= addr && | |
657 | addr < (pcdimm_info->addr + pcdimm_info->size)) { | |
658 | return pcdimm_info->node; | |
659 | } | |
660 | } | |
661 | } | |
662 | ||
663 | return -1; | |
664 | } | |
665 | ||
03d196b7 BR |
666 | /* |
667 | * Adds ibm,dynamic-reconfiguration-memory node. | |
668 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
669 | * of this device tree node. | |
670 | */ | |
671 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
672 | { | |
673 | MachineState *machine = MACHINE(spapr); | |
674 | int ret, i, offset; | |
675 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
676 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
677 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
678 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
679 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
680 | lmb_size; | |
03d196b7 | 681 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 682 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
f47bd1c8 | 683 | MemoryDeviceInfoList *dimms = NULL; |
03d196b7 | 684 | |
16c25aef | 685 | /* |
d0e5a8f2 | 686 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 687 | */ |
d0e5a8f2 | 688 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
689 | return 0; |
690 | } | |
691 | ||
ef001f06 TH |
692 | /* |
693 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
694 | * or ibm,associativity-lookup-arrays | |
695 | */ | |
696 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
697 | * sizeof(uint32_t); | |
03d196b7 BR |
698 | cur_index = int_buf = g_malloc0(buf_len); |
699 | ||
700 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
701 | ||
702 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
703 | sizeof(prop_lmb_size)); | |
704 | if (ret < 0) { | |
705 | goto out; | |
706 | } | |
707 | ||
708 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
709 | if (ret < 0) { | |
710 | goto out; | |
711 | } | |
712 | ||
713 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
714 | if (ret < 0) { | |
715 | goto out; | |
716 | } | |
717 | ||
f47bd1c8 IM |
718 | if (hotplug_lmb_start) { |
719 | MemoryDeviceInfoList **prev = &dimms; | |
720 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
721 | } | |
722 | ||
03d196b7 BR |
723 | /* ibm,dynamic-memory */ |
724 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
725 | cur_index++; | |
726 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 727 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
728 | uint32_t *dynamic_memory = cur_index; |
729 | ||
d0e5a8f2 BR |
730 | if (i >= hotplug_lmb_start) { |
731 | sPAPRDRConnector *drc; | |
d0e5a8f2 | 732 | |
fbf55397 | 733 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 734 | g_assert(drc); |
d0e5a8f2 BR |
735 | |
736 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
737 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 738 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 739 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 740 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
741 | if (memory_region_present(get_system_memory(), addr)) { |
742 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
743 | } else { | |
744 | dynamic_memory[5] = cpu_to_be32(0); | |
745 | } | |
03d196b7 | 746 | } else { |
d0e5a8f2 BR |
747 | /* |
748 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
749 | * hotplug memory region -- all these are marked as reserved | |
750 | * and as having no valid DRC. | |
751 | */ | |
752 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
753 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
754 | dynamic_memory[2] = cpu_to_be32(0); | |
755 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
756 | dynamic_memory[4] = cpu_to_be32(-1); | |
757 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
758 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
759 | } |
760 | ||
761 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
762 | } | |
f47bd1c8 | 763 | qapi_free_MemoryDeviceInfoList(dimms); |
03d196b7 BR |
764 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); |
765 | if (ret < 0) { | |
766 | goto out; | |
767 | } | |
768 | ||
769 | /* ibm,associativity-lookup-arrays */ | |
770 | cur_index = int_buf; | |
6663864e | 771 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
772 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
773 | cur_index += 2; | |
6663864e | 774 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
775 | uint32_t associativity[] = { |
776 | cpu_to_be32(0x0), | |
777 | cpu_to_be32(0x0), | |
778 | cpu_to_be32(0x0), | |
779 | cpu_to_be32(i) | |
780 | }; | |
781 | memcpy(cur_index, associativity, sizeof(associativity)); | |
782 | cur_index += 4; | |
783 | } | |
784 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
785 | (cur_index - int_buf) * sizeof(uint32_t)); | |
786 | out: | |
787 | g_free(int_buf); | |
788 | return ret; | |
789 | } | |
790 | ||
6787d27b MR |
791 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
792 | sPAPROptionVector *ov5_updates) | |
793 | { | |
794 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 795 | int ret = 0, offset; |
6787d27b MR |
796 | |
797 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
798 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
799 | g_assert(smc->dr_lmb_enabled); | |
800 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
801 | if (ret) { |
802 | goto out; | |
803 | } | |
6787d27b MR |
804 | } |
805 | ||
417ece33 MR |
806 | offset = fdt_path_offset(fdt, "/chosen"); |
807 | if (offset < 0) { | |
808 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
809 | if (offset < 0) { | |
810 | return offset; | |
811 | } | |
812 | } | |
813 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
814 | "ibm,architecture-vec-5"); | |
815 | ||
816 | out: | |
6787d27b MR |
817 | return ret; |
818 | } | |
819 | ||
10f12e64 DHB |
820 | static bool spapr_hotplugged_dev_before_cas(void) |
821 | { | |
822 | Object *drc_container, *obj; | |
823 | ObjectProperty *prop; | |
824 | ObjectPropertyIterator iter; | |
825 | ||
826 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
827 | object_property_iter_init(&iter, drc_container); | |
828 | while ((prop = object_property_iter_next(&iter))) { | |
829 | if (!strstart(prop->type, "link<", NULL)) { | |
830 | continue; | |
831 | } | |
832 | obj = object_property_get_link(drc_container, prop->name, NULL); | |
833 | if (spapr_drc_needed(obj)) { | |
834 | return true; | |
835 | } | |
836 | } | |
837 | return false; | |
838 | } | |
839 | ||
03d196b7 BR |
840 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
841 | target_ulong addr, target_ulong size, | |
6787d27b | 842 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
843 | { |
844 | void *fdt, *fdt_skel; | |
845 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 | 846 | |
10f12e64 DHB |
847 | if (spapr_hotplugged_dev_before_cas()) { |
848 | return 1; | |
849 | } | |
850 | ||
827b17c4 GK |
851 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
852 | error_report("SLOF provided an unexpected CAS buffer size " | |
853 | TARGET_FMT_lu " (min: %zu, max: %u)", | |
854 | size, sizeof(hdr), FW_MAX_SIZE); | |
855 | exit(EXIT_FAILURE); | |
856 | } | |
857 | ||
03d196b7 BR |
858 | size -= sizeof(hdr); |
859 | ||
10f12e64 | 860 | /* Create skeleton */ |
03d196b7 BR |
861 | fdt_skel = g_malloc0(size); |
862 | _FDT((fdt_create(fdt_skel, size))); | |
863 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
864 | _FDT((fdt_end_node(fdt_skel))); | |
865 | _FDT((fdt_finish(fdt_skel))); | |
866 | fdt = g_malloc0(size); | |
867 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
868 | g_free(fdt_skel); | |
869 | ||
870 | /* Fixup cpu nodes */ | |
5b120785 | 871 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 872 | |
6787d27b MR |
873 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
874 | return -1; | |
03d196b7 BR |
875 | } |
876 | ||
877 | /* Pack resulting tree */ | |
878 | _FDT((fdt_pack(fdt))); | |
879 | ||
880 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
881 | trace_spapr_cas_failed(size); | |
882 | return -1; | |
883 | } | |
884 | ||
885 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
886 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
887 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
888 | g_free(fdt); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
3f5dabce DG |
893 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
894 | { | |
895 | int rtas; | |
896 | GString *hypertas = g_string_sized_new(256); | |
897 | GString *qemu_hypertas = g_string_sized_new(256); | |
898 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
899 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
900 | memory_region_size(&spapr->hotplug_memory.mr); | |
901 | uint32_t lrdr_capacity[] = { | |
902 | cpu_to_be32(max_hotplug_addr >> 32), | |
903 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
904 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
905 | cpu_to_be32(max_cpus / smp_threads), | |
906 | }; | |
907 | ||
908 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
909 | ||
910 | /* hypertas */ | |
911 | add_str(hypertas, "hcall-pft"); | |
912 | add_str(hypertas, "hcall-term"); | |
913 | add_str(hypertas, "hcall-dabr"); | |
914 | add_str(hypertas, "hcall-interrupt"); | |
915 | add_str(hypertas, "hcall-tce"); | |
916 | add_str(hypertas, "hcall-vio"); | |
917 | add_str(hypertas, "hcall-splpar"); | |
918 | add_str(hypertas, "hcall-bulk"); | |
919 | add_str(hypertas, "hcall-set-mode"); | |
920 | add_str(hypertas, "hcall-sprg0"); | |
921 | add_str(hypertas, "hcall-copy"); | |
922 | add_str(hypertas, "hcall-debug"); | |
923 | add_str(qemu_hypertas, "hcall-memop1"); | |
924 | ||
925 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
926 | add_str(hypertas, "hcall-multi-tce"); | |
927 | } | |
30f4b05b DG |
928 | |
929 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
930 | add_str(hypertas, "hcall-hpt-resize"); | |
931 | } | |
932 | ||
3f5dabce DG |
933 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
934 | hypertas->str, hypertas->len)); | |
935 | g_string_free(hypertas, TRUE); | |
936 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
937 | qemu_hypertas->str, qemu_hypertas->len)); | |
938 | g_string_free(qemu_hypertas, TRUE); | |
939 | ||
940 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
941 | refpoints, sizeof(refpoints))); | |
942 | ||
943 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
944 | RTAS_ERROR_LOG_MAX)); | |
945 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
946 | RTAS_EVENT_SCAN_RATE)); | |
947 | ||
4f441474 DG |
948 | g_assert(msi_nonbroken); |
949 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
950 | |
951 | /* | |
952 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
953 | * back to the guest cpu. | |
954 | * | |
955 | * While an additional ibm,extended-os-term property indicates | |
956 | * that rtas call return will always occur. Set this property. | |
957 | */ | |
958 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
959 | ||
960 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
961 | lrdr_capacity, sizeof(lrdr_capacity))); | |
962 | ||
963 | spapr_dt_rtas_tokens(fdt, rtas); | |
964 | } | |
965 | ||
9fb4541f SB |
966 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
967 | * that the guest may request and thus the valid values for bytes 24..26 of | |
968 | * option vector 5: */ | |
969 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
970 | { | |
545d6e2b SJS |
971 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
972 | ||
f2b14e3a | 973 | char val[2 * 4] = { |
21f3f8db | 974 | 23, 0x00, /* Xive mode, filled in below. */ |
9fb4541f SB |
975 | 24, 0x00, /* Hash/Radix, filled in below. */ |
976 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
977 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
978 | }; | |
979 | ||
7abd43ba SJS |
980 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
981 | first_ppc_cpu->compat_pvr)) { | |
982 | /* If we're in a pre POWER9 compat mode then the guest should do hash */ | |
983 | val[3] = 0x00; /* Hash */ | |
984 | } else if (kvm_enabled()) { | |
9fb4541f | 985 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 986 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 987 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 988 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 989 | } else { |
f2b14e3a | 990 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
991 | } |
992 | } else { | |
7abd43ba SJS |
993 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
994 | val[3] = 0xC0; | |
9fb4541f SB |
995 | } |
996 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
997 | val, sizeof(val))); | |
998 | } | |
999 | ||
7c866c6a DG |
1000 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
1001 | { | |
1002 | MachineState *machine = MACHINE(spapr); | |
1003 | int chosen; | |
1004 | const char *boot_device = machine->boot_order; | |
1005 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1006 | size_t cb = 0; | |
1007 | char *bootlist = get_boot_devices_list(&cb, true); | |
7c866c6a DG |
1008 | |
1009 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1010 | ||
7c866c6a DG |
1011 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
1012 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1013 | spapr->initrd_base)); | |
1014 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1015 | spapr->initrd_base + spapr->initrd_size)); | |
1016 | ||
1017 | if (spapr->kernel_size) { | |
1018 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
1019 | cpu_to_be64(spapr->kernel_size) }; | |
1020 | ||
1021 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
1022 | &kprop, sizeof(kprop))); | |
1023 | if (spapr->kernel_le) { | |
1024 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1025 | } | |
1026 | } | |
1027 | if (boot_menu) { | |
1028 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1029 | } | |
1030 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1031 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1032 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
1033 | ||
1034 | if (cb && bootlist) { | |
1035 | int i; | |
1036 | ||
1037 | for (i = 0; i < cb; i++) { | |
1038 | if (bootlist[i] == '\n') { | |
1039 | bootlist[i] = ' '; | |
1040 | } | |
1041 | } | |
1042 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
1043 | } | |
1044 | ||
1045 | if (boot_device && strlen(boot_device)) { | |
1046 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1047 | } | |
1048 | ||
1049 | if (!spapr->has_graphics && stdout_path) { | |
1050 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
1051 | } | |
1052 | ||
9fb4541f SB |
1053 | spapr_dt_ov5_platform_support(fdt, chosen); |
1054 | ||
7c866c6a DG |
1055 | g_free(stdout_path); |
1056 | g_free(bootlist); | |
1057 | } | |
1058 | ||
fca5f2dc DG |
1059 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1060 | { | |
1061 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1062 | * KVM to work under pHyp with some guest co-operation */ | |
1063 | int hypervisor; | |
1064 | uint8_t hypercall[16]; | |
1065 | ||
1066 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1067 | /* indicate KVM hypercall interface */ | |
1068 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1069 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1070 | /* | |
1071 | * Older KVM versions with older guest kernels were broken | |
1072 | * with the magic page, don't allow the guest to map it. | |
1073 | */ | |
1074 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1075 | sizeof(hypercall))) { | |
1076 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1077 | hypercall, sizeof(hypercall))); | |
1078 | } | |
1079 | } | |
1080 | } | |
1081 | ||
997b6cfc DG |
1082 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1083 | hwaddr rtas_addr, | |
1084 | hwaddr rtas_size) | |
a3467baa | 1085 | { |
c86c1aff | 1086 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1087 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1088 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1089 | int ret; |
a3467baa | 1090 | void *fdt; |
3384f95c | 1091 | sPAPRPHBState *phb; |
398a0bd5 | 1092 | char *buf; |
a3467baa | 1093 | |
398a0bd5 DG |
1094 | fdt = g_malloc0(FDT_MAX_SIZE); |
1095 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1096 | |
398a0bd5 DG |
1097 | /* Root node */ |
1098 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1099 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1100 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1101 | ||
1102 | /* | |
1103 | * Add info to guest to indentify which host is it being run on | |
1104 | * and what is the uuid of the guest | |
1105 | */ | |
1106 | if (kvmppc_get_host_model(&buf)) { | |
1107 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1108 | g_free(buf); | |
1109 | } | |
1110 | if (kvmppc_get_host_serial(&buf)) { | |
1111 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1112 | g_free(buf); | |
1113 | } | |
1114 | ||
1115 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1116 | ||
1117 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1118 | if (qemu_uuid_set) { | |
1119 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1120 | } | |
1121 | g_free(buf); | |
1122 | ||
1123 | if (qemu_get_vm_name()) { | |
1124 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1125 | qemu_get_vm_name())); | |
1126 | } | |
1127 | ||
1128 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1129 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1130 | |
fc7e0765 DG |
1131 | /* /interrupt controller */ |
1132 | spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); | |
1133 | ||
e8f986fc BR |
1134 | ret = spapr_populate_memory(spapr, fdt); |
1135 | if (ret < 0) { | |
ce9863b7 | 1136 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1137 | exit(1); |
7f763a5d DG |
1138 | } |
1139 | ||
bf5a6696 DG |
1140 | /* /vdevice */ |
1141 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1142 | |
4d9392be TH |
1143 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1144 | ret = spapr_rng_populate_dt(fdt); | |
1145 | if (ret < 0) { | |
ce9863b7 | 1146 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1147 | exit(1); |
1148 | } | |
1149 | } | |
1150 | ||
3384f95c | 1151 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 1152 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
1153 | if (ret < 0) { |
1154 | error_report("couldn't setup PCI devices in fdt"); | |
1155 | exit(1); | |
1156 | } | |
3384f95c DG |
1157 | } |
1158 | ||
0da6f3fe BR |
1159 | /* cpus */ |
1160 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1161 | |
c20d332a BR |
1162 | if (smc->dr_lmb_enabled) { |
1163 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1164 | } | |
1165 | ||
c5514d0e | 1166 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1167 | int offset = fdt_path_offset(fdt, "/cpus"); |
1168 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1169 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1170 | if (ret < 0) { | |
1171 | error_report("Couldn't set up CPU DR device tree properties"); | |
1172 | exit(1); | |
1173 | } | |
1174 | } | |
1175 | ||
ffb1e275 | 1176 | /* /event-sources */ |
ffbb1705 | 1177 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1178 | |
3f5dabce DG |
1179 | /* /rtas */ |
1180 | spapr_dt_rtas(spapr, fdt); | |
1181 | ||
7c866c6a DG |
1182 | /* /chosen */ |
1183 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1184 | |
fca5f2dc DG |
1185 | /* /hypervisor */ |
1186 | if (kvm_enabled()) { | |
1187 | spapr_dt_hypervisor(spapr, fdt); | |
1188 | } | |
1189 | ||
cf6e5223 DG |
1190 | /* Build memory reserve map */ |
1191 | if (spapr->kernel_size) { | |
1192 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1193 | } | |
1194 | if (spapr->initrd_size) { | |
1195 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1196 | } | |
1197 | ||
6787d27b MR |
1198 | /* ibm,client-architecture-support updates */ |
1199 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1200 | if (ret < 0) { | |
1201 | error_report("couldn't setup CAS properties fdt"); | |
1202 | exit(1); | |
1203 | } | |
1204 | ||
997b6cfc | 1205 | return fdt; |
9fdf0c29 DG |
1206 | } |
1207 | ||
1208 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1209 | { | |
1210 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1211 | } | |
1212 | ||
1d1be34d DG |
1213 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1214 | PowerPCCPU *cpu) | |
9fdf0c29 | 1215 | { |
1b14670a AF |
1216 | CPUPPCState *env = &cpu->env; |
1217 | ||
8d04fb55 JK |
1218 | /* The TCG path should also be holding the BQL at this point */ |
1219 | g_assert(qemu_mutex_iothread_locked()); | |
1220 | ||
efcb9383 DG |
1221 | if (msr_pr) { |
1222 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1223 | env->gpr[3] = H_PRIVILEGE; | |
1224 | } else { | |
aa100fa4 | 1225 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1226 | } |
9fdf0c29 DG |
1227 | } |
1228 | ||
9861bb3e SJS |
1229 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1230 | { | |
1231 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1232 | ||
1233 | return spapr->patb_entry; | |
1234 | } | |
1235 | ||
e6b8fd24 SMJ |
1236 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1237 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1238 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1239 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1240 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1241 | ||
715c5407 DG |
1242 | /* |
1243 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1244 | */ | |
1245 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1246 | { | |
14b0d748 GK |
1247 | Error *local_err = NULL; |
1248 | ||
715c5407 DG |
1249 | if (spapr->htab_fd >= 0) { |
1250 | return spapr->htab_fd; | |
1251 | } | |
1252 | ||
14b0d748 | 1253 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1254 | if (spapr->htab_fd < 0) { |
14b0d748 | 1255 | error_report_err(local_err); |
715c5407 DG |
1256 | } |
1257 | ||
1258 | return spapr->htab_fd; | |
1259 | } | |
1260 | ||
b4db5413 | 1261 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1262 | { |
1263 | if (spapr->htab_fd >= 0) { | |
1264 | close(spapr->htab_fd); | |
1265 | } | |
1266 | spapr->htab_fd = -1; | |
1267 | } | |
1268 | ||
e57ca75c DG |
1269 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1270 | { | |
1271 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1272 | ||
1273 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1274 | } | |
1275 | ||
1ec26c75 GK |
1276 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1277 | { | |
1278 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1279 | ||
1280 | assert(kvm_enabled()); | |
1281 | ||
1282 | if (!spapr->htab) { | |
1283 | return 0; | |
1284 | } | |
1285 | ||
1286 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1287 | } | |
1288 | ||
e57ca75c DG |
1289 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1290 | hwaddr ptex, int n) | |
1291 | { | |
1292 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1293 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1294 | ||
1295 | if (!spapr->htab) { | |
1296 | /* | |
1297 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1298 | */ | |
1299 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1300 | kvmppc_read_hptes(hptes, ptex, n); | |
1301 | return hptes; | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * HTAB is controlled by QEMU. Just point to the internally | |
1306 | * accessible PTEG. | |
1307 | */ | |
1308 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1309 | } | |
1310 | ||
1311 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1312 | const ppc_hash_pte64_t *hptes, | |
1313 | hwaddr ptex, int n) | |
1314 | { | |
1315 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1316 | ||
1317 | if (!spapr->htab) { | |
1318 | g_free((void *)hptes); | |
1319 | } | |
1320 | ||
1321 | /* Nothing to do for qemu managed HPT */ | |
1322 | } | |
1323 | ||
1324 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1325 | uint64_t pte0, uint64_t pte1) | |
1326 | { | |
1327 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1328 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1329 | ||
1330 | if (!spapr->htab) { | |
1331 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1332 | } else { | |
1333 | stq_p(spapr->htab + offset, pte0); | |
1334 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1335 | } | |
1336 | } | |
1337 | ||
0b0b8310 | 1338 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1339 | { |
1340 | int shift; | |
1341 | ||
1342 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1343 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1344 | * that's much more than is needed for Linux guests */ | |
1345 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1346 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1347 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1348 | return shift; | |
1349 | } | |
1350 | ||
06ec79e8 BR |
1351 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1352 | { | |
1353 | g_free(spapr->htab); | |
1354 | spapr->htab = NULL; | |
1355 | spapr->htab_shift = 0; | |
1356 | close_htab_fd(spapr); | |
1357 | } | |
1358 | ||
2772cf6b DG |
1359 | void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1360 | Error **errp) | |
7f763a5d | 1361 | { |
c5f54f3e DG |
1362 | long rc; |
1363 | ||
1364 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1365 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1366 | |
1367 | rc = kvmppc_reset_htab(shift); | |
1368 | if (rc < 0) { | |
1369 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1370 | error_setg_errno(errp, errno, | |
1371 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1372 | shift); | |
1373 | /* This is almost certainly fatal, but if the caller really | |
1374 | * wants to carry on with shift == 0, it's welcome to try */ | |
1375 | } else if (rc > 0) { | |
1376 | /* kernel-side HPT allocated */ | |
1377 | if (rc != shift) { | |
1378 | error_setg(errp, | |
1379 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1380 | shift, rc); | |
7735feda BR |
1381 | } |
1382 | ||
7f763a5d | 1383 | spapr->htab_shift = shift; |
c18ad9a5 | 1384 | spapr->htab = NULL; |
b817772a | 1385 | } else { |
c5f54f3e DG |
1386 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1387 | size_t size = 1ULL << shift; | |
1388 | int i; | |
b817772a | 1389 | |
c5f54f3e DG |
1390 | spapr->htab = qemu_memalign(size, size); |
1391 | if (!spapr->htab) { | |
1392 | error_setg_errno(errp, errno, | |
1393 | "Could not allocate HPT of order %d", shift); | |
1394 | return; | |
7735feda BR |
1395 | } |
1396 | ||
c5f54f3e DG |
1397 | memset(spapr->htab, 0, size); |
1398 | spapr->htab_shift = shift; | |
e6b8fd24 | 1399 | |
c5f54f3e DG |
1400 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1401 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1402 | } |
7f763a5d | 1403 | } |
ee4d9ecc SJS |
1404 | /* We're setting up a hash table, so that means we're not radix */ |
1405 | spapr->patb_entry = 0; | |
9fdf0c29 DG |
1406 | } |
1407 | ||
b4db5413 SJS |
1408 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1409 | { | |
2772cf6b DG |
1410 | int hpt_shift; |
1411 | ||
1412 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) | |
1413 | || (spapr->cas_reboot | |
1414 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { | |
1415 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1416 | } else { | |
768a20f3 DG |
1417 | uint64_t current_ram_size; |
1418 | ||
1419 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1420 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1421 | } |
1422 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1423 | ||
b4db5413 | 1424 | if (spapr->vrma_adjust) { |
c86c1aff | 1425 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
b4db5413 SJS |
1426 | spapr->htab_shift); |
1427 | } | |
b4db5413 SJS |
1428 | } |
1429 | ||
4f01a637 | 1430 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1431 | { |
1432 | bool matched = false; | |
1433 | ||
1434 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1435 | matched = true; | |
1436 | } | |
1437 | ||
1438 | if (!matched) { | |
1439 | error_report("Device %s is not supported by this machine yet.", | |
1440 | qdev_fw_name(DEVICE(sbdev))); | |
1441 | exit(1); | |
1442 | } | |
9e3f9733 AG |
1443 | } |
1444 | ||
82512483 GK |
1445 | static int spapr_reset_drcs(Object *child, void *opaque) |
1446 | { | |
1447 | sPAPRDRConnector *drc = | |
1448 | (sPAPRDRConnector *) object_dynamic_cast(child, | |
1449 | TYPE_SPAPR_DR_CONNECTOR); | |
1450 | ||
1451 | if (drc) { | |
1452 | spapr_drc_reset(drc); | |
1453 | } | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
bcb5ce08 | 1458 | static void spapr_machine_reset(void) |
a3467baa | 1459 | { |
c5f54f3e DG |
1460 | MachineState *machine = MACHINE(qdev_get_machine()); |
1461 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1462 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1463 | uint32_t rtas_limit; |
cae172ab | 1464 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1465 | void *fdt; |
1466 | int rc; | |
259186a7 | 1467 | |
9e3f9733 AG |
1468 | /* Check for unknown sysbus devices */ |
1469 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1470 | ||
33face6b DG |
1471 | spapr_caps_reset(spapr); |
1472 | ||
1481fe5f LV |
1473 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1474 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
1475 | ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, | |
1476 | spapr->max_compat_pvr)) { | |
b4db5413 SJS |
1477 | /* If using KVM with radix mode available, VCPUs can be started |
1478 | * without a HPT because KVM will start them in radix mode. | |
1479 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1480 | spapr->patb_entry = PATBE1_GR; | |
1481 | } else { | |
b4db5413 | 1482 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1483 | } |
a3467baa | 1484 | |
c8787ad4 | 1485 | qemu_devices_reset(); |
82512483 GK |
1486 | |
1487 | /* DRC reset may cause a device to be unplugged. This will cause troubles | |
1488 | * if this device is used by another device (eg, a running vhost backend | |
1489 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1490 | * situations, we reset DRCs after all devices have been reset. | |
1491 | */ | |
1492 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1493 | ||
56258174 | 1494 | spapr_clear_pending_events(spapr); |
a3467baa | 1495 | |
b7d1f77a BH |
1496 | /* |
1497 | * We place the device tree and RTAS just below either the top of the RMA, | |
1498 | * or just below 2GB, whichever is lowere, so that it can be | |
1499 | * processed with 32-bit real mode code if necessary | |
1500 | */ | |
1501 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1502 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1503 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1504 | |
6787d27b MR |
1505 | /* if this reset wasn't generated by CAS, we should reset our |
1506 | * negotiated options and start from scratch */ | |
1507 | if (!spapr->cas_reboot) { | |
1508 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1509 | spapr->ov5_cas = spapr_ovec_new(); | |
66d5c492 | 1510 | |
51f84465 | 1511 | ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); |
6787d27b MR |
1512 | } |
1513 | ||
cae172ab | 1514 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1515 | |
2cac78c1 | 1516 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1517 | |
997b6cfc DG |
1518 | rc = fdt_pack(fdt); |
1519 | ||
1520 | /* Should only fail if we've built a corrupted tree */ | |
1521 | assert(rc == 0); | |
1522 | ||
1523 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1524 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1525 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1526 | exit(1); | |
1527 | } | |
1528 | ||
1529 | /* Load the fdt */ | |
1530 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1531 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1532 | g_free(fdt); |
1533 | ||
a3467baa | 1534 | /* Set up the entry state */ |
cae172ab | 1535 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1536 | first_ppc_cpu->env.gpr[5] = 0; |
1537 | first_cpu->halted = 0; | |
1b718907 | 1538 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa | 1539 | |
6787d27b | 1540 | spapr->cas_reboot = false; |
a3467baa DG |
1541 | } |
1542 | ||
28e02042 | 1543 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1544 | { |
2ff3de68 | 1545 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1546 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1547 | |
3978b863 | 1548 | if (dinfo) { |
6231a6da MA |
1549 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1550 | &error_fatal); | |
639e8102 DG |
1551 | } |
1552 | ||
1553 | qdev_init_nofail(dev); | |
1554 | ||
1555 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1556 | } | |
1557 | ||
28e02042 | 1558 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1559 | { |
147ff807 CLG |
1560 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1561 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1562 | &error_fatal); | |
1563 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1564 | &error_fatal); | |
1565 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1566 | "date", &error_fatal); | |
28df36a1 DG |
1567 | } |
1568 | ||
8c57b867 | 1569 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1570 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1571 | { |
8c57b867 | 1572 | switch (vga_interface_type) { |
8c57b867 | 1573 | case VGA_NONE: |
7effdaa3 MW |
1574 | return false; |
1575 | case VGA_DEVICE: | |
1576 | return true; | |
1ddcae82 | 1577 | case VGA_STD: |
b798c190 | 1578 | case VGA_VIRTIO: |
1ddcae82 | 1579 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1580 | default: |
14c6a894 DG |
1581 | error_setg(errp, |
1582 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1583 | return false; | |
f28359d8 | 1584 | } |
f28359d8 LZ |
1585 | } |
1586 | ||
880ae7de DG |
1587 | static int spapr_post_load(void *opaque, int version_id) |
1588 | { | |
28e02042 | 1589 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1590 | int err = 0; |
1591 | ||
a7ff1212 | 1592 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1593 | CPUState *cs; |
1594 | CPU_FOREACH(cs) { | |
1595 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1596 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1597 | } |
1598 | } | |
1599 | ||
631b22ea | 1600 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1601 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1602 | * So when migrating from those versions, poke the incoming offset | |
1603 | * value into the RTC device */ | |
1604 | if (version_id < 3) { | |
147ff807 | 1605 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1606 | } |
1607 | ||
0c86b2df | 1608 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 BR |
1609 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1610 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1611 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1612 | ||
1613 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1614 | if (err) { | |
1615 | error_report("Process table config unsupported by the host"); | |
1616 | return -EINVAL; | |
1617 | } | |
1618 | } | |
1619 | ||
880ae7de DG |
1620 | return err; |
1621 | } | |
1622 | ||
1623 | static bool version_before_3(void *opaque, int version_id) | |
1624 | { | |
1625 | return version_id < 3; | |
1626 | } | |
1627 | ||
fd38804b DHB |
1628 | static bool spapr_pending_events_needed(void *opaque) |
1629 | { | |
1630 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1631 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1632 | } | |
1633 | ||
1634 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1635 | .name = "spapr_event_log_entry", | |
1636 | .version_id = 1, | |
1637 | .minimum_version_id = 1, | |
1638 | .fields = (VMStateField[]) { | |
5341258e DG |
1639 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1640 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1641 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1642 | NULL, extended_length), |
fd38804b DHB |
1643 | VMSTATE_END_OF_LIST() |
1644 | }, | |
1645 | }; | |
1646 | ||
1647 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1648 | .name = "spapr_pending_events", | |
1649 | .version_id = 1, | |
1650 | .minimum_version_id = 1, | |
1651 | .needed = spapr_pending_events_needed, | |
1652 | .fields = (VMStateField[]) { | |
1653 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1654 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1655 | VMSTATE_END_OF_LIST() | |
1656 | }, | |
1657 | }; | |
1658 | ||
62ef3760 MR |
1659 | static bool spapr_ov5_cas_needed(void *opaque) |
1660 | { | |
1661 | sPAPRMachineState *spapr = opaque; | |
1662 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1663 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1664 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1665 | bool cas_needed; | |
1666 | ||
1667 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1668 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1669 | * Both of these options encode machine topology into the device-tree | |
1670 | * in such a way that the now-booted OS should still be able to interact | |
1671 | * appropriately with QEMU regardless of what options were actually | |
1672 | * negotiatied on the source side. | |
1673 | * | |
1674 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1675 | * are the only options available on the current machine/platform. | |
1676 | * Since these are the only options available for pseries-2.7 and | |
1677 | * earlier, this allows us to maintain old->new/new->old migration | |
1678 | * compatibility. | |
1679 | * | |
1680 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1681 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1682 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1683 | * of the actual CAS-negotiated values to continue working properly. For | |
1684 | * example, availability of memory unplug depends on knowing whether | |
1685 | * OV5_HP_EVT was negotiated via CAS. | |
1686 | * | |
1687 | * Thus, for any cases where the set of available CAS-negotiatable | |
1688 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
1689 | * include the CAS-negotiated options in the migration stream. | |
1690 | */ | |
1691 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1692 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
1693 | ||
1694 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1695 | * the mask itself since in the future it's possible "legacy" bits may be | |
1696 | * removed via machine options, which could generate a false positive | |
1697 | * that breaks migration. | |
1698 | */ | |
1699 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1700 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1701 | ||
1702 | spapr_ovec_cleanup(ov5_mask); | |
1703 | spapr_ovec_cleanup(ov5_legacy); | |
1704 | spapr_ovec_cleanup(ov5_removed); | |
1705 | ||
1706 | return cas_needed; | |
1707 | } | |
1708 | ||
1709 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1710 | .name = "spapr_option_vector_ov5_cas", | |
1711 | .version_id = 1, | |
1712 | .minimum_version_id = 1, | |
1713 | .needed = spapr_ov5_cas_needed, | |
1714 | .fields = (VMStateField[]) { | |
1715 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1716 | vmstate_spapr_ovec, sPAPROptionVector), | |
1717 | VMSTATE_END_OF_LIST() | |
1718 | }, | |
1719 | }; | |
1720 | ||
9861bb3e SJS |
1721 | static bool spapr_patb_entry_needed(void *opaque) |
1722 | { | |
1723 | sPAPRMachineState *spapr = opaque; | |
1724 | ||
1725 | return !!spapr->patb_entry; | |
1726 | } | |
1727 | ||
1728 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1729 | .name = "spapr_patb_entry", | |
1730 | .version_id = 1, | |
1731 | .minimum_version_id = 1, | |
1732 | .needed = spapr_patb_entry_needed, | |
1733 | .fields = (VMStateField[]) { | |
1734 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1735 | VMSTATE_END_OF_LIST() | |
1736 | }, | |
1737 | }; | |
1738 | ||
4be21d56 DG |
1739 | static const VMStateDescription vmstate_spapr = { |
1740 | .name = "spapr", | |
880ae7de | 1741 | .version_id = 3, |
4be21d56 | 1742 | .minimum_version_id = 1, |
880ae7de | 1743 | .post_load = spapr_post_load, |
3aff6c2f | 1744 | .fields = (VMStateField[]) { |
880ae7de DG |
1745 | /* used to be @next_irq */ |
1746 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1747 | |
1748 | /* RTC offset */ | |
28e02042 | 1749 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1750 | |
28e02042 | 1751 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1752 | VMSTATE_END_OF_LIST() |
1753 | }, | |
62ef3760 MR |
1754 | .subsections = (const VMStateDescription*[]) { |
1755 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1756 | &vmstate_spapr_patb_entry, |
fd38804b | 1757 | &vmstate_spapr_pending_events, |
62ef3760 MR |
1758 | NULL |
1759 | } | |
4be21d56 DG |
1760 | }; |
1761 | ||
4be21d56 DG |
1762 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1763 | { | |
28e02042 | 1764 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1765 | |
4be21d56 | 1766 | /* "Iteration" header */ |
3a384297 BR |
1767 | if (!spapr->htab_shift) { |
1768 | qemu_put_be32(f, -1); | |
1769 | } else { | |
1770 | qemu_put_be32(f, spapr->htab_shift); | |
1771 | } | |
4be21d56 | 1772 | |
e68cb8b4 AK |
1773 | if (spapr->htab) { |
1774 | spapr->htab_save_index = 0; | |
1775 | spapr->htab_first_pass = true; | |
1776 | } else { | |
3a384297 BR |
1777 | if (spapr->htab_shift) { |
1778 | assert(kvm_enabled()); | |
1779 | } | |
e68cb8b4 AK |
1780 | } |
1781 | ||
1782 | ||
4be21d56 DG |
1783 | return 0; |
1784 | } | |
1785 | ||
332f7721 GK |
1786 | static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, |
1787 | int chunkstart, int n_valid, int n_invalid) | |
1788 | { | |
1789 | qemu_put_be32(f, chunkstart); | |
1790 | qemu_put_be16(f, n_valid); | |
1791 | qemu_put_be16(f, n_invalid); | |
1792 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1793 | HASH_PTE_SIZE_64 * n_valid); | |
1794 | } | |
1795 | ||
1796 | static void htab_save_end_marker(QEMUFile *f) | |
1797 | { | |
1798 | qemu_put_be32(f, 0); | |
1799 | qemu_put_be16(f, 0); | |
1800 | qemu_put_be16(f, 0); | |
1801 | } | |
1802 | ||
28e02042 | 1803 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1804 | int64_t max_ns) |
1805 | { | |
378bc217 | 1806 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1807 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1808 | int index = spapr->htab_save_index; | |
bc72ad67 | 1809 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1810 | |
1811 | assert(spapr->htab_first_pass); | |
1812 | ||
1813 | do { | |
1814 | int chunkstart; | |
1815 | ||
1816 | /* Consume invalid HPTEs */ | |
1817 | while ((index < htabslots) | |
1818 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 1819 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1820 | index++; |
4be21d56 DG |
1821 | } |
1822 | ||
1823 | /* Consume valid HPTEs */ | |
1824 | chunkstart = index; | |
338c25b6 | 1825 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 1826 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 1827 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 1828 | index++; |
4be21d56 DG |
1829 | } |
1830 | ||
1831 | if (index > chunkstart) { | |
1832 | int n_valid = index - chunkstart; | |
1833 | ||
332f7721 | 1834 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 1835 | |
378bc217 DG |
1836 | if (has_timeout && |
1837 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1838 | break; |
1839 | } | |
1840 | } | |
1841 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1842 | ||
1843 | if (index >= htabslots) { | |
1844 | assert(index == htabslots); | |
1845 | index = 0; | |
1846 | spapr->htab_first_pass = false; | |
1847 | } | |
1848 | spapr->htab_save_index = index; | |
1849 | } | |
1850 | ||
28e02042 | 1851 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1852 | int64_t max_ns) |
4be21d56 DG |
1853 | { |
1854 | bool final = max_ns < 0; | |
1855 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1856 | int examined = 0, sent = 0; | |
1857 | int index = spapr->htab_save_index; | |
bc72ad67 | 1858 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1859 | |
1860 | assert(!spapr->htab_first_pass); | |
1861 | ||
1862 | do { | |
1863 | int chunkstart, invalidstart; | |
1864 | ||
1865 | /* Consume non-dirty HPTEs */ | |
1866 | while ((index < htabslots) | |
1867 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1868 | index++; | |
1869 | examined++; | |
1870 | } | |
1871 | ||
1872 | chunkstart = index; | |
1873 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1874 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1875 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1876 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1877 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1878 | index++; | |
1879 | examined++; | |
1880 | } | |
1881 | ||
1882 | invalidstart = index; | |
1883 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1884 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1885 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1886 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1887 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1888 | index++; | |
1889 | examined++; | |
1890 | } | |
1891 | ||
1892 | if (index > chunkstart) { | |
1893 | int n_valid = invalidstart - chunkstart; | |
1894 | int n_invalid = index - invalidstart; | |
1895 | ||
332f7721 | 1896 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
1897 | sent += index - chunkstart; |
1898 | ||
bc72ad67 | 1899 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1900 | break; |
1901 | } | |
1902 | } | |
1903 | ||
1904 | if (examined >= htabslots) { | |
1905 | break; | |
1906 | } | |
1907 | ||
1908 | if (index >= htabslots) { | |
1909 | assert(index == htabslots); | |
1910 | index = 0; | |
1911 | } | |
1912 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1913 | ||
1914 | if (index >= htabslots) { | |
1915 | assert(index == htabslots); | |
1916 | index = 0; | |
1917 | } | |
1918 | ||
1919 | spapr->htab_save_index = index; | |
1920 | ||
e68cb8b4 | 1921 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1922 | } |
1923 | ||
e68cb8b4 AK |
1924 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1925 | #define MAX_KVM_BUF_SIZE 2048 | |
1926 | ||
4be21d56 DG |
1927 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1928 | { | |
28e02042 | 1929 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1930 | int fd; |
e68cb8b4 | 1931 | int rc = 0; |
4be21d56 DG |
1932 | |
1933 | /* Iteration header */ | |
3a384297 BR |
1934 | if (!spapr->htab_shift) { |
1935 | qemu_put_be32(f, -1); | |
e8cd4247 | 1936 | return 1; |
3a384297 BR |
1937 | } else { |
1938 | qemu_put_be32(f, 0); | |
1939 | } | |
4be21d56 | 1940 | |
e68cb8b4 AK |
1941 | if (!spapr->htab) { |
1942 | assert(kvm_enabled()); | |
1943 | ||
715c5407 DG |
1944 | fd = get_htab_fd(spapr); |
1945 | if (fd < 0) { | |
1946 | return fd; | |
01a57972 SMJ |
1947 | } |
1948 | ||
715c5407 | 1949 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1950 | if (rc < 0) { |
1951 | return rc; | |
1952 | } | |
1953 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1954 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1955 | } else { | |
e68cb8b4 | 1956 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1957 | } |
1958 | ||
332f7721 | 1959 | htab_save_end_marker(f); |
4be21d56 | 1960 | |
e68cb8b4 | 1961 | return rc; |
4be21d56 DG |
1962 | } |
1963 | ||
1964 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1965 | { | |
28e02042 | 1966 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1967 | int fd; |
4be21d56 DG |
1968 | |
1969 | /* Iteration header */ | |
3a384297 BR |
1970 | if (!spapr->htab_shift) { |
1971 | qemu_put_be32(f, -1); | |
1972 | return 0; | |
1973 | } else { | |
1974 | qemu_put_be32(f, 0); | |
1975 | } | |
4be21d56 | 1976 | |
e68cb8b4 AK |
1977 | if (!spapr->htab) { |
1978 | int rc; | |
1979 | ||
1980 | assert(kvm_enabled()); | |
1981 | ||
715c5407 DG |
1982 | fd = get_htab_fd(spapr); |
1983 | if (fd < 0) { | |
1984 | return fd; | |
01a57972 SMJ |
1985 | } |
1986 | ||
715c5407 | 1987 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1988 | if (rc < 0) { |
1989 | return rc; | |
1990 | } | |
e68cb8b4 | 1991 | } else { |
378bc217 DG |
1992 | if (spapr->htab_first_pass) { |
1993 | htab_save_first_pass(f, spapr, -1); | |
1994 | } | |
e68cb8b4 AK |
1995 | htab_save_later_pass(f, spapr, -1); |
1996 | } | |
4be21d56 DG |
1997 | |
1998 | /* End marker */ | |
332f7721 | 1999 | htab_save_end_marker(f); |
4be21d56 DG |
2000 | |
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2005 | { | |
28e02042 | 2006 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 2007 | uint32_t section_hdr; |
e68cb8b4 | 2008 | int fd = -1; |
14b0d748 | 2009 | Error *local_err = NULL; |
4be21d56 DG |
2010 | |
2011 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2012 | error_report("htab_load() bad version"); |
4be21d56 DG |
2013 | return -EINVAL; |
2014 | } | |
2015 | ||
2016 | section_hdr = qemu_get_be32(f); | |
2017 | ||
3a384297 BR |
2018 | if (section_hdr == -1) { |
2019 | spapr_free_hpt(spapr); | |
2020 | return 0; | |
2021 | } | |
2022 | ||
4be21d56 | 2023 | if (section_hdr) { |
c5f54f3e DG |
2024 | /* First section gives the htab size */ |
2025 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2026 | if (local_err) { | |
2027 | error_report_err(local_err); | |
4be21d56 DG |
2028 | return -EINVAL; |
2029 | } | |
2030 | return 0; | |
2031 | } | |
2032 | ||
e68cb8b4 AK |
2033 | if (!spapr->htab) { |
2034 | assert(kvm_enabled()); | |
2035 | ||
14b0d748 | 2036 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2037 | if (fd < 0) { |
14b0d748 | 2038 | error_report_err(local_err); |
82be8e73 | 2039 | return fd; |
e68cb8b4 AK |
2040 | } |
2041 | } | |
2042 | ||
4be21d56 DG |
2043 | while (true) { |
2044 | uint32_t index; | |
2045 | uint16_t n_valid, n_invalid; | |
2046 | ||
2047 | index = qemu_get_be32(f); | |
2048 | n_valid = qemu_get_be16(f); | |
2049 | n_invalid = qemu_get_be16(f); | |
2050 | ||
2051 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2052 | /* End of Stream */ | |
2053 | break; | |
2054 | } | |
2055 | ||
e68cb8b4 | 2056 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2057 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2058 | /* Bad index in stream */ | |
98a5d100 DG |
2059 | error_report( |
2060 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2061 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2062 | return -EINVAL; |
2063 | } | |
2064 | ||
e68cb8b4 AK |
2065 | if (spapr->htab) { |
2066 | if (n_valid) { | |
2067 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2068 | HASH_PTE_SIZE_64 * n_valid); | |
2069 | } | |
2070 | if (n_invalid) { | |
2071 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2072 | HASH_PTE_SIZE_64 * n_invalid); | |
2073 | } | |
2074 | } else { | |
2075 | int rc; | |
2076 | ||
2077 | assert(fd >= 0); | |
2078 | ||
2079 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2080 | if (rc < 0) { | |
2081 | return rc; | |
2082 | } | |
4be21d56 DG |
2083 | } |
2084 | } | |
2085 | ||
e68cb8b4 AK |
2086 | if (!spapr->htab) { |
2087 | assert(fd >= 0); | |
2088 | close(fd); | |
2089 | } | |
2090 | ||
4be21d56 DG |
2091 | return 0; |
2092 | } | |
2093 | ||
70f794fc | 2094 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
2095 | { |
2096 | sPAPRMachineState *spapr = opaque; | |
2097 | ||
2098 | close_htab_fd(spapr); | |
2099 | } | |
2100 | ||
4be21d56 | 2101 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2102 | .save_setup = htab_save_setup, |
4be21d56 | 2103 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2104 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2105 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2106 | .load_state = htab_load, |
2107 | }; | |
2108 | ||
5b2128d2 AG |
2109 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2110 | Error **errp) | |
2111 | { | |
c86c1aff | 2112 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2113 | machine->boot_order = g_strdup(boot_device); |
2114 | } | |
2115 | ||
224245bf DG |
2116 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2117 | { | |
2118 | MachineState *machine = MACHINE(spapr); | |
2119 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2120 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2121 | int i; |
2122 | ||
2123 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2124 | uint64_t addr; |
2125 | ||
e8f986fc | 2126 | addr = i * lmb_size + spapr->hotplug_memory.base; |
6caf3ac6 DG |
2127 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2128 | addr / lmb_size); | |
224245bf DG |
2129 | } |
2130 | } | |
2131 | ||
2132 | /* | |
2133 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2134 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2135 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2136 | */ | |
7c150d6f | 2137 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2138 | { |
2139 | int i; | |
2140 | ||
7c150d6f DG |
2141 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2142 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
2143 | " is not aligned to %llu MiB", | |
2144 | machine->ram_size, | |
2145 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2146 | return; | |
2147 | } | |
2148 | ||
2149 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2150 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
2151 | " is not aligned to %llu MiB", | |
2152 | machine->ram_size, | |
2153 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2154 | return; | |
224245bf DG |
2155 | } |
2156 | ||
2157 | for (i = 0; i < nb_numa_nodes; i++) { | |
2158 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2159 | error_setg(errp, |
2160 | "Node %d memory size 0x%" PRIx64 | |
2161 | " is not aligned to %llu MiB", | |
2162 | i, numa_info[i].node_mem, | |
2163 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
2164 | return; | |
224245bf DG |
2165 | } |
2166 | } | |
2167 | } | |
2168 | ||
535455fd IM |
2169 | /* find cpu slot in machine->possible_cpus by core_id */ |
2170 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2171 | { | |
2172 | int index = id / smp_threads; | |
2173 | ||
2174 | if (index >= ms->possible_cpus->len) { | |
2175 | return NULL; | |
2176 | } | |
2177 | if (idx) { | |
2178 | *idx = index; | |
2179 | } | |
2180 | return &ms->possible_cpus->cpus[index]; | |
2181 | } | |
2182 | ||
0c86d0fd DG |
2183 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2184 | { | |
2185 | MachineState *machine = MACHINE(spapr); | |
2186 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2e9c10eb | 2187 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); |
0c86d0fd | 2188 | int smt = kvmppc_smt_threads(); |
535455fd IM |
2189 | const CPUArchIdList *possible_cpus; |
2190 | int boot_cores_nr = smp_cpus / smp_threads; | |
0c86d0fd DG |
2191 | int i; |
2192 | ||
2193 | if (!type) { | |
2194 | error_report("Unable to find sPAPR CPU Core definition"); | |
2195 | exit(1); | |
2196 | } | |
2197 | ||
535455fd | 2198 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
c5514d0e | 2199 | if (mc->has_hotpluggable_cpus) { |
0c86d0fd DG |
2200 | if (smp_cpus % smp_threads) { |
2201 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2202 | smp_cpus, smp_threads); | |
2203 | exit(1); | |
2204 | } | |
2205 | if (max_cpus % smp_threads) { | |
2206 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2207 | max_cpus, smp_threads); | |
2208 | exit(1); | |
2209 | } | |
0c86d0fd DG |
2210 | } else { |
2211 | if (max_cpus != smp_cpus) { | |
2212 | error_report("This machine version does not support CPU hotplug"); | |
2213 | exit(1); | |
2214 | } | |
535455fd | 2215 | boot_cores_nr = possible_cpus->len; |
0c86d0fd DG |
2216 | } |
2217 | ||
535455fd | 2218 | for (i = 0; i < possible_cpus->len; i++) { |
0c86d0fd DG |
2219 | int core_id = i * smp_threads; |
2220 | ||
c5514d0e | 2221 | if (mc->has_hotpluggable_cpus) { |
6caf3ac6 DG |
2222 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, |
2223 | (core_id / smp_threads) * smt); | |
0c86d0fd DG |
2224 | } |
2225 | ||
535455fd | 2226 | if (i < boot_cores_nr) { |
0c86d0fd DG |
2227 | Object *core = object_new(type); |
2228 | int nr_threads = smp_threads; | |
2229 | ||
2230 | /* Handle the partially filled core for older machine types */ | |
2231 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2232 | nr_threads = smp_cpus - i * smp_threads; | |
2233 | } | |
2234 | ||
2235 | object_property_set_int(core, nr_threads, "nr-threads", | |
2236 | &error_fatal); | |
2237 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2238 | &error_fatal); | |
2239 | object_property_set_bool(core, true, "realized", &error_fatal); | |
2240 | } | |
2241 | } | |
0c86d0fd DG |
2242 | } |
2243 | ||
fa98fbfc SB |
2244 | static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) |
2245 | { | |
2246 | Error *local_err = NULL; | |
2247 | bool vsmt_user = !!spapr->vsmt; | |
2248 | int kvm_smt = kvmppc_smt_threads(); | |
2249 | int ret; | |
2250 | ||
2251 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2252 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2253 | "on a pseries machine"); | |
2254 | goto out; | |
2255 | } | |
2256 | if (!is_power_of_2(smp_threads)) { | |
2257 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2258 | "machine because it must be a power of 2", smp_threads); | |
2259 | goto out; | |
2260 | } | |
2261 | ||
2262 | /* Detemine the VSMT mode to use: */ | |
2263 | if (vsmt_user) { | |
2264 | if (spapr->vsmt < smp_threads) { | |
2265 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2266 | " because it must be >= threads/core (%d)", | |
2267 | spapr->vsmt, smp_threads); | |
2268 | goto out; | |
2269 | } | |
2270 | /* In this case, spapr->vsmt has been set by the command line */ | |
2271 | } else { | |
2272 | /* Choose a VSMT mode that may be higher than necessary but is | |
2273 | * likely to be compatible with hosts that don't have VSMT. */ | |
2274 | spapr->vsmt = MAX(kvm_smt, smp_threads); | |
2275 | } | |
2276 | ||
2277 | /* KVM: If necessary, set the SMT mode: */ | |
2278 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2279 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2280 | if (ret) { | |
2281 | error_setg(&local_err, | |
2282 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2283 | spapr->vsmt, ret); | |
2284 | if (!vsmt_user) { | |
2285 | error_append_hint(&local_err, "On PPC, a VM with %d threads/" | |
2286 | "core on a host with %d threads/core requires " | |
2287 | " the use of VSMT mode %d.\n", | |
2288 | smp_threads, kvm_smt, spapr->vsmt); | |
2289 | } | |
2290 | kvmppc_hint_smt_possible(&local_err); | |
2291 | goto out; | |
2292 | } | |
2293 | } | |
2294 | /* else TCG: nothing to do currently */ | |
2295 | out: | |
2296 | error_propagate(errp, local_err); | |
2297 | } | |
2298 | ||
9fdf0c29 | 2299 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2300 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2301 | { |
28e02042 | 2302 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2303 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2304 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2305 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2306 | PCIHostState *phb; |
9fdf0c29 | 2307 | int i; |
890c2b77 AK |
2308 | MemoryRegion *sysmem = get_system_memory(); |
2309 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
2310 | MemoryRegion *rma_region; |
2311 | void *rma = NULL; | |
a8170e5e | 2312 | hwaddr rma_alloc_size; |
c86c1aff | 2313 | hwaddr node0_size = spapr_node0_size(machine); |
b7d1f77a | 2314 | long load_limit, fw_size; |
39ac8455 | 2315 | char *filename; |
30f4b05b | 2316 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2317 | |
33face6b DG |
2318 | spapr_caps_validate(spapr, &error_fatal); |
2319 | ||
226419d6 | 2320 | msi_nonbroken = true; |
0ee2c058 | 2321 | |
d43b45e2 | 2322 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2323 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2324 | |
30f4b05b DG |
2325 | /* Check HPT resizing availability */ |
2326 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); | |
2327 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2328 | /* | |
2329 | * If the user explicitly requested a mode we should either | |
2330 | * supply it, or fail completely (which we do below). But if | |
2331 | * it's not set explicitly, we reset our mode to something | |
2332 | * that works | |
2333 | */ | |
2334 | if (resize_hpt_err) { | |
2335 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2336 | error_free(resize_hpt_err); | |
2337 | resize_hpt_err = NULL; | |
2338 | } else { | |
2339 | spapr->resize_hpt = smc->resize_hpt_default; | |
2340 | } | |
2341 | } | |
2342 | ||
2343 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2344 | ||
2345 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2346 | /* | |
2347 | * User requested HPT resize, but this host can't supply it. Bail out | |
2348 | */ | |
2349 | error_report_err(resize_hpt_err); | |
2350 | exit(1); | |
2351 | } | |
2352 | ||
354ac20a | 2353 | /* Allocate RMA if necessary */ |
658fa66b | 2354 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
2355 | |
2356 | if (rma_alloc_size == -1) { | |
730fce59 | 2357 | error_report("Unable to create RMA"); |
354ac20a DG |
2358 | exit(1); |
2359 | } | |
7f763a5d | 2360 | |
c4177479 | 2361 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 2362 | spapr->rma_size = rma_alloc_size; |
354ac20a | 2363 | } else { |
c4177479 | 2364 | spapr->rma_size = node0_size; |
7f763a5d DG |
2365 | |
2366 | /* With KVM, we don't actually know whether KVM supports an | |
2367 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2368 | * (HV KVM using VRMA), so we always assume the latter | |
2369 | * | |
2370 | * In that case, we also limit the initial allocations for RTAS | |
2371 | * etc... to 256M since we have no way to know what the VRMA size | |
2372 | * is going to be as it depends on the size of the hash table | |
2373 | * isn't determined yet. | |
2374 | */ | |
2375 | if (kvm_enabled()) { | |
2376 | spapr->vrma_adjust = 1; | |
2377 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
2378 | } | |
912acdf4 BH |
2379 | |
2380 | /* Actually we don't support unbounded RMA anymore since we | |
2381 | * added proper emulation of HV mode. The max we can get is | |
2382 | * 16G which also happens to be what we configure for PAPR | |
2383 | * mode so make sure we don't do anything bigger than that | |
2384 | */ | |
2385 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
2386 | } |
2387 | ||
c4177479 | 2388 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2389 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2390 | spapr->rma_size); | |
c4177479 AK |
2391 | exit(1); |
2392 | } | |
2393 | ||
b7d1f77a BH |
2394 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2395 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2396 | |
7b565160 | 2397 | /* Set up Interrupt Controller before we create the VCPUs */ |
71cd4dac | 2398 | xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); |
7b565160 | 2399 | |
dc1b5eee GK |
2400 | /* Set up containers for ibm,client-architecture-support negotiated options |
2401 | */ | |
facdb8b6 MR |
2402 | spapr->ov5 = spapr_ovec_new(); |
2403 | spapr->ov5_cas = spapr_ovec_new(); | |
2404 | ||
224245bf | 2405 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2406 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2407 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2408 | } |
2409 | ||
417ece33 | 2410 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
545d6e2b SJS |
2411 | if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { |
2412 | /* KVM and TCG always allow GTSE with radix... */ | |
9fb4541f SB |
2413 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); |
2414 | } | |
2415 | /* ... but not with hash (currently). */ | |
417ece33 | 2416 | |
ffbb1705 MR |
2417 | /* advertise support for dedicated HP event source to guests */ |
2418 | if (spapr->use_hotplug_event_source) { | |
2419 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2420 | } | |
2421 | ||
2772cf6b DG |
2422 | /* advertise support for HPT resizing */ |
2423 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2424 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2425 | } | |
2426 | ||
9fdf0c29 | 2427 | /* init CPUs */ |
fa98fbfc SB |
2428 | spapr_set_vsmt_mode(spapr, &error_fatal); |
2429 | ||
0c86d0fd | 2430 | spapr_init_cpus(spapr); |
9fdf0c29 | 2431 | |
026bfd89 DG |
2432 | if (kvm_enabled()) { |
2433 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2434 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2435 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2436 | |
2437 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2438 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2439 | } |
2440 | ||
9fdf0c29 | 2441 | /* allocate RAM */ |
f92f5da1 | 2442 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2443 | machine->ram_size); |
f92f5da1 | 2444 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2445 | |
658fa66b AK |
2446 | if (rma_alloc_size && rma) { |
2447 | rma_region = g_new(MemoryRegion, 1); | |
2448 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
2449 | rma_alloc_size, rma); | |
2450 | vmstate_register_ram_global(rma_region); | |
2451 | memory_region_add_subregion(sysmem, 0, rma_region); | |
2452 | } | |
2453 | ||
4a1c9cf0 BR |
2454 | /* initialize hotplug memory address space */ |
2455 | if (machine->ram_size < machine->maxram_size) { | |
2456 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
2457 | /* |
2458 | * Limit the number of hotpluggable memory slots to half the number | |
2459 | * slots that KVM supports, leaving the other half for PCI and other | |
2460 | * devices. However ensure that number of slots doesn't drop below 32. | |
2461 | */ | |
2462 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2463 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2464 | |
71c9a3dd BR |
2465 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2466 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2467 | } | |
2468 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2469 | error_report("Specified number of memory slots %" |
2470 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2471 | machine->ram_slots, max_memslots); |
d54e4d76 | 2472 | exit(1); |
4a1c9cf0 BR |
2473 | } |
2474 | ||
2475 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
2476 | SPAPR_HOTPLUG_MEM_ALIGN); | |
2477 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
2478 | "hotplug-memory", hotplug_mem_size); | |
2479 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
2480 | &spapr->hotplug_memory.mr); | |
2481 | } | |
2482 | ||
224245bf DG |
2483 | if (smc->dr_lmb_enabled) { |
2484 | spapr_create_lmb_dr_connectors(spapr); | |
2485 | } | |
2486 | ||
39ac8455 | 2487 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2488 | if (!filename) { |
730fce59 | 2489 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2490 | exit(1); |
2491 | } | |
b7d1f77a | 2492 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2493 | if (spapr->rtas_size < 0) { |
2494 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2495 | exit(1); | |
2496 | } | |
b7d1f77a BH |
2497 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2498 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2499 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2500 | exit(1); |
2501 | } | |
4d8d5467 | 2502 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2503 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2504 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2505 | exit(1); |
2506 | } | |
7267c094 | 2507 | g_free(filename); |
39ac8455 | 2508 | |
ffbb1705 | 2509 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2510 | spapr_events_init(spapr); |
2511 | ||
12f42174 | 2512 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2513 | spapr_rtc_create(spapr); |
12f42174 | 2514 | |
b5cec4c5 | 2515 | /* Set up VIO bus */ |
4040ab72 DG |
2516 | spapr->vio_bus = spapr_vio_bus_init(); |
2517 | ||
277f9acf | 2518 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 2519 | if (serial_hds[i]) { |
d601fac4 | 2520 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
2521 | } |
2522 | } | |
9fdf0c29 | 2523 | |
639e8102 DG |
2524 | /* We always have at least the nvram device on VIO */ |
2525 | spapr_create_nvram(spapr); | |
2526 | ||
3384f95c | 2527 | /* Set up PCI */ |
fa28f71b AK |
2528 | spapr_pci_rtas_init(); |
2529 | ||
89dfd6e1 | 2530 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2531 | |
277f9acf | 2532 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2533 | NICInfo *nd = &nd_table[i]; |
2534 | ||
2535 | if (!nd->model) { | |
7267c094 | 2536 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
2537 | } |
2538 | ||
2539 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 2540 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2541 | } else { |
29b358f9 | 2542 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2543 | } |
2544 | } | |
2545 | ||
6e270446 | 2546 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2547 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2548 | } |
2549 | ||
f28359d8 | 2550 | /* Graphics */ |
14c6a894 | 2551 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2552 | spapr->has_graphics = true; |
c6e76503 | 2553 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2554 | } |
2555 | ||
4ee9ced9 | 2556 | if (machine->usb) { |
57040d45 TH |
2557 | if (smc->use_ohci_by_default) { |
2558 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2559 | } else { | |
2560 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2561 | } | |
c86580b8 | 2562 | |
35139a59 | 2563 | if (spapr->has_graphics) { |
c86580b8 MA |
2564 | USBBus *usb_bus = usb_bus_find(-1); |
2565 | ||
2566 | usb_create_simple(usb_bus, "usb-kbd"); | |
2567 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2568 | } |
2569 | } | |
2570 | ||
7f763a5d | 2571 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
2572 | error_report( |
2573 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2574 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2575 | exit(1); |
2576 | } | |
2577 | ||
9fdf0c29 DG |
2578 | if (kernel_filename) { |
2579 | uint64_t lowaddr = 0; | |
2580 | ||
a19f7fb0 DG |
2581 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2582 | NULL, NULL, &lowaddr, NULL, 1, | |
2583 | PPC_ELF_MACHINE, 0, 0); | |
2584 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2585 | spapr->kernel_size = load_elf(kernel_filename, | |
2586 | translate_kernel_address, NULL, NULL, | |
2587 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2588 | 0, 0); | |
2589 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2590 | } |
a19f7fb0 DG |
2591 | if (spapr->kernel_size < 0) { |
2592 | error_report("error loading %s: %s", kernel_filename, | |
2593 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2594 | exit(1); |
2595 | } | |
2596 | ||
2597 | /* load initrd */ | |
2598 | if (initrd_filename) { | |
4d8d5467 BH |
2599 | /* Try to locate the initrd in the gap between the kernel |
2600 | * and the firmware. Add a bit of space just in case | |
2601 | */ | |
a19f7fb0 DG |
2602 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2603 | + 0x1ffff) & ~0xffff; | |
2604 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2605 | spapr->initrd_base, | |
2606 | load_limit | |
2607 | - spapr->initrd_base); | |
2608 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2609 | error_report("could not load initial ram disk '%s'", |
2610 | initrd_filename); | |
9fdf0c29 DG |
2611 | exit(1); |
2612 | } | |
9fdf0c29 | 2613 | } |
4d8d5467 | 2614 | } |
a3467baa | 2615 | |
8e7ea787 AF |
2616 | if (bios_name == NULL) { |
2617 | bios_name = FW_FILE_NAME; | |
2618 | } | |
2619 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2620 | if (!filename) { |
68fea5a0 | 2621 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2622 | exit(1); |
2623 | } | |
4d8d5467 | 2624 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2625 | if (fw_size <= 0) { |
2626 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2627 | exit(1); |
2628 | } | |
2629 | g_free(filename); | |
4d8d5467 | 2630 | |
28e02042 DG |
2631 | /* FIXME: Should register things through the MachineState's qdev |
2632 | * interface, this is a legacy from the sPAPREnvironment structure | |
2633 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2634 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2635 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2636 | &savevm_htab_handlers, spapr); | |
2637 | ||
5b2128d2 | 2638 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2639 | |
42043e4f | 2640 | if (kvm_enabled()) { |
3dc410ae | 2641 | /* to stop and start vmclock */ |
42043e4f LV |
2642 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2643 | &spapr->tb); | |
3dc410ae AK |
2644 | |
2645 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2646 | } |
9fdf0c29 DG |
2647 | } |
2648 | ||
135a129a AK |
2649 | static int spapr_kvm_type(const char *vm_type) |
2650 | { | |
2651 | if (!vm_type) { | |
2652 | return 0; | |
2653 | } | |
2654 | ||
2655 | if (!strcmp(vm_type, "HV")) { | |
2656 | return 1; | |
2657 | } | |
2658 | ||
2659 | if (!strcmp(vm_type, "PR")) { | |
2660 | return 2; | |
2661 | } | |
2662 | ||
2663 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2664 | exit(1); | |
2665 | } | |
2666 | ||
71461b0f | 2667 | /* |
627b84f4 | 2668 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2669 | * for the bootindex property handling. |
2670 | */ | |
2671 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2672 | DeviceState *dev) | |
2673 | { | |
2674 | #define CAST(type, obj, name) \ | |
2675 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2676 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2677 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2678 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2679 | |
2680 | if (d) { | |
2681 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2682 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2683 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2684 | ||
2685 | if (spapr) { | |
2686 | /* | |
2687 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2688 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2689 | * in the top 16 bits of the 64-bit LUN | |
2690 | */ | |
2691 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2692 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2693 | (uint64_t)id << 48); | |
2694 | } else if (virtio) { | |
2695 | /* | |
2696 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2697 | * in the top 32 bits of the 64-bit LUN | |
2698 | * Note: the quote above is from SLOF and it is wrong, | |
2699 | * the actual binding is: | |
2700 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2701 | */ | |
2702 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
2703 | if (d->lun >= 256) { |
2704 | /* Use the LUN "flat space addressing method" */ | |
2705 | id |= 0x4000; | |
2706 | } | |
71461b0f AK |
2707 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
2708 | (uint64_t)id << 32); | |
2709 | } else if (usb) { | |
2710 | /* | |
2711 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2712 | * in the top 32 bits of the 64-bit LUN | |
2713 | */ | |
2714 | unsigned usb_port = atoi(usb->port->path); | |
2715 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2716 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2717 | (uint64_t)id << 32); | |
2718 | } | |
2719 | } | |
2720 | ||
b99260eb TH |
2721 | /* |
2722 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2723 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2724 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2725 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2726 | */ | |
2727 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2728 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2729 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2730 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2731 | } | |
2732 | } | |
2733 | ||
71461b0f AK |
2734 | if (phb) { |
2735 | /* Replace "pci" with "pci@800000020000000" */ | |
2736 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2737 | } | |
2738 | ||
c4e13492 FF |
2739 | if (vsc) { |
2740 | /* Same logic as virtio above */ | |
2741 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2742 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2743 | } | |
2744 | ||
4871dd4c TH |
2745 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2746 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2747 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2748 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2749 | } | |
2750 | ||
71461b0f AK |
2751 | return NULL; |
2752 | } | |
2753 | ||
23825581 EH |
2754 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2755 | { | |
28e02042 | 2756 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2757 | |
28e02042 | 2758 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2759 | } |
2760 | ||
2761 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2762 | { | |
28e02042 | 2763 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2764 | |
28e02042 DG |
2765 | g_free(spapr->kvm_type); |
2766 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2767 | } |
2768 | ||
f6229214 MR |
2769 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2770 | { | |
2771 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2772 | ||
2773 | return spapr->use_hotplug_event_source; | |
2774 | } | |
2775 | ||
2776 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2777 | Error **errp) | |
2778 | { | |
2779 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2780 | ||
2781 | spapr->use_hotplug_event_source = value; | |
2782 | } | |
2783 | ||
30f4b05b DG |
2784 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2785 | { | |
2786 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2787 | ||
2788 | switch (spapr->resize_hpt) { | |
2789 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2790 | return g_strdup("default"); | |
2791 | case SPAPR_RESIZE_HPT_DISABLED: | |
2792 | return g_strdup("disabled"); | |
2793 | case SPAPR_RESIZE_HPT_ENABLED: | |
2794 | return g_strdup("enabled"); | |
2795 | case SPAPR_RESIZE_HPT_REQUIRED: | |
2796 | return g_strdup("required"); | |
2797 | } | |
2798 | g_assert_not_reached(); | |
2799 | } | |
2800 | ||
2801 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
2802 | { | |
2803 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2804 | ||
2805 | if (strcmp(value, "default") == 0) { | |
2806 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
2807 | } else if (strcmp(value, "disabled") == 0) { | |
2808 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2809 | } else if (strcmp(value, "enabled") == 0) { | |
2810 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
2811 | } else if (strcmp(value, "required") == 0) { | |
2812 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
2813 | } else { | |
2814 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
2815 | } | |
2816 | } | |
2817 | ||
fa98fbfc SB |
2818 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
2819 | void *opaque, Error **errp) | |
2820 | { | |
2821 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2822 | } | |
2823 | ||
2824 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, | |
2825 | void *opaque, Error **errp) | |
2826 | { | |
2827 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
2828 | } | |
2829 | ||
bcb5ce08 | 2830 | static void spapr_instance_init(Object *obj) |
23825581 | 2831 | { |
715c5407 DG |
2832 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2833 | ||
2834 | spapr->htab_fd = -1; | |
f6229214 | 2835 | spapr->use_hotplug_event_source = true; |
23825581 EH |
2836 | object_property_add_str(obj, "kvm-type", |
2837 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2838 | object_property_set_description(obj, "kvm-type", |
2839 | "Specifies the KVM virtualization mode (HV, PR)", | |
2840 | NULL); | |
f6229214 MR |
2841 | object_property_add_bool(obj, "modern-hotplug-events", |
2842 | spapr_get_modern_hotplug_events, | |
2843 | spapr_set_modern_hotplug_events, | |
2844 | NULL); | |
2845 | object_property_set_description(obj, "modern-hotplug-events", | |
2846 | "Use dedicated hotplug event mechanism in" | |
2847 | " place of standard EPOW events when possible" | |
2848 | " (required for memory hot-unplug support)", | |
2849 | NULL); | |
7843c0d6 DG |
2850 | |
2851 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, | |
2852 | "Maximum permitted CPU compatibility mode", | |
2853 | &error_fatal); | |
30f4b05b DG |
2854 | |
2855 | object_property_add_str(obj, "resize-hpt", | |
2856 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
2857 | object_property_set_description(obj, "resize-hpt", | |
2858 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
2859 | NULL); | |
fa98fbfc SB |
2860 | object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, |
2861 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); | |
2862 | object_property_set_description(obj, "vsmt", | |
2863 | "Virtual SMT: KVM behaves as if this were" | |
2864 | " the host's SMT mode", &error_abort); | |
23825581 EH |
2865 | } |
2866 | ||
87bbdd9c DG |
2867 | static void spapr_machine_finalizefn(Object *obj) |
2868 | { | |
2869 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2870 | ||
2871 | g_free(spapr->kvm_type); | |
2872 | } | |
2873 | ||
1c7ad77e | 2874 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 2875 | { |
34316482 AK |
2876 | cpu_synchronize_state(cs); |
2877 | ppc_cpu_do_system_reset(cs); | |
2878 | } | |
2879 | ||
2880 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2881 | { | |
2882 | CPUState *cs; | |
2883 | ||
2884 | CPU_FOREACH(cs) { | |
1c7ad77e | 2885 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
2886 | } |
2887 | } | |
2888 | ||
79b78a6b MR |
2889 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
2890 | uint32_t node, bool dedicated_hp_event_source, | |
2891 | Error **errp) | |
c20d332a BR |
2892 | { |
2893 | sPAPRDRConnector *drc; | |
c20d332a BR |
2894 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
2895 | int i, fdt_offset, fdt_size; | |
2896 | void *fdt; | |
79b78a6b | 2897 | uint64_t addr = addr_start; |
94fd9cba | 2898 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 2899 | Error *local_err = NULL; |
c20d332a | 2900 | |
c20d332a | 2901 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
2902 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2903 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
2904 | g_assert(drc); |
2905 | ||
2906 | fdt = create_device_tree(&fdt_size); | |
2907 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2908 | SPAPR_MEMORY_BLOCK_SIZE); | |
2909 | ||
160bb678 GK |
2910 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
2911 | if (local_err) { | |
2912 | while (addr > addr_start) { | |
2913 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
2914 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
2915 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 2916 | spapr_drc_detach(drc); |
160bb678 GK |
2917 | } |
2918 | g_free(fdt); | |
2919 | error_propagate(errp, local_err); | |
2920 | return; | |
2921 | } | |
94fd9cba LV |
2922 | if (!hotplugged) { |
2923 | spapr_drc_reset(drc); | |
2924 | } | |
c20d332a BR |
2925 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2926 | } | |
5dd5238c JD |
2927 | /* send hotplug notification to the |
2928 | * guest only in case of hotplugged memory | |
2929 | */ | |
94fd9cba | 2930 | if (hotplugged) { |
79b78a6b | 2931 | if (dedicated_hp_event_source) { |
fbf55397 DG |
2932 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
2933 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
2934 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
2935 | nr_lmbs, | |
0b55aa91 | 2936 | spapr_drc_index(drc)); |
79b78a6b MR |
2937 | } else { |
2938 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2939 | nr_lmbs); | |
2940 | } | |
5dd5238c | 2941 | } |
c20d332a BR |
2942 | } |
2943 | ||
2944 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2945 | uint32_t node, Error **errp) | |
2946 | { | |
2947 | Error *local_err = NULL; | |
2948 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2949 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2950 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
2951 | MemoryRegion *mr; |
2952 | uint64_t align, size, addr; | |
2953 | ||
2954 | mr = ddc->get_memory_region(dimm, &local_err); | |
2955 | if (local_err) { | |
2956 | goto out; | |
2957 | } | |
2958 | align = memory_region_get_alignment(mr); | |
2959 | size = memory_region_size(mr); | |
df587133 | 2960 | |
d6a9b0b8 | 2961 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2962 | if (local_err) { |
2963 | goto out; | |
2964 | } | |
2965 | ||
9ed442b8 MAL |
2966 | addr = object_property_get_uint(OBJECT(dimm), |
2967 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 2968 | if (local_err) { |
160bb678 | 2969 | goto out_unplug; |
c20d332a BR |
2970 | } |
2971 | ||
79b78a6b MR |
2972 | spapr_add_lmbs(dev, addr, size, node, |
2973 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
2974 | &local_err); |
2975 | if (local_err) { | |
2976 | goto out_unplug; | |
2977 | } | |
2978 | ||
2979 | return; | |
c20d332a | 2980 | |
160bb678 GK |
2981 | out_unplug: |
2982 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
c20d332a BR |
2983 | out: |
2984 | error_propagate(errp, local_err); | |
2985 | } | |
2986 | ||
c871bc70 LV |
2987 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2988 | Error **errp) | |
2989 | { | |
2990 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2991 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
2992 | MemoryRegion *mr; |
2993 | uint64_t size; | |
c871bc70 LV |
2994 | char *mem_dev; |
2995 | ||
04790978 TH |
2996 | mr = ddc->get_memory_region(dimm, errp); |
2997 | if (!mr) { | |
2998 | return; | |
2999 | } | |
3000 | size = memory_region_size(mr); | |
3001 | ||
c871bc70 LV |
3002 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3003 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
3004 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
3005 | return; | |
3006 | } | |
3007 | ||
3008 | mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); | |
3009 | if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { | |
3010 | error_setg(errp, "Memory backend has bad page size. " | |
3011 | "Use 'memory-backend-file' with correct mem-path."); | |
8a9e0e7b | 3012 | goto out; |
c871bc70 | 3013 | } |
8a9e0e7b GK |
3014 | |
3015 | out: | |
3016 | g_free(mem_dev); | |
c871bc70 LV |
3017 | } |
3018 | ||
0cffce56 DG |
3019 | struct sPAPRDIMMState { |
3020 | PCDIMMDevice *dimm; | |
cf632463 | 3021 | uint32_t nr_lmbs; |
0cffce56 DG |
3022 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
3023 | }; | |
3024 | ||
3025 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
3026 | PCDIMMDevice *dimm) | |
3027 | { | |
3028 | sPAPRDIMMState *dimm_state = NULL; | |
3029 | ||
3030 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3031 | if (dimm_state->dimm == dimm) { | |
3032 | break; | |
3033 | } | |
3034 | } | |
3035 | return dimm_state; | |
3036 | } | |
3037 | ||
8d5981c4 BR |
3038 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, |
3039 | uint32_t nr_lmbs, | |
3040 | PCDIMMDevice *dimm) | |
0cffce56 | 3041 | { |
8d5981c4 BR |
3042 | sPAPRDIMMState *ds = NULL; |
3043 | ||
3044 | /* | |
3045 | * If this request is for a DIMM whose removal had failed earlier | |
3046 | * (due to guest's refusal to remove the LMBs), we would have this | |
3047 | * dimm already in the pending_dimm_unplugs list. In that | |
3048 | * case don't add again. | |
3049 | */ | |
3050 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3051 | if (!ds) { | |
3052 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
3053 | ds->nr_lmbs = nr_lmbs; | |
3054 | ds->dimm = dimm; | |
3055 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3056 | } | |
3057 | return ds; | |
0cffce56 DG |
3058 | } |
3059 | ||
3060 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
3061 | sPAPRDIMMState *dimm_state) | |
3062 | { | |
3063 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3064 | g_free(dimm_state); | |
3065 | } | |
cf632463 | 3066 | |
16ee9980 DHB |
3067 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
3068 | PCDIMMDevice *dimm) | |
3069 | { | |
3070 | sPAPRDRConnector *drc; | |
3071 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3072 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
16ee9980 DHB |
3073 | uint64_t size = memory_region_size(mr); |
3074 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3075 | uint32_t avail_lmbs = 0; | |
3076 | uint64_t addr_start, addr; | |
3077 | int i; | |
16ee9980 DHB |
3078 | |
3079 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3080 | &error_abort); | |
3081 | ||
3082 | addr = addr_start; | |
3083 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3084 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3085 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3086 | g_assert(drc); |
454b580a | 3087 | if (drc->dev) { |
16ee9980 DHB |
3088 | avail_lmbs++; |
3089 | } | |
3090 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3091 | } | |
3092 | ||
8d5981c4 | 3093 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3094 | } |
3095 | ||
31834723 DHB |
3096 | /* Callback to be called during DRC release. */ |
3097 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3098 | { |
765d1bdd DG |
3099 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); |
3100 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3101 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 3102 | MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); |
0cffce56 | 3103 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 3104 | |
16ee9980 DHB |
3105 | /* This information will get lost if a migration occurs |
3106 | * during the unplug process. In this case recover it. */ | |
3107 | if (ds == NULL) { | |
3108 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3109 | g_assert(ds); |
454b580a DG |
3110 | /* The DRC being examined by the caller at least must be counted */ |
3111 | g_assert(ds->nr_lmbs); | |
3112 | } | |
3113 | ||
3114 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3115 | return; |
3116 | } | |
3117 | ||
cf632463 BR |
3118 | /* |
3119 | * Now that all the LMBs have been removed by the guest, call the | |
3120 | * pc-dimm unplug handler to cleanup up the pc-dimm device. | |
3121 | */ | |
765d1bdd | 3122 | pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); |
cf632463 | 3123 | object_unparent(OBJECT(dev)); |
2a129767 | 3124 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3125 | } |
3126 | ||
3127 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3128 | DeviceState *dev, Error **errp) | |
3129 | { | |
0cffce56 | 3130 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3131 | Error *local_err = NULL; |
3132 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
3133 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 TH |
3134 | MemoryRegion *mr; |
3135 | uint32_t nr_lmbs; | |
3136 | uint64_t size, addr_start, addr; | |
0cffce56 DG |
3137 | int i; |
3138 | sPAPRDRConnector *drc; | |
04790978 TH |
3139 | |
3140 | mr = ddc->get_memory_region(dimm, &local_err); | |
3141 | if (local_err) { | |
3142 | goto out; | |
3143 | } | |
3144 | size = memory_region_size(mr); | |
3145 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; | |
3146 | ||
9ed442b8 | 3147 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3148 | &local_err); |
cf632463 BR |
3149 | if (local_err) { |
3150 | goto out; | |
3151 | } | |
3152 | ||
2a129767 DHB |
3153 | /* |
3154 | * An existing pending dimm state for this DIMM means that there is an | |
3155 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3156 | * callback to complete the job (BQL can't cover that far). In this case, | |
3157 | * bail out to avoid detaching DRCs that were already released. | |
3158 | */ | |
3159 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3160 | error_setg(&local_err, | |
3161 | "Memory unplug already in progress for device %s", | |
3162 | dev->id); | |
3163 | goto out; | |
3164 | } | |
3165 | ||
8d5981c4 | 3166 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3167 | |
3168 | addr = addr_start; | |
3169 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3170 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3171 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3172 | g_assert(drc); |
3173 | ||
a8dc47fd | 3174 | spapr_drc_detach(drc); |
0cffce56 DG |
3175 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3176 | } | |
3177 | ||
fbf55397 DG |
3178 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3179 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3180 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3181 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3182 | out: |
3183 | error_propagate(errp, local_err); | |
3184 | } | |
3185 | ||
04d0ffbd GK |
3186 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
3187 | sPAPRMachineState *spapr) | |
af81cf32 BR |
3188 | { |
3189 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3190 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2e886fb3 | 3191 | int id = spapr_vcpu_id(cpu); |
af81cf32 BR |
3192 | void *fdt; |
3193 | int offset, fdt_size; | |
3194 | char *nodename; | |
3195 | ||
3196 | fdt = create_device_tree(&fdt_size); | |
3197 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3198 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3199 | ||
3200 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
3201 | g_free(nodename); | |
3202 | ||
3203 | *fdt_offset = offset; | |
3204 | return fdt; | |
3205 | } | |
3206 | ||
765d1bdd DG |
3207 | /* Callback to be called during DRC release. */ |
3208 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3209 | { |
765d1bdd | 3210 | MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); |
46f7afa3 | 3211 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3212 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3213 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3214 | |
46f7afa3 GK |
3215 | if (smc->pre_2_10_has_unused_icps) { |
3216 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
46f7afa3 GK |
3217 | int i; |
3218 | ||
3219 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3220 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3221 | |
3222 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3223 | } | |
3224 | } | |
3225 | ||
07572c06 | 3226 | assert(core_slot); |
535455fd | 3227 | core_slot->cpu = NULL; |
ff9006dd IM |
3228 | object_unparent(OBJECT(dev)); |
3229 | } | |
3230 | ||
115debf2 IM |
3231 | static |
3232 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3233 | Error **errp) | |
ff9006dd | 3234 | { |
535455fd IM |
3235 | int index; |
3236 | sPAPRDRConnector *drc; | |
535455fd IM |
3237 | CPUCore *cc = CPU_CORE(dev); |
3238 | int smt = kvmppc_smt_threads(); | |
ff9006dd | 3239 | |
535455fd IM |
3240 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3241 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3242 | cc->core_id); | |
3243 | return; | |
3244 | } | |
ff9006dd IM |
3245 | if (index == 0) { |
3246 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3247 | return; | |
3248 | } | |
3249 | ||
fbf55397 | 3250 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd IM |
3251 | g_assert(drc); |
3252 | ||
a8dc47fd | 3253 | spapr_drc_detach(drc); |
ff9006dd IM |
3254 | |
3255 | spapr_hotplug_req_remove_by_index(drc); | |
3256 | } | |
3257 | ||
3258 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3259 | Error **errp) | |
3260 | { | |
3261 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3262 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3263 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3264 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3265 | CPUCore *cc = CPU_CORE(dev); | |
94ad93bd | 3266 | CPUState *cs = CPU(core->threads[0]); |
ff9006dd IM |
3267 | sPAPRDRConnector *drc; |
3268 | Error *local_err = NULL; | |
ff9006dd | 3269 | int smt = kvmppc_smt_threads(); |
535455fd IM |
3270 | CPUArchId *core_slot; |
3271 | int index; | |
94fd9cba | 3272 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3273 | |
535455fd IM |
3274 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3275 | if (!core_slot) { | |
3276 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3277 | cc->core_id); | |
3278 | return; | |
3279 | } | |
fbf55397 | 3280 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); |
ff9006dd | 3281 | |
c5514d0e | 3282 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3283 | |
ff9006dd | 3284 | if (drc) { |
e49c63d5 GK |
3285 | void *fdt; |
3286 | int fdt_offset; | |
3287 | ||
3288 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3289 | ||
5c1da812 | 3290 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3291 | if (local_err) { |
3292 | g_free(fdt); | |
ff9006dd IM |
3293 | error_propagate(errp, local_err); |
3294 | return; | |
3295 | } | |
ff9006dd | 3296 | |
94fd9cba LV |
3297 | if (hotplugged) { |
3298 | /* | |
3299 | * Send hotplug notification interrupt to the guest only | |
3300 | * in case of hotplugged CPUs. | |
3301 | */ | |
3302 | spapr_hotplug_req_add_by_index(drc); | |
3303 | } else { | |
3304 | spapr_drc_reset(drc); | |
3305 | } | |
ff9006dd | 3306 | } |
94fd9cba | 3307 | |
535455fd | 3308 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3309 | |
3310 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 GK |
3311 | int i; |
3312 | ||
3313 | for (i = 0; i < cc->nr_threads; i++) { | |
3314 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); | |
46f7afa3 | 3315 | |
94ad93bd | 3316 | cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3317 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3318 | } | |
3319 | } | |
ff9006dd IM |
3320 | } |
3321 | ||
3322 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3323 | Error **errp) | |
3324 | { | |
3325 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3326 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3327 | Error *local_err = NULL; |
3328 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3329 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3330 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3331 | CPUArchId *core_slot; |
3332 | int index; | |
ff9006dd | 3333 | |
c5514d0e | 3334 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3335 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3336 | goto out; | |
3337 | } | |
3338 | ||
3339 | if (strcmp(base_core_type, type)) { | |
3340 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3341 | goto out; | |
3342 | } | |
3343 | ||
3344 | if (cc->core_id % smp_threads) { | |
3345 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3346 | goto out; | |
3347 | } | |
3348 | ||
459264ef DG |
3349 | /* |
3350 | * In general we should have homogeneous threads-per-core, but old | |
3351 | * (pre hotplug support) machine types allow the last core to have | |
3352 | * reduced threads as a compatibility hack for when we allowed | |
3353 | * total vcpus not a multiple of threads-per-core. | |
3354 | */ | |
3355 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3356 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3357 | cc->nr_threads, smp_threads); |
df8658de | 3358 | goto out; |
8149e299 DG |
3359 | } |
3360 | ||
535455fd IM |
3361 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3362 | if (!core_slot) { | |
ff9006dd IM |
3363 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3364 | goto out; | |
3365 | } | |
3366 | ||
535455fd | 3367 | if (core_slot->cpu) { |
ff9006dd IM |
3368 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3369 | goto out; | |
3370 | } | |
3371 | ||
a0ceb640 | 3372 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3373 | |
ff9006dd | 3374 | out: |
ff9006dd IM |
3375 | error_propagate(errp, local_err); |
3376 | } | |
3377 | ||
c20d332a BR |
3378 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3379 | DeviceState *dev, Error **errp) | |
3380 | { | |
c86c1aff DHB |
3381 | MachineState *ms = MACHINE(hotplug_dev); |
3382 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); | |
c20d332a BR |
3383 | |
3384 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 3385 | int node; |
c20d332a BR |
3386 | |
3387 | if (!smc->dr_lmb_enabled) { | |
3388 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3389 | return; | |
3390 | } | |
9ed442b8 | 3391 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); |
c20d332a BR |
3392 | if (*errp) { |
3393 | return; | |
3394 | } | |
1a5512bb GA |
3395 | if (node < 0 || node >= MAX_NODES) { |
3396 | error_setg(errp, "Invaild node %d", node); | |
3397 | return; | |
3398 | } | |
c20d332a | 3399 | |
b556854b BR |
3400 | /* |
3401 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
3402 | * memory-less node, but instead will silently add the memory | |
3403 | * to the first node that has some memory. This causes two | |
3404 | * unexpected behaviours for the user. | |
3405 | * | |
3406 | * - Memory gets hotplugged to a different node than what the user | |
3407 | * specified. | |
3408 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
3409 | * to memory-less node, a reboot will set things accordingly | |
3410 | * and the previously hotplugged memory now ends in the right node. | |
3411 | * This appears as if some memory moved from one node to another. | |
3412 | * | |
3413 | * So until kernel starts supporting memory hotplug to memory-less | |
3414 | * nodes, just prevent such attempts upfront in QEMU. | |
3415 | */ | |
3416 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
3417 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
3418 | node); | |
3419 | return; | |
3420 | } | |
3421 | ||
c20d332a | 3422 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
3423 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3424 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3425 | } |
3426 | } | |
3427 | ||
cf632463 BR |
3428 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3429 | DeviceState *dev, Error **errp) | |
3430 | { | |
c86c1aff DHB |
3431 | sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3432 | MachineClass *mc = MACHINE_GET_CLASS(sms); | |
cf632463 BR |
3433 | |
3434 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3435 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3436 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3437 | } else { | |
3438 | /* NOTE: this means there is a window after guest reset, prior to | |
3439 | * CAS negotiation, where unplug requests will fail due to the | |
3440 | * capability not being detected yet. This is a bit different than | |
3441 | * the case with PCI unplug, where the events will be queued and | |
3442 | * eventually handled by the guest after boot | |
3443 | */ | |
3444 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3445 | } | |
6f4b5c3e | 3446 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3447 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3448 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3449 | return; | |
3450 | } | |
115debf2 | 3451 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3452 | } |
3453 | } | |
3454 | ||
94a94e4c BR |
3455 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3456 | DeviceState *dev, Error **errp) | |
3457 | { | |
c871bc70 LV |
3458 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3459 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3460 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3461 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3462 | } | |
3463 | } | |
3464 | ||
7ebaf795 BR |
3465 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3466 | DeviceState *dev) | |
c20d332a | 3467 | { |
94a94e4c BR |
3468 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3469 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3470 | return HOTPLUG_HANDLER(machine); |
3471 | } | |
3472 | return NULL; | |
3473 | } | |
3474 | ||
ea089eeb IM |
3475 | static CpuInstanceProperties |
3476 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3477 | { |
ea089eeb IM |
3478 | CPUArchId *core_slot; |
3479 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3480 | ||
3481 | /* make sure possible_cpu are intialized */ | |
3482 | mc->possible_cpu_arch_ids(machine); | |
3483 | /* get CPU core slot containing thread that matches cpu_index */ | |
3484 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3485 | assert(core_slot); | |
3486 | return core_slot->props; | |
20bb648d DG |
3487 | } |
3488 | ||
79e07936 IM |
3489 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
3490 | { | |
3491 | return idx / smp_cores % nb_numa_nodes; | |
3492 | } | |
3493 | ||
535455fd IM |
3494 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3495 | { | |
3496 | int i; | |
3497 | int spapr_max_cores = max_cpus / smp_threads; | |
3498 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3499 | ||
c5514d0e | 3500 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3501 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3502 | } | |
3503 | if (machine->possible_cpus) { | |
3504 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3505 | return machine->possible_cpus; | |
3506 | } | |
3507 | ||
3508 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
3509 | sizeof(CPUArchId) * spapr_max_cores); | |
3510 | machine->possible_cpus->len = spapr_max_cores; | |
3511 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3512 | int core_id = i * smp_threads; | |
3513 | ||
f2d672c2 | 3514 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3515 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3516 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3517 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
3518 | } |
3519 | return machine->possible_cpus; | |
3520 | } | |
3521 | ||
6737d9ad | 3522 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3523 | uint64_t *buid, hwaddr *pio, |
3524 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3525 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3526 | { | |
357d1e3b DG |
3527 | /* |
3528 | * New-style PHB window placement. | |
3529 | * | |
3530 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3531 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3532 | * windows. | |
3533 | * | |
3534 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3535 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3536 | * | |
3537 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3538 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3539 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3540 | * 1TiB 64-bit MMIO windows for each PHB. | |
3541 | */ | |
6737d9ad | 3542 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3543 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3544 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3545 | int i; |
3546 | ||
357d1e3b DG |
3547 | /* Sanity check natural alignments */ |
3548 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3549 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3550 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3551 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3552 | /* Sanity check bounds */ | |
25e6a118 MT |
3553 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3554 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3555 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3556 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3557 | ||
3558 | if (index >= SPAPR_MAX_PHBS) { | |
3559 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3560 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3561 | return; |
3562 | } | |
3563 | ||
3564 | *buid = base_buid + index; | |
3565 | for (i = 0; i < n_dma; ++i) { | |
3566 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3567 | } | |
3568 | ||
357d1e3b DG |
3569 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3570 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3571 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3572 | } |
3573 | ||
7844e12b CLG |
3574 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3575 | { | |
3576 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3577 | ||
3578 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3579 | } | |
3580 | ||
3581 | static void spapr_ics_resend(XICSFabric *dev) | |
3582 | { | |
3583 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3584 | ||
3585 | ics_resend(spapr->ics); | |
3586 | } | |
3587 | ||
81210c20 | 3588 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 3589 | { |
2e886fb3 | 3590 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 3591 | |
5bc8d26d | 3592 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3593 | } |
3594 | ||
60c6823b CLG |
3595 | #define ICS_IRQ_FREE(ics, srcno) \ |
3596 | (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) | |
3597 | ||
3598 | static int ics_find_free_block(ICSState *ics, int num, int alignnum) | |
3599 | { | |
3600 | int first, i; | |
3601 | ||
3602 | for (first = 0; first < ics->nr_irqs; first += alignnum) { | |
3603 | if (num > (ics->nr_irqs - first)) { | |
3604 | return -1; | |
3605 | } | |
3606 | for (i = first; i < first + num; ++i) { | |
3607 | if (!ICS_IRQ_FREE(ics, i)) { | |
3608 | break; | |
3609 | } | |
3610 | } | |
3611 | if (i == (first + num)) { | |
3612 | return first; | |
3613 | } | |
3614 | } | |
3615 | ||
3616 | return -1; | |
3617 | } | |
3618 | ||
9e7dc5fc CLG |
3619 | /* |
3620 | * Allocate the IRQ number and set the IRQ type, LSI or MSI | |
3621 | */ | |
3622 | static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi) | |
3623 | { | |
3624 | ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi); | |
3625 | } | |
3626 | ||
60c6823b CLG |
3627 | int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, |
3628 | Error **errp) | |
3629 | { | |
3630 | ICSState *ics = spapr->ics; | |
3631 | int irq; | |
3632 | ||
3633 | if (!ics) { | |
3634 | return -1; | |
3635 | } | |
3636 | if (irq_hint) { | |
3637 | if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { | |
3638 | error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); | |
3639 | return -1; | |
3640 | } | |
3641 | irq = irq_hint; | |
3642 | } else { | |
3643 | irq = ics_find_free_block(ics, 1, 1); | |
3644 | if (irq < 0) { | |
3645 | error_setg(errp, "can't allocate IRQ: no IRQ left"); | |
3646 | return -1; | |
3647 | } | |
3648 | irq += ics->offset; | |
3649 | } | |
3650 | ||
9e7dc5fc | 3651 | spapr_irq_set_lsi(spapr, irq, lsi); |
60c6823b CLG |
3652 | trace_spapr_irq_alloc(irq); |
3653 | ||
3654 | return irq; | |
3655 | } | |
3656 | ||
3657 | /* | |
3658 | * Allocate block of consecutive IRQs, and return the number of the first IRQ in | |
3659 | * the block. If align==true, aligns the first IRQ number to num. | |
3660 | */ | |
3661 | int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, | |
3662 | bool align, Error **errp) | |
3663 | { | |
3664 | ICSState *ics = spapr->ics; | |
3665 | int i, first = -1; | |
3666 | ||
3667 | if (!ics) { | |
3668 | return -1; | |
3669 | } | |
3670 | ||
3671 | /* | |
3672 | * MSIMesage::data is used for storing VIRQ so | |
3673 | * it has to be aligned to num to support multiple | |
3674 | * MSI vectors. MSI-X is not affected by this. | |
3675 | * The hint is used for the first IRQ, the rest should | |
3676 | * be allocated continuously. | |
3677 | */ | |
3678 | if (align) { | |
3679 | assert((num == 1) || (num == 2) || (num == 4) || | |
3680 | (num == 8) || (num == 16) || (num == 32)); | |
3681 | first = ics_find_free_block(ics, num, num); | |
3682 | } else { | |
3683 | first = ics_find_free_block(ics, num, 1); | |
3684 | } | |
3685 | if (first < 0) { | |
3686 | error_setg(errp, "can't find a free %d-IRQ block", num); | |
3687 | return -1; | |
3688 | } | |
3689 | ||
9e7dc5fc | 3690 | first += ics->offset; |
60c6823b | 3691 | for (i = first; i < first + num; ++i) { |
9e7dc5fc | 3692 | spapr_irq_set_lsi(spapr, i, lsi); |
60c6823b | 3693 | } |
60c6823b CLG |
3694 | |
3695 | trace_spapr_irq_alloc_block(first, num, lsi, align); | |
3696 | ||
3697 | return first; | |
3698 | } | |
3699 | ||
3700 | void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) | |
3701 | { | |
3702 | ICSState *ics = spapr->ics; | |
3703 | int srcno = irq - ics->offset; | |
3704 | int i; | |
3705 | ||
3706 | if (ics_valid_irq(ics, irq)) { | |
3707 | trace_spapr_irq_free(0, irq, num); | |
3708 | for (i = srcno; i < srcno + num; ++i) { | |
3709 | if (ICS_IRQ_FREE(ics, i)) { | |
3710 | trace_spapr_irq_free_warn(0, i + ics->offset); | |
3711 | } | |
3712 | memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); | |
3713 | } | |
3714 | } | |
3715 | } | |
3716 | ||
77183755 CLG |
3717 | qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) |
3718 | { | |
3719 | ICSState *ics = spapr->ics; | |
3720 | ||
3721 | if (ics_valid_irq(ics, irq)) { | |
3722 | return ics->qirqs[irq - ics->offset]; | |
3723 | } | |
3724 | ||
3725 | return NULL; | |
3726 | } | |
3727 | ||
6449da45 CLG |
3728 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3729 | Monitor *mon) | |
3730 | { | |
3731 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
5bc8d26d CLG |
3732 | CPUState *cs; |
3733 | ||
3734 | CPU_FOREACH(cs) { | |
3735 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
6449da45 | 3736 | |
5bc8d26d | 3737 | icp_pic_print_info(ICP(cpu->intc), mon); |
6449da45 CLG |
3738 | } |
3739 | ||
3740 | ics_pic_print_info(spapr->ics, mon); | |
3741 | } | |
3742 | ||
2e886fb3 SB |
3743 | int spapr_vcpu_id(PowerPCCPU *cpu) |
3744 | { | |
3745 | CPUState *cs = CPU(cpu); | |
3746 | ||
3747 | if (kvm_enabled()) { | |
3748 | return kvm_arch_vcpu_id(cs); | |
3749 | } else { | |
3750 | return cs->cpu_index; | |
3751 | } | |
3752 | } | |
3753 | ||
3754 | PowerPCCPU *spapr_find_cpu(int vcpu_id) | |
3755 | { | |
3756 | CPUState *cs; | |
3757 | ||
3758 | CPU_FOREACH(cs) { | |
3759 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3760 | ||
3761 | if (spapr_vcpu_id(cpu) == vcpu_id) { | |
3762 | return cpu; | |
3763 | } | |
3764 | } | |
3765 | ||
3766 | return NULL; | |
3767 | } | |
3768 | ||
29ee3247 AK |
3769 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3770 | { | |
3771 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3772 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3773 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3774 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3775 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3776 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3777 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3778 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3779 | |
0eb9054c | 3780 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
3781 | |
3782 | /* | |
3783 | * We set up the default / latest behaviour here. The class_init | |
3784 | * functions for the specific versioned machine types can override | |
3785 | * these details for backwards compatibility | |
3786 | */ | |
bcb5ce08 DG |
3787 | mc->init = spapr_machine_init; |
3788 | mc->reset = spapr_machine_reset; | |
958db90c | 3789 | mc->block_default_type = IF_SCSI; |
6244bb7e | 3790 | mc->max_cpus = 1024; |
958db90c | 3791 | mc->no_parallel = 1; |
5b2128d2 | 3792 | mc->default_boot_order = ""; |
a34944fe | 3793 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 3794 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 3795 | mc->has_dynamic_sysbus = true; |
e4024630 | 3796 | mc->pci_allow_0_address = true; |
7ebaf795 | 3797 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3798 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 3799 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 3800 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 3801 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 3802 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3803 | hc->unplug_request = spapr_machine_device_unplug_request; |
00b4fbe2 | 3804 | |
fc9f38c3 | 3805 | smc->dr_lmb_enabled = true; |
2e9c10eb | 3806 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
c5514d0e | 3807 | mc->has_hotpluggable_cpus = true; |
52b81ab5 | 3808 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 3809 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3810 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3811 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3812 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3813 | vhc->hpt_mask = spapr_hpt_mask; |
3814 | vhc->map_hptes = spapr_map_hptes; | |
3815 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3816 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3817 | vhc->get_patbe = spapr_get_patbe; |
1ec26c75 | 3818 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
7844e12b CLG |
3819 | xic->ics_get = spapr_ics_get; |
3820 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3821 | xic->icp_get = spapr_icp_get; |
6449da45 | 3822 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3823 | /* Force NUMA node memory size to be a multiple of |
3824 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3825 | * in which LMBs are represented and hot-added | |
3826 | */ | |
3827 | mc->numa_mem_align_shift = 28; | |
33face6b DG |
3828 | |
3829 | smc->default_caps = spapr_caps(0); | |
3830 | spapr_caps_add_properties(smc, &error_abort); | |
29ee3247 AK |
3831 | } |
3832 | ||
3833 | static const TypeInfo spapr_machine_info = { | |
3834 | .name = TYPE_SPAPR_MACHINE, | |
3835 | .parent = TYPE_MACHINE, | |
4aee7362 | 3836 | .abstract = true, |
6ca1502e | 3837 | .instance_size = sizeof(sPAPRMachineState), |
bcb5ce08 | 3838 | .instance_init = spapr_instance_init, |
87bbdd9c | 3839 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3840 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3841 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3842 | .interfaces = (InterfaceInfo[]) { |
3843 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3844 | { TYPE_NMI }, |
c20d332a | 3845 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3846 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3847 | { TYPE_XICS_FABRIC }, |
6449da45 | 3848 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3849 | { } |
3850 | }, | |
29ee3247 AK |
3851 | }; |
3852 | ||
fccbc785 | 3853 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3854 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3855 | void *data) \ | |
3856 | { \ | |
3857 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3858 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3859 | if (latest) { \ |
3860 | mc->alias = "pseries"; \ | |
3861 | mc->is_default = 1; \ | |
3862 | } \ | |
5013c547 DG |
3863 | } \ |
3864 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
3865 | { \ | |
3866 | MachineState *machine = MACHINE(obj); \ | |
3867 | spapr_machine_##suffix##_instance_options(machine); \ | |
3868 | } \ | |
3869 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
3870 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3871 | .parent = TYPE_SPAPR_MACHINE, \ | |
3872 | .class_init = spapr_machine_##suffix##_class_init, \ | |
3873 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
3874 | }; \ | |
3875 | static void spapr_machine_register_##suffix(void) \ | |
3876 | { \ | |
3877 | type_register(&spapr_machine_##suffix##_info); \ | |
3878 | } \ | |
0e6aac87 | 3879 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3880 | |
2b615412 DG |
3881 | /* |
3882 | * pseries-2.12 | |
3883 | */ | |
3884 | static void spapr_machine_2_12_instance_options(MachineState *machine) | |
3885 | { | |
3886 | } | |
3887 | ||
3888 | static void spapr_machine_2_12_class_options(MachineClass *mc) | |
3889 | { | |
3890 | /* Defaults for the latest behaviour inherited from the base class */ | |
3891 | } | |
3892 | ||
3893 | DEFINE_SPAPR_MACHINE(2_12, "2.12", true); | |
3894 | ||
e2676b16 GK |
3895 | /* |
3896 | * pseries-2.11 | |
3897 | */ | |
2b615412 DG |
3898 | #define SPAPR_COMPAT_2_11 \ |
3899 | HW_COMPAT_2_11 | |
3900 | ||
e2676b16 GK |
3901 | static void spapr_machine_2_11_instance_options(MachineState *machine) |
3902 | { | |
2b615412 | 3903 | spapr_machine_2_12_instance_options(machine); |
e2676b16 GK |
3904 | } |
3905 | ||
3906 | static void spapr_machine_2_11_class_options(MachineClass *mc) | |
3907 | { | |
ee76a09f DG |
3908 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3909 | ||
2b615412 | 3910 | spapr_machine_2_12_class_options(mc); |
ee76a09f | 3911 | smc->default_caps = spapr_caps(SPAPR_CAP_HTM); |
2b615412 | 3912 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); |
e2676b16 GK |
3913 | } |
3914 | ||
2b615412 | 3915 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 3916 | |
3fa14fbe DG |
3917 | /* |
3918 | * pseries-2.10 | |
3919 | */ | |
e2676b16 | 3920 | #define SPAPR_COMPAT_2_10 \ |
2b615412 | 3921 | HW_COMPAT_2_10 |
e2676b16 | 3922 | |
3fa14fbe DG |
3923 | static void spapr_machine_2_10_instance_options(MachineState *machine) |
3924 | { | |
2b615412 | 3925 | spapr_machine_2_11_instance_options(machine); |
3fa14fbe DG |
3926 | } |
3927 | ||
3928 | static void spapr_machine_2_10_class_options(MachineClass *mc) | |
3929 | { | |
e2676b16 GK |
3930 | spapr_machine_2_11_class_options(mc); |
3931 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); | |
3fa14fbe DG |
3932 | } |
3933 | ||
e2676b16 | 3934 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 3935 | |
fa325e6c DG |
3936 | /* |
3937 | * pseries-2.9 | |
3938 | */ | |
3fa14fbe | 3939 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
3940 | HW_COMPAT_2_9 \ |
3941 | { \ | |
3942 | .driver = TYPE_POWERPC_CPU, \ | |
3943 | .property = "pre-2.10-migration", \ | |
3944 | .value = "on", \ | |
3945 | }, \ | |
3fa14fbe | 3946 | |
fa325e6c DG |
3947 | static void spapr_machine_2_9_instance_options(MachineState *machine) |
3948 | { | |
3fa14fbe | 3949 | spapr_machine_2_10_instance_options(machine); |
fa325e6c DG |
3950 | } |
3951 | ||
3952 | static void spapr_machine_2_9_class_options(MachineClass *mc) | |
3953 | { | |
46f7afa3 GK |
3954 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3955 | ||
3fa14fbe DG |
3956 | spapr_machine_2_10_class_options(mc); |
3957 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 3958 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 3959 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 3960 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
3961 | } |
3962 | ||
3fa14fbe | 3963 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 3964 | |
db800b21 DG |
3965 | /* |
3966 | * pseries-2.8 | |
3967 | */ | |
82516263 DG |
3968 | #define SPAPR_COMPAT_2_8 \ |
3969 | HW_COMPAT_2_8 \ | |
3970 | { \ | |
3971 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3972 | .property = "pcie-extended-configuration-space", \ | |
3973 | .value = "off", \ | |
3974 | }, | |
fa325e6c | 3975 | |
db800b21 DG |
3976 | static void spapr_machine_2_8_instance_options(MachineState *machine) |
3977 | { | |
fa325e6c | 3978 | spapr_machine_2_9_instance_options(machine); |
db800b21 DG |
3979 | } |
3980 | ||
3981 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
3982 | { | |
fa325e6c DG |
3983 | spapr_machine_2_9_class_options(mc); |
3984 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 3985 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
3986 | } |
3987 | ||
fa325e6c | 3988 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 3989 | |
1ea1eefc BR |
3990 | /* |
3991 | * pseries-2.7 | |
3992 | */ | |
357d1e3b DG |
3993 | #define SPAPR_COMPAT_2_7 \ |
3994 | HW_COMPAT_2_7 \ | |
3995 | { \ | |
3996 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
3997 | .property = "mem_win_size", \ | |
3998 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
3999 | }, \ | |
4000 | { \ | |
4001 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4002 | .property = "mem64_win_size", \ | |
4003 | .value = "0", \ | |
146c11f1 DG |
4004 | }, \ |
4005 | { \ | |
4006 | .driver = TYPE_POWERPC_CPU, \ | |
4007 | .property = "pre-2.8-migration", \ | |
4008 | .value = "on", \ | |
5c4537bd DG |
4009 | }, \ |
4010 | { \ | |
4011 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4012 | .property = "pre-2.8-migration", \ | |
4013 | .value = "on", \ | |
357d1e3b DG |
4014 | }, |
4015 | ||
4016 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
4017 | uint64_t *buid, hwaddr *pio, | |
4018 | hwaddr *mmio32, hwaddr *mmio64, | |
4019 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
4020 | { | |
4021 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4022 | const uint64_t base_buid = 0x800000020000000ULL; | |
4023 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4024 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4025 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4026 | const uint32_t max_index = 255; | |
4027 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4028 | ||
4029 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4030 | hwaddr phb0_base, phb_base; | |
4031 | int i; | |
4032 | ||
4033 | /* Do we have hotpluggable memory? */ | |
4034 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
4035 | /* Can't just use maxram_size, because there may be an | |
4036 | * alignment gap between normal and hotpluggable memory | |
4037 | * regions */ | |
4038 | ram_top = spapr->hotplug_memory.base + | |
4039 | memory_region_size(&spapr->hotplug_memory.mr); | |
4040 | } | |
4041 | ||
4042 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4043 | ||
4044 | if (index > max_index) { | |
4045 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4046 | max_index); | |
4047 | return; | |
4048 | } | |
4049 | ||
4050 | *buid = base_buid + index; | |
4051 | for (i = 0; i < n_dma; ++i) { | |
4052 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4053 | } | |
4054 | ||
4055 | phb_base = phb0_base + index * phb_spacing; | |
4056 | *pio = phb_base + pio_offset; | |
4057 | *mmio32 = phb_base + mmio_offset; | |
4058 | /* | |
4059 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4060 | * fallback behaviour of automatically splitting a large "32-bit" | |
4061 | * window into contiguous 32-bit and 64-bit windows | |
4062 | */ | |
4063 | } | |
db800b21 | 4064 | |
1ea1eefc BR |
4065 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
4066 | { | |
f6229214 MR |
4067 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
4068 | ||
672de881 | 4069 | spapr_machine_2_8_instance_options(machine); |
f6229214 | 4070 | spapr->use_hotplug_event_source = false; |
1ea1eefc BR |
4071 | } |
4072 | ||
4073 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
4074 | { | |
3daa4a9f TH |
4075 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4076 | ||
db800b21 | 4077 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4078 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
db800b21 | 4079 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 4080 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4081 | } |
4082 | ||
db800b21 | 4083 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4084 | |
4b23699c DG |
4085 | /* |
4086 | * pseries-2.6 | |
4087 | */ | |
1ea1eefc | 4088 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
4089 | HW_COMPAT_2_6 \ |
4090 | { \ | |
4091 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4092 | .property = "ddw",\ | |
4093 | .value = stringify(off),\ | |
4094 | }, | |
1ea1eefc | 4095 | |
4b23699c DG |
4096 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
4097 | { | |
672de881 | 4098 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
4099 | } |
4100 | ||
4101 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
4102 | { | |
1ea1eefc | 4103 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4104 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 4105 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
4106 | } |
4107 | ||
1ea1eefc | 4108 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4109 | |
1c5f29bb DG |
4110 | /* |
4111 | * pseries-2.5 | |
4112 | */ | |
4b23699c | 4113 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
4114 | HW_COMPAT_2_5 \ |
4115 | { \ | |
4116 | .driver = "spapr-vlan", \ | |
4117 | .property = "use-rx-buffer-pools", \ | |
4118 | .value = "off", \ | |
4119 | }, | |
4b23699c | 4120 | |
5013c547 | 4121 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 4122 | { |
672de881 | 4123 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
4124 | } |
4125 | ||
4126 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
4127 | { | |
57040d45 TH |
4128 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4129 | ||
4b23699c | 4130 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4131 | smc->use_ohci_by_default = true; |
4b23699c | 4132 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
4133 | } |
4134 | ||
4b23699c | 4135 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4136 | |
4137 | /* | |
4138 | * pseries-2.4 | |
4139 | */ | |
80fd50f9 CH |
4140 | #define SPAPR_COMPAT_2_4 \ |
4141 | HW_COMPAT_2_4 | |
4142 | ||
5013c547 | 4143 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 4144 | { |
5013c547 DG |
4145 | spapr_machine_2_5_instance_options(machine); |
4146 | } | |
1c5f29bb | 4147 | |
5013c547 DG |
4148 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4149 | { | |
fc9f38c3 DG |
4150 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4151 | ||
4152 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4153 | smc->dr_lmb_enabled = false; |
f949b4e5 | 4154 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
4155 | } |
4156 | ||
fccbc785 | 4157 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4158 | |
4159 | /* | |
4160 | * pseries-2.3 | |
4161 | */ | |
38ff32c6 | 4162 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
4163 | HW_COMPAT_2_3 \ |
4164 | {\ | |
4165 | .driver = "spapr-pci-host-bridge",\ | |
4166 | .property = "dynamic-reconfiguration",\ | |
4167 | .value = "off",\ | |
4168 | }, | |
38ff32c6 | 4169 | |
5013c547 | 4170 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 4171 | { |
5013c547 | 4172 | spapr_machine_2_4_instance_options(machine); |
d25228e7 JW |
4173 | } |
4174 | ||
5013c547 | 4175 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4176 | { |
fc9f38c3 | 4177 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 4178 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 4179 | } |
fccbc785 | 4180 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4181 | |
1c5f29bb DG |
4182 | /* |
4183 | * pseries-2.2 | |
4184 | */ | |
4185 | ||
4186 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
4187 | HW_COMPAT_2_2 \ |
4188 | {\ | |
4189 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4190 | .property = "mem_win_size",\ | |
4191 | .value = "0x20000000",\ | |
4192 | }, | |
4193 | ||
5013c547 | 4194 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 4195 | { |
5013c547 | 4196 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 4197 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
4198 | } |
4199 | ||
5013c547 | 4200 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4201 | { |
fc9f38c3 | 4202 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 4203 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 4204 | } |
fccbc785 | 4205 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4206 | |
1c5f29bb DG |
4207 | /* |
4208 | * pseries-2.1 | |
4209 | */ | |
4210 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 4211 | HW_COMPAT_2_1 |
3dab0244 | 4212 | |
5013c547 | 4213 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 4214 | { |
5013c547 | 4215 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 4216 | } |
d25228e7 | 4217 | |
5013c547 | 4218 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4219 | { |
fc9f38c3 | 4220 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 4221 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 4222 | } |
fccbc785 | 4223 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4224 | |
29ee3247 | 4225 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4226 | { |
29ee3247 | 4227 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4228 | } |
4229 | ||
29ee3247 | 4230 | type_init(spapr_machine_register_types) |