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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
e35704ba | 30 | #include "sysemu/numa.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
03dd024f | 32 | #include "qemu/log.h" |
71461b0f | 33 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 34 | #include "elf.h" |
1422e32d | 35 | #include "net/net.h" |
ad440b4a | 36 | #include "sysemu/device_tree.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 PB |
38 | #include "sysemu/cpus.h" |
39 | #include "sysemu/kvm.h" | |
c20d332a | 40 | #include "sysemu/device_tree.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
ff14e817 | 42 | #include "migration/migration.h" |
4be21d56 | 43 | #include "mmu-hash64.h" |
3794d548 | 44 | #include "qom/cpu.h" |
9fdf0c29 DG |
45 | |
46 | #include "hw/boards.h" | |
0d09e41a | 47 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
48 | #include "hw/loader.h" |
49 | ||
7804c353 | 50 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
51 | #include "hw/ppc/spapr.h" |
52 | #include "hw/ppc/spapr_vio.h" | |
53 | #include "hw/pci-host/spapr.h" | |
54 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 55 | #include "hw/pci/msi.h" |
9fdf0c29 | 56 | |
83c9f4ca | 57 | #include "hw/pci/pci.h" |
71461b0f AK |
58 | #include "hw/scsi/scsi.h" |
59 | #include "hw/virtio/virtio-scsi.h" | |
f61b4bed | 60 | |
022c62cb | 61 | #include "exec/address-spaces.h" |
35139a59 | 62 | #include "hw/usb.h" |
1de7afc9 | 63 | #include "qemu/config-file.h" |
135a129a | 64 | #include "qemu/error-report.h" |
2a6593cb | 65 | #include "trace.h" |
34316482 | 66 | #include "hw/nmi.h" |
890c2b77 | 67 | |
68a27b20 | 68 | #include "hw/compat.h" |
f348b6d1 | 69 | #include "qemu/cutils.h" |
94a94e4c | 70 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 71 | #include "qmp-commands.h" |
68a27b20 | 72 | |
9fdf0c29 DG |
73 | #include <libfdt.h> |
74 | ||
4d8d5467 BH |
75 | /* SLOF memory layout: |
76 | * | |
77 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
78 | * device-tree, then position SLOF itself 31M below that | |
79 | * | |
80 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
81 | * and more | |
82 | * | |
83 | * We load our kernel at 4M, leaving space for SLOF initial image | |
84 | */ | |
38b02bd8 | 85 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 86 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 87 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
88 | #define FW_MAX_SIZE 0x400000 |
89 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
90 | #define FW_OVERHEAD 0x2800000 |
91 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 92 | |
4d8d5467 | 93 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 94 | |
0c103f8e DG |
95 | #define PHANDLE_XICP 0x00001111 |
96 | ||
7f763a5d DG |
97 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
98 | ||
c04d6cfa | 99 | static XICSState *try_create_xics(const char *type, int nr_servers, |
34f2af3d | 100 | int nr_irqs, Error **errp) |
c04d6cfa | 101 | { |
34f2af3d | 102 | Error *err = NULL; |
c04d6cfa AL |
103 | DeviceState *dev; |
104 | ||
105 | dev = qdev_create(NULL, type); | |
106 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
107 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
34f2af3d MA |
108 | object_property_set_bool(OBJECT(dev), true, "realized", &err); |
109 | if (err) { | |
110 | error_propagate(errp, err); | |
111 | object_unparent(OBJECT(dev)); | |
c04d6cfa AL |
112 | return NULL; |
113 | } | |
5a3d7b23 | 114 | return XICS_COMMON(dev); |
c04d6cfa AL |
115 | } |
116 | ||
446f16a6 | 117 | static XICSState *xics_system_init(MachineState *machine, |
1e49182d | 118 | int nr_servers, int nr_irqs, Error **errp) |
c04d6cfa | 119 | { |
27f24582 | 120 | XICSState *xics = NULL; |
c04d6cfa | 121 | |
11ad93f6 | 122 | if (kvm_enabled()) { |
34f2af3d MA |
123 | Error *err = NULL; |
124 | ||
446f16a6 | 125 | if (machine_kernel_irqchip_allowed(machine)) { |
27f24582 BH |
126 | xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, |
127 | &err); | |
11ad93f6 | 128 | } |
27f24582 | 129 | if (machine_kernel_irqchip_required(machine) && !xics) { |
b83baa60 MA |
130 | error_reportf_err(err, |
131 | "kernel_irqchip requested but unavailable: "); | |
132 | } else { | |
133 | error_free(err); | |
11ad93f6 DG |
134 | } |
135 | } | |
136 | ||
27f24582 BH |
137 | if (!xics) { |
138 | xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); | |
c04d6cfa AL |
139 | } |
140 | ||
27f24582 | 141 | return xics; |
c04d6cfa AL |
142 | } |
143 | ||
833d4668 AK |
144 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
145 | int smt_threads) | |
146 | { | |
147 | int i, ret = 0; | |
148 | uint32_t servers_prop[smt_threads]; | |
149 | uint32_t gservers_prop[smt_threads * 2]; | |
150 | int index = ppc_get_vcpu_dt_id(cpu); | |
151 | ||
6d9412ea | 152 | if (cpu->cpu_version) { |
4bce526e | 153 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); |
6d9412ea AK |
154 | if (ret < 0) { |
155 | return ret; | |
156 | } | |
157 | } | |
158 | ||
833d4668 AK |
159 | /* Build interrupt servers and gservers properties */ |
160 | for (i = 0; i < smt_threads; i++) { | |
161 | servers_prop[i] = cpu_to_be32(index + i); | |
162 | /* Hack, direct the group queues back to cpu 0 */ | |
163 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
164 | gservers_prop[i*2 + 1] = 0; | |
165 | } | |
166 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
167 | servers_prop, sizeof(servers_prop)); | |
168 | if (ret < 0) { | |
169 | return ret; | |
170 | } | |
171 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
172 | gservers_prop, sizeof(gservers_prop)); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
0da6f3fe BR |
177 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) |
178 | { | |
179 | int ret = 0; | |
180 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
181 | int index = ppc_get_vcpu_dt_id(cpu); | |
182 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
183 | cpu_to_be32(0x0), | |
184 | cpu_to_be32(0x0), | |
185 | cpu_to_be32(0x0), | |
186 | cpu_to_be32(cs->numa_node), | |
187 | cpu_to_be32(index)}; | |
188 | ||
189 | /* Advertise NUMA via ibm,associativity */ | |
190 | if (nb_numa_nodes > 1) { | |
191 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
192 | sizeof(associativity)); | |
193 | } | |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
28e02042 | 198 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 199 | { |
82677ed2 AK |
200 | int ret = 0, offset, cpus_offset; |
201 | CPUState *cs; | |
6e806cc3 BR |
202 | char cpu_model[32]; |
203 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 204 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 205 | |
82677ed2 AK |
206 | CPU_FOREACH(cs) { |
207 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
208 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
209 | int index = ppc_get_vcpu_dt_id(cpu); | |
6e806cc3 | 210 | |
0f20ba62 | 211 | if ((index % smt) != 0) { |
6e806cc3 BR |
212 | continue; |
213 | } | |
214 | ||
82677ed2 | 215 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 216 | |
82677ed2 AK |
217 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
218 | if (cpus_offset < 0) { | |
219 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
220 | "cpus"); | |
221 | if (cpus_offset < 0) { | |
222 | return cpus_offset; | |
223 | } | |
224 | } | |
225 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 226 | if (offset < 0) { |
82677ed2 AK |
227 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
228 | if (offset < 0) { | |
229 | return offset; | |
230 | } | |
6e806cc3 BR |
231 | } |
232 | ||
7f763a5d DG |
233 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
234 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
235 | if (ret < 0) { |
236 | return ret; | |
237 | } | |
833d4668 | 238 | |
0da6f3fe BR |
239 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); |
240 | if (ret < 0) { | |
241 | return ret; | |
242 | } | |
243 | ||
82677ed2 | 244 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, |
2a48d993 | 245 | ppc_get_compat_smt_threads(cpu)); |
833d4668 AK |
246 | if (ret < 0) { |
247 | return ret; | |
248 | } | |
6e806cc3 BR |
249 | } |
250 | return ret; | |
251 | } | |
252 | ||
b082d65a AK |
253 | static hwaddr spapr_node0_size(void) |
254 | { | |
fb164994 DG |
255 | MachineState *machine = MACHINE(qdev_get_machine()); |
256 | ||
b082d65a AK |
257 | if (nb_numa_nodes) { |
258 | int i; | |
259 | for (i = 0; i < nb_numa_nodes; ++i) { | |
260 | if (numa_info[i].node_mem) { | |
fb164994 DG |
261 | return MIN(pow2floor(numa_info[i].node_mem), |
262 | machine->ram_size); | |
b082d65a AK |
263 | } |
264 | } | |
265 | } | |
fb164994 | 266 | return machine->ram_size; |
b082d65a AK |
267 | } |
268 | ||
a1d59c0f AK |
269 | static void add_str(GString *s, const gchar *s1) |
270 | { | |
271 | g_string_append_len(s, s1, strlen(s1) + 1); | |
272 | } | |
7f763a5d | 273 | |
a19f7fb0 | 274 | static void *spapr_create_fdt_skel(sPAPRMachineState *spapr) |
9fdf0c29 DG |
275 | { |
276 | void *fdt; | |
ef951443 | 277 | char *buf; |
9fdf0c29 | 278 | |
7267c094 | 279 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
280 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
281 | ||
282 | _FDT((fdt_finish_reservemap(fdt))); | |
283 | ||
284 | /* Root node */ | |
285 | _FDT((fdt_begin_node(fdt, ""))); | |
286 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 287 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 288 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 | 289 | |
ef951443 ND |
290 | /* |
291 | * Add info to guest to indentify which host is it being run on | |
292 | * and what is the uuid of the guest | |
293 | */ | |
294 | if (kvmppc_get_host_model(&buf)) { | |
295 | _FDT((fdt_property_string(fdt, "host-model", buf))); | |
296 | g_free(buf); | |
297 | } | |
298 | if (kvmppc_get_host_serial(&buf)) { | |
299 | _FDT((fdt_property_string(fdt, "host-serial", buf))); | |
300 | g_free(buf); | |
301 | } | |
302 | ||
9c5ce8db | 303 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); |
ef951443 ND |
304 | |
305 | _FDT((fdt_property_string(fdt, "vm,uuid", buf))); | |
3dc0a66d AK |
306 | if (qemu_uuid_set) { |
307 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
308 | } | |
ef951443 ND |
309 | g_free(buf); |
310 | ||
2c1aaa81 SB |
311 | if (qemu_get_vm_name()) { |
312 | _FDT((fdt_property_string(fdt, "ibm,partition-name", | |
313 | qemu_get_vm_name()))); | |
314 | } | |
315 | ||
9fdf0c29 DG |
316 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
317 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
318 | ||
4040ab72 DG |
319 | /* vdevice */ |
320 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
321 | ||
322 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
323 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
324 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
325 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
326 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
327 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
328 | |
329 | _FDT((fdt_end_node(fdt))); | |
330 | ||
9fdf0c29 DG |
331 | _FDT((fdt_end_node(fdt))); /* close root node */ |
332 | _FDT((fdt_finish(fdt))); | |
333 | ||
a3467baa DG |
334 | return fdt; |
335 | } | |
336 | ||
03d196b7 | 337 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
338 | hwaddr size) |
339 | { | |
340 | uint32_t associativity[] = { | |
341 | cpu_to_be32(0x4), /* length */ | |
342 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 343 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
344 | }; |
345 | char mem_name[32]; | |
346 | uint64_t mem_reg_property[2]; | |
347 | int off; | |
348 | ||
349 | mem_reg_property[0] = cpu_to_be64(start); | |
350 | mem_reg_property[1] = cpu_to_be64(size); | |
351 | ||
352 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
353 | off = fdt_add_subnode(fdt, 0, mem_name); | |
354 | _FDT(off); | |
355 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
356 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
357 | sizeof(mem_reg_property)))); | |
358 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
359 | sizeof(associativity)))); | |
03d196b7 | 360 | return off; |
26a8c353 AK |
361 | } |
362 | ||
28e02042 | 363 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 364 | { |
fb164994 | 365 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
366 | hwaddr mem_start, node_size; |
367 | int i, nb_nodes = nb_numa_nodes; | |
368 | NodeInfo *nodes = numa_info; | |
369 | NodeInfo ramnode; | |
370 | ||
371 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
372 | if (!nb_numa_nodes) { | |
373 | nb_nodes = 1; | |
fb164994 | 374 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 375 | nodes = &ramnode; |
5fe269b1 | 376 | } |
7f763a5d | 377 | |
7db8a127 AK |
378 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
379 | if (!nodes[i].node_mem) { | |
380 | continue; | |
381 | } | |
fb164994 | 382 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
383 | node_size = 0; |
384 | } else { | |
7db8a127 | 385 | node_size = nodes[i].node_mem; |
fb164994 DG |
386 | if (node_size > machine->ram_size - mem_start) { |
387 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
388 | } |
389 | } | |
7db8a127 AK |
390 | if (!mem_start) { |
391 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 392 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
393 | mem_start += spapr->rma_size; |
394 | node_size -= spapr->rma_size; | |
395 | } | |
6010818c AK |
396 | for ( ; node_size; ) { |
397 | hwaddr sizetmp = pow2floor(node_size); | |
398 | ||
399 | /* mem_start != 0 here */ | |
400 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
401 | sizetmp = 1ULL << ctzl(mem_start); | |
402 | } | |
403 | ||
404 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
405 | node_size -= sizetmp; | |
406 | mem_start += sizetmp; | |
407 | } | |
7f763a5d DG |
408 | } |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
230bf719 TH |
413 | /* Populate the "ibm,pa-features" property */ |
414 | static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) | |
415 | { | |
416 | uint8_t pa_features_206[] = { 6, 0, | |
417 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
418 | uint8_t pa_features_207[] = { 24, 0, | |
419 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
420 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
421 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
bac3bf28 | 422 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; |
230bf719 TH |
423 | uint8_t *pa_features; |
424 | size_t pa_size; | |
425 | ||
4cbec30d TH |
426 | switch (env->mmu_model) { |
427 | case POWERPC_MMU_2_06: | |
428 | case POWERPC_MMU_2_06a: | |
230bf719 TH |
429 | pa_features = pa_features_206; |
430 | pa_size = sizeof(pa_features_206); | |
4cbec30d TH |
431 | break; |
432 | case POWERPC_MMU_2_07: | |
433 | case POWERPC_MMU_2_07a: | |
230bf719 TH |
434 | pa_features = pa_features_207; |
435 | pa_size = sizeof(pa_features_207); | |
4cbec30d TH |
436 | break; |
437 | default: | |
438 | return; | |
230bf719 TH |
439 | } |
440 | ||
441 | if (env->ci_large_pages) { | |
442 | /* | |
443 | * Note: we keep CI large pages off by default because a 64K capable | |
444 | * guest provisioned with large pages might otherwise try to map a qemu | |
445 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
446 | * even if that qemu runs on a 4k host. | |
447 | * We dd this bit back here if we are confident this is not an issue | |
448 | */ | |
449 | pa_features[3] |= 0x20; | |
450 | } | |
bac3bf28 TH |
451 | if (kvmppc_has_cap_htm() && pa_size > 24) { |
452 | pa_features[24] |= 0x80; /* Transactional memory support */ | |
453 | } | |
230bf719 TH |
454 | |
455 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
456 | } | |
457 | ||
0da6f3fe BR |
458 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
459 | sPAPRMachineState *spapr) | |
460 | { | |
461 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
462 | CPUPPCState *env = &cpu->env; | |
463 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
464 | int index = ppc_get_vcpu_dt_id(cpu); | |
465 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
466 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
467 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
468 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
469 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
470 | uint32_t page_sizes_prop[64]; | |
471 | size_t page_sizes_prop_size; | |
22419c2a | 472 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 473 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
af81cf32 BR |
474 | sPAPRDRConnector *drc; |
475 | sPAPRDRConnectorClass *drck; | |
476 | int drc_index; | |
477 | ||
478 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); | |
479 | if (drc) { | |
480 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
481 | drc_index = drck->get_index(drc); | |
482 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); | |
483 | } | |
0da6f3fe BR |
484 | |
485 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
486 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
487 | ||
488 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
489 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
490 | env->dcache_line_size))); | |
491 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
492 | env->dcache_line_size))); | |
493 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
494 | env->icache_line_size))); | |
495 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
496 | env->icache_line_size))); | |
497 | ||
498 | if (pcc->l1_dcache_size) { | |
499 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
500 | pcc->l1_dcache_size))); | |
501 | } else { | |
ce9863b7 | 502 | error_report("Warning: Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
503 | } |
504 | if (pcc->l1_icache_size) { | |
505 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
506 | pcc->l1_icache_size))); | |
507 | } else { | |
ce9863b7 | 508 | error_report("Warning: Unknown L1 icache size for cpu"); |
0da6f3fe BR |
509 | } |
510 | ||
511 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
512 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 513 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
514 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
515 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
516 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
517 | ||
518 | if (env->spr_cb[SPR_PURR].oea_read) { | |
519 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
520 | } | |
521 | ||
522 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
523 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
524 | segs, sizeof(segs)))); | |
525 | } | |
526 | ||
527 | /* Advertise VMX/VSX (vector extensions) if available | |
528 | * 0 / no property == no vector extensions | |
529 | * 1 == VMX / Altivec available | |
530 | * 2 == VSX available */ | |
531 | if (env->insns_flags & PPC_ALTIVEC) { | |
532 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
533 | ||
534 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
535 | } | |
536 | ||
537 | /* Advertise DFP (Decimal Floating Point) if available | |
538 | * 0 / no property == no DFP | |
539 | * 1 == DFP available */ | |
540 | if (env->insns_flags2 & PPC2_DFP) { | |
541 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
542 | } | |
543 | ||
3654fa95 | 544 | page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, |
0da6f3fe BR |
545 | sizeof(page_sizes_prop)); |
546 | if (page_sizes_prop_size) { | |
547 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
548 | page_sizes_prop, page_sizes_prop_size))); | |
549 | } | |
550 | ||
230bf719 | 551 | spapr_populate_pa_features(env, fdt, offset); |
90da0d5a | 552 | |
0da6f3fe | 553 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 554 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
555 | |
556 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
557 | pft_size_prop, sizeof(pft_size_prop)))); | |
558 | ||
559 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); | |
560 | ||
561 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, | |
562 | ppc_get_compat_smt_threads(cpu))); | |
563 | } | |
564 | ||
565 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
566 | { | |
567 | CPUState *cs; | |
568 | int cpus_offset; | |
569 | char *nodename; | |
570 | int smt = kvmppc_smt_threads(); | |
571 | ||
572 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
573 | _FDT(cpus_offset); | |
574 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
575 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
576 | ||
577 | /* | |
578 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
579 | * created by fdt_add_subnode() end up in the right order in FDT | |
580 | * for the guest kernel the enumerate the CPUs correctly. | |
581 | */ | |
582 | CPU_FOREACH_REVERSE(cs) { | |
583 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
584 | int index = ppc_get_vcpu_dt_id(cpu); | |
585 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
586 | int offset; | |
587 | ||
588 | if ((index % smt) != 0) { | |
589 | continue; | |
590 | } | |
591 | ||
592 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
593 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
594 | g_free(nodename); | |
595 | _FDT(offset); | |
596 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
597 | } | |
598 | ||
599 | } | |
600 | ||
03d196b7 BR |
601 | /* |
602 | * Adds ibm,dynamic-reconfiguration-memory node. | |
603 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
604 | * of this device tree node. | |
605 | */ | |
606 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
607 | { | |
608 | MachineState *machine = MACHINE(spapr); | |
609 | int ret, i, offset; | |
610 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
611 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
612 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
613 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
614 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
615 | lmb_size; | |
03d196b7 | 616 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 617 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 618 | |
16c25aef | 619 | /* |
d0e5a8f2 | 620 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 621 | */ |
d0e5a8f2 | 622 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
623 | return 0; |
624 | } | |
625 | ||
ef001f06 TH |
626 | /* |
627 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
628 | * or ibm,associativity-lookup-arrays | |
629 | */ | |
630 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
631 | * sizeof(uint32_t); | |
03d196b7 BR |
632 | cur_index = int_buf = g_malloc0(buf_len); |
633 | ||
634 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
635 | ||
636 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
637 | sizeof(prop_lmb_size)); | |
638 | if (ret < 0) { | |
639 | goto out; | |
640 | } | |
641 | ||
642 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
643 | if (ret < 0) { | |
644 | goto out; | |
645 | } | |
646 | ||
647 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
648 | if (ret < 0) { | |
649 | goto out; | |
650 | } | |
651 | ||
652 | /* ibm,dynamic-memory */ | |
653 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
654 | cur_index++; | |
655 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 656 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
657 | uint32_t *dynamic_memory = cur_index; |
658 | ||
d0e5a8f2 BR |
659 | if (i >= hotplug_lmb_start) { |
660 | sPAPRDRConnector *drc; | |
661 | sPAPRDRConnectorClass *drck; | |
662 | ||
663 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); | |
664 | g_assert(drc); | |
665 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
666 | ||
667 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
668 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
669 | dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); | |
670 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
671 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
672 | if (memory_region_present(get_system_memory(), addr)) { | |
673 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
674 | } else { | |
675 | dynamic_memory[5] = cpu_to_be32(0); | |
676 | } | |
03d196b7 | 677 | } else { |
d0e5a8f2 BR |
678 | /* |
679 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
680 | * hotplug memory region -- all these are marked as reserved | |
681 | * and as having no valid DRC. | |
682 | */ | |
683 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
684 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
685 | dynamic_memory[2] = cpu_to_be32(0); | |
686 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
687 | dynamic_memory[4] = cpu_to_be32(-1); | |
688 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
689 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
690 | } |
691 | ||
692 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
693 | } | |
694 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
695 | if (ret < 0) { | |
696 | goto out; | |
697 | } | |
698 | ||
699 | /* ibm,associativity-lookup-arrays */ | |
700 | cur_index = int_buf; | |
6663864e | 701 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
702 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
703 | cur_index += 2; | |
6663864e | 704 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
705 | uint32_t associativity[] = { |
706 | cpu_to_be32(0x0), | |
707 | cpu_to_be32(0x0), | |
708 | cpu_to_be32(0x0), | |
709 | cpu_to_be32(i) | |
710 | }; | |
711 | memcpy(cur_index, associativity, sizeof(associativity)); | |
712 | cur_index += 4; | |
713 | } | |
714 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
715 | (cur_index - int_buf) * sizeof(uint32_t)); | |
716 | out: | |
717 | g_free(int_buf); | |
718 | return ret; | |
719 | } | |
720 | ||
721 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, | |
722 | target_ulong addr, target_ulong size, | |
723 | bool cpu_update, bool memory_update) | |
724 | { | |
725 | void *fdt, *fdt_skel; | |
726 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
727 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
728 | ||
729 | size -= sizeof(hdr); | |
730 | ||
731 | /* Create sceleton */ | |
732 | fdt_skel = g_malloc0(size); | |
733 | _FDT((fdt_create(fdt_skel, size))); | |
734 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
735 | _FDT((fdt_end_node(fdt_skel))); | |
736 | _FDT((fdt_finish(fdt_skel))); | |
737 | fdt = g_malloc0(size); | |
738 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
739 | g_free(fdt_skel); | |
740 | ||
741 | /* Fixup cpu nodes */ | |
742 | if (cpu_update) { | |
743 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); | |
744 | } | |
745 | ||
16c25aef | 746 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ |
03d196b7 BR |
747 | if (memory_update && smc->dr_lmb_enabled) { |
748 | _FDT((spapr_populate_drconf_memory(spapr, fdt))); | |
03d196b7 BR |
749 | } |
750 | ||
751 | /* Pack resulting tree */ | |
752 | _FDT((fdt_pack(fdt))); | |
753 | ||
754 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
755 | trace_spapr_cas_failed(size); | |
756 | return -1; | |
757 | } | |
758 | ||
759 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
760 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
761 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
762 | g_free(fdt); | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
3f5dabce DG |
767 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
768 | { | |
769 | int rtas; | |
770 | GString *hypertas = g_string_sized_new(256); | |
771 | GString *qemu_hypertas = g_string_sized_new(256); | |
772 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
773 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
774 | memory_region_size(&spapr->hotplug_memory.mr); | |
775 | uint32_t lrdr_capacity[] = { | |
776 | cpu_to_be32(max_hotplug_addr >> 32), | |
777 | cpu_to_be32(max_hotplug_addr & 0xffffffff), | |
778 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), | |
779 | cpu_to_be32(max_cpus / smp_threads), | |
780 | }; | |
781 | ||
782 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
783 | ||
784 | /* hypertas */ | |
785 | add_str(hypertas, "hcall-pft"); | |
786 | add_str(hypertas, "hcall-term"); | |
787 | add_str(hypertas, "hcall-dabr"); | |
788 | add_str(hypertas, "hcall-interrupt"); | |
789 | add_str(hypertas, "hcall-tce"); | |
790 | add_str(hypertas, "hcall-vio"); | |
791 | add_str(hypertas, "hcall-splpar"); | |
792 | add_str(hypertas, "hcall-bulk"); | |
793 | add_str(hypertas, "hcall-set-mode"); | |
794 | add_str(hypertas, "hcall-sprg0"); | |
795 | add_str(hypertas, "hcall-copy"); | |
796 | add_str(hypertas, "hcall-debug"); | |
797 | add_str(qemu_hypertas, "hcall-memop1"); | |
798 | ||
799 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
800 | add_str(hypertas, "hcall-multi-tce"); | |
801 | } | |
802 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", | |
803 | hypertas->str, hypertas->len)); | |
804 | g_string_free(hypertas, TRUE); | |
805 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
806 | qemu_hypertas->str, qemu_hypertas->len)); | |
807 | g_string_free(qemu_hypertas, TRUE); | |
808 | ||
809 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
810 | refpoints, sizeof(refpoints))); | |
811 | ||
812 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", | |
813 | RTAS_ERROR_LOG_MAX)); | |
814 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
815 | RTAS_EVENT_SCAN_RATE)); | |
816 | ||
817 | if (msi_nonbroken) { | |
818 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
819 | } | |
820 | ||
821 | /* | |
822 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
823 | * back to the guest cpu. | |
824 | * | |
825 | * While an additional ibm,extended-os-term property indicates | |
826 | * that rtas call return will always occur. Set this property. | |
827 | */ | |
828 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
829 | ||
830 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
831 | lrdr_capacity, sizeof(lrdr_capacity))); | |
832 | ||
833 | spapr_dt_rtas_tokens(fdt, rtas); | |
834 | } | |
835 | ||
7c866c6a DG |
836 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
837 | { | |
838 | MachineState *machine = MACHINE(spapr); | |
839 | int chosen; | |
840 | const char *boot_device = machine->boot_order; | |
841 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
842 | size_t cb = 0; | |
843 | char *bootlist = get_boot_devices_list(&cb, true); | |
844 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; | |
845 | ||
846 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
847 | ||
848 | /* Set Form1_affinity */ | |
849 | _FDT(fdt_setprop(fdt, chosen, "ibm,architecture-vec-5", | |
850 | vec5, sizeof(vec5))); | |
851 | ||
852 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); | |
853 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
854 | spapr->initrd_base)); | |
855 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
856 | spapr->initrd_base + spapr->initrd_size)); | |
857 | ||
858 | if (spapr->kernel_size) { | |
859 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
860 | cpu_to_be64(spapr->kernel_size) }; | |
861 | ||
862 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
863 | &kprop, sizeof(kprop))); | |
864 | if (spapr->kernel_le) { | |
865 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
866 | } | |
867 | } | |
868 | if (boot_menu) { | |
869 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
870 | } | |
871 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
872 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
873 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
874 | ||
875 | if (cb && bootlist) { | |
876 | int i; | |
877 | ||
878 | for (i = 0; i < cb; i++) { | |
879 | if (bootlist[i] == '\n') { | |
880 | bootlist[i] = ' '; | |
881 | } | |
882 | } | |
883 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
884 | } | |
885 | ||
886 | if (boot_device && strlen(boot_device)) { | |
887 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
888 | } | |
889 | ||
890 | if (!spapr->has_graphics && stdout_path) { | |
891 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); | |
892 | } | |
893 | ||
894 | g_free(stdout_path); | |
895 | g_free(bootlist); | |
896 | } | |
897 | ||
fca5f2dc DG |
898 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
899 | { | |
900 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
901 | * KVM to work under pHyp with some guest co-operation */ | |
902 | int hypervisor; | |
903 | uint8_t hypercall[16]; | |
904 | ||
905 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
906 | /* indicate KVM hypercall interface */ | |
907 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
908 | if (kvmppc_has_cap_fixup_hcalls()) { | |
909 | /* | |
910 | * Older KVM versions with older guest kernels were broken | |
911 | * with the magic page, don't allow the guest to map it. | |
912 | */ | |
913 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
914 | sizeof(hypercall))) { | |
915 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
916 | hypercall, sizeof(hypercall))); | |
917 | } | |
918 | } | |
919 | } | |
920 | ||
997b6cfc DG |
921 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
922 | hwaddr rtas_addr, | |
923 | hwaddr rtas_size) | |
a3467baa | 924 | { |
5b2128d2 | 925 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c0c47e3 | 926 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 927 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 928 | int ret; |
a3467baa | 929 | void *fdt; |
3384f95c | 930 | sPAPRPHBState *phb; |
a3467baa | 931 | |
7267c094 | 932 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
933 | |
934 | /* open out the base tree into a temp buffer for the final tweaks */ | |
935 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 936 | |
9b9a1908 DG |
937 | /* /interrupt controller */ |
938 | spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP); | |
939 | ||
e8f986fc BR |
940 | ret = spapr_populate_memory(spapr, fdt); |
941 | if (ret < 0) { | |
ce9863b7 | 942 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 943 | exit(1); |
7f763a5d DG |
944 | } |
945 | ||
4040ab72 DG |
946 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
947 | if (ret < 0) { | |
ce9863b7 | 948 | error_report("couldn't setup vio devices in fdt"); |
4040ab72 DG |
949 | exit(1); |
950 | } | |
951 | ||
4d9392be TH |
952 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
953 | ret = spapr_rng_populate_dt(fdt); | |
954 | if (ret < 0) { | |
ce9863b7 | 955 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
956 | exit(1); |
957 | } | |
958 | } | |
959 | ||
3384f95c | 960 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 961 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
962 | if (ret < 0) { |
963 | error_report("couldn't setup PCI devices in fdt"); | |
964 | exit(1); | |
965 | } | |
3384f95c DG |
966 | } |
967 | ||
0da6f3fe BR |
968 | /* cpus */ |
969 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 970 | |
c20d332a BR |
971 | if (smc->dr_lmb_enabled) { |
972 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
973 | } | |
974 | ||
3c0c47e3 | 975 | if (mc->query_hotpluggable_cpus) { |
af81cf32 BR |
976 | int offset = fdt_path_offset(fdt, "/cpus"); |
977 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
978 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
979 | if (ret < 0) { | |
980 | error_report("Couldn't set up CPU DR device tree properties"); | |
981 | exit(1); | |
982 | } | |
983 | } | |
984 | ||
ffb1e275 DG |
985 | /* /event-sources */ |
986 | spapr_dt_events(fdt, spapr->check_exception_irq); | |
987 | ||
3f5dabce DG |
988 | /* /rtas */ |
989 | spapr_dt_rtas(spapr, fdt); | |
990 | ||
7c866c6a DG |
991 | /* /chosen */ |
992 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 993 | |
fca5f2dc DG |
994 | /* /hypervisor */ |
995 | if (kvm_enabled()) { | |
996 | spapr_dt_hypervisor(spapr, fdt); | |
997 | } | |
998 | ||
cf6e5223 DG |
999 | /* Build memory reserve map */ |
1000 | if (spapr->kernel_size) { | |
1001 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1002 | } | |
1003 | if (spapr->initrd_size) { | |
1004 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1005 | } | |
1006 | ||
997b6cfc | 1007 | return fdt; |
9fdf0c29 DG |
1008 | } |
1009 | ||
1010 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1011 | { | |
1012 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1013 | } | |
1014 | ||
1b14670a | 1015 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 1016 | { |
1b14670a AF |
1017 | CPUPPCState *env = &cpu->env; |
1018 | ||
efcb9383 DG |
1019 | if (msr_pr) { |
1020 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1021 | env->gpr[3] = H_PRIVILEGE; | |
1022 | } else { | |
aa100fa4 | 1023 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1024 | } |
9fdf0c29 DG |
1025 | } |
1026 | ||
e6b8fd24 SMJ |
1027 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1028 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1029 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1030 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1031 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1032 | ||
715c5407 DG |
1033 | /* |
1034 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1035 | */ | |
1036 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1037 | { | |
1038 | if (spapr->htab_fd >= 0) { | |
1039 | return spapr->htab_fd; | |
1040 | } | |
1041 | ||
1042 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1043 | if (spapr->htab_fd < 0) { | |
1044 | error_report("Unable to open fd for reading hash table from KVM: %s", | |
1045 | strerror(errno)); | |
1046 | } | |
1047 | ||
1048 | return spapr->htab_fd; | |
1049 | } | |
1050 | ||
1051 | static void close_htab_fd(sPAPRMachineState *spapr) | |
1052 | { | |
1053 | if (spapr->htab_fd >= 0) { | |
1054 | close(spapr->htab_fd); | |
1055 | } | |
1056 | spapr->htab_fd = -1; | |
1057 | } | |
1058 | ||
8dfe8e7f DG |
1059 | static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1060 | { | |
1061 | int shift; | |
1062 | ||
1063 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1064 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1065 | * that's much more than is needed for Linux guests */ | |
1066 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1067 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1068 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1069 | return shift; | |
1070 | } | |
1071 | ||
c5f54f3e DG |
1072 | static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1073 | Error **errp) | |
7f763a5d | 1074 | { |
c5f54f3e DG |
1075 | long rc; |
1076 | ||
1077 | /* Clean up any HPT info from a previous boot */ | |
1078 | g_free(spapr->htab); | |
1079 | spapr->htab = NULL; | |
1080 | spapr->htab_shift = 0; | |
1081 | close_htab_fd(spapr); | |
1082 | ||
1083 | rc = kvmppc_reset_htab(shift); | |
1084 | if (rc < 0) { | |
1085 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1086 | error_setg_errno(errp, errno, | |
1087 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1088 | shift); | |
1089 | /* This is almost certainly fatal, but if the caller really | |
1090 | * wants to carry on with shift == 0, it's welcome to try */ | |
1091 | } else if (rc > 0) { | |
1092 | /* kernel-side HPT allocated */ | |
1093 | if (rc != shift) { | |
1094 | error_setg(errp, | |
1095 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1096 | shift, rc); | |
7735feda BR |
1097 | } |
1098 | ||
7f763a5d | 1099 | spapr->htab_shift = shift; |
c18ad9a5 | 1100 | spapr->htab = NULL; |
b817772a | 1101 | } else { |
c5f54f3e DG |
1102 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1103 | size_t size = 1ULL << shift; | |
1104 | int i; | |
b817772a | 1105 | |
c5f54f3e DG |
1106 | spapr->htab = qemu_memalign(size, size); |
1107 | if (!spapr->htab) { | |
1108 | error_setg_errno(errp, errno, | |
1109 | "Could not allocate HPT of order %d", shift); | |
1110 | return; | |
7735feda BR |
1111 | } |
1112 | ||
c5f54f3e DG |
1113 | memset(spapr->htab, 0, size); |
1114 | spapr->htab_shift = shift; | |
e6b8fd24 | 1115 | |
c5f54f3e DG |
1116 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1117 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1118 | } |
7f763a5d | 1119 | } |
9fdf0c29 DG |
1120 | } |
1121 | ||
4f01a637 | 1122 | static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
9e3f9733 AG |
1123 | { |
1124 | bool matched = false; | |
1125 | ||
1126 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1127 | matched = true; | |
1128 | } | |
1129 | ||
1130 | if (!matched) { | |
1131 | error_report("Device %s is not supported by this machine yet.", | |
1132 | qdev_fw_name(DEVICE(sbdev))); | |
1133 | exit(1); | |
1134 | } | |
9e3f9733 AG |
1135 | } |
1136 | ||
c8787ad4 | 1137 | static void ppc_spapr_reset(void) |
a3467baa | 1138 | { |
c5f54f3e DG |
1139 | MachineState *machine = MACHINE(qdev_get_machine()); |
1140 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1141 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1142 | uint32_t rtas_limit; |
cae172ab | 1143 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1144 | void *fdt; |
1145 | int rc; | |
259186a7 | 1146 | |
9e3f9733 AG |
1147 | /* Check for unknown sysbus devices */ |
1148 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1149 | ||
c5f54f3e DG |
1150 | /* Allocate and/or reset the hash page table */ |
1151 | spapr_reallocate_hpt(spapr, | |
1152 | spapr_hpt_shift_for_ramsize(machine->maxram_size), | |
1153 | &error_fatal); | |
1154 | ||
1155 | /* Update the RMA size if necessary */ | |
1156 | if (spapr->vrma_adjust) { | |
1157 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), | |
1158 | spapr->htab_shift); | |
1159 | } | |
a3467baa | 1160 | |
c8787ad4 | 1161 | qemu_devices_reset(); |
a3467baa | 1162 | |
b7d1f77a BH |
1163 | /* |
1164 | * We place the device tree and RTAS just below either the top of the RMA, | |
1165 | * or just below 2GB, whichever is lowere, so that it can be | |
1166 | * processed with 32-bit real mode code if necessary | |
1167 | */ | |
1168 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1169 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1170 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1171 | |
cae172ab | 1172 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1173 | |
2cac78c1 | 1174 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1175 | |
997b6cfc DG |
1176 | rc = fdt_pack(fdt); |
1177 | ||
1178 | /* Should only fail if we've built a corrupted tree */ | |
1179 | assert(rc == 0); | |
1180 | ||
1181 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1182 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1183 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1184 | exit(1); | |
1185 | } | |
1186 | ||
1187 | /* Load the fdt */ | |
1188 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1189 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1190 | g_free(fdt); |
1191 | ||
a3467baa | 1192 | /* Set up the entry state */ |
182735ef | 1193 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
cae172ab | 1194 | first_ppc_cpu->env.gpr[3] = fdt_addr; |
182735ef AF |
1195 | first_ppc_cpu->env.gpr[5] = 0; |
1196 | first_cpu->halted = 0; | |
1b718907 | 1197 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa DG |
1198 | |
1199 | } | |
1200 | ||
28e02042 | 1201 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1202 | { |
2ff3de68 | 1203 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1204 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1205 | |
3978b863 | 1206 | if (dinfo) { |
6231a6da MA |
1207 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1208 | &error_fatal); | |
639e8102 DG |
1209 | } |
1210 | ||
1211 | qdev_init_nofail(dev); | |
1212 | ||
1213 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1214 | } | |
1215 | ||
28e02042 | 1216 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 DG |
1217 | { |
1218 | DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); | |
1219 | ||
1220 | qdev_init_nofail(dev); | |
1221 | spapr->rtc = dev; | |
74e5ae28 DG |
1222 | |
1223 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
1224 | OBJECT(spapr->rtc), "date", NULL); | |
28df36a1 DG |
1225 | } |
1226 | ||
8c57b867 | 1227 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1228 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1229 | { |
8c57b867 | 1230 | switch (vga_interface_type) { |
8c57b867 | 1231 | case VGA_NONE: |
7effdaa3 MW |
1232 | return false; |
1233 | case VGA_DEVICE: | |
1234 | return true; | |
1ddcae82 | 1235 | case VGA_STD: |
b798c190 | 1236 | case VGA_VIRTIO: |
1ddcae82 | 1237 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1238 | default: |
14c6a894 DG |
1239 | error_setg(errp, |
1240 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1241 | return false; | |
f28359d8 | 1242 | } |
f28359d8 LZ |
1243 | } |
1244 | ||
880ae7de DG |
1245 | static int spapr_post_load(void *opaque, int version_id) |
1246 | { | |
28e02042 | 1247 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1248 | int err = 0; |
1249 | ||
631b22ea | 1250 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1251 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1252 | * So when migrating from those versions, poke the incoming offset | |
1253 | * value into the RTC device */ | |
1254 | if (version_id < 3) { | |
1255 | err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); | |
1256 | } | |
1257 | ||
1258 | return err; | |
1259 | } | |
1260 | ||
1261 | static bool version_before_3(void *opaque, int version_id) | |
1262 | { | |
1263 | return version_id < 3; | |
1264 | } | |
1265 | ||
4be21d56 DG |
1266 | static const VMStateDescription vmstate_spapr = { |
1267 | .name = "spapr", | |
880ae7de | 1268 | .version_id = 3, |
4be21d56 | 1269 | .minimum_version_id = 1, |
880ae7de | 1270 | .post_load = spapr_post_load, |
3aff6c2f | 1271 | .fields = (VMStateField[]) { |
880ae7de DG |
1272 | /* used to be @next_irq */ |
1273 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1274 | |
1275 | /* RTC offset */ | |
28e02042 | 1276 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1277 | |
28e02042 | 1278 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1279 | VMSTATE_END_OF_LIST() |
1280 | }, | |
1281 | }; | |
1282 | ||
4be21d56 DG |
1283 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1284 | { | |
28e02042 | 1285 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1286 | |
4be21d56 DG |
1287 | /* "Iteration" header */ |
1288 | qemu_put_be32(f, spapr->htab_shift); | |
1289 | ||
e68cb8b4 AK |
1290 | if (spapr->htab) { |
1291 | spapr->htab_save_index = 0; | |
1292 | spapr->htab_first_pass = true; | |
1293 | } else { | |
1294 | assert(kvm_enabled()); | |
e68cb8b4 AK |
1295 | } |
1296 | ||
1297 | ||
4be21d56 DG |
1298 | return 0; |
1299 | } | |
1300 | ||
28e02042 | 1301 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1302 | int64_t max_ns) |
1303 | { | |
378bc217 | 1304 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1305 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1306 | int index = spapr->htab_save_index; | |
bc72ad67 | 1307 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1308 | |
1309 | assert(spapr->htab_first_pass); | |
1310 | ||
1311 | do { | |
1312 | int chunkstart; | |
1313 | ||
1314 | /* Consume invalid HPTEs */ | |
1315 | while ((index < htabslots) | |
1316 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1317 | index++; | |
1318 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1319 | } | |
1320 | ||
1321 | /* Consume valid HPTEs */ | |
1322 | chunkstart = index; | |
338c25b6 | 1323 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1324 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
1325 | index++; | |
1326 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1327 | } | |
1328 | ||
1329 | if (index > chunkstart) { | |
1330 | int n_valid = index - chunkstart; | |
1331 | ||
1332 | qemu_put_be32(f, chunkstart); | |
1333 | qemu_put_be16(f, n_valid); | |
1334 | qemu_put_be16(f, 0); | |
1335 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1336 | HASH_PTE_SIZE_64 * n_valid); | |
1337 | ||
378bc217 DG |
1338 | if (has_timeout && |
1339 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1340 | break; |
1341 | } | |
1342 | } | |
1343 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1344 | ||
1345 | if (index >= htabslots) { | |
1346 | assert(index == htabslots); | |
1347 | index = 0; | |
1348 | spapr->htab_first_pass = false; | |
1349 | } | |
1350 | spapr->htab_save_index = index; | |
1351 | } | |
1352 | ||
28e02042 | 1353 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1354 | int64_t max_ns) |
4be21d56 DG |
1355 | { |
1356 | bool final = max_ns < 0; | |
1357 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1358 | int examined = 0, sent = 0; | |
1359 | int index = spapr->htab_save_index; | |
bc72ad67 | 1360 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1361 | |
1362 | assert(!spapr->htab_first_pass); | |
1363 | ||
1364 | do { | |
1365 | int chunkstart, invalidstart; | |
1366 | ||
1367 | /* Consume non-dirty HPTEs */ | |
1368 | while ((index < htabslots) | |
1369 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1370 | index++; | |
1371 | examined++; | |
1372 | } | |
1373 | ||
1374 | chunkstart = index; | |
1375 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1376 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1377 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1378 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1379 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1380 | index++; | |
1381 | examined++; | |
1382 | } | |
1383 | ||
1384 | invalidstart = index; | |
1385 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1386 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1387 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1388 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1389 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1390 | index++; | |
1391 | examined++; | |
1392 | } | |
1393 | ||
1394 | if (index > chunkstart) { | |
1395 | int n_valid = invalidstart - chunkstart; | |
1396 | int n_invalid = index - invalidstart; | |
1397 | ||
1398 | qemu_put_be32(f, chunkstart); | |
1399 | qemu_put_be16(f, n_valid); | |
1400 | qemu_put_be16(f, n_invalid); | |
1401 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1402 | HASH_PTE_SIZE_64 * n_valid); | |
1403 | sent += index - chunkstart; | |
1404 | ||
bc72ad67 | 1405 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1406 | break; |
1407 | } | |
1408 | } | |
1409 | ||
1410 | if (examined >= htabslots) { | |
1411 | break; | |
1412 | } | |
1413 | ||
1414 | if (index >= htabslots) { | |
1415 | assert(index == htabslots); | |
1416 | index = 0; | |
1417 | } | |
1418 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1419 | ||
1420 | if (index >= htabslots) { | |
1421 | assert(index == htabslots); | |
1422 | index = 0; | |
1423 | } | |
1424 | ||
1425 | spapr->htab_save_index = index; | |
1426 | ||
e68cb8b4 | 1427 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1428 | } |
1429 | ||
e68cb8b4 AK |
1430 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1431 | #define MAX_KVM_BUF_SIZE 2048 | |
1432 | ||
4be21d56 DG |
1433 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1434 | { | |
28e02042 | 1435 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1436 | int fd; |
e68cb8b4 | 1437 | int rc = 0; |
4be21d56 DG |
1438 | |
1439 | /* Iteration header */ | |
1440 | qemu_put_be32(f, 0); | |
1441 | ||
e68cb8b4 AK |
1442 | if (!spapr->htab) { |
1443 | assert(kvm_enabled()); | |
1444 | ||
715c5407 DG |
1445 | fd = get_htab_fd(spapr); |
1446 | if (fd < 0) { | |
1447 | return fd; | |
01a57972 SMJ |
1448 | } |
1449 | ||
715c5407 | 1450 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1451 | if (rc < 0) { |
1452 | return rc; | |
1453 | } | |
1454 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1455 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1456 | } else { | |
e68cb8b4 | 1457 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1458 | } |
1459 | ||
1460 | /* End marker */ | |
1461 | qemu_put_be32(f, 0); | |
1462 | qemu_put_be16(f, 0); | |
1463 | qemu_put_be16(f, 0); | |
1464 | ||
e68cb8b4 | 1465 | return rc; |
4be21d56 DG |
1466 | } |
1467 | ||
1468 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1469 | { | |
28e02042 | 1470 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1471 | int fd; |
4be21d56 DG |
1472 | |
1473 | /* Iteration header */ | |
1474 | qemu_put_be32(f, 0); | |
1475 | ||
e68cb8b4 AK |
1476 | if (!spapr->htab) { |
1477 | int rc; | |
1478 | ||
1479 | assert(kvm_enabled()); | |
1480 | ||
715c5407 DG |
1481 | fd = get_htab_fd(spapr); |
1482 | if (fd < 0) { | |
1483 | return fd; | |
01a57972 SMJ |
1484 | } |
1485 | ||
715c5407 | 1486 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1487 | if (rc < 0) { |
1488 | return rc; | |
1489 | } | |
e68cb8b4 | 1490 | } else { |
378bc217 DG |
1491 | if (spapr->htab_first_pass) { |
1492 | htab_save_first_pass(f, spapr, -1); | |
1493 | } | |
e68cb8b4 AK |
1494 | htab_save_later_pass(f, spapr, -1); |
1495 | } | |
4be21d56 DG |
1496 | |
1497 | /* End marker */ | |
1498 | qemu_put_be32(f, 0); | |
1499 | qemu_put_be16(f, 0); | |
1500 | qemu_put_be16(f, 0); | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1506 | { | |
28e02042 | 1507 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1508 | uint32_t section_hdr; |
e68cb8b4 | 1509 | int fd = -1; |
4be21d56 DG |
1510 | |
1511 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 1512 | error_report("htab_load() bad version"); |
4be21d56 DG |
1513 | return -EINVAL; |
1514 | } | |
1515 | ||
1516 | section_hdr = qemu_get_be32(f); | |
1517 | ||
1518 | if (section_hdr) { | |
9897e462 | 1519 | Error *local_err = NULL; |
c5f54f3e DG |
1520 | |
1521 | /* First section gives the htab size */ | |
1522 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
1523 | if (local_err) { | |
1524 | error_report_err(local_err); | |
4be21d56 DG |
1525 | return -EINVAL; |
1526 | } | |
1527 | return 0; | |
1528 | } | |
1529 | ||
e68cb8b4 AK |
1530 | if (!spapr->htab) { |
1531 | assert(kvm_enabled()); | |
1532 | ||
1533 | fd = kvmppc_get_htab_fd(true); | |
1534 | if (fd < 0) { | |
98a5d100 DG |
1535 | error_report("Unable to open fd to restore KVM hash table: %s", |
1536 | strerror(errno)); | |
e68cb8b4 AK |
1537 | } |
1538 | } | |
1539 | ||
4be21d56 DG |
1540 | while (true) { |
1541 | uint32_t index; | |
1542 | uint16_t n_valid, n_invalid; | |
1543 | ||
1544 | index = qemu_get_be32(f); | |
1545 | n_valid = qemu_get_be16(f); | |
1546 | n_invalid = qemu_get_be16(f); | |
1547 | ||
1548 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1549 | /* End of Stream */ | |
1550 | break; | |
1551 | } | |
1552 | ||
e68cb8b4 | 1553 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1554 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1555 | /* Bad index in stream */ | |
98a5d100 DG |
1556 | error_report( |
1557 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
1558 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
1559 | return -EINVAL; |
1560 | } | |
1561 | ||
e68cb8b4 AK |
1562 | if (spapr->htab) { |
1563 | if (n_valid) { | |
1564 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1565 | HASH_PTE_SIZE_64 * n_valid); | |
1566 | } | |
1567 | if (n_invalid) { | |
1568 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1569 | HASH_PTE_SIZE_64 * n_invalid); | |
1570 | } | |
1571 | } else { | |
1572 | int rc; | |
1573 | ||
1574 | assert(fd >= 0); | |
1575 | ||
1576 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1577 | if (rc < 0) { | |
1578 | return rc; | |
1579 | } | |
4be21d56 DG |
1580 | } |
1581 | } | |
1582 | ||
e68cb8b4 AK |
1583 | if (!spapr->htab) { |
1584 | assert(fd >= 0); | |
1585 | close(fd); | |
1586 | } | |
1587 | ||
4be21d56 DG |
1588 | return 0; |
1589 | } | |
1590 | ||
c573fc03 TH |
1591 | static void htab_cleanup(void *opaque) |
1592 | { | |
1593 | sPAPRMachineState *spapr = opaque; | |
1594 | ||
1595 | close_htab_fd(spapr); | |
1596 | } | |
1597 | ||
4be21d56 DG |
1598 | static SaveVMHandlers savevm_htab_handlers = { |
1599 | .save_live_setup = htab_save_setup, | |
1600 | .save_live_iterate = htab_save_iterate, | |
a3e06c3d | 1601 | .save_live_complete_precopy = htab_save_complete, |
c573fc03 | 1602 | .cleanup = htab_cleanup, |
4be21d56 DG |
1603 | .load_state = htab_load, |
1604 | }; | |
1605 | ||
5b2128d2 AG |
1606 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1607 | Error **errp) | |
1608 | { | |
1609 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1610 | machine->boot_order = g_strdup(boot_device); | |
1611 | } | |
1612 | ||
224245bf DG |
1613 | /* |
1614 | * Reset routine for LMB DR devices. | |
1615 | * | |
1616 | * Unlike PCI DR devices, LMB DR devices explicitly register this reset | |
1617 | * routine. Reset for PCI DR devices will be handled by PHB reset routine | |
1618 | * when it walks all its children devices. LMB devices reset occurs | |
1619 | * as part of spapr_ppc_reset(). | |
1620 | */ | |
1621 | static void spapr_drc_reset(void *opaque) | |
1622 | { | |
1623 | sPAPRDRConnector *drc = opaque; | |
1624 | DeviceState *d = DEVICE(drc); | |
1625 | ||
1626 | if (d) { | |
1627 | device_reset(d); | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) | |
1632 | { | |
1633 | MachineState *machine = MACHINE(spapr); | |
1634 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 1635 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
1636 | int i; |
1637 | ||
1638 | for (i = 0; i < nr_lmbs; i++) { | |
1639 | sPAPRDRConnector *drc; | |
1640 | uint64_t addr; | |
1641 | ||
e8f986fc | 1642 | addr = i * lmb_size + spapr->hotplug_memory.base; |
224245bf DG |
1643 | drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, |
1644 | addr/lmb_size); | |
1645 | qemu_register_reset(spapr_drc_reset, drc); | |
1646 | } | |
1647 | } | |
1648 | ||
1649 | /* | |
1650 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
1651 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
1652 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
1653 | */ | |
7c150d6f | 1654 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
1655 | { |
1656 | int i; | |
1657 | ||
7c150d6f DG |
1658 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
1659 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
1660 | " is not aligned to %llu MiB", | |
1661 | machine->ram_size, | |
1662 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1663 | return; | |
1664 | } | |
1665 | ||
1666 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
1667 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
1668 | " is not aligned to %llu MiB", | |
1669 | machine->ram_size, | |
1670 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1671 | return; | |
224245bf DG |
1672 | } |
1673 | ||
1674 | for (i = 0; i < nb_numa_nodes; i++) { | |
1675 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
1676 | error_setg(errp, |
1677 | "Node %d memory size 0x%" PRIx64 | |
1678 | " is not aligned to %llu MiB", | |
1679 | i, numa_info[i].node_mem, | |
1680 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1681 | return; | |
224245bf DG |
1682 | } |
1683 | } | |
1684 | } | |
1685 | ||
9fdf0c29 | 1686 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 1687 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 1688 | { |
28e02042 | 1689 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3c0c47e3 | 1690 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
224245bf | 1691 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 1692 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 1693 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 1694 | PCIHostState *phb; |
9fdf0c29 | 1695 | int i; |
890c2b77 AK |
1696 | MemoryRegion *sysmem = get_system_memory(); |
1697 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
1698 | MemoryRegion *rma_region; |
1699 | void *rma = NULL; | |
a8170e5e | 1700 | hwaddr rma_alloc_size; |
b082d65a | 1701 | hwaddr node0_size = spapr_node0_size(); |
b7d1f77a | 1702 | long load_limit, fw_size; |
39ac8455 | 1703 | char *filename; |
94a94e4c BR |
1704 | int smt = kvmppc_smt_threads(); |
1705 | int spapr_cores = smp_cpus / smp_threads; | |
1706 | int spapr_max_cores = max_cpus / smp_threads; | |
1707 | ||
3c0c47e3 | 1708 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1709 | if (smp_cpus % smp_threads) { |
1710 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
1711 | smp_cpus, smp_threads); | |
1712 | exit(1); | |
1713 | } | |
1714 | if (max_cpus % smp_threads) { | |
1715 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
1716 | max_cpus, smp_threads); | |
1717 | exit(1); | |
1718 | } | |
1719 | } | |
9fdf0c29 | 1720 | |
226419d6 | 1721 | msi_nonbroken = true; |
0ee2c058 | 1722 | |
d43b45e2 DG |
1723 | QLIST_INIT(&spapr->phbs); |
1724 | ||
9fdf0c29 DG |
1725 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1726 | ||
354ac20a | 1727 | /* Allocate RMA if necessary */ |
658fa66b | 1728 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
1729 | |
1730 | if (rma_alloc_size == -1) { | |
730fce59 | 1731 | error_report("Unable to create RMA"); |
354ac20a DG |
1732 | exit(1); |
1733 | } | |
7f763a5d | 1734 | |
c4177479 | 1735 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1736 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1737 | } else { |
c4177479 | 1738 | spapr->rma_size = node0_size; |
7f763a5d DG |
1739 | |
1740 | /* With KVM, we don't actually know whether KVM supports an | |
1741 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1742 | * (HV KVM using VRMA), so we always assume the latter | |
1743 | * | |
1744 | * In that case, we also limit the initial allocations for RTAS | |
1745 | * etc... to 256M since we have no way to know what the VRMA size | |
1746 | * is going to be as it depends on the size of the hash table | |
1747 | * isn't determined yet. | |
1748 | */ | |
1749 | if (kvm_enabled()) { | |
1750 | spapr->vrma_adjust = 1; | |
1751 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1752 | } | |
912acdf4 BH |
1753 | |
1754 | /* Actually we don't support unbounded RMA anymore since we | |
1755 | * added proper emulation of HV mode. The max we can get is | |
1756 | * 16G which also happens to be what we configure for PAPR | |
1757 | * mode so make sure we don't do anything bigger than that | |
1758 | */ | |
1759 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
1760 | } |
1761 | ||
c4177479 | 1762 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
1763 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
1764 | spapr->rma_size); | |
c4177479 AK |
1765 | exit(1); |
1766 | } | |
1767 | ||
b7d1f77a BH |
1768 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
1769 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 1770 | |
7b565160 | 1771 | /* Set up Interrupt Controller before we create the VCPUs */ |
27f24582 BH |
1772 | spapr->xics = xics_system_init(machine, |
1773 | DIV_ROUND_UP(max_cpus * smt, smp_threads), | |
1774 | XICS_IRQS_SPAPR, &error_fatal); | |
7b565160 | 1775 | |
224245bf | 1776 | if (smc->dr_lmb_enabled) { |
7c150d6f | 1777 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
1778 | } |
1779 | ||
9fdf0c29 | 1780 | /* init CPUs */ |
19fb2c36 | 1781 | if (machine->cpu_model == NULL) { |
3daa4a9f | 1782 | machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; |
9fdf0c29 | 1783 | } |
94a94e4c | 1784 | |
e703d2f7 GK |
1785 | ppc_cpu_parse_features(machine->cpu_model); |
1786 | ||
3c0c47e3 | 1787 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1788 | char *type = spapr_get_cpu_core_type(machine->cpu_model); |
1789 | ||
4babfaf0 | 1790 | if (type == NULL) { |
caebf378 CLG |
1791 | error_report("Unable to find sPAPR CPU Core definition"); |
1792 | exit(1); | |
1793 | } | |
1794 | ||
94a94e4c | 1795 | spapr->cores = g_new0(Object *, spapr_max_cores); |
af81cf32 | 1796 | for (i = 0; i < spapr_max_cores; i++) { |
12bf2d33 | 1797 | int core_id = i * smp_threads; |
af81cf32 BR |
1798 | sPAPRDRConnector *drc = |
1799 | spapr_dr_connector_new(OBJECT(spapr), | |
12bf2d33 GK |
1800 | SPAPR_DR_CONNECTOR_TYPE_CPU, |
1801 | (core_id / smp_threads) * smt); | |
af81cf32 BR |
1802 | |
1803 | qemu_register_reset(spapr_drc_reset, drc); | |
1804 | ||
1805 | if (i < spapr_cores) { | |
caebf378 | 1806 | Object *core = object_new(type); |
af81cf32 BR |
1807 | object_property_set_int(core, smp_threads, "nr-threads", |
1808 | &error_fatal); | |
12bf2d33 | 1809 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, |
af81cf32 BR |
1810 | &error_fatal); |
1811 | object_property_set_bool(core, true, "realized", &error_fatal); | |
94a94e4c | 1812 | } |
9fdf0c29 | 1813 | } |
94a94e4c BR |
1814 | g_free(type); |
1815 | } else { | |
1816 | for (i = 0; i < smp_cpus; i++) { | |
1817 | PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); | |
1818 | if (cpu == NULL) { | |
1819 | error_report("Unable to find PowerPC CPU definition"); | |
1820 | exit(1); | |
1821 | } | |
1822 | spapr_cpu_init(spapr, cpu, &error_fatal); | |
1823 | } | |
9fdf0c29 DG |
1824 | } |
1825 | ||
026bfd89 DG |
1826 | if (kvm_enabled()) { |
1827 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
1828 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 1829 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
1830 | |
1831 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
1832 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
1833 | } |
1834 | ||
9fdf0c29 | 1835 | /* allocate RAM */ |
f92f5da1 | 1836 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 1837 | machine->ram_size); |
f92f5da1 | 1838 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 1839 | |
658fa66b AK |
1840 | if (rma_alloc_size && rma) { |
1841 | rma_region = g_new(MemoryRegion, 1); | |
1842 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
1843 | rma_alloc_size, rma); | |
1844 | vmstate_register_ram_global(rma_region); | |
1845 | memory_region_add_subregion(sysmem, 0, rma_region); | |
1846 | } | |
1847 | ||
4a1c9cf0 BR |
1848 | /* initialize hotplug memory address space */ |
1849 | if (machine->ram_size < machine->maxram_size) { | |
1850 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
1851 | /* |
1852 | * Limit the number of hotpluggable memory slots to half the number | |
1853 | * slots that KVM supports, leaving the other half for PCI and other | |
1854 | * devices. However ensure that number of slots doesn't drop below 32. | |
1855 | */ | |
1856 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
1857 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 1858 | |
71c9a3dd BR |
1859 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
1860 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
1861 | } | |
1862 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
1863 | error_report("Specified number of memory slots %" |
1864 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 1865 | machine->ram_slots, max_memslots); |
d54e4d76 | 1866 | exit(1); |
4a1c9cf0 BR |
1867 | } |
1868 | ||
1869 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
1870 | SPAPR_HOTPLUG_MEM_ALIGN); | |
1871 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
1872 | "hotplug-memory", hotplug_mem_size); | |
1873 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
1874 | &spapr->hotplug_memory.mr); | |
1875 | } | |
1876 | ||
224245bf DG |
1877 | if (smc->dr_lmb_enabled) { |
1878 | spapr_create_lmb_dr_connectors(spapr); | |
1879 | } | |
1880 | ||
39ac8455 | 1881 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 1882 | if (!filename) { |
730fce59 | 1883 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
1884 | exit(1); |
1885 | } | |
b7d1f77a | 1886 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
1887 | if (spapr->rtas_size < 0) { |
1888 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
1889 | exit(1); | |
1890 | } | |
b7d1f77a BH |
1891 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
1892 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 1893 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
1894 | exit(1); |
1895 | } | |
4d8d5467 | 1896 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
1897 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
1898 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
1899 | exit(1); |
1900 | } | |
7267c094 | 1901 | g_free(filename); |
39ac8455 | 1902 | |
74d042e5 DG |
1903 | /* Set up EPOW events infrastructure */ |
1904 | spapr_events_init(spapr); | |
1905 | ||
12f42174 | 1906 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 1907 | spapr_rtc_create(spapr); |
12f42174 | 1908 | |
b5cec4c5 | 1909 | /* Set up VIO bus */ |
4040ab72 DG |
1910 | spapr->vio_bus = spapr_vio_bus_init(); |
1911 | ||
277f9acf | 1912 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1913 | if (serial_hds[i]) { |
d601fac4 | 1914 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1915 | } |
1916 | } | |
9fdf0c29 | 1917 | |
639e8102 DG |
1918 | /* We always have at least the nvram device on VIO */ |
1919 | spapr_create_nvram(spapr); | |
1920 | ||
3384f95c | 1921 | /* Set up PCI */ |
fa28f71b AK |
1922 | spapr_pci_rtas_init(); |
1923 | ||
89dfd6e1 | 1924 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1925 | |
277f9acf | 1926 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1927 | NICInfo *nd = &nd_table[i]; |
1928 | ||
1929 | if (!nd->model) { | |
7267c094 | 1930 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1931 | } |
1932 | ||
1933 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1934 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1935 | } else { |
29b358f9 | 1936 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1937 | } |
1938 | } | |
1939 | ||
6e270446 | 1940 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1941 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1942 | } |
1943 | ||
f28359d8 | 1944 | /* Graphics */ |
14c6a894 | 1945 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 1946 | spapr->has_graphics = true; |
c6e76503 | 1947 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
1948 | } |
1949 | ||
4ee9ced9 | 1950 | if (machine->usb) { |
57040d45 TH |
1951 | if (smc->use_ohci_by_default) { |
1952 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
1953 | } else { | |
1954 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
1955 | } | |
c86580b8 | 1956 | |
35139a59 | 1957 | if (spapr->has_graphics) { |
c86580b8 MA |
1958 | USBBus *usb_bus = usb_bus_find(-1); |
1959 | ||
1960 | usb_create_simple(usb_bus, "usb-kbd"); | |
1961 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
1962 | } |
1963 | } | |
1964 | ||
7f763a5d | 1965 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
1966 | error_report( |
1967 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
1968 | MIN_RMA_SLOF); | |
4d8d5467 BH |
1969 | exit(1); |
1970 | } | |
1971 | ||
9fdf0c29 DG |
1972 | if (kernel_filename) { |
1973 | uint64_t lowaddr = 0; | |
1974 | ||
a19f7fb0 DG |
1975 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
1976 | NULL, NULL, &lowaddr, NULL, 1, | |
1977 | PPC_ELF_MACHINE, 0, 0); | |
1978 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
1979 | spapr->kernel_size = load_elf(kernel_filename, | |
1980 | translate_kernel_address, NULL, NULL, | |
1981 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
1982 | 0, 0); | |
1983 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 1984 | } |
a19f7fb0 DG |
1985 | if (spapr->kernel_size < 0) { |
1986 | error_report("error loading %s: %s", kernel_filename, | |
1987 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
1988 | exit(1); |
1989 | } | |
1990 | ||
1991 | /* load initrd */ | |
1992 | if (initrd_filename) { | |
4d8d5467 BH |
1993 | /* Try to locate the initrd in the gap between the kernel |
1994 | * and the firmware. Add a bit of space just in case | |
1995 | */ | |
a19f7fb0 DG |
1996 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
1997 | + 0x1ffff) & ~0xffff; | |
1998 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
1999 | spapr->initrd_base, | |
2000 | load_limit | |
2001 | - spapr->initrd_base); | |
2002 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2003 | error_report("could not load initial ram disk '%s'", |
2004 | initrd_filename); | |
9fdf0c29 DG |
2005 | exit(1); |
2006 | } | |
9fdf0c29 | 2007 | } |
4d8d5467 | 2008 | } |
a3467baa | 2009 | |
8e7ea787 AF |
2010 | if (bios_name == NULL) { |
2011 | bios_name = FW_FILE_NAME; | |
2012 | } | |
2013 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2014 | if (!filename) { |
68fea5a0 | 2015 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2016 | exit(1); |
2017 | } | |
4d8d5467 | 2018 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2019 | if (fw_size <= 0) { |
2020 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2021 | exit(1); |
2022 | } | |
2023 | g_free(filename); | |
4d8d5467 | 2024 | |
28e02042 DG |
2025 | /* FIXME: Should register things through the MachineState's qdev |
2026 | * interface, this is a legacy from the sPAPREnvironment structure | |
2027 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2028 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2029 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2030 | &savevm_htab_handlers, spapr); | |
2031 | ||
9fdf0c29 | 2032 | /* Prepare the device tree */ |
a19f7fb0 | 2033 | spapr->fdt_skel = spapr_create_fdt_skel(spapr); |
a3467baa | 2034 | assert(spapr->fdt_skel != NULL); |
5b2128d2 | 2035 | |
46503c2b MR |
2036 | /* used by RTAS */ |
2037 | QTAILQ_INIT(&spapr->ccs_list); | |
2038 | qemu_register_reset(spapr_ccs_reset_hook, spapr); | |
2039 | ||
5b2128d2 | 2040 | qemu_register_boot_set(spapr_boot_set, spapr); |
9fdf0c29 DG |
2041 | } |
2042 | ||
135a129a AK |
2043 | static int spapr_kvm_type(const char *vm_type) |
2044 | { | |
2045 | if (!vm_type) { | |
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | if (!strcmp(vm_type, "HV")) { | |
2050 | return 1; | |
2051 | } | |
2052 | ||
2053 | if (!strcmp(vm_type, "PR")) { | |
2054 | return 2; | |
2055 | } | |
2056 | ||
2057 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2058 | exit(1); | |
2059 | } | |
2060 | ||
71461b0f | 2061 | /* |
627b84f4 | 2062 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2063 | * for the bootindex property handling. |
2064 | */ | |
2065 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2066 | DeviceState *dev) | |
2067 | { | |
2068 | #define CAST(type, obj, name) \ | |
2069 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2070 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2071 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
2072 | ||
2073 | if (d) { | |
2074 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2075 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2076 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2077 | ||
2078 | if (spapr) { | |
2079 | /* | |
2080 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2081 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2082 | * in the top 16 bits of the 64-bit LUN | |
2083 | */ | |
2084 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2085 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2086 | (uint64_t)id << 48); | |
2087 | } else if (virtio) { | |
2088 | /* | |
2089 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2090 | * in the top 32 bits of the 64-bit LUN | |
2091 | * Note: the quote above is from SLOF and it is wrong, | |
2092 | * the actual binding is: | |
2093 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2094 | */ | |
2095 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2096 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2097 | (uint64_t)id << 32); | |
2098 | } else if (usb) { | |
2099 | /* | |
2100 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2101 | * in the top 32 bits of the 64-bit LUN | |
2102 | */ | |
2103 | unsigned usb_port = atoi(usb->port->path); | |
2104 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2105 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2106 | (uint64_t)id << 32); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | if (phb) { | |
2111 | /* Replace "pci" with "pci@800000020000000" */ | |
2112 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2113 | } | |
2114 | ||
2115 | return NULL; | |
2116 | } | |
2117 | ||
23825581 EH |
2118 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2119 | { | |
28e02042 | 2120 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2121 | |
28e02042 | 2122 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2123 | } |
2124 | ||
2125 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2126 | { | |
28e02042 | 2127 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2128 | |
28e02042 DG |
2129 | g_free(spapr->kvm_type); |
2130 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2131 | } |
2132 | ||
2133 | static void spapr_machine_initfn(Object *obj) | |
2134 | { | |
715c5407 DG |
2135 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2136 | ||
2137 | spapr->htab_fd = -1; | |
23825581 EH |
2138 | object_property_add_str(obj, "kvm-type", |
2139 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2140 | object_property_set_description(obj, "kvm-type", |
2141 | "Specifies the KVM virtualization mode (HV, PR)", | |
2142 | NULL); | |
23825581 EH |
2143 | } |
2144 | ||
87bbdd9c DG |
2145 | static void spapr_machine_finalizefn(Object *obj) |
2146 | { | |
2147 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2148 | ||
2149 | g_free(spapr->kvm_type); | |
2150 | } | |
2151 | ||
e0eeb4a2 | 2152 | static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg) |
34316482 | 2153 | { |
34316482 AK |
2154 | cpu_synchronize_state(cs); |
2155 | ppc_cpu_do_system_reset(cs); | |
2156 | } | |
2157 | ||
2158 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2159 | { | |
2160 | CPUState *cs; | |
2161 | ||
2162 | CPU_FOREACH(cs) { | |
e0eeb4a2 | 2163 | async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL); |
34316482 AK |
2164 | } |
2165 | } | |
2166 | ||
c20d332a BR |
2167 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, |
2168 | uint32_t node, Error **errp) | |
2169 | { | |
2170 | sPAPRDRConnector *drc; | |
2171 | sPAPRDRConnectorClass *drck; | |
2172 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; | |
2173 | int i, fdt_offset, fdt_size; | |
2174 | void *fdt; | |
2175 | ||
c20d332a BR |
2176 | for (i = 0; i < nr_lmbs; i++) { |
2177 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2178 | addr/SPAPR_MEMORY_BLOCK_SIZE); | |
2179 | g_assert(drc); | |
2180 | ||
2181 | fdt = create_device_tree(&fdt_size); | |
2182 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2183 | SPAPR_MEMORY_BLOCK_SIZE); | |
2184 | ||
2185 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2186 | drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); | |
c20d332a BR |
2187 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2188 | } | |
5dd5238c JD |
2189 | /* send hotplug notification to the |
2190 | * guest only in case of hotplugged memory | |
2191 | */ | |
2192 | if (dev->hotplugged) { | |
2193 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); | |
2194 | } | |
c20d332a BR |
2195 | } |
2196 | ||
2197 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2198 | uint32_t node, Error **errp) | |
2199 | { | |
2200 | Error *local_err = NULL; | |
2201 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2202 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2203 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2204 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2205 | uint64_t align = memory_region_get_alignment(mr); | |
2206 | uint64_t size = memory_region_size(mr); | |
2207 | uint64_t addr; | |
2208 | ||
2209 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2210 | error_setg(&local_err, "Hotplugged memory size must be a multiple of " | |
2211 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
2212 | goto out; | |
2213 | } | |
2214 | ||
d6a9b0b8 | 2215 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2216 | if (local_err) { |
2217 | goto out; | |
2218 | } | |
2219 | ||
2220 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2221 | if (local_err) { | |
2222 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2223 | goto out; | |
2224 | } | |
2225 | ||
2226 | spapr_add_lmbs(dev, addr, size, node, &error_abort); | |
2227 | ||
2228 | out: | |
2229 | error_propagate(errp, local_err); | |
2230 | } | |
2231 | ||
af81cf32 BR |
2232 | void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
2233 | sPAPRMachineState *spapr) | |
2234 | { | |
2235 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2236 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2237 | int id = ppc_get_vcpu_dt_id(cpu); | |
2238 | void *fdt; | |
2239 | int offset, fdt_size; | |
2240 | char *nodename; | |
2241 | ||
2242 | fdt = create_device_tree(&fdt_size); | |
2243 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
2244 | offset = fdt_add_subnode(fdt, 0, nodename); | |
2245 | ||
2246 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
2247 | g_free(nodename); | |
2248 | ||
2249 | *fdt_offset = offset; | |
2250 | return fdt; | |
2251 | } | |
2252 | ||
c20d332a BR |
2253 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
2254 | DeviceState *dev, Error **errp) | |
2255 | { | |
2256 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
2257 | ||
2258 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 2259 | int node; |
c20d332a BR |
2260 | |
2261 | if (!smc->dr_lmb_enabled) { | |
2262 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
2263 | return; | |
2264 | } | |
2265 | node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); | |
2266 | if (*errp) { | |
2267 | return; | |
2268 | } | |
1a5512bb GA |
2269 | if (node < 0 || node >= MAX_NODES) { |
2270 | error_setg(errp, "Invaild node %d", node); | |
2271 | return; | |
2272 | } | |
c20d332a | 2273 | |
b556854b BR |
2274 | /* |
2275 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
2276 | * memory-less node, but instead will silently add the memory | |
2277 | * to the first node that has some memory. This causes two | |
2278 | * unexpected behaviours for the user. | |
2279 | * | |
2280 | * - Memory gets hotplugged to a different node than what the user | |
2281 | * specified. | |
2282 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
2283 | * to memory-less node, a reboot will set things accordingly | |
2284 | * and the previously hotplugged memory now ends in the right node. | |
2285 | * This appears as if some memory moved from one node to another. | |
2286 | * | |
2287 | * So until kernel starts supporting memory hotplug to memory-less | |
2288 | * nodes, just prevent such attempts upfront in QEMU. | |
2289 | */ | |
2290 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
2291 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
2292 | node); | |
2293 | return; | |
2294 | } | |
2295 | ||
c20d332a | 2296 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
2297 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
2298 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
2299 | } |
2300 | } | |
2301 | ||
2302 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, | |
2303 | DeviceState *dev, Error **errp) | |
2304 | { | |
3c0c47e3 | 2305 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
6f4b5c3e | 2306 | |
c20d332a BR |
2307 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2308 | error_setg(errp, "Memory hot unplug not supported by sPAPR"); | |
6f4b5c3e | 2309 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3c0c47e3 | 2310 | if (!mc->query_hotpluggable_cpus) { |
6f4b5c3e BR |
2311 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
2312 | return; | |
2313 | } | |
2314 | spapr_core_unplug(hotplug_dev, dev, errp); | |
c20d332a BR |
2315 | } |
2316 | } | |
2317 | ||
94a94e4c BR |
2318 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
2319 | DeviceState *dev, Error **errp) | |
2320 | { | |
2321 | if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
2322 | spapr_core_pre_plug(hotplug_dev, dev, errp); | |
2323 | } | |
2324 | } | |
2325 | ||
7ebaf795 BR |
2326 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
2327 | DeviceState *dev) | |
c20d332a | 2328 | { |
94a94e4c BR |
2329 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2330 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
2331 | return HOTPLUG_HANDLER(machine); |
2332 | } | |
2333 | return NULL; | |
2334 | } | |
2335 | ||
20bb648d DG |
2336 | static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) |
2337 | { | |
2338 | /* Allocate to NUMA nodes on a "socket" basis (not that concept of | |
2339 | * socket means much for the paravirtualized PAPR platform) */ | |
2340 | return cpu_index / smp_threads / smp_cores; | |
2341 | } | |
2342 | ||
2474bfd4 IM |
2343 | static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) |
2344 | { | |
2345 | int i; | |
2346 | HotpluggableCPUList *head = NULL; | |
2347 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
2348 | int spapr_max_cores = max_cpus / smp_threads; | |
2474bfd4 IM |
2349 | |
2350 | for (i = 0; i < spapr_max_cores; i++) { | |
2351 | HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); | |
2352 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); | |
2353 | CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); | |
2354 | ||
2355 | cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); | |
2356 | cpu_item->vcpus_count = smp_threads; | |
27393c33 | 2357 | cpu_props->has_core_id = true; |
12bf2d33 | 2358 | cpu_props->core_id = i * smp_threads; |
2474bfd4 IM |
2359 | /* TODO: add 'has_node/node' here to describe |
2360 | to which node core belongs */ | |
2361 | ||
2362 | cpu_item->props = cpu_props; | |
2363 | if (spapr->cores[i]) { | |
2364 | cpu_item->has_qom_path = true; | |
2365 | cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); | |
2366 | } | |
2367 | list_item->value = cpu_item; | |
2368 | list_item->next = head; | |
2369 | head = list_item; | |
2370 | } | |
2371 | return head; | |
2372 | } | |
2373 | ||
6737d9ad | 2374 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
2375 | uint64_t *buid, hwaddr *pio, |
2376 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
2377 | unsigned n_dma, uint32_t *liobns, Error **errp) |
2378 | { | |
357d1e3b DG |
2379 | /* |
2380 | * New-style PHB window placement. | |
2381 | * | |
2382 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
2383 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
2384 | * windows. | |
2385 | * | |
2386 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
2387 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
2388 | * | |
2389 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
2390 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
2391 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
2392 | * 1TiB 64-bit MMIO windows for each PHB. | |
2393 | */ | |
6737d9ad | 2394 | const uint64_t base_buid = 0x800000020000000ULL; |
357d1e3b DG |
2395 | const int max_phbs = |
2396 | (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1; | |
6737d9ad DG |
2397 | int i; |
2398 | ||
357d1e3b DG |
2399 | /* Sanity check natural alignments */ |
2400 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
2401 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
2402 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
2403 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
2404 | /* Sanity check bounds */ | |
2405 | QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE); | |
2406 | QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE); | |
2efff1c0 | 2407 | |
357d1e3b | 2408 | if (index >= max_phbs) { |
6737d9ad | 2409 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", |
357d1e3b | 2410 | max_phbs - 1); |
6737d9ad DG |
2411 | return; |
2412 | } | |
2413 | ||
2414 | *buid = base_buid + index; | |
2415 | for (i = 0; i < n_dma; ++i) { | |
2416 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
2417 | } | |
2418 | ||
357d1e3b DG |
2419 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
2420 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
2421 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
2422 | } |
2423 | ||
29ee3247 AK |
2424 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
2425 | { | |
2426 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 2427 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 2428 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 2429 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 2430 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
958db90c | 2431 | |
0eb9054c | 2432 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
2433 | |
2434 | /* | |
2435 | * We set up the default / latest behaviour here. The class_init | |
2436 | * functions for the specific versioned machine types can override | |
2437 | * these details for backwards compatibility | |
2438 | */ | |
958db90c MA |
2439 | mc->init = ppc_spapr_init; |
2440 | mc->reset = ppc_spapr_reset; | |
2441 | mc->block_default_type = IF_SCSI; | |
079019f2 | 2442 | mc->max_cpus = 255; |
958db90c | 2443 | mc->no_parallel = 1; |
5b2128d2 | 2444 | mc->default_boot_order = ""; |
a34944fe | 2445 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 2446 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 2447 | mc->has_dynamic_sysbus = true; |
e4024630 | 2448 | mc->pci_allow_0_address = true; |
7ebaf795 | 2449 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 2450 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a BR |
2451 | hc->plug = spapr_machine_device_plug; |
2452 | hc->unplug = spapr_machine_device_unplug; | |
20bb648d | 2453 | mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; |
00b4fbe2 | 2454 | |
fc9f38c3 | 2455 | smc->dr_lmb_enabled = true; |
3daa4a9f | 2456 | smc->tcg_default_cpu = "POWER8"; |
3c0c47e3 | 2457 | mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; |
71461b0f | 2458 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 2459 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 2460 | smc->phb_placement = spapr_phb_placement; |
29ee3247 AK |
2461 | } |
2462 | ||
2463 | static const TypeInfo spapr_machine_info = { | |
2464 | .name = TYPE_SPAPR_MACHINE, | |
2465 | .parent = TYPE_MACHINE, | |
4aee7362 | 2466 | .abstract = true, |
6ca1502e | 2467 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 2468 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 2469 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 2470 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 2471 | .class_init = spapr_machine_class_init, |
71461b0f AK |
2472 | .interfaces = (InterfaceInfo[]) { |
2473 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 2474 | { TYPE_NMI }, |
c20d332a | 2475 | { TYPE_HOTPLUG_HANDLER }, |
71461b0f AK |
2476 | { } |
2477 | }, | |
29ee3247 AK |
2478 | }; |
2479 | ||
fccbc785 | 2480 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
2481 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
2482 | void *data) \ | |
2483 | { \ | |
2484 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
2485 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
2486 | if (latest) { \ |
2487 | mc->alias = "pseries"; \ | |
2488 | mc->is_default = 1; \ | |
2489 | } \ | |
5013c547 DG |
2490 | } \ |
2491 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
2492 | { \ | |
2493 | MachineState *machine = MACHINE(obj); \ | |
2494 | spapr_machine_##suffix##_instance_options(machine); \ | |
2495 | } \ | |
2496 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
2497 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
2498 | .parent = TYPE_SPAPR_MACHINE, \ | |
2499 | .class_init = spapr_machine_##suffix##_class_init, \ | |
2500 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
2501 | }; \ | |
2502 | static void spapr_machine_register_##suffix(void) \ | |
2503 | { \ | |
2504 | type_register(&spapr_machine_##suffix##_info); \ | |
2505 | } \ | |
0e6aac87 | 2506 | type_init(spapr_machine_register_##suffix) |
5013c547 | 2507 | |
db800b21 DG |
2508 | /* |
2509 | * pseries-2.8 | |
2510 | */ | |
2511 | static void spapr_machine_2_8_instance_options(MachineState *machine) | |
2512 | { | |
2513 | } | |
2514 | ||
2515 | static void spapr_machine_2_8_class_options(MachineClass *mc) | |
2516 | { | |
2517 | /* Defaults for the latest behaviour inherited from the base class */ | |
2518 | } | |
2519 | ||
2520 | DEFINE_SPAPR_MACHINE(2_8, "2.8", true); | |
2521 | ||
1ea1eefc BR |
2522 | /* |
2523 | * pseries-2.7 | |
2524 | */ | |
357d1e3b DG |
2525 | #define SPAPR_COMPAT_2_7 \ |
2526 | HW_COMPAT_2_7 \ | |
2527 | { \ | |
2528 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
2529 | .property = "mem_win_size", \ | |
2530 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
2531 | }, \ | |
2532 | { \ | |
2533 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
2534 | .property = "mem64_win_size", \ | |
2535 | .value = "0", \ | |
2536 | }, | |
2537 | ||
2538 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
2539 | uint64_t *buid, hwaddr *pio, | |
2540 | hwaddr *mmio32, hwaddr *mmio64, | |
2541 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
2542 | { | |
2543 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
2544 | const uint64_t base_buid = 0x800000020000000ULL; | |
2545 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
2546 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
2547 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
2548 | const uint32_t max_index = 255; | |
2549 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
2550 | ||
2551 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
2552 | hwaddr phb0_base, phb_base; | |
2553 | int i; | |
2554 | ||
2555 | /* Do we have hotpluggable memory? */ | |
2556 | if (MACHINE(spapr)->maxram_size > ram_top) { | |
2557 | /* Can't just use maxram_size, because there may be an | |
2558 | * alignment gap between normal and hotpluggable memory | |
2559 | * regions */ | |
2560 | ram_top = spapr->hotplug_memory.base + | |
2561 | memory_region_size(&spapr->hotplug_memory.mr); | |
2562 | } | |
2563 | ||
2564 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
2565 | ||
2566 | if (index > max_index) { | |
2567 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
2568 | max_index); | |
2569 | return; | |
2570 | } | |
2571 | ||
2572 | *buid = base_buid + index; | |
2573 | for (i = 0; i < n_dma; ++i) { | |
2574 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
2575 | } | |
2576 | ||
2577 | phb_base = phb0_base + index * phb_spacing; | |
2578 | *pio = phb_base + pio_offset; | |
2579 | *mmio32 = phb_base + mmio_offset; | |
2580 | /* | |
2581 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
2582 | * fallback behaviour of automatically splitting a large "32-bit" | |
2583 | * window into contiguous 32-bit and 64-bit windows | |
2584 | */ | |
2585 | } | |
db800b21 | 2586 | |
1ea1eefc BR |
2587 | static void spapr_machine_2_7_instance_options(MachineState *machine) |
2588 | { | |
672de881 | 2589 | spapr_machine_2_8_instance_options(machine); |
1ea1eefc BR |
2590 | } |
2591 | ||
2592 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
2593 | { | |
3daa4a9f TH |
2594 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2595 | ||
db800b21 | 2596 | spapr_machine_2_8_class_options(mc); |
3daa4a9f | 2597 | smc->tcg_default_cpu = "POWER7"; |
db800b21 | 2598 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 2599 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
2600 | } |
2601 | ||
db800b21 | 2602 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 2603 | |
4b23699c DG |
2604 | /* |
2605 | * pseries-2.6 | |
2606 | */ | |
1ea1eefc | 2607 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
2608 | HW_COMPAT_2_6 \ |
2609 | { \ | |
2610 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2611 | .property = "ddw",\ | |
2612 | .value = stringify(off),\ | |
2613 | }, | |
1ea1eefc | 2614 | |
4b23699c DG |
2615 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
2616 | { | |
672de881 | 2617 | spapr_machine_2_7_instance_options(machine); |
4b23699c DG |
2618 | } |
2619 | ||
2620 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
2621 | { | |
1ea1eefc | 2622 | spapr_machine_2_7_class_options(mc); |
3c0c47e3 | 2623 | mc->query_hotpluggable_cpus = NULL; |
1ea1eefc | 2624 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
2625 | } |
2626 | ||
1ea1eefc | 2627 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 2628 | |
1c5f29bb DG |
2629 | /* |
2630 | * pseries-2.5 | |
2631 | */ | |
4b23699c | 2632 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
2633 | HW_COMPAT_2_5 \ |
2634 | { \ | |
2635 | .driver = "spapr-vlan", \ | |
2636 | .property = "use-rx-buffer-pools", \ | |
2637 | .value = "off", \ | |
2638 | }, | |
4b23699c | 2639 | |
5013c547 | 2640 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 2641 | { |
672de881 | 2642 | spapr_machine_2_6_instance_options(machine); |
5013c547 DG |
2643 | } |
2644 | ||
2645 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
2646 | { | |
57040d45 TH |
2647 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2648 | ||
4b23699c | 2649 | spapr_machine_2_6_class_options(mc); |
57040d45 | 2650 | smc->use_ohci_by_default = true; |
4b23699c | 2651 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
2652 | } |
2653 | ||
4b23699c | 2654 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
2655 | |
2656 | /* | |
2657 | * pseries-2.4 | |
2658 | */ | |
80fd50f9 CH |
2659 | #define SPAPR_COMPAT_2_4 \ |
2660 | HW_COMPAT_2_4 | |
2661 | ||
5013c547 | 2662 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 2663 | { |
5013c547 DG |
2664 | spapr_machine_2_5_instance_options(machine); |
2665 | } | |
1c5f29bb | 2666 | |
5013c547 DG |
2667 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
2668 | { | |
fc9f38c3 DG |
2669 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2670 | ||
2671 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 2672 | smc->dr_lmb_enabled = false; |
f949b4e5 | 2673 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
2674 | } |
2675 | ||
fccbc785 | 2676 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
2677 | |
2678 | /* | |
2679 | * pseries-2.3 | |
2680 | */ | |
38ff32c6 | 2681 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
2682 | HW_COMPAT_2_3 \ |
2683 | {\ | |
2684 | .driver = "spapr-pci-host-bridge",\ | |
2685 | .property = "dynamic-reconfiguration",\ | |
2686 | .value = "off",\ | |
2687 | }, | |
38ff32c6 | 2688 | |
5013c547 | 2689 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 2690 | { |
5013c547 | 2691 | spapr_machine_2_4_instance_options(machine); |
ff14e817 | 2692 | savevm_skip_section_footers(); |
13d16814 | 2693 | global_state_set_optional(); |
09b5e30d | 2694 | savevm_skip_configuration(); |
d25228e7 JW |
2695 | } |
2696 | ||
5013c547 | 2697 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 2698 | { |
fc9f38c3 | 2699 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 2700 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 2701 | } |
fccbc785 | 2702 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 2703 | |
1c5f29bb DG |
2704 | /* |
2705 | * pseries-2.2 | |
2706 | */ | |
2707 | ||
2708 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
2709 | HW_COMPAT_2_2 \ |
2710 | {\ | |
2711 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2712 | .property = "mem_win_size",\ | |
2713 | .value = "0x20000000",\ | |
2714 | }, | |
2715 | ||
5013c547 | 2716 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 2717 | { |
5013c547 | 2718 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 2719 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
2720 | } |
2721 | ||
5013c547 | 2722 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 2723 | { |
fc9f38c3 | 2724 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 2725 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 2726 | } |
fccbc785 | 2727 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 2728 | |
1c5f29bb DG |
2729 | /* |
2730 | * pseries-2.1 | |
2731 | */ | |
2732 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 2733 | HW_COMPAT_2_1 |
3dab0244 | 2734 | |
5013c547 | 2735 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 2736 | { |
5013c547 | 2737 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 2738 | } |
d25228e7 | 2739 | |
5013c547 | 2740 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 2741 | { |
fc9f38c3 | 2742 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 2743 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 2744 | } |
fccbc785 | 2745 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 2746 | |
29ee3247 | 2747 | static void spapr_machine_register_types(void) |
9fdf0c29 | 2748 | { |
29ee3247 | 2749 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
2750 | } |
2751 | ||
29ee3247 | 2752 | type_init(spapr_machine_register_types) |