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74d042e5 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * RTAS events handling | |
5 | * | |
6 | * Copyright (c) 2012 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
64552b6b | 27 | |
0d75590d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
74d042e5 | 30 | #include "cpu.h" |
9c17d615 | 31 | #include "sysemu/device_tree.h" |
54d31236 | 32 | #include "sysemu/runstate.h" |
74d042e5 | 33 | |
7804c353 | 34 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
35 | #include "hw/ppc/spapr.h" |
36 | #include "hw/ppc/spapr_vio.h" | |
31fe14d1 | 37 | #include "hw/pci/pci.h" |
64552b6b | 38 | #include "hw/irq.h" |
31fe14d1 NF |
39 | #include "hw/pci-host/spapr.h" |
40 | #include "hw/ppc/spapr_drc.h" | |
f348b6d1 VB |
41 | #include "qemu/help_option.h" |
42 | #include "qemu/bcd.h" | |
9ac703ac | 43 | #include "qemu/main-loop.h" |
ffbb1705 | 44 | #include "hw/ppc/spapr_ovec.h" |
74d042e5 | 45 | #include <libfdt.h> |
2500fb42 | 46 | #include "migration/blocker.h" |
74d042e5 | 47 | |
74d042e5 DG |
48 | #define RTAS_LOG_VERSION_MASK 0xff000000 |
49 | #define RTAS_LOG_VERSION_6 0x06000000 | |
50 | #define RTAS_LOG_SEVERITY_MASK 0x00e00000 | |
51 | #define RTAS_LOG_SEVERITY_ALREADY_REPORTED 0x00c00000 | |
52 | #define RTAS_LOG_SEVERITY_FATAL 0x00a00000 | |
53 | #define RTAS_LOG_SEVERITY_ERROR 0x00800000 | |
54 | #define RTAS_LOG_SEVERITY_ERROR_SYNC 0x00600000 | |
55 | #define RTAS_LOG_SEVERITY_WARNING 0x00400000 | |
56 | #define RTAS_LOG_SEVERITY_EVENT 0x00200000 | |
57 | #define RTAS_LOG_SEVERITY_NO_ERROR 0x00000000 | |
58 | #define RTAS_LOG_DISPOSITION_MASK 0x00180000 | |
59 | #define RTAS_LOG_DISPOSITION_FULLY_RECOVERED 0x00000000 | |
60 | #define RTAS_LOG_DISPOSITION_LIMITED_RECOVERY 0x00080000 | |
61 | #define RTAS_LOG_DISPOSITION_NOT_RECOVERED 0x00100000 | |
62 | #define RTAS_LOG_OPTIONAL_PART_PRESENT 0x00040000 | |
63 | #define RTAS_LOG_INITIATOR_MASK 0x0000f000 | |
64 | #define RTAS_LOG_INITIATOR_UNKNOWN 0x00000000 | |
65 | #define RTAS_LOG_INITIATOR_CPU 0x00001000 | |
66 | #define RTAS_LOG_INITIATOR_PCI 0x00002000 | |
67 | #define RTAS_LOG_INITIATOR_MEMORY 0x00004000 | |
68 | #define RTAS_LOG_INITIATOR_HOTPLUG 0x00006000 | |
69 | #define RTAS_LOG_TARGET_MASK 0x00000f00 | |
70 | #define RTAS_LOG_TARGET_UNKNOWN 0x00000000 | |
71 | #define RTAS_LOG_TARGET_CPU 0x00000100 | |
72 | #define RTAS_LOG_TARGET_PCI 0x00000200 | |
73 | #define RTAS_LOG_TARGET_MEMORY 0x00000400 | |
74 | #define RTAS_LOG_TARGET_HOTPLUG 0x00000600 | |
75 | #define RTAS_LOG_TYPE_MASK 0x000000ff | |
76 | #define RTAS_LOG_TYPE_OTHER 0x00000000 | |
77 | #define RTAS_LOG_TYPE_RETRY 0x00000001 | |
78 | #define RTAS_LOG_TYPE_TCE_ERR 0x00000002 | |
79 | #define RTAS_LOG_TYPE_INTERN_DEV_FAIL 0x00000003 | |
80 | #define RTAS_LOG_TYPE_TIMEOUT 0x00000004 | |
81 | #define RTAS_LOG_TYPE_DATA_PARITY 0x00000005 | |
82 | #define RTAS_LOG_TYPE_ADDR_PARITY 0x00000006 | |
83 | #define RTAS_LOG_TYPE_CACHE_PARITY 0x00000007 | |
84 | #define RTAS_LOG_TYPE_ADDR_INVALID 0x00000008 | |
85 | #define RTAS_LOG_TYPE_ECC_UNCORR 0x00000009 | |
86 | #define RTAS_LOG_TYPE_ECC_CORR 0x0000000a | |
87 | #define RTAS_LOG_TYPE_EPOW 0x00000040 | |
31fe14d1 | 88 | #define RTAS_LOG_TYPE_HOTPLUG 0x000000e5 |
74d042e5 | 89 | |
5341258e DG |
90 | struct rtas_error_log { |
91 | uint32_t summary; | |
92 | uint32_t extended_length; | |
93 | } QEMU_PACKED; | |
94 | ||
74d042e5 DG |
95 | struct rtas_event_log_v6 { |
96 | uint8_t b0; | |
97 | #define RTAS_LOG_V6_B0_VALID 0x80 | |
98 | #define RTAS_LOG_V6_B0_UNRECOVERABLE_ERROR 0x40 | |
99 | #define RTAS_LOG_V6_B0_RECOVERABLE_ERROR 0x20 | |
100 | #define RTAS_LOG_V6_B0_DEGRADED_OPERATION 0x10 | |
101 | #define RTAS_LOG_V6_B0_PREDICTIVE_ERROR 0x08 | |
102 | #define RTAS_LOG_V6_B0_NEW_LOG 0x04 | |
103 | #define RTAS_LOG_V6_B0_BIGENDIAN 0x02 | |
104 | uint8_t _resv1; | |
105 | uint8_t b2; | |
106 | #define RTAS_LOG_V6_B2_POWERPC_FORMAT 0x80 | |
107 | #define RTAS_LOG_V6_B2_LOG_FORMAT_MASK 0x0f | |
108 | #define RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT 0x0e | |
109 | uint8_t _resv2[9]; | |
110 | uint32_t company; | |
111 | #define RTAS_LOG_V6_COMPANY_IBM 0x49424d00 /* IBM<null> */ | |
112 | } QEMU_PACKED; | |
113 | ||
114 | struct rtas_event_log_v6_section_header { | |
115 | uint16_t section_id; | |
116 | uint16_t section_length; | |
117 | uint8_t section_version; | |
118 | uint8_t section_subtype; | |
119 | uint16_t creator_component_id; | |
120 | } QEMU_PACKED; | |
121 | ||
122 | struct rtas_event_log_v6_maina { | |
123 | #define RTAS_LOG_V6_SECTION_ID_MAINA 0x5048 /* PH */ | |
124 | struct rtas_event_log_v6_section_header hdr; | |
125 | uint32_t creation_date; /* BCD: YYYYMMDD */ | |
126 | uint32_t creation_time; /* BCD: HHMMSS00 */ | |
127 | uint8_t _platform1[8]; | |
128 | char creator_id; | |
129 | uint8_t _resv1[2]; | |
130 | uint8_t section_count; | |
131 | uint8_t _resv2[4]; | |
132 | uint8_t _platform2[8]; | |
133 | uint32_t plid; | |
134 | uint8_t _platform3[4]; | |
135 | } QEMU_PACKED; | |
136 | ||
137 | struct rtas_event_log_v6_mainb { | |
138 | #define RTAS_LOG_V6_SECTION_ID_MAINB 0x5548 /* UH */ | |
139 | struct rtas_event_log_v6_section_header hdr; | |
140 | uint8_t subsystem_id; | |
141 | uint8_t _platform1; | |
142 | uint8_t event_severity; | |
143 | uint8_t event_subtype; | |
144 | uint8_t _platform2[4]; | |
145 | uint8_t _resv1[2]; | |
146 | uint16_t action_flags; | |
147 | uint8_t _resv2[4]; | |
148 | } QEMU_PACKED; | |
149 | ||
150 | struct rtas_event_log_v6_epow { | |
151 | #define RTAS_LOG_V6_SECTION_ID_EPOW 0x4550 /* EP */ | |
152 | struct rtas_event_log_v6_section_header hdr; | |
153 | uint8_t sensor_value; | |
154 | #define RTAS_LOG_V6_EPOW_ACTION_RESET 0 | |
155 | #define RTAS_LOG_V6_EPOW_ACTION_WARN_COOLING 1 | |
156 | #define RTAS_LOG_V6_EPOW_ACTION_WARN_POWER 2 | |
157 | #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN 3 | |
158 | #define RTAS_LOG_V6_EPOW_ACTION_SYSTEM_HALT 4 | |
159 | #define RTAS_LOG_V6_EPOW_ACTION_MAIN_ENCLOSURE 5 | |
160 | #define RTAS_LOG_V6_EPOW_ACTION_POWER_OFF 7 | |
161 | uint8_t event_modifier; | |
162 | #define RTAS_LOG_V6_EPOW_MODIFIER_NORMAL 1 | |
163 | #define RTAS_LOG_V6_EPOW_MODIFIER_ON_UPS 2 | |
164 | #define RTAS_LOG_V6_EPOW_MODIFIER_CRITICAL 3 | |
165 | #define RTAS_LOG_V6_EPOW_MODIFIER_TEMPERATURE 4 | |
166 | uint8_t extended_modifier; | |
167 | #define RTAS_LOG_V6_EPOW_XMODIFIER_SYSTEM_WIDE 0 | |
168 | #define RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC 1 | |
169 | uint8_t _resv; | |
170 | uint64_t reason_code; | |
171 | } QEMU_PACKED; | |
172 | ||
fd38804b | 173 | struct epow_extended_log { |
74d042e5 DG |
174 | struct rtas_event_log_v6 v6hdr; |
175 | struct rtas_event_log_v6_maina maina; | |
176 | struct rtas_event_log_v6_mainb mainb; | |
177 | struct rtas_event_log_v6_epow epow; | |
178 | } QEMU_PACKED; | |
179 | ||
afdbd403 BR |
180 | union drc_identifier { |
181 | uint32_t index; | |
182 | uint32_t count; | |
183 | struct { | |
184 | uint32_t count; | |
185 | uint32_t index; | |
186 | } count_indexed; | |
187 | char name[1]; | |
188 | } QEMU_PACKED; | |
189 | ||
31fe14d1 NF |
190 | struct rtas_event_log_v6_hp { |
191 | #define RTAS_LOG_V6_SECTION_ID_HOTPLUG 0x4850 /* HP */ | |
192 | struct rtas_event_log_v6_section_header hdr; | |
193 | uint8_t hotplug_type; | |
194 | #define RTAS_LOG_V6_HP_TYPE_CPU 1 | |
195 | #define RTAS_LOG_V6_HP_TYPE_MEMORY 2 | |
196 | #define RTAS_LOG_V6_HP_TYPE_SLOT 3 | |
197 | #define RTAS_LOG_V6_HP_TYPE_PHB 4 | |
198 | #define RTAS_LOG_V6_HP_TYPE_PCI 5 | |
ee3a71e3 | 199 | #define RTAS_LOG_V6_HP_TYPE_PMEM 6 |
31fe14d1 NF |
200 | uint8_t hotplug_action; |
201 | #define RTAS_LOG_V6_HP_ACTION_ADD 1 | |
202 | #define RTAS_LOG_V6_HP_ACTION_REMOVE 2 | |
203 | uint8_t hotplug_identifier; | |
204 | #define RTAS_LOG_V6_HP_ID_DRC_NAME 1 | |
205 | #define RTAS_LOG_V6_HP_ID_DRC_INDEX 2 | |
206 | #define RTAS_LOG_V6_HP_ID_DRC_COUNT 3 | |
afdbd403 | 207 | #define RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED 4 |
31fe14d1 | 208 | uint8_t reserved; |
afdbd403 | 209 | union drc_identifier drc_id; |
31fe14d1 NF |
210 | } QEMU_PACKED; |
211 | ||
fd38804b | 212 | struct hp_extended_log { |
31fe14d1 NF |
213 | struct rtas_event_log_v6 v6hdr; |
214 | struct rtas_event_log_v6_maina maina; | |
215 | struct rtas_event_log_v6_mainb mainb; | |
216 | struct rtas_event_log_v6_hp hp; | |
217 | } QEMU_PACKED; | |
218 | ||
81fe70e4 AP |
219 | struct rtas_event_log_v6_mc { |
220 | #define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ | |
221 | struct rtas_event_log_v6_section_header hdr; | |
222 | uint32_t fru_id; | |
223 | uint32_t proc_id; | |
224 | uint8_t error_type; | |
225 | #define RTAS_LOG_V6_MC_TYPE_UE 0 | |
226 | #define RTAS_LOG_V6_MC_TYPE_SLB 1 | |
227 | #define RTAS_LOG_V6_MC_TYPE_ERAT 2 | |
228 | #define RTAS_LOG_V6_MC_TYPE_TLB 4 | |
229 | #define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 | |
230 | #define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 | |
231 | uint8_t sub_err_type; | |
232 | #define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 | |
233 | #define RTAS_LOG_V6_MC_UE_IFETCH 1 | |
234 | #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 | |
235 | #define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 | |
236 | #define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 | |
237 | #define RTAS_LOG_V6_MC_SLB_PARITY 0 | |
238 | #define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 | |
239 | #define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 | |
240 | #define RTAS_LOG_V6_MC_ERAT_PARITY 1 | |
241 | #define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 | |
242 | #define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 | |
243 | #define RTAS_LOG_V6_MC_TLB_PARITY 1 | |
244 | #define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 | |
245 | #define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 | |
cb9fb64d MS |
246 | /* |
247 | * Per PAPR, | |
248 | * For UE error type, set bit 1 of sub_err_type to indicate effective addr is | |
249 | * provided. For other error types (SLB/ERAT/TLB), set bit 0 to indicate | |
250 | * same. | |
251 | */ | |
252 | #define RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED 0x40 | |
253 | #define RTAS_LOG_V6_MC_EA_ADDR_PROVIDED 0x80 | |
81fe70e4 AP |
254 | uint8_t reserved_1[6]; |
255 | uint64_t effective_address; | |
256 | uint64_t logical_address; | |
257 | } QEMU_PACKED; | |
258 | ||
259 | struct mc_extended_log { | |
260 | struct rtas_event_log_v6 v6hdr; | |
261 | struct rtas_event_log_v6_mc mc; | |
262 | } QEMU_PACKED; | |
263 | ||
264 | struct MC_ierror_table { | |
265 | unsigned long srr1_mask; | |
266 | unsigned long srr1_value; | |
267 | bool nip_valid; /* nip is a valid indicator of faulting address */ | |
268 | uint8_t error_type; | |
269 | uint8_t error_subtype; | |
270 | unsigned int initiator; | |
271 | unsigned int severity; | |
272 | }; | |
273 | ||
274 | static const struct MC_ierror_table mc_ierror_table[] = { | |
275 | { 0x00000000081c0000, 0x0000000000040000, true, | |
276 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, | |
277 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
278 | { 0x00000000081c0000, 0x0000000000080000, true, | |
279 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, | |
280 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
281 | { 0x00000000081c0000, 0x00000000000c0000, true, | |
282 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, | |
283 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
284 | { 0x00000000081c0000, 0x0000000000100000, true, | |
285 | RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, | |
286 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
287 | { 0x00000000081c0000, 0x0000000000140000, true, | |
288 | RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, | |
289 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
290 | { 0x00000000081c0000, 0x0000000000180000, true, | |
291 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, | |
292 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; | |
293 | ||
294 | struct MC_derror_table { | |
295 | unsigned long dsisr_value; | |
296 | bool dar_valid; /* dar is a valid indicator of faulting address */ | |
297 | uint8_t error_type; | |
298 | uint8_t error_subtype; | |
299 | unsigned int initiator; | |
300 | unsigned int severity; | |
301 | }; | |
302 | ||
303 | static const struct MC_derror_table mc_derror_table[] = { | |
304 | { 0x00008000, false, | |
305 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, | |
306 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
307 | { 0x00004000, true, | |
308 | RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, | |
309 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
310 | { 0x00000800, true, | |
311 | RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, | |
312 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
313 | { 0x00000400, true, | |
314 | RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, | |
315 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
316 | { 0x00000080, true, | |
317 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY */ | |
318 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, | |
319 | { 0x00000100, true, | |
320 | RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, | |
321 | RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, } }; | |
322 | ||
323 | #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) | |
324 | ||
ffbb1705 MR |
325 | typedef enum EventClass { |
326 | EVENT_CLASS_INTERNAL_ERRORS = 0, | |
327 | EVENT_CLASS_EPOW = 1, | |
328 | EVENT_CLASS_RESERVED = 2, | |
329 | EVENT_CLASS_HOT_PLUG = 3, | |
330 | EVENT_CLASS_IO = 4, | |
331 | EVENT_CLASS_MAX | |
332 | } EventClassIndex; | |
333 | #define EVENT_CLASS_MASK(index) (1 << (31 - index)) | |
334 | ||
335 | static const char * const event_names[EVENT_CLASS_MAX] = { | |
336 | [EVENT_CLASS_INTERNAL_ERRORS] = "internal-errors", | |
337 | [EVENT_CLASS_EPOW] = "epow-events", | |
338 | [EVENT_CLASS_HOT_PLUG] = "hot-plug-events", | |
339 | [EVENT_CLASS_IO] = "ibm,io-events", | |
340 | }; | |
341 | ||
ce2918cb | 342 | struct SpaprEventSource { |
ffbb1705 MR |
343 | int irq; |
344 | uint32_t mask; | |
345 | bool enabled; | |
346 | }; | |
347 | ||
ce2918cb | 348 | static SpaprEventSource *spapr_event_sources_new(void) |
ffbb1705 | 349 | { |
ce2918cb | 350 | return g_new0(SpaprEventSource, EVENT_CLASS_MAX); |
ffbb1705 MR |
351 | } |
352 | ||
ce2918cb | 353 | static void spapr_event_sources_register(SpaprEventSource *event_sources, |
ffbb1705 MR |
354 | EventClassIndex index, int irq) |
355 | { | |
356 | /* we only support 1 irq per event class at the moment */ | |
357 | g_assert(event_sources); | |
358 | g_assert(!event_sources[index].enabled); | |
359 | event_sources[index].irq = irq; | |
360 | event_sources[index].mask = EVENT_CLASS_MASK(index); | |
361 | event_sources[index].enabled = true; | |
362 | } | |
363 | ||
ce2918cb DG |
364 | static const SpaprEventSource * |
365 | spapr_event_sources_get_source(SpaprEventSource *event_sources, | |
ffbb1705 MR |
366 | EventClassIndex index) |
367 | { | |
368 | g_assert(index < EVENT_CLASS_MAX); | |
369 | g_assert(event_sources); | |
370 | ||
371 | return &event_sources[index]; | |
372 | } | |
74d042e5 | 373 | |
ce2918cb | 374 | void spapr_dt_events(SpaprMachineState *spapr, void *fdt) |
74d042e5 | 375 | { |
ffbb1705 MR |
376 | uint32_t irq_ranges[EVENT_CLASS_MAX * 2]; |
377 | int i, count = 0, event_sources; | |
ce2918cb | 378 | SpaprEventSource *events = spapr->event_sources; |
ffbb1705 MR |
379 | |
380 | g_assert(events); | |
74d042e5 | 381 | |
ffb1e275 | 382 | _FDT(event_sources = fdt_add_subnode(fdt, 0, "event-sources")); |
74d042e5 | 383 | |
ffbb1705 MR |
384 | for (i = 0, count = 0; i < EVENT_CLASS_MAX; i++) { |
385 | int node_offset; | |
386 | uint32_t interrupts[2]; | |
ce2918cb | 387 | const SpaprEventSource *source = |
ffbb1705 MR |
388 | spapr_event_sources_get_source(events, i); |
389 | const char *source_name = event_names[i]; | |
390 | ||
391 | if (!source->enabled) { | |
392 | continue; | |
393 | } | |
394 | ||
5c7adcf4 | 395 | spapr_dt_irq(interrupts, source->irq, false); |
ffbb1705 MR |
396 | |
397 | _FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name)); | |
398 | _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, | |
399 | sizeof(interrupts))); | |
400 | ||
401 | irq_ranges[count++] = interrupts[0]; | |
402 | irq_ranges[count++] = cpu_to_be32(1); | |
403 | } | |
404 | ||
ffbb1705 MR |
405 | _FDT((fdt_setprop(fdt, event_sources, "interrupt-controller", NULL, 0))); |
406 | _FDT((fdt_setprop_cell(fdt, event_sources, "#interrupt-cells", 2))); | |
407 | _FDT((fdt_setprop(fdt, event_sources, "interrupt-ranges", | |
408 | irq_ranges, count * sizeof(uint32_t)))); | |
409 | } | |
410 | ||
ce2918cb DG |
411 | static const SpaprEventSource * |
412 | rtas_event_log_to_source(SpaprMachineState *spapr, int log_type) | |
ffbb1705 | 413 | { |
ce2918cb | 414 | const SpaprEventSource *source; |
ffbb1705 MR |
415 | |
416 | g_assert(spapr->event_sources); | |
417 | ||
418 | switch (log_type) { | |
419 | case RTAS_LOG_TYPE_HOTPLUG: | |
420 | source = spapr_event_sources_get_source(spapr->event_sources, | |
421 | EVENT_CLASS_HOT_PLUG); | |
422 | if (spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)) { | |
423 | g_assert(source->enabled); | |
424 | break; | |
425 | } | |
54db89f5 | 426 | /* fall through back to epow for legacy hotplug interrupt source */ |
ffbb1705 MR |
427 | case RTAS_LOG_TYPE_EPOW: |
428 | source = spapr_event_sources_get_source(spapr->event_sources, | |
429 | EVENT_CLASS_EPOW); | |
430 | break; | |
431 | default: | |
432 | source = NULL; | |
433 | } | |
434 | ||
435 | return source; | |
436 | } | |
437 | ||
ce2918cb | 438 | static int rtas_event_log_to_irq(SpaprMachineState *spapr, int log_type) |
ffbb1705 | 439 | { |
ce2918cb | 440 | const SpaprEventSource *source; |
74d042e5 | 441 | |
ffbb1705 MR |
442 | source = rtas_event_log_to_source(spapr, log_type); |
443 | g_assert(source); | |
444 | g_assert(source->enabled); | |
445 | ||
446 | return source->irq; | |
74d042e5 DG |
447 | } |
448 | ||
ce2918cb | 449 | static uint32_t spapr_event_log_entry_type(SpaprEventLogEntry *entry) |
31fe14d1 | 450 | { |
5341258e | 451 | return entry->summary & RTAS_LOG_TYPE_MASK; |
fd38804b | 452 | } |
74d042e5 | 453 | |
ce2918cb DG |
454 | static void rtas_event_log_queue(SpaprMachineState *spapr, |
455 | SpaprEventLogEntry *entry) | |
fd38804b | 456 | { |
31fe14d1 NF |
457 | QTAILQ_INSERT_TAIL(&spapr->pending_events, entry, next); |
458 | } | |
459 | ||
ce2918cb | 460 | static SpaprEventLogEntry *rtas_event_log_dequeue(SpaprMachineState *spapr, |
fd38804b | 461 | uint32_t event_mask) |
74d042e5 | 462 | { |
ce2918cb | 463 | SpaprEventLogEntry *entry = NULL; |
74d042e5 | 464 | |
31fe14d1 | 465 | QTAILQ_FOREACH(entry, &spapr->pending_events, next) { |
ce2918cb | 466 | const SpaprEventSource *source = |
fd38804b DHB |
467 | rtas_event_log_to_source(spapr, |
468 | spapr_event_log_entry_type(entry)); | |
ffbb1705 | 469 | |
59d0533b | 470 | g_assert(source); |
ffbb1705 | 471 | if (source->mask & event_mask) { |
31fe14d1 NF |
472 | break; |
473 | } | |
474 | } | |
475 | ||
476 | if (entry) { | |
477 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); | |
478 | } | |
479 | ||
480 | return entry; | |
481 | } | |
482 | ||
bff30638 | 483 | static bool rtas_event_log_contains(uint32_t event_mask) |
31fe14d1 | 484 | { |
ce2918cb DG |
485 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
486 | SpaprEventLogEntry *entry = NULL; | |
31fe14d1 | 487 | |
31fe14d1 | 488 | QTAILQ_FOREACH(entry, &spapr->pending_events, next) { |
ce2918cb | 489 | const SpaprEventSource *source = |
fd38804b DHB |
490 | rtas_event_log_to_source(spapr, |
491 | spapr_event_log_entry_type(entry)); | |
ffbb1705 | 492 | |
ffbb1705 | 493 | if (source->mask & event_mask) { |
31fe14d1 NF |
494 | return true; |
495 | } | |
496 | } | |
497 | ||
498 | return false; | |
499 | } | |
74d042e5 | 500 | |
31fe14d1 NF |
501 | static uint32_t next_plid; |
502 | ||
503 | static void spapr_init_v6hdr(struct rtas_event_log_v6 *v6hdr) | |
504 | { | |
74d042e5 DG |
505 | v6hdr->b0 = RTAS_LOG_V6_B0_VALID | RTAS_LOG_V6_B0_NEW_LOG |
506 | | RTAS_LOG_V6_B0_BIGENDIAN; | |
507 | v6hdr->b2 = RTAS_LOG_V6_B2_POWERPC_FORMAT | |
508 | | RTAS_LOG_V6_B2_LOG_FORMAT_PLATFORM_EVENT; | |
509 | v6hdr->company = cpu_to_be32(RTAS_LOG_V6_COMPANY_IBM); | |
31fe14d1 NF |
510 | } |
511 | ||
512 | static void spapr_init_maina(struct rtas_event_log_v6_maina *maina, | |
513 | int section_count) | |
514 | { | |
ce2918cb | 515 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
31fe14d1 NF |
516 | struct tm tm; |
517 | int year; | |
74d042e5 DG |
518 | |
519 | maina->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINA); | |
520 | maina->hdr.section_length = cpu_to_be16(sizeof(*maina)); | |
521 | /* FIXME: section version, subtype and creator id? */ | |
147ff807 | 522 | spapr_rtc_read(&spapr->rtc, &tm, NULL); |
74d042e5 DG |
523 | year = tm.tm_year + 1900; |
524 | maina->creation_date = cpu_to_be32((to_bcd(year / 100) << 24) | |
525 | | (to_bcd(year % 100) << 16) | |
526 | | (to_bcd(tm.tm_mon + 1) << 8) | |
527 | | to_bcd(tm.tm_mday)); | |
528 | maina->creation_time = cpu_to_be32((to_bcd(tm.tm_hour) << 24) | |
529 | | (to_bcd(tm.tm_min) << 16) | |
530 | | (to_bcd(tm.tm_sec) << 8)); | |
531 | maina->creator_id = 'H'; /* Hypervisor */ | |
31fe14d1 | 532 | maina->section_count = section_count; |
74d042e5 | 533 | maina->plid = next_plid++; |
31fe14d1 NF |
534 | } |
535 | ||
536 | static void spapr_powerdown_req(Notifier *n, void *opaque) | |
537 | { | |
ce2918cb DG |
538 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
539 | SpaprEventLogEntry *entry; | |
31fe14d1 NF |
540 | struct rtas_event_log_v6 *v6hdr; |
541 | struct rtas_event_log_v6_maina *maina; | |
542 | struct rtas_event_log_v6_mainb *mainb; | |
543 | struct rtas_event_log_v6_epow *epow; | |
fd38804b | 544 | struct epow_extended_log *new_epow; |
31fe14d1 | 545 | |
ce2918cb | 546 | entry = g_new(SpaprEventLogEntry, 1); |
31fe14d1 | 547 | new_epow = g_malloc0(sizeof(*new_epow)); |
fd38804b DHB |
548 | entry->extended_log = new_epow; |
549 | ||
31fe14d1 NF |
550 | v6hdr = &new_epow->v6hdr; |
551 | maina = &new_epow->maina; | |
552 | mainb = &new_epow->mainb; | |
553 | epow = &new_epow->epow; | |
554 | ||
5341258e | 555 | entry->summary = RTAS_LOG_VERSION_6 |
fd38804b DHB |
556 | | RTAS_LOG_SEVERITY_EVENT |
557 | | RTAS_LOG_DISPOSITION_NOT_RECOVERED | |
558 | | RTAS_LOG_OPTIONAL_PART_PRESENT | |
559 | | RTAS_LOG_TYPE_EPOW; | |
5341258e | 560 | entry->extended_length = sizeof(*new_epow); |
31fe14d1 NF |
561 | |
562 | spapr_init_v6hdr(v6hdr); | |
563 | spapr_init_maina(maina, 3 /* Main-A, Main-B and EPOW */); | |
74d042e5 DG |
564 | |
565 | mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); | |
566 | mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); | |
567 | /* FIXME: section version, subtype and creator id? */ | |
568 | mainb->subsystem_id = 0xa0; /* External environment */ | |
569 | mainb->event_severity = 0x00; /* Informational / non-error */ | |
570 | mainb->event_subtype = 0xd0; /* Normal shutdown */ | |
571 | ||
572 | epow->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_EPOW); | |
573 | epow->hdr.section_length = cpu_to_be16(sizeof(*epow)); | |
574 | epow->hdr.section_version = 2; /* includes extended modifier */ | |
575 | /* FIXME: section subtype and creator id? */ | |
576 | epow->sensor_value = RTAS_LOG_V6_EPOW_ACTION_SYSTEM_SHUTDOWN; | |
577 | epow->event_modifier = RTAS_LOG_V6_EPOW_MODIFIER_NORMAL; | |
578 | epow->extended_modifier = RTAS_LOG_V6_EPOW_XMODIFIER_PARTITION_SPECIFIC; | |
579 | ||
fd38804b | 580 | rtas_event_log_queue(spapr, entry); |
31fe14d1 | 581 | |
77183755 CLG |
582 | qemu_irq_pulse(spapr_qirq(spapr, |
583 | rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_EPOW))); | |
31fe14d1 NF |
584 | } |
585 | ||
7a36ae7a | 586 | static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action, |
ce2918cb | 587 | SpaprDrcType drc_type, |
afdbd403 | 588 | union drc_identifier *drc_id) |
31fe14d1 | 589 | { |
ce2918cb DG |
590 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
591 | SpaprEventLogEntry *entry; | |
fd38804b | 592 | struct hp_extended_log *new_hp; |
31fe14d1 NF |
593 | struct rtas_event_log_v6 *v6hdr; |
594 | struct rtas_event_log_v6_maina *maina; | |
595 | struct rtas_event_log_v6_mainb *mainb; | |
596 | struct rtas_event_log_v6_hp *hp; | |
31fe14d1 | 597 | |
ce2918cb | 598 | entry = g_new(SpaprEventLogEntry, 1); |
fd38804b DHB |
599 | new_hp = g_malloc0(sizeof(struct hp_extended_log)); |
600 | entry->extended_log = new_hp; | |
601 | ||
31fe14d1 NF |
602 | v6hdr = &new_hp->v6hdr; |
603 | maina = &new_hp->maina; | |
604 | mainb = &new_hp->mainb; | |
605 | hp = &new_hp->hp; | |
606 | ||
5341258e DG |
607 | entry->summary = RTAS_LOG_VERSION_6 |
608 | | RTAS_LOG_SEVERITY_EVENT | |
609 | | RTAS_LOG_DISPOSITION_NOT_RECOVERED | |
610 | | RTAS_LOG_OPTIONAL_PART_PRESENT | |
611 | | RTAS_LOG_INITIATOR_HOTPLUG | |
612 | | RTAS_LOG_TYPE_HOTPLUG; | |
613 | entry->extended_length = sizeof(*new_hp); | |
31fe14d1 NF |
614 | |
615 | spapr_init_v6hdr(v6hdr); | |
616 | spapr_init_maina(maina, 3 /* Main-A, Main-B, HP */); | |
617 | ||
618 | mainb->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MAINB); | |
619 | mainb->hdr.section_length = cpu_to_be16(sizeof(*mainb)); | |
620 | mainb->subsystem_id = 0x80; /* External environment */ | |
621 | mainb->event_severity = 0x00; /* Informational / non-error */ | |
622 | mainb->event_subtype = 0x00; /* Normal shutdown */ | |
623 | ||
624 | hp->hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_HOTPLUG); | |
625 | hp->hdr.section_length = cpu_to_be16(sizeof(*hp)); | |
626 | hp->hdr.section_version = 1; /* includes extended modifier */ | |
627 | hp->hotplug_action = hp_action; | |
7a36ae7a | 628 | hp->hotplug_identifier = hp_id; |
31fe14d1 NF |
629 | |
630 | switch (drc_type) { | |
631 | case SPAPR_DR_CONNECTOR_TYPE_PCI: | |
31fe14d1 NF |
632 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PCI; |
633 | break; | |
c20d332a BR |
634 | case SPAPR_DR_CONNECTOR_TYPE_LMB: |
635 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_MEMORY; | |
636 | break; | |
af81cf32 BR |
637 | case SPAPR_DR_CONNECTOR_TYPE_CPU: |
638 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_CPU; | |
639 | break; | |
4b6d336f MR |
640 | case SPAPR_DR_CONNECTOR_TYPE_PHB: |
641 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PHB; | |
642 | break; | |
ee3a71e3 SB |
643 | case SPAPR_DR_CONNECTOR_TYPE_PMEM: |
644 | hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PMEM; | |
645 | break; | |
31fe14d1 NF |
646 | default: |
647 | /* we shouldn't be signaling hotplug events for resources | |
648 | * that don't support them | |
649 | */ | |
650 | g_assert(false); | |
651 | return; | |
652 | } | |
653 | ||
7a36ae7a | 654 | if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT) { |
afdbd403 | 655 | hp->drc_id.count = cpu_to_be32(drc_id->count); |
7a36ae7a | 656 | } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_INDEX) { |
afdbd403 BR |
657 | hp->drc_id.index = cpu_to_be32(drc_id->index); |
658 | } else if (hp_id == RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED) { | |
659 | /* we should not be using count_indexed value unless the guest | |
660 | * supports dedicated hotplug event source | |
661 | */ | |
662 | g_assert(spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT)); | |
663 | hp->drc_id.count_indexed.count = | |
664 | cpu_to_be32(drc_id->count_indexed.count); | |
665 | hp->drc_id.count_indexed.index = | |
666 | cpu_to_be32(drc_id->count_indexed.index); | |
7a36ae7a BR |
667 | } |
668 | ||
fd38804b | 669 | rtas_event_log_queue(spapr, entry); |
31fe14d1 | 670 | |
77183755 CLG |
671 | qemu_irq_pulse(spapr_qirq(spapr, |
672 | rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_HOTPLUG))); | |
31fe14d1 NF |
673 | } |
674 | ||
ce2918cb | 675 | void spapr_hotplug_req_add_by_index(SpaprDrc *drc) |
7a36ae7a | 676 | { |
ce2918cb | 677 | SpaprDrcType drc_type = spapr_drc_type(drc); |
afdbd403 | 678 | union drc_identifier drc_id; |
7a36ae7a | 679 | |
0b55aa91 | 680 | drc_id.index = spapr_drc_index(drc); |
7a36ae7a | 681 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, |
afdbd403 | 682 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); |
7a36ae7a BR |
683 | } |
684 | ||
ce2918cb | 685 | void spapr_hotplug_req_remove_by_index(SpaprDrc *drc) |
7a36ae7a | 686 | { |
ce2918cb | 687 | SpaprDrcType drc_type = spapr_drc_type(drc); |
afdbd403 | 688 | union drc_identifier drc_id; |
7a36ae7a | 689 | |
0b55aa91 | 690 | drc_id.index = spapr_drc_index(drc); |
7a36ae7a | 691 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_INDEX, |
afdbd403 | 692 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); |
7a36ae7a BR |
693 | } |
694 | ||
ce2918cb | 695 | void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, |
7a36ae7a | 696 | uint32_t count) |
31fe14d1 | 697 | { |
afdbd403 BR |
698 | union drc_identifier drc_id; |
699 | ||
700 | drc_id.count = count; | |
7a36ae7a | 701 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, |
afdbd403 | 702 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); |
31fe14d1 NF |
703 | } |
704 | ||
ce2918cb | 705 | void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, |
7a36ae7a | 706 | uint32_t count) |
31fe14d1 | 707 | { |
afdbd403 BR |
708 | union drc_identifier drc_id; |
709 | ||
710 | drc_id.count = count; | |
7a36ae7a | 711 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT, |
afdbd403 BR |
712 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); |
713 | } | |
714 | ||
ce2918cb | 715 | void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, |
afdbd403 BR |
716 | uint32_t count, uint32_t index) |
717 | { | |
718 | union drc_identifier drc_id; | |
719 | ||
720 | drc_id.count_indexed.count = count; | |
721 | drc_id.count_indexed.index = index; | |
722 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, | |
723 | RTAS_LOG_V6_HP_ACTION_ADD, drc_type, &drc_id); | |
724 | } | |
725 | ||
ce2918cb | 726 | void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, |
afdbd403 BR |
727 | uint32_t count, uint32_t index) |
728 | { | |
729 | union drc_identifier drc_id; | |
730 | ||
731 | drc_id.count_indexed.count = count; | |
732 | drc_id.count_indexed.index = index; | |
733 | spapr_hotplug_req_event(RTAS_LOG_V6_HP_ID_DRC_COUNT_INDEXED, | |
734 | RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); | |
74d042e5 DG |
735 | } |
736 | ||
cb9fb64d MS |
737 | static void spapr_mc_set_ea_provided_flag(struct mc_extended_log *ext_elog) |
738 | { | |
739 | switch (ext_elog->mc.error_type) { | |
740 | case RTAS_LOG_V6_MC_TYPE_UE: | |
741 | ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED; | |
742 | break; | |
743 | case RTAS_LOG_V6_MC_TYPE_SLB: | |
744 | case RTAS_LOG_V6_MC_TYPE_ERAT: | |
745 | case RTAS_LOG_V6_MC_TYPE_TLB: | |
746 | ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_EA_ADDR_PROVIDED; | |
747 | break; | |
748 | default: | |
749 | break; | |
750 | } | |
751 | } | |
752 | ||
81fe70e4 AP |
753 | static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, |
754 | struct mc_extended_log *ext_elog) | |
755 | { | |
756 | int i; | |
757 | CPUPPCState *env = &cpu->env; | |
758 | uint32_t summary; | |
759 | uint64_t dsisr = env->spr[SPR_DSISR]; | |
760 | ||
761 | summary = RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; | |
762 | if (recovered) { | |
763 | summary |= RTAS_LOG_DISPOSITION_FULLY_RECOVERED; | |
764 | } else { | |
765 | summary |= RTAS_LOG_DISPOSITION_NOT_RECOVERED; | |
766 | } | |
767 | ||
768 | if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { | |
769 | for (i = 0; i < ARRAY_SIZE(mc_derror_table); i++) { | |
770 | if (!(dsisr & mc_derror_table[i].dsisr_value)) { | |
771 | continue; | |
772 | } | |
773 | ||
774 | ext_elog->mc.error_type = mc_derror_table[i].error_type; | |
775 | ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype; | |
776 | if (mc_derror_table[i].dar_valid) { | |
777 | ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]); | |
cb9fb64d | 778 | spapr_mc_set_ea_provided_flag(ext_elog); |
81fe70e4 AP |
779 | } |
780 | ||
781 | summary |= mc_derror_table[i].initiator | |
782 | | mc_derror_table[i].severity; | |
783 | ||
784 | return summary; | |
785 | } | |
786 | } else { | |
787 | for (i = 0; i < ARRAY_SIZE(mc_ierror_table); i++) { | |
788 | if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) != | |
789 | mc_ierror_table[i].srr1_value) { | |
790 | continue; | |
791 | } | |
792 | ||
793 | ext_elog->mc.error_type = mc_ierror_table[i].error_type; | |
794 | ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype; | |
795 | if (mc_ierror_table[i].nip_valid) { | |
796 | ext_elog->mc.effective_address = cpu_to_be64(env->nip); | |
cb9fb64d | 797 | spapr_mc_set_ea_provided_flag(ext_elog); |
81fe70e4 AP |
798 | } |
799 | ||
800 | summary |= mc_ierror_table[i].initiator | |
801 | | mc_ierror_table[i].severity; | |
802 | ||
803 | return summary; | |
804 | } | |
805 | } | |
806 | ||
807 | summary |= RTAS_LOG_INITIATOR_CPU; | |
808 | return summary; | |
809 | } | |
810 | ||
811 | static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered) | |
812 | { | |
813 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
ad77c6ca | 814 | CPUState *cs = CPU(cpu); |
81fe70e4 | 815 | CPUPPCState *env = &cpu->env; |
ad77c6ca | 816 | uint64_t rtas_addr; |
81fe70e4 AP |
817 | struct rtas_error_log log; |
818 | struct mc_extended_log *ext_elog; | |
819 | uint32_t summary; | |
820 | ||
81fe70e4 AP |
821 | ext_elog = g_malloc0(sizeof(*ext_elog)); |
822 | summary = spapr_mce_get_elog_type(cpu, recovered, ext_elog); | |
823 | ||
824 | log.summary = cpu_to_be32(summary); | |
825 | log.extended_length = cpu_to_be32(sizeof(*ext_elog)); | |
826 | ||
827 | spapr_init_v6hdr(&ext_elog->v6hdr); | |
828 | ext_elog->mc.hdr.section_id = cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); | |
829 | ext_elog->mc.hdr.section_length = | |
830 | cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); | |
831 | ext_elog->mc.hdr.section_version = 1; | |
832 | ||
833 | /* get rtas addr from fdt */ | |
834 | rtas_addr = spapr_get_rtas_addr(); | |
835 | if (!rtas_addr) { | |
4f7a11f9 NP |
836 | if (!recovered) { |
837 | error_report( | |
b90b9ecb | 838 | "FWNMI: Unable to deliver machine check to guest: rtas_addr not found."); |
4f7a11f9 NP |
839 | qemu_system_guest_panicked(NULL); |
840 | } else { | |
841 | warn_report( | |
842 | "FWNMI: Unable to deliver machine check to guest: rtas_addr not found. " | |
843 | "Machine check recovered."); | |
844 | } | |
81fe70e4 AP |
845 | g_free(ext_elog); |
846 | return; | |
847 | } | |
848 | ||
4f7a11f9 NP |
849 | /* |
850 | * By taking the interlock, we assume that the MCE will be | |
851 | * delivered to the guest. CAUTION: don't add anything that could | |
852 | * prevent the MCE to be delivered after this line, otherwise the | |
853 | * guest won't be able to release the interlock and ultimately | |
854 | * hang/crash? | |
855 | */ | |
856 | spapr->fwnmi_machine_check_interlock = cpu->vcpu_id; | |
857 | ||
81fe70e4 AP |
858 | stq_be_phys(&address_space_memory, rtas_addr + RTAS_ERROR_LOG_OFFSET, |
859 | env->gpr[3]); | |
860 | cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + | |
861 | sizeof(env->gpr[3]), &log, sizeof(log)); | |
862 | cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + | |
863 | sizeof(env->gpr[3]) + sizeof(log), ext_elog, | |
864 | sizeof(*ext_elog)); | |
ad77c6ca | 865 | g_free(ext_elog); |
81fe70e4 AP |
866 | |
867 | env->gpr[3] = rtas_addr + RTAS_ERROR_LOG_OFFSET; | |
81fe70e4 | 868 | |
ad77c6ca | 869 | ppc_cpu_do_fwnmi_machine_check(cs, spapr->fwnmi_machine_check_addr); |
81fe70e4 AP |
870 | } |
871 | ||
872 | void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) | |
9ac703ac AP |
873 | { |
874 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
875 | CPUState *cs = CPU(cpu); | |
2500fb42 AP |
876 | int ret; |
877 | Error *local_err = NULL; | |
9ac703ac | 878 | |
8af7e1fe | 879 | if (spapr->fwnmi_machine_check_addr == -1) { |
6c3dd24c | 880 | /* Non-FWNMI case, deliver it like an architected CPU interrupt. */ |
9ac703ac AP |
881 | cs->exception_index = POWERPC_EXCP_MCHECK; |
882 | ppc_cpu_do_interrupt(cs); | |
883 | return; | |
884 | } | |
885 | ||
6c3dd24c | 886 | /* Wait for FWNMI interlock. */ |
8af7e1fe | 887 | while (spapr->fwnmi_machine_check_interlock != -1) { |
9ac703ac AP |
888 | /* |
889 | * Check whether the same CPU got machine check error | |
890 | * while still handling the mc error (i.e., before | |
891 | * that CPU called "ibm,nmi-interlock") | |
892 | */ | |
8af7e1fe | 893 | if (spapr->fwnmi_machine_check_interlock == cpu->vcpu_id) { |
4f7a11f9 NP |
894 | if (!recovered) { |
895 | error_report( | |
b90b9ecb | 896 | "FWNMI: Unable to deliver machine check to guest: nested machine check."); |
4f7a11f9 NP |
897 | qemu_system_guest_panicked(NULL); |
898 | } else { | |
899 | warn_report( | |
900 | "FWNMI: Unable to deliver machine check to guest: nested machine check. " | |
901 | "Machine check recovered."); | |
902 | } | |
9ac703ac AP |
903 | return; |
904 | } | |
8af7e1fe | 905 | qemu_cond_wait_iothread(&spapr->fwnmi_machine_check_interlock_cond); |
8af7e1fe | 906 | if (spapr->fwnmi_machine_check_addr == -1) { |
6c3dd24c NP |
907 | /* |
908 | * If the machine was reset while waiting for the interlock, | |
909 | * abort the delivery. The machine check applies to a context | |
910 | * that no longer exists, so it wouldn't make sense to deliver | |
911 | * it now. | |
912 | */ | |
9ac703ac AP |
913 | return; |
914 | } | |
915 | } | |
81fe70e4 | 916 | |
2500fb42 AP |
917 | ret = migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err); |
918 | if (ret == -EBUSY) { | |
919 | /* | |
920 | * We don't want to abort so we let the migration to continue. | |
921 | * In a rare case, the machine check handler will run on the target. | |
922 | * Though this is not preferable, it is better than aborting | |
6c3dd24c NP |
923 | * the migration or killing the VM. It is okay to call |
924 | * migrate_del_blocker on a blocker that was not added (which the | |
925 | * nmi-interlock handler would do when it's called after this). | |
2500fb42 AP |
926 | */ |
927 | warn_report("Received a fwnmi while migration was in progress"); | |
928 | } | |
929 | ||
81fe70e4 | 930 | spapr_mce_dispatch_elog(cpu, recovered); |
9ac703ac AP |
931 | } |
932 | ||
ce2918cb | 933 | static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, |
74d042e5 DG |
934 | uint32_t token, uint32_t nargs, |
935 | target_ulong args, | |
936 | uint32_t nret, target_ulong rets) | |
937 | { | |
31fe14d1 | 938 | uint32_t mask, buf, len, event_len; |
74d042e5 | 939 | uint64_t xinfo; |
ce2918cb | 940 | SpaprEventLogEntry *event; |
5341258e | 941 | struct rtas_error_log header; |
ffbb1705 | 942 | int i; |
74d042e5 DG |
943 | |
944 | if ((nargs < 6) || (nargs > 7) || nret != 1) { | |
a64d325d | 945 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
74d042e5 DG |
946 | return; |
947 | } | |
948 | ||
949 | xinfo = rtas_ld(args, 1); | |
950 | mask = rtas_ld(args, 2); | |
951 | buf = rtas_ld(args, 4); | |
952 | len = rtas_ld(args, 5); | |
953 | if (nargs == 7) { | |
954 | xinfo |= (uint64_t)rtas_ld(args, 6) << 32; | |
955 | } | |
956 | ||
fd38804b | 957 | event = rtas_event_log_dequeue(spapr, mask); |
31fe14d1 NF |
958 | if (!event) { |
959 | goto out_no_events; | |
960 | } | |
74d042e5 | 961 | |
5341258e | 962 | event_len = event->extended_length + sizeof(header); |
31fe14d1 NF |
963 | |
964 | if (event_len < len) { | |
965 | len = event_len; | |
966 | } | |
967 | ||
5341258e DG |
968 | header.summary = cpu_to_be32(event->summary); |
969 | header.extended_length = cpu_to_be32(event->extended_length); | |
970 | cpu_physical_memory_write(buf, &header, sizeof(header)); | |
971 | cpu_physical_memory_write(buf + sizeof(header), event->extended_log, | |
972 | event->extended_length); | |
31fe14d1 | 973 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
fd38804b | 974 | g_free(event->extended_log); |
31fe14d1 NF |
975 | g_free(event); |
976 | ||
977 | /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if | |
978 | * there are still pending events to be fetched via check-exception. We | |
979 | * do the latter here, since our code relies on edge-triggered | |
980 | * interrupts. | |
981 | */ | |
ffbb1705 | 982 | for (i = 0; i < EVENT_CLASS_MAX; i++) { |
bff30638 | 983 | if (rtas_event_log_contains(EVENT_CLASS_MASK(i))) { |
ce2918cb | 984 | const SpaprEventSource *source = |
ffbb1705 MR |
985 | spapr_event_sources_get_source(spapr->event_sources, i); |
986 | ||
987 | g_assert(source->enabled); | |
77183755 | 988 | qemu_irq_pulse(spapr_qirq(spapr, source->irq)); |
ffbb1705 | 989 | } |
74d042e5 | 990 | } |
31fe14d1 NF |
991 | |
992 | return; | |
993 | ||
994 | out_no_events: | |
995 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); | |
74d042e5 DG |
996 | } |
997 | ||
ce2918cb | 998 | static void event_scan(PowerPCCPU *cpu, SpaprMachineState *spapr, |
79853e18 TD |
999 | uint32_t token, uint32_t nargs, |
1000 | target_ulong args, | |
1001 | uint32_t nret, target_ulong rets) | |
1002 | { | |
79853e18 TD |
1003 | if (nargs != 4 || nret != 1) { |
1004 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
1005 | return; | |
1006 | } | |
79853e18 TD |
1007 | rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); |
1008 | } | |
1009 | ||
ce2918cb | 1010 | void spapr_clear_pending_events(SpaprMachineState *spapr) |
56258174 | 1011 | { |
ce2918cb | 1012 | SpaprEventLogEntry *entry = NULL, *next_entry; |
56258174 | 1013 | |
d492a75c | 1014 | QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) { |
56258174 DHB |
1015 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); |
1016 | g_free(entry->extended_log); | |
1017 | g_free(entry); | |
1018 | } | |
1019 | } | |
1020 | ||
ad334d89 GK |
1021 | void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr) |
1022 | { | |
1023 | SpaprEventLogEntry *entry = NULL, *next_entry; | |
1024 | ||
1025 | QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) { | |
1026 | if (spapr_event_log_entry_type(entry) == RTAS_LOG_TYPE_HOTPLUG) { | |
1027 | QTAILQ_REMOVE(&spapr->pending_events, entry, next); | |
1028 | g_free(entry->extended_log); | |
1029 | g_free(entry); | |
1030 | } | |
1031 | } | |
1032 | } | |
1033 | ||
ce2918cb | 1034 | void spapr_events_init(SpaprMachineState *spapr) |
74d042e5 | 1035 | { |
82cffa2e | 1036 | int epow_irq = SPAPR_IRQ_EPOW; |
4fe75a8c | 1037 | |
82cffa2e CLG |
1038 | if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
1039 | epow_irq = spapr_irq_findone(spapr, &error_fatal); | |
1040 | } | |
4fe75a8c CLG |
1041 | |
1042 | spapr_irq_claim(spapr, epow_irq, false, &error_fatal); | |
1043 | ||
31fe14d1 | 1044 | QTAILQ_INIT(&spapr->pending_events); |
ffbb1705 MR |
1045 | |
1046 | spapr->event_sources = spapr_event_sources_new(); | |
1047 | ||
1048 | spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_EPOW, | |
4fe75a8c | 1049 | epow_irq); |
ffbb1705 MR |
1050 | |
1051 | /* NOTE: if machine supports modern/dedicated hotplug event source, | |
1052 | * we add it to the device-tree unconditionally. This means we may | |
1053 | * have cases where the source is enabled in QEMU, but unused by the | |
1054 | * guest because it does not support modern hotplug events, so we | |
1055 | * take care to rely on checking for negotiation of OV5_HP_EVT option | |
1056 | * before attempting to use it to signal events, rather than simply | |
1057 | * checking that it's enabled. | |
1058 | */ | |
1059 | if (spapr->use_hotplug_event_source) { | |
82cffa2e | 1060 | int hp_irq = SPAPR_IRQ_HOTPLUG; |
4fe75a8c | 1061 | |
82cffa2e CLG |
1062 | if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
1063 | hp_irq = spapr_irq_findone(spapr, &error_fatal); | |
1064 | } | |
4fe75a8c CLG |
1065 | |
1066 | spapr_irq_claim(spapr, hp_irq, false, &error_fatal); | |
1067 | ||
ffbb1705 | 1068 | spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT_PLUG, |
4fe75a8c | 1069 | hp_irq); |
ffbb1705 MR |
1070 | } |
1071 | ||
74d042e5 DG |
1072 | spapr->epow_notifier.notify = spapr_powerdown_req; |
1073 | qemu_register_powerdown_notifier(&spapr->epow_notifier); | |
3a3b8502 AK |
1074 | spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception", |
1075 | check_exception); | |
79853e18 | 1076 | spapr_rtas_register(RTAS_EVENT_SCAN, "event-scan", event_scan); |
74d042e5 | 1077 | } |